JP2021019169A - Electronic component built-in substrate and method for manufacturing the same - Google Patents

Abstract

To prevent separation of a via conductor for heat discharge in an electronic component built-in substrate with an electronic component such as a semiconductor IC buried therein.SOLUTION: An electronic component built-in substrate 1 includes: a substrate having wire layers L1 to L4 and insulating layers 11 to 14; an electronic component 40 buried in the substrate, the electronic component having a back surface 44 covered with a metal laminate film 50; a via conductor 35 connecting the wire layer L4 and the metal laminate film 50 to each other. The metal laminate film 50 has a laminate structure including highly adhesive metal films 51 and 52 and a metal film 53 between the metal films. The via conductor 35 penetrates the metal film 52 and extends into the metal film 53. Since the highly adhesive metal films 51, 52 are formed on both sides of the metal laminate film 50 and the back surface 44 of the electronic component 40 is covered by the metal laminate film and the via conductor 35 extends into the metal film 53, the via conductor 35 can be prevented from separating due to temperature change.SELECTED DRAWING: Figure 2

Description

The present invention relates to an electronic component-embedded substrate and a method for manufacturing the same, and more particularly to an electronic component-embedded substrate in which electronic components such as a semiconductor IC are embedded and a method for manufacturing the same.

As an electronic component-embedded substrate in which an electronic component such as a semiconductor IC is embedded, the electronic component-embedded substrate described in Patent Documents 1 and 2 is known. Since the electronic component-embedded substrates described in Patent Documents 1 and 2 include a via conductor for heat dissipation in contact with the back surface of the semiconductor IC, heat generated by the operation of the semiconductor IC can be efficiently dissipated.

However, since the silicon constituting the semiconductor IC and the metal material constituting the via conductor have significantly different coefficients of thermal expansion, there is a problem that the interface between the back surface of the semiconductor IC and the via conductor is easily peeled off due to a temperature change. Here, Patent Document 2 gives an example in which a metal film is formed on the back surface of a semiconductor IC. In this way, if a metal film is formed on the back surface of the semiconductor IC and a via conductor is formed so as to be in contact with the metal film, peeling is less likely to occur.

International Publication No. 2008/07569 Pamphlet Japanese Unexamined Patent Publication No. 2013-229548

However, copper (Cu), which is mainly used as a material for a metal film, does not always have sufficient adhesion to a material constituting an element body of an electronic component such as silicon, and therefore simply forms a metal film on the back surface of a semiconductor IC. It was difficult to reliably prevent peeling due to temperature changes simply by doing so.

Therefore, an object of the present invention is to more effectively prevent peeling of a via conductor for heat dissipation in an electronic component-embedded substrate in which an electronic component such as a semiconductor IC is embedded and a method for manufacturing the same.

The substrate with built-in electronic components according to the present invention is mainly composed of a substrate in which a plurality of wiring layers including a first wiring layer and a plurality of insulating layers including first and second insulating layers are laminated, and a terminal electrode is formed. A substrate having a surface and a back surface located on the opposite side of the main surface and covered with a metal laminate, so that the main surface is covered with a first insulating layer and the back surface is covered with a second insulating layer. It is provided with an electronic component embedded in the metal and a via conductor provided through a second insulating layer and connecting the first wiring layer and the metal laminated film, and the metal laminated film is in contact with the back surface of the electronic component. A first metal including a first metal film, a second metal film in contact with a second insulating layer, and a third metal film located between the first metal film and the second metal film. The film is made of a metal material having a higher adhesion to electronic parts than the third metal film, and the second metal film is made of a metal material having a higher adhesion to the second insulating layer than the third metal film. The via conductor is characterized in that it penetrates the second metal film and bites into the third metal film.

According to the present invention, the back surface of the electronic component is covered with the metal laminated film in which the first and second metal films having high adhesion are located on both sides, and the via conductor is formed so as to bite into the third metal film. Since it is provided, it is possible to prevent peeling of the via conductor due to a temperature change.

In the present invention, the end portion of the via conductor may be located in the third metal film without being in contact with the first metal film. According to this, when the via hole forming the via conductor is formed, the electronic component is not damaged.

In the present invention, the diameter of the via conductor in the third metal film may be larger than the opening diameter of the second metal film. According to this, the increase in the contact area between the via conductor and the third metal film makes it difficult for peeling to occur at the interface between the two.

In the present invention, the third metal film and the via conductor may be made of the same metal material. According to this, since the adhesion between the via conductor and the third metal film is enhanced, peeling at the interface between the two is less likely to occur. In this case, both the third metal film and the via conductor may be made of copper (Cu). According to this, it is possible to achieve both high thermal conductivity and low cost.

In the present invention, the first and second metal films may be made of titanium (Ti), nickel (Ni) or palladium (Pd). According to this, it is possible to secure high adhesion to electronic parts and the second insulating layer.

In the present invention, the thickness of the third metal film may be thicker than the total thickness of the first and second metal films. According to this, by selecting a material having high thermal conductivity and low cost as the material of the third metal film, it is possible to achieve both high thermal conductivity and low cost. In this case, the thickness of the third metal film may be 3 μm or more. According to this, it is possible to secure a sufficient margin for forming the via hole.

The method for manufacturing an electronic component-embedded substrate according to the present invention prepares an electronic component having a main surface on which terminal electrodes are formed and a back surface located on the opposite side of the main surface, and the back surface is covered with a metal laminate film. The main surface is covered with the first insulating layer on the substrate in which the process and the plurality of wiring layers including the first wiring layer and the plurality of insulating layers including the first and second insulating layers are laminated, and the back surface is covered with the first insulating layer. A step of embedding an electronic component so that the metal is covered with a second insulating layer, a step of exposing a metal laminated film by forming a via hole penetrating the second insulating layer, and a via conductor being formed in the via hole. Thereby, the step of connecting the first wiring layer and the metal laminated film is provided, and the metal laminated film includes a first metal film in contact with the back surface of the electronic component and a second metal in contact with the second insulating layer. The first metal film includes a film and a third metal film located between the first metal film and the second metal film, and the first metal film is a metal having higher adhesion to electronic parts than the third metal film. The second metal film is made of a metal material having a higher adhesion to the second insulating layer than the third metal film, and the step of exposing the metal laminated film penetrates the second metal film. It is characterized in that a via hole is formed, thereby exposing a third metal film.

According to the present invention, since the via hole is formed so as to penetrate the second metal film, it is possible to form the via conductor so as to bite into the third metal film. This makes it possible to prevent the via conductor from peeling due to a temperature change.

The method for manufacturing a substrate with built-in electronic components according to the present invention further includes a step of cleaning the inside of the via hole with a cleaning liquid, and the third metal film may have a higher etching rate with the cleaning liquid than the second metal film. .. According to this, since the diameter of the via conductor in the third metal film can be made larger than the opening diameter of the second metal film, the contact area between the via conductor and the third metal film increases, and both Peeling at the interface of the above is less likely to occur.

As described above, according to the present invention, it is possible to more effectively prevent peeling of the via conductor for heat dissipation in the electronic component built-in substrate in which electronic components such as semiconductor ICs are embedded and the manufacturing method thereof.

FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention. FIG. 2 is a schematic enlarged view of a joint portion between the metal laminated film 50 and the via conductor 35. FIG. 3 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 4 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 5 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 6 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 7 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 8 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 9 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 10 is a process diagram for explaining a method of manufacturing the electronic component built-in substrate 1. FIG. 11 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 12 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 13 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 14 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 15 is a process diagram for explaining a manufacturing method of the electronic component built-in substrate 1. FIG. 16 is a schematic view for explaining the shape of the via hole 85 immediately after the formation. FIG. 17 is a schematic view for explaining the shape of the via hole 85 after the desmear treatment is performed.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view for explaining the structure of the electronic component built-in substrate 1 according to the preferred embodiment of the present invention.

As shown in FIG. 1, the electronic component-embedded substrate 1 according to the present embodiment has four insulating layers 11 to 14, wiring layers L1 to L4 formed on the surfaces of the insulating layers 11 to 14, and wiring layers L2, respectively. An electronic component 40 embedded between the wiring layer L3 and the wiring layer L3 is provided. Although not particularly limited, the insulating layer 11 located at the top layer and the insulating layer 14 located at the bottom layer are core layers in which a core material such as glass fiber is impregnated with a resin material such as glass epoxy. It doesn't matter. On the other hand, the insulating layers 12 and 13 may be made of a resin material that does not contain a core material such as glass cloth. In particular, the coefficient of thermal expansion of the insulating layers 11 and 14 is preferably smaller than the coefficient of thermal expansion of the insulating layers 12 and 13.

The type of the electronic component 40 is not particularly limited, but may be, for example, a semiconductor IC in a bare chip state. In the example shown in FIG. 1, the electronic component 40 is embedded in a face-up manner so that the main surface 42 on which the terminal electrode 41 is formed faces upward. Therefore, the main surface 42 and the side surface 43 of the electronic component 40 are covered with the insulating layer 12, and the back surface 44 of the electronic component 40 is covered with the insulating layer 13 via the metal laminated film 50.

The wiring layer L1 is a wiring layer located at the uppermost layer, and most of the wiring layer L1 is covered with the solder resist 21. A region of the wiring layer L1 that is not covered by the solder resist 21 constitutes an external terminal E1 on which chip components and the like are mounted. The wiring layer L4 is a wiring layer located at the lowest layer, and most of the wiring layer L4 is covered with the solder resist 22. A region of the wiring layer L4 that is not covered by the solder resist 22 constitutes an external terminal E2 that is connected to the motherboard via solder. On the other hand, the wiring layers L2 and L3 are located in the inner layer. Of these, the wiring layer L2 is located between the insulating layer 11 and the insulating layer 12, and the wiring layer L3 is located between the insulating layer 13 and the insulating layer 14. The wiring layer L1 and the wiring layer L2 are connected via the via conductor 31, the wiring layer L2 and the terminal electrode 41 of the electronic component 40 are connected via the via conductor 32, and the wiring layer L2 and the wiring layer L3 are connected via the via conductor. It is connected via 33, and the wiring layer L3 and the wiring layer L4 are connected via the via conductor 34. Further, the wiring layer L4 and the metal laminated film 50 are connected via the via conductor 35. The via conductor 35 constitutes a heat dissipation route for efficiently dissipating heat generated by the operation of the electronic component 40, and is usually given a ground potential. In order to improve heat dissipation efficiency, it is preferable to provide a large number of via conductors 35.

FIG. 2 is a schematic enlarged view of a joint portion between the metal laminated film 50 and the via conductor 35.

As shown in FIG. 2, the metal laminated film 50 has a three-layer structure, and the first metal film 51 forming the surface on the electronic component 40 side and the second metal forming the surface on the insulating layer 13 side. It is composed of a third metal film 53 located between the film 52 and the first and second metal films 51 and 52. The first and second metal films 51 and 52 are made of a metal material having high adhesion such as titanium (Ti), nickel (Ni) and palladium (Pd), and the third metal film 53 is copper (Cu) or the like. It is made of an inexpensive metal material with high thermal conductivity. The specific metal materials constituting these metal films 51 to 53 are not limited to the above-mentioned metal materials, but at least the first metal film 51 has a third metal film having adhesion to the electronic component 40. It needs to be made of a metal material higher than 53, and the second metal film 52 needs to be made of a metal material having a higher adhesion to the insulating layer 13 than the third metal film 53. As a result, the adhesion between the metal laminated film 50 and the electronic component 40 and the insulating layer 13 is enhanced.

Here, when the thicknesses of the metal films 51 to 53 are H1 to H3, respectively, the thickness H3 of the third metal film 53 is the thickness H1 of the first metal film 51 and the thickness H1 of the second metal film 52. It is preferably sufficiently thicker than the thickness H2, and more preferably thicker than the total thickness H1 + H2 of the first and second metal films 51 and 52. In other words
H1 + H2 <H3
Is preferable. This is because the roles of the first and second metal films 51 and 52 are to improve the adhesion to the electronic component 40 and the insulating layer 13, so that it is sufficient to be located only on the surface layer, and it is made of a relatively expensive material. On the other hand, the role of the third metal film 53 is to improve heat dissipation and adhesion to the via conductor 35, and a certain thickness is required.

As shown in FIG. 2, the via conductor 35 is provided so as to penetrate the second metal film 52 and bite into the third metal film 53. The via conductor 35 is preferably made of the same metal material as the third metal film 53, for example, copper (Cu), and the area of the interface between the via conductor 35 is provided so as to bite into the third metal film 53. Is expanding. When the via conductor 35 and the third metal film 53 are made of the same metal material, the interface between the two has high adhesion. Therefore, by expanding the area of this interface, the via conductor 35 and the third metal film 53 can be formed. Peeling at the interface is less likely to occur.

Moreover, in the present embodiment, the diameter W1 of the via conductor 35 in the portion biting into the third metal film 53 is larger than the opening diameter W2 of the second metal film 52, and the end portion of the via conductor has an anchor shape. Have. As a result, the area of the interface between the via conductor 35 and the third metal film 53 is further expanded, so that peeling is less likely to occur. Here, when the distance between the tip of the via conductor 35 and the first metal film 51, that is, the thickness of the third metal film 53 at the portion where the via conductor 35 bites is H3a,
H3a ≧ H3 × 0.1
Is preferable. That is, it is preferable that the via conductor 35 does not penetrate the third metal film 53 and its tip is located in the third metal film 53 without contacting the first metal film 51, and the third metal film 53 is used as a margin thereof. It is preferably 10% or more of the thickness H3 of the metal film 53. This is because if the via conductor 35 penetrates the third metal film 53, the electronic component 40 may be damaged when forming the via hole. Further, in order to sufficiently secure such a margin, it is preferable that the thickness of the third metal film 53 is 3 μm or more.

As described above, in the electronic component built-in substrate 1 according to the present embodiment, the metal laminated film 50 covering the back surface 44 of the electronic component 40 has a three-layer structure, and both sides are made of a metal material having high adhesion. , It is possible to improve the adhesion between the metal laminated film 50 and the electronic component 40 and the insulating layer 13. Moreover, since the via conductor 35 is provided so as to penetrate the second metal film 52 and bite into the third metal film 53, the adhesion between the via conductor 35 and the metal laminated film 50 is also enhanced, and the temperature changes. It is possible to prevent peeling of the interface between the two.

3 to 15 are process diagrams for explaining the manufacturing method of the electronic component built-in substrate 1 according to the present embodiment.

First, as shown in FIG. 3, a base material in which a metal film L3a is formed on one surface of an insulating layer 14 containing a core material such as glass fiber, and a laminated film of metal films L4a and L4b is formed on the other surface. (Workboard) is prepared and attached to a support 70 made of stainless steel or the like via a release layer 71.

Next, as shown in FIG. 4, the wiring layer L3 is formed by patterning the metal film L3a using a photolithography method or the like. Next, as shown in FIG. 5, the insulating layer 13 is formed by laminating, for example, an uncured (B stage state) resin sheet or the like on the surface of the insulating layer 14 by vacuum pressure bonding or the like so as to embed the wiring layer L3. To do.

Next, as shown in FIG. 6, the electronic component 40 on which the metal laminated film 50 is formed is placed on the surface of the insulating layer 13. The electronic component 40 is, for example, a semiconductor IC in a bare chip state, and is mounted in a face-up manner so that the main surface 42 on which the terminal electrode 41 is formed faces upward. Therefore, the metal laminated film 50 is interposed between the back surface 44 of the electronic component 40 and the insulating layer 13.

Next, as shown in FIG. 7, the insulating layer 12 and the metal film L2a are formed so as to cover the electronic component 40. As a result, the main surface 42 and the side surface 43 of the electronic component 40 are covered with the insulating layer 12. The insulating layer 12 is formed, for example, by applying a thermosetting resin in an uncured or semi-cured state, heating the uncured resin to semi-cure it, and further using a pressing means together with the metal film L2a. Curing molding is preferable. As the insulating layer 12, a resin sheet that does not contain fibers that hinder the embedding of the electronic component 40 is desirable.

Next, as shown in FIG. 8, after removing a part of the metal film L2a by etching using a known method such as a photolithography method, a known laser is applied to a predetermined portion from which the metal film L2a has been removed. Via holes 82 and 83 are formed by processing and blasting. Of these, the via hole 83 is provided so as to penetrate the insulating layers 12 and 13, and the wiring layer L3 is exposed at the bottom of the via hole 83. Further, the via hole 82 exposes the terminal electrode 41 of the electronic component 40.

Next, as shown in FIG. 9, by performing electroless plating and electrolytic plating, a metal film L2b is formed on the surface of the insulating layer 12, and via conductors 32 and 33 are formed inside the via holes 82 and 83, respectively. To do. Then, as shown in FIG. 10, the wiring layer L2 is formed by patterning the metal film L2b using a photolithography method or the like.

Next, as shown in FIG. 11, a sheet in which the insulating layer 11 and the metal films L1a and L1b are laminated is vacuum-heat pressed so as to embed the wiring layer L2. The material and thickness used for the insulating layer 11 may be the same as that of the insulating layer 14. Next, as shown in FIG. 12, the substrate is separated from the support 70 by peeling off the interface between the metal films L1a and L1b and peeling off the interface between the metal films L4a and L4b.

Next, as shown in FIG. 13, after a part of the metal films L1a and L4a is removed by etching using a known method such as a photolithography method, the metal films L1a and L4a are removed from the predetermined portion. By performing the known laser processing and blast processing, the via hole 81 is formed in the insulating layer 11, the via hole 84 is formed in the insulating layer 14, and the via hole 85 is formed in the insulating layers 14 and 13. The via hole 81 is provided so as to penetrate the insulating layer 11, and the wiring layer L2 is exposed at the bottom of the via hole 81. Further, the via hole 84 is provided so as to penetrate the insulating layer 14, and the wiring layer L3 is exposed at the bottom of the via hole 84. Further, the via hole 85 is provided so as to penetrate the insulating layers 14 and 13, and the metal laminated film 50 is exposed at the bottom of the via hole 85.

In the formation of the via hole 85, a slight overetching is performed so that the metal laminated film 50 is surely exposed on the bottom thereof. Here, since the thickness of the second metal film 52 constituting the surface layer of the metal laminated film 50 is thin, the via hole 85 penetrates the second metal film 52 and is formed at the bottom thereof, as shown in FIG. The third metal film 53 is exposed. At this point, the diameter of the overetched region is W2 for both the second and third metal films 52 and 53.

After the via hole 85 is formed, a desmear treatment is performed to clean the inside of the via hole 85 with a cleaning liquid. Since the cleaning liquid used for the desmear treatment contains an acid, the metal laminated film 50 exposed at the bottom of the via hole 85 is slightly etched when the desmear treatment is performed. Here, the metal material having high adhesion used for the first and second metal films 51 and 52 has a lower etching rate with respect to acid than the metal material such as copper (Cu) used for the third metal film 53. Therefore, the third metal film 53 having a high etching rate is eroded more quickly, and the bottom of the via hole 85 expands like a mushroom, as shown in FIG. That is, when the desmear treatment is performed, the diameter of the via hole 85 remains almost W2 at the portion penetrating the second metal film 52, but expands to W1 at the portion biting into the third metal film 53. ..

Next, as shown in FIG. 14, by performing electroless plating and electrolytic plating, metal films L1c and L4c are formed on the surfaces of the insulating layers 11 and 14, respectively, and the insides of the via holes 81, 84 and 85, respectively. Via conductors 31, 34, 35 are formed. As a result, the via conductor 31 is in contact with the wiring layer L2, the via conductor 34 is in contact with the wiring layer L3, and the via conductor 35 is in contact with the metal laminated film 50. The shape of the tip of the via conductor 35 is as described with reference to FIG. 2, and has a shape that bites into the third metal film 53 in an anchor shape. Then, as shown in FIG. 15, the wiring layers L1 and L4 are formed by patterning the metal films L1c and L4c by using a photolithography method or the like.

Then, if solder resists 21 and 22 are formed on the surfaces of the insulating layers 11 and 14, respectively, the electronic component-embedded substrate 1 shown in FIG. 1 is completed.

As described above, in the present embodiment, after the opening is formed in the second metal film 52 by overetching when forming the via hole 85, the third metal film 53 is mushroomed with the acid used for the desmear treatment. Since it is etched in a shape, the tip of the via conductor 35 can be made to bite into the third metal film 53 in an anchor shape.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention, and these are also the present invention. It goes without saying that it is included in the range.

1 Substrate with built-in electronic components 11-14 Insulation layer 21,22 Solder resist 31-35 Via conductor 40 Electronic component 41 Terminal electrode 42 Main surface 43 Side surface 44 Back surface 50 Metal laminated film 51 First metal film 52 Second metal film 53 Third metal film 70 Support 71 Peeling layer 81-85 Via holes E1, E2 External terminals L1 to L4 Wiring layers L1a to L1c, L2a, L2b, L3a, L4a to L4c Metal film

Claims (10)

A substrate formed by laminating a plurality of wiring layers including a first wiring layer and a plurality of insulating layers including the first and second insulating layers.
It has a main surface on which terminal electrodes are formed and a back surface located on the opposite side of the main surface and covered with a metal laminated film. The main surface is covered with the first insulating layer, and the back surface is covered with the first insulating layer. An electronic component embedded in the substrate so as to be covered with the second insulating layer,
A via conductor provided so as to penetrate the second insulating layer and connecting the first wiring layer and the metal laminated film is provided.
The metal laminated film includes a first metal film in contact with the back surface of the electronic component, a second metal film in contact with the second insulating layer, the first metal film, and the second metal film. Including a third metal film located between
The first metal film is made of a metal material having a higher adhesion to the electronic component than the third metal film.
The second metal film is made of a metal material having a higher adhesion to the second insulating layer than the third metal film.
The via conductor is a substrate with built-in electronic components, which penetrates the second metal film and bites into the third metal film. The electronic component built-in substrate according to claim 1, wherein the end portion of the via conductor is located in the third metal film without being in contact with the first metal film. The electronic component-embedded substrate according to claim 1 or 2, wherein the diameter of the via conductor in the third metal film is larger than the opening diameter of the second metal film. The electronic component-embedded substrate according to any one of claims 1 to 3, wherein the third metal film and the via conductor are made of the same metal material. The electronic component built-in substrate according to claim 4, wherein both the third metal film and the via conductor are made of copper (Cu). The electronic component built-in substrate according to any one of claims 1 to 5, wherein the first and second metal films are made of titanium (Ti), nickel (Ni) or palladium (Pd). The electronic component-embedded substrate according to any one of claims 1 to 6, wherein the thickness of the third metal film is thicker than the total thickness of the first and second metal films. The substrate for incorporating electronic components according to claim 7, wherein the thickness of the third metal film is 3 μm or more. A step of preparing an electronic component having a main surface on which a terminal electrode is formed and a back surface located on the opposite side of the main surface and the back surface of which is covered with a metal laminated film.
The main surface is covered with the first insulating layer on a substrate in which a plurality of wiring layers including the first wiring layer and a plurality of insulating layers including the first and second insulating layers are laminated. The step of embedding the electronic component so that the back surface is covered with the second insulating layer,
A step of exposing the metal laminated film by forming a via hole penetrating the second insulating layer, and
A step of connecting the first wiring layer and the metal laminated film by forming a via conductor in the via hole is provided.
The metal laminated film includes a first metal film in contact with the back surface of the electronic component, a second metal film in contact with the second insulating layer, the first metal film, and the second metal film. Including a third metal film located between
The first metal film is made of a metal material having a higher adhesion to the electronic component than the third metal film.
The second metal film is made of a metal material having a higher adhesion to the second insulating layer than the third metal film.
The step of exposing the metal laminated film is a method for manufacturing an electronic component-embedded substrate, which comprises forming the via hole so as to penetrate the second metal film, thereby exposing the third metal film. A step of cleaning the inside of the via hole with a cleaning liquid is further provided.
The method for manufacturing an electronic component-embedded substrate according to claim 9, wherein the third metal film has a higher etching rate by the cleaning liquid than the second metal film.

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