JP2020188206A - Vertical resonator type surface light-emitting element - Google Patents

Abstract

To provide a vertical resonator type surface light-emitting element for enabling high current injection and high output operation at a low threshold and with high slope efficiency.SOLUTION: A vertical resonator type surface light-emitting element includes a c plane GAN substrate 11 having an off angle, a semiconductor DBR 12 formed on the substrate, a group III nitride semiconductor device layer 22, and a dielectric DBR 27. The device layer comprises: a first semiconductor layer 13, an active layer 15 and a second semiconductor layer 17; a tunnel junction mesa 18 composed of a second conductive type high impurity concentration semiconductor layer 18A and a first conductive type high impurity concentration semiconductor layer 18B sequentially formed on the second semiconductor layer 17; and a semiconductor embedded layer 19. Here, the height H of the tunnel junction mesa, the layer thickness TH of the semiconductor embedded layer, and the thickness layer TB of the first conductive type high impurity concentration semiconductor layer satisfy TB≤H<TH/20, and when the resonance wavelength of a DBR resonator is regarded as λc, an effective refractive index in the resonator as neff, 1.75λc/neff≤TH≤18.75λc/neff is satisfied.SELECTED DRAWING: Figure 1

Description

The present invention relates to a vertical resonator type surface emitting element, particularly a vertical resonator type surface emitting laser.

Conventionally, there is known a Vertical Cavity Surface Emitting Laser (VCSEL) configured to include a pair of reflectors (resonators) above and below the active layer (light emitting layer).

For example, Patent Document 1 uses a current constriction structure having an insulating transparent electrode having a resonator composed of a semiconductor DBR (Distributed Bragg Reflector) and a dielectric DBR, provided under the dielectric DBR, and having an opening. The VCSEL of the nitride-based semiconductor material that has been used is disclosed.

Further, Patent Document 2 discloses a VCSEL having a tunnel junction, in which a tunnel junction having a mesa structure is embedded with a semiconductor layer and a current flows only through the tunnel junction when a reverse bias is applied. There is.

Further, Non-Patent Document 1 discloses the relationship between the substrate off angle and the surface morphology in GaN homoepitaxial growth.

JP-A-2018-098347 JP-A-2017-0921558

Proceedings of the 65th JSAP Spring Meeting (19a-C302-11), 2018

However, in the current constriction structure using the insulating transparent electrode, since the absorption coefficient of the material (ITO or the like) used for the transparent electrode is high, it is necessary to use a thin film, and the sheet resistance of the transparent electrode portion is high. Further, there is a problem in reliability, such as the film thickness tends to be thinned locally near the step of the opening, and a failure such as non-lighting due to disconnection is likely to occur at the time of high current injection (high output).

Further, if the reflectors (DBRs) constituting the resonator are not formed in parallel, the scattering loss increases, and problems such as an increase in the threshold current and a decrease in the slope efficiency occur. In the current constriction structure, there is a problem that the dielectric DBR is bent at a step at the end of the opening of the insulating film and the reflectance is lowered.

Further, in the current constriction structure using the embedded tunnel junction, a convex portion (step) is formed on the upper surface of the semiconductor laminated structure, and it is difficult to form a dielectric DBR having high reflection performance on the convex portion (step).

Ideally, a flat reflector (DBR) is formed in a sufficiently wide range with respect to the light emitting region, but in the prior art, the region where the dielectric DBR is flat and has high reflectance is equivalent to the current constriction region. There is a problem that scattering loss is likely to occur because of the following.

The present invention has been made in view of the above points, and has a tunnel junction semiconductor light emitting structure layer having an extremely flat surface and a DBR on the semiconductor light emitting structure layer, and has a low threshold value, high slope efficiency, and high current. It is an object of the present invention to provide a vertical resonator type surface emitting device having high light emitting performance capable of injection (high output) operation.

The vertical resonator type surface emitting device according to one embodiment of the present invention is
A GaN substrate whose surface is a c-plane having an off-angle and
A semiconductor DBR (Distributed Bragg Reflector) formed on the GaN substrate and
A device layer made of a group III nitride semiconductor formed on the semiconductor DBR and
The dielectric DBR formed on the device layer and
Have,
The device layer is
A first conductive type first semiconductor layer, an active layer, and a second conductive type second semiconductor layer which is a conductive type opposite to the first conductive type are formed on the semiconductor DBR in this order. With the light emitting structure layer
A mesa-shaped tunnel junction mesa including a tunnel junction region of a tunnel junction layer composed of a second conductive type high impurity concentration semiconductor layer and a first conductive type high impurity concentration semiconductor layer formed in this order on the second semiconductor layer. When,
It is composed of a semiconductor embedded layer formed on the second semiconductor layer so as to embed the tunnel junction mesa.
When the height of the tunnel junction mesa is H, the layer thickness of the high impurity concentration semiconductor layer of the first conductive type is TB, and the layer thickness of the semiconductor embedded layer is TH.
Satisfy TB <H <TH / 20 and
When the resonance wavelength of the resonator formed by the semiconductor DBR and the dielectric DBR is λc and the effective refractive index in the resonator is n _eff
1.75λc / n _eff ≤ TH ≤ 18.75λc / n _eff
Meet.

It is sectional drawing which shows typically the structure of the vertical resonator type surface light emitting element 10 by one Embodiment of this invention. It is an AFM image which shows the surface of the region just above a mesa. It is sectional drawing which shows typically the embedding process in the manufacturing method of the vertical resonator type surface light emitting element 10. It is sectional drawing which shows typically the embedding process in the manufacturing method of the vertical resonator type surface light emitting element 10. It is sectional drawing which shows typically the embedding process in the manufacturing method of the vertical resonator type surface light emitting element 10. It is sectional drawing which shows typically the embedding process in the manufacturing method of the vertical resonator type surface light emitting element 10. It is a figure which shows the mesa height dependence of the surface state of the embedding layer 19. The actual measurement result which shows the presence or absence of the inclined surface on the surface of the embedding layer 19 is shown. FIG. 5 is a cross-sectional view showing another example of the relationship between the height H of the tunnel junction mesa MS and the layer thickness of the p ⁺ −GaInN layer 18A and the n ⁺ −GaN layer 18B. FIG. 5 is a cross-sectional view showing another example of the relationship between the height H of the tunnel junction mesa MS and the layer thickness of the p ⁺ −GaInN layer 18A and the n ⁺ −GaN layer 18B. It is a figure which shows the EL spectrum in the room temperature CW operation of a vertical resonator type surface light emitting element 10. It is a figure which shows the optical output-current characteristic in room temperature CW operation of a vertical resonator type surface light emitting element 10.

Hereinafter, preferred examples of the present invention will be described, but these may be appropriately modified and combined. Further, in the following description and the accompanying drawings, substantially the same or equivalent parts will be described with the same reference numerals.
[Structure of semiconductor light emitting device]
FIG. 1 is a cross-sectional view schematically showing the structure of a vertical resonator type surface emitting device 10 according to one embodiment of the present invention. An example of the structure of the vertical resonator type surface emitting device 10 will be described with reference to FIG.

Specifically, the vertical resonator type surface emitting device 10 has a GaN substrate 11 having a c-plane having an off-angle surface and a buffer layer formed on the c-plane GaN substrate 11 having the off-angle (not shown). ) And a semiconductor DBR (Distributed Bragg Reflector) 12. The semiconductor DBR12 may be undoped or may have a first conductive type.

An active layer (light emitting layer) 15 is formed on the n-GaN layer 13 (first semiconductor layer) and the n-GaN layer 13 on the semiconductor DBR 12, and a p-AlGaN electron block layer is formed on the active layer 15. A semiconductor layer 17 (second semiconductor layer) composed of 17A and a p-GaN layer 17B is formed. The first semiconductor layer may contain AlGaN or GaInN, AlInN, or a superlattice structure thereof. Further, GaN, GaInN, AlGaN, and their superlattice structures may be contained between the active layer 15 and the p-AlGaN electron block layer 17A. Here, the layer composed of the first semiconductor layer 13, the active layer 15, and the second semiconductor layer 17 is referred to as a light emitting structure layer 21. The first semiconductor layer 13 and the second semiconductor layer 17 may include an undoped layer or an intrinsic semiconductor layer (i layer), respectively.

A tunnel junction layer 18 (hereinafter, also referred to as a tunnel junction mesa MS) having a cylindrical mesa structure is formed on the p-GaN layer 17B. The tunnel junction layer 18 includes a p ⁺ −GaInN layer (second conductive type high impurity concentration semiconductor layer: layer thickness TA, first high impurity concentration semiconductor layer) 18A formed on the p-GaN layer 17B, and p. It includes an n ⁺ -GaN layer 18B (first conductive type high impurity concentration semiconductor layer: layer thickness TB, second high impurity concentration semiconductor layer) formed on the ⁺ −GaInN layer 18A. The first conductive type high impurity concentration semiconductor layer may be n ⁺ −GaInN or n ⁺ − AlGaN, and may have an In composition and an Al composition inclination (composition inclination). Further, the second conductive type high impurity concentration semiconductor layer may be p ⁺ −GaN or p ⁺ −AlGaN, and may have an In composition and an Al composition inclination (composition inclination).

An n-GaN embedded layer 19 is formed on the p-GaN layer 17B so as to embed the tunnel junction layer 18 having a mesa structure. The n-GaN embedded layer 19 may be n-AlInN and n-AlGaN, or a superlattice structure thereof from the viewpoint of lateral light confinement. Here, the device structure layer composed of the light emitting structure layer 21, the tunnel junction layer 18 having a mesa structure, and the embedded layer 19 is referred to as a device layer 22.

The device layer 22 is formed as a mesa-shaped device structure semiconductor layer that reaches into the n-GaN layer 13 from the surface of the embedded layer 19 and stands up (protrudes) perpendicularly to the GaN substrate 11. The device layer 22 is a cylindrical mesa (hereinafter referred to as a device mesa DM) having an axis perpendicular to the GaN substrate 11 as a central axis CX.

The side surface and the upper surface of the mesa-shaped device layer 22 are covered with an insulator 25 such as SiO ₂ . The insulator 25 has a circular opening 25A on the upper surface of the device layer 22, which is a central region of the opening 25A, and a cylindrical dielectric DBR27 is formed on the n-GaN embedded layer 19.

In the gap between the opening 25A of the insulator 25 and the dielectric DBR27 (outer peripheral region of the opening 25A), a p-side electrode (second electrode) 26 which is annularly contacted with the n-GaN embedded layer 19 is provided. It is formed. The distance between the p-side electrode 26 and the tunnel junction mesa MS as seen from the upper surface of the vertical resonator type surface emitting device 10 is better from the viewpoint of lateral resistance in the n-GaN embedded layer 19, and is 5 μm or less. preferable.

On the flat portion of the n-GaN layer 13, an n-side electrode (first electrode) 14 in which the n-GaN layer 13 is annularly contacted is formed. When the first conductive type semiconductor DBR 12 is used, even if the n-side electrode in circular contact is formed on the back surface side of the GaN substrate 11 (the side opposite to the side on which the semiconductor DBR is formed). Good.

The tunnel junction layer 18 and the dielectric DBR 27 are formed so as to be coaxial with the axis perpendicular to the GaN substrate 11 as the central axis. Preferably, the tunnel junction layer 18 and the dielectric DBR 27 are formed so as to be coaxial with the central axis CX of the device layer 22.

Further, it is preferable that the n-side electrode 14 (first electrode) and the p-side electrode (second electrode) 26 are formed so as to be coaxial with the central axis CX of the device layer 22 (device mesa DM). ..

Here, the cylindrical shape or the annular shape includes the case where the elliptical pillar shape or the elliptical ring shape or the like is used.
[Manufacturing method of vertical resonator type surface emitting element]
An example of a method for manufacturing the vertical resonator type surface emitting device 10 according to one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

The vertical resonator type surface emitting element 10 of the embodiment is a VCSEL (BTJ-VCSEL) element having a Burried Tunnel Junction structure having an oscillation wavelength (λc) of 410 nm and a resonator length of 5.5λ. The case will be described, but it goes without saying that various sizes such as oscillation wavelength, resonator length, layer thickness and diameter, conductive type, and element parameters such as impurities and impurity concentration are merely examples and can be appropriately modified and applied. Yes.

Further, a case where the organic metal vapor phase growth method (MOCVD method) is used for the growth of each semiconductor layer will be described. The crystal plane, crystal orientation, etc. of the substrate and the growth layer include the equivalent plane, the equivalent orientation, and the like.
(First step)
An undoped GaN buffer layer is grown on a c-plane GaN substrate 11 having an off angle of 0.4 ° in the (-1100) direction, that is, the m-axis direction, and a semiconductor DBR12 composed of 40 pairs of AlInN / GaN is grown on the layer.

Next, on the semiconductor DBR12, an n-GaN layer 13 (layer thickness 425 nm), an active layer 15 having a quantum well (QW) structure, and a p-Al _0.2 Ga _0.8 N electron block layer (EBL: Electron) are sequentially applied. Blocking Layer) 17A (layer thickness 20 nm) and p-GaN layer 17B (layer thickness 70 nm) are grown. The active layer 15 includes, for example, five GaInN quantum well layers and a GaN barrier layer alternately formed with the quantum well layers.

The p-GaN layer 17B includes p ⁺ -Ga _0.65 In _0.35 N layer 18A (layer thickness TA: 2 nm, Mg doping concentration: 2 × 10 ²⁰ cm ^-3 ) and n ⁺ -GaN layer 18B (layer). A tunnel junction layer 18 containing a thickness TB: 5 nm and a Si doping concentration: 6 × 10 ²⁰ cm ^-3 ) is grown.
(Second step)
A tunnel junction mesa MS for performing current constriction is formed on a substrate (a substrate with a growth layer) in which the above layers are grown. That is, first, a circular SiO ₂ mask having a diameter of 6 to 10 μm is formed by patterning on a substrate with a growth layer by using photolithography and an ion beam deposition method (EB).

Next, for example, a portion outside the SiO ₂ mask is etched with chlorine (Cl ₂ ) gas to form a cylindrical mesa (tunnel junction mesa MS). The etching ^depth, n + -GaN layer 18B thickness of ⁿ + -GaN layer 18B which can partition the removal (TB: 5 nm) is greater than the depth. For example, the surface of the n ⁺ −GaN layer 18B is etched to a depth of 7 nm to form a tunnel junction mesa MS having a height H of 7 nm.

By this etching, the p-GaN layer 17B is exposed outside the tunnel junction mesa MS. Finally, the SiO ₂ mask is peeled off with a hydrofluoric acid (HF) solution to form a cylindrical tunnel junction mesa MS having a diameter of 6 to 10 μm.
(Third step)
Embedded growth is performed on the substrate on which the tunnel junction mesa MS is formed. The formation of the n-GaN embedded layer 19 consists of two steps.

More specifically, the substrate on which the tunnel junction mesa MS was formed was set in a MOCVD reaction furnace, heated to 725 ° C. in an NH ₃ and nitrogen (N ₂ ) atmosphere, and n-GaN was grown by 10 nm at that temperature. (Low temperature growth n-GaN). The Si doping concentration at this time is 2 × 10 ¹⁸ cm ^-3 .

By growing the low-temperature growth n-GaN (LT-nGaN) having a low Si concentration, the next high-temperature embedded growth can be performed while protecting the tunnel junction and without roughening the surface.

Next, the temperature is raised to 1080 ° C. in an atmosphere of NH ₃ and hydrogen (H ₂ ), and n-GaN is grown by 270 nm at that temperature (high temperature growth n-GaN, HT-nGaN). The Si doping concentration at this time is 1 × 10 ¹⁹ cm ^-3 . At this point, the region directly above the mesa is a surface having only a step of 5 nm or less with respect to the outside of the region (outer peripheral portion), and the steps are clearly shown as shown in the AFM (atomic force microscope) image of FIG. It has an atomically flat surface that can be seen.
(4th step)
An element structure that operates as a surface emitting laser is formed on a substrate that has finished growing. First, a mesa (device mesa DM) having a diameter 30 μm larger than that of the tunnel junction mesa MS is formed by photolithography and dry etching using Cl ₂ gas. Dry etching is performed until the n-GaN layer 13 is exposed.

Next, 725 ° C. The substrate with the device mesa DM in an _{N 2} atmosphere, annealing is performed for 30 minutes. As a result, H is desorbed from the side wall of the mesa to activate Mg in the p-AlGaN layer 17A, the p-GaN layer 17B, and the p ⁺ -GaInN layer 18A.

Next, a SiO ₂ insulating film having a layer thickness of 250 nm is formed by a sputtering method, and a circular opening 25A extending from the end of the device mesa DM to the inside by 5 μm is formed by lift-off.

Next, the ring-shaped p-side electrode 26 and n-side electrode 14 are formed by an ion beam vapor deposition method. The p-side electrode 26 and the n-side electrode 14 are formed by, for example, depositing Cr / Ni / Au in this order.

Finally, a dielectric DBR27 composed of 8 pairs of SiO ₂ / Nb ₂ O ₅ is formed in the opening 25A directly above the tunnel junction mesa MS by a sputtering method.
[Formation of an embedded layer with a flat surface]
As described above, the present invention has been devised in order to reduce the scattering loss due to the surface convex portion after the embedded growth, which has been a factor that hinders the oscillation of the embedded tunnel junction VCSEL.

According to an embodiment of the present invention, using a tunnel junction mesa MS including a tunnel junction of height H formed on a c-plane GaN substrate having an off angle, embedded growth is performed so that step flow growth occurs preferentially. It is possible to obtain a flat surface in which the embedded growth surface is atomically flat and no protrusions due to the tunnel junction mesa MS remain. As a result, the dielectric DBR formed on the embedded growth surface is not curved, and the scattering loss can be reduced. The details will be described below.
(1) Relationship between Mesa Height H and Embedded Thickness TH FIG. 3A-3D is a cross-sectional view schematically showing an embedding process in a method for manufacturing a vertical resonator type surface light emitting element 10.

As shown in FIG. 3A, the tunnel junction mesa MS has a diameter D and a height H. The surface of the tunnel junction mesa MS has an off-angle θ ([STEP1]).

As shown in FIG. 3B, when embedded growth is performed by regrowth, step flow growth (lateral growth mode) occurs at the growth rate of R _s inside and outside the Mesa MS due to the off-angle in the substrate, and the growth film thickness is increased. In the direction (vertical direction of the substrate), it grows at the growth rate of R _ver ([STEP2]).

As shown in FIG. 3C, the inside of the surface of the mesa MS is a “closed area” in which steps do not extend from outside the mesa MS, and growth proceeds until there are no steps inside the mesa surface, so-called “steps”. A "free surface" SF is formed.

Once the step-free surface is formed, growth occurs only in the c-axis direction, that is, in the direction perpendicular to the step-free surface SF. That is, the growth rate R ^sf _ver in the growth film thickness direction is much smaller than that of R _ver . Under this circumstance, step flow growth continues to progress outside of Mesa MS, gradually covering the step-free side ([STEP3]).

Finally, as shown in FIG. 3D, the step-free surface is completely covered with the outer layer of the mesa and flattened ([STEP4]).

When the growth rate difference between the inside and outside of the mesa MS is large (R _ver >> R ^sf _ver ), the growth layer outside the mesa catches up with the growth layer on the mesa, but when the R _ver is large, that is, the frequency of two-dimensional nucleation. Will be high, and ideal step flow growth will be difficult. As a result, the surface becomes rough, which is not suitable for forming a dielectric DBR having a high reflectance.

In order to allow the growth layer outside the mesa to catch up with the growth layer on the mesa at an early stage within the desired resonator length without changing the R _ver , the mesa height H may be reduced. By reducing the mesa height H, the growth covering the step-free surface is started when the mesa height H grows, and the step-free surface can be embedded at an early stage.

Actually, the mesa height dependence of the surface state of the embedded layer 19 when the off-angle θ = 0.4 °, D = 10 μm, and TH = 280 nm (corresponding to 1.75λ with an oscillation wavelength of 410 nm) is shown in FIG. Shown in.

In FIG. 4, the cross-sectional profile of the surface of the embedded layer 19 is shown in the upper row, and the laser microscope image of the surface of the embedded layer 19 is shown in the lower row. Further, on the right side of the lower row, an illustration in which the end positions of the Mesa MS and the cross section of the Mesa MS are schematically drawn by broken lines is shown.

More specifically, the cases where the mesa height H is (a) 6.7 nm, (b) 10.1 nm, (c) 25.9 nm, and (d) 81.2 nm are shown, and are shown in the upper cross-sectional profile. As described above, in each case, the step at the surface position corresponding to the upper part of the end of the mesa MS was (a) below the measurement limit, (b) 5 nm, (c) 13 nm, and (d) 15 nm. ..

From FIG. 4, it can be seen that by reducing the mesa height H, it becomes easier to obtain an embedded surface in which the inclined surface derived from the step-free surface does not remain. More specifically, it is necessary to set the mesa height to satisfy the following conditions.

Further, FIG. 5 shows the actual measurement results of examining the presence or absence of an inclined surface on the surface of the embedded layer 19 with respect to the mesa diameter D, the mesa height H, the embedded layer thickness TH, and the ratio of TH to H (TH / H). Is. As described above, as a result of diligent studies, the mesa height H (nm) must satisfy the following conditions in order to obtain an embedded surface in which the inclined surface derived from the step-free surface does not remain. The layer thickness of the n ⁺ −GaN layer 18B is TB.

TB <H <TH / 20 ... (Equation 1)
(2) Mesa height H
In the case shown in FIG. 1, p ⁺ −GaInN layer 18A (second conductive type high impurity concentration semiconductor layer: layer thickness TA) and n ⁺ −GaN layer 18B (first conductive type) outside the tunnel junction mesa MS. The high impurity concentration semiconductor layer of the mold: layer thickness TB) is removed to the outermost surface of the p-GaN layer 17B. That is, the case where the height H of the tunnel junction mesa MS is H = TA + TB is shown.

However, the height H of the tunnel junction mesa MS may be set within the range satisfying the above (Equation 1). For example, as shown in the cross-sectional view of FIG. 5, on the outside of the tunnel junction mesa MS, the p ⁺ −GaInN layer 18A, the n ⁺ −GaN layer 18B, and the p-GaN layer 17B are formed up to the inside of the p-GaN layer 17B. The tunnel junction mesa MS may be formed so as to have the removed height. In this case, the tunnel junction mesa MS includes a part of the second semiconductor layer 17 (p-GaN layer 17B) and protrudes from the second semiconductor layer 17. The height H of the tunnel junction mesa MS is H> TA + TB.

Further, as shown in the sectional view of FIG. ^7, p + -GaInN layer 18A is a removed halfway, i.e. be formed tunnel junction mesa MS as well ^p + -GaInN layer 18A on the outer side of the mesa MS remains Good. That is, at least the tunnel junction region of the tunnel junction layer 18 (the interface region or the depletion layer of the p ⁺ −GaInN layer 18A and the n ⁺ −GaN layer 18B) may be included in the tunnel junction mesa MS. In this case, the height H of the tunnel junction mesa MS is TB <H <TA + TB.
(3) Embedded film thickness TH
The embedded layer thickness is determined by the desired cavity length. Although the diffraction loss increases as the cavity length increases, the thermal resistance can be expected to decrease. It was found that the effect of reducing the thermal resistance is saturated when the cavity length is about 15λ. Further, if the embedded layer thickness (resonator length) is too large, mode hopping (longitudinal mode) is likely to occur. From the mode spacing, the overall resonator length was estimated to be up to 20λ (mode spacing is 10 nm (less than 1/2 of the DBR bandwidth). Semiconductor DBR12 to p ^{+ − to} the center of the GaInN layer 18A. Since the resonator length is at least 1.25λ (the minimum resonator length of the entire resonator is 3λ), the embedded film thickness TH (nm) must satisfy the following conditions.

When the resonance wavelength (or oscillation wavelength) [lambda] c, the effective refractive index in the resonator was set to n _eff,
1.75λc / n _eff ≤ TH ≤ 18.75λc / n _eff ... (Equation 2)
It is preferable to satisfy.
(4) Off angle θ
In the nitride VCSEL, it is important that the surface of the epi layer is atomically flat in order to form a dielectric DBR that requires high reflectance on the surface of the epi layer. The range of off-angles at which good morphology can be obtained on a c-plane GaN substrate is reported in Non-Patent Document 1 described above. A flat epilayer surface can be achieved by encouraging step-flow growth in growth on substrates with off-angles. In the present invention, the off angle θ is in the following range.

0.3 ° ≤ θ ≤ 0.7 ° ・ ・ ・ (Equation 3)
Further, the off angle θ is preferably an angle with respect to the m-axis direction or the a-axis direction.
(5) Mesa diameter D
Transverse mode single mode oscillation is desirable in consideration of coupling efficiency with optical components during application. In general, increasing the lateral light confinement and the current injection diameter promotes multimode oscillation. In order to oscillate in a single mode for a nitride-based VCSEL having a waveguide structure (0 ≦ d (n _eff ) ≦ 0.01, where d is a refractive index difference), the diameter D of the tunnel junction mesa MS is 10 μm or less. , Preferably 6 μm or less.

Further, considering that the diffraction loss becomes large when the diameter D of the mesa MS is too small, the lower limit is about 3 μm. Therefore, it is preferable to satisfy 3 μm ≦ D ≦ 10 μm, and more preferably 3 μm ≦ D ≦ 6 μm.

When the tunnel junction mesa MS has an elliptical column shape, its major axis may be D.
[Flatness of the surface of the embedded layer 19]
Again, referring to FIG. 2, the surface of the embedded layer 19 in the region directly above the mesa MS is an atomically flat surface where the steps are clearly visible. In other words, the surface of the region directly above the mesa MS had a flatness exhibiting a morphology with step-and-terrace periodicity. As shown in FIG. 2, it was confirmed that the traveling direction of the striped step was the m-axis direction.

When the ideal value of Ra (arithmetic mean roughness) of step and terrace was calculated from the height of one atom of the step of GaN (0.25 nm), it was Ra = 0.06 nm. Therefore, the lower limit of Ra is 0.06 nm.

Further, when Ra becomes 1.2 nm or more, the scattering loss of the dielectric DBR becomes 25 cm ^-1 or more, and oscillation becomes impossible. When the scattering loss of the dielectric DBR is 2 cm ^-1 or less, which is 5% or less of the loss in the resonator, Ra is preferably 0.3 nm or less.

That is, the value of Ra on the surface of the embedded layer 19 at least in the region directly above the mesa MS is preferably 0.06 ≦ Ra ≦ 0.3 nm.

As shown in FIG. 2, Ra on the surface of the embedded layer 19 produced by the above-mentioned production method was 0.07 nm, and it was confirmed that an extremely flat growth surface was obtained.
[Device characteristics]
FIG. 8 shows an EL spectrum of the vertical resonator type surface emitting device 10 manufactured by the above configuration and manufacturing method in room temperature CW operation, and FIG. 9 shows an optical output-current characteristic.

It can be seen from the EL spectrum of FIG. 8 that a spectrum having a narrow line width is obtained. A small peak is seen on the short wavelength side of the main peak, which is due to the bias of the current injection based on the electrode of the prepared sample, and can be improved to a complete single mode.

Further, from the optical output-current characteristics of FIG. 9, it can be seen that a clear rise in optical output and high optical output are obtained when the mesa diameter is 6 μm to 10 μm.

As described above, according to the present invention, a vertical resonator type surface emission having a tunnel-junction semiconductor light emitting structure layer having an extremely flat surface and a DBR formed on the flat surface of the semiconductor light emitting structure layer. The element is provided. Therefore, a vertical resonator type surface emitting device having high light emitting performance capable of low threshold value, high slope efficiency, high current injection, and high output operation is provided.

10 Vertical resonator type surface light emitting element 11 Substrate 12 Semiconductor DBR
13 n-GaN layer (first semiconductor layer)
15 Active layer 17 Second semiconductor layer 17A Electronic block layer 17B p-GaN layer 18 Tunnel junction layer 18A p ⁺ -GaInN layer 18B n ⁺ -GaN layer 19 n-GaN embedded layer 22 Device layer 25 Insulator 27 Dielectric DBR
MS tunnel junction mesa

Claims (7)

A GaN substrate whose surface is a c-plane having an off-angle and
A semiconductor DBR (Distributed Bragg Reflector) formed on the GaN substrate and
A device layer made of a group III nitride semiconductor formed on the semiconductor DBR and
The dielectric DBR formed on the device layer and
Have,
The device layer is
A first conductive type first semiconductor layer, an active layer, and a second conductive type second semiconductor layer which is a conductive type opposite to the first conductive type are formed on the semiconductor DBR in this order. With the light emitting structure layer
A mesa-shaped tunnel junction mesa including a tunnel junction region of a tunnel junction layer composed of a second conductive type high impurity concentration semiconductor layer and a first conductive type high impurity concentration semiconductor layer formed in this order on the second semiconductor layer. When,
It is composed of a semiconductor embedded layer formed on the second semiconductor layer so as to embed the tunnel junction mesa.
When the height of the tunnel junction mesa is H, the layer thickness of the high impurity concentration semiconductor layer of the first conductive type is TB, and the layer thickness of the semiconductor embedded layer is TH.
Satisfy TB <H <TH / 20 and
When the resonance wavelength of the resonator formed by the semiconductor DBR and the dielectric DBR is λc and the effective refractive index in the resonator is n _eff
1.75λc / n _eff ≤ TH ≤ 18.75λc / n _eff
Vertical resonator type surface emitting device that satisfies the above conditions. The vertical resonator type surface emitting device according to claim 1, wherein at least the surface of the semiconductor embedded layer immediately above the tunnel junction mesa exhibits a morphology having a step-and-terrace-like periodicity. The vertical resonator type surface light emitting device according to claim 1, wherein the surface roughness Ra of at least the region directly above the tunnel junction mesa of the semiconductor embedded layer is 0.06 ≦ Ra ≦ 0.3 nm. The vertical resonator type surface emitting device according to any one of claims 1 to 3, wherein the tunnel junction mesa has a cylindrical shape or an elliptical column shape, and its diameter or major axis D satisfies 3 μm ≦ D ≦ 10 μm. The vertical resonator type surface light emitting device according to any one of claims 1 to 4, wherein the off angle (θ) of the GaN substrate is 0.3 ° ≤ θ ≤ 0.7 °. The vertical resonator type surface light emitting device according to any one of claims 1 to 5, wherein the off angle (θ) of the GaN substrate is an angle related to the m-axis direction or the a-axis direction. The vertical resonator type according to any one of claims 1 to 6, wherein the step between the surface of the semiconductor embedded layer and the region immediately above the tunnel junction mesa and the outer peripheral portion thereof is 5 nm or less. Surface emitting element.