JPH11135770A - Iii-v compd. semiconductor, manufacture thereof and semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a III-V compd. semiconductor with a thin film having an embedded structure, III-V compd. semiconductor, and III-V compd. semiconductor light-emitting element. SOLUTION: This III-V compd. semiconductor has a pattern 2 made of a material different from first and second III-V compd. semiconductors on a layer of the first III-V compd. semiconductor 1 shown by Inu Gav Alw N (0<=u, v, w<=1, u+v+w=1) and a layer 2 of the second III-V compd. semiconductor shown by Inx Gay Alz N (0<=x, y, z<=1, x+y+z=1) on the first III-V compd. semiconductor and the pattern 2 which is a line pattern of 1.0 μm wide or less, approximately parallel to the (1-100) orientation of the first III-V compd. semiconductor and made of the III-V compd. semiconductor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to compounds of the general formula an In _x Ga _y
Al _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦
1, x + y + z = 1), a nitride-based group III-V compound semiconductor, a method for producing the same, a group III-V compound semiconductor device using the group III-V compound semiconductor, and a group III-V compound semiconductor light-emitting device About.

[0002]

BACKGROUND OF THE INVENTION In general formula In _x Ga _y Al _z N (where, 0 ≦
The group III-V compound semiconductor represented by x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) has a band gap from a visible region to an ultraviolet region depending on a mixed crystal ratio, that is, a so-called wide gap. Semiconductor. Hereinafter, x and y in this general formula
And z may be referred to as an InN mixed crystal ratio, a GaN mixed crystal ratio, and an AlN mixed crystal ratio, respectively. The compound semiconductor is
Because it has a large band gap, Si, GaAs, etc.
It is promising as a material for electronic devices that can operate at high temperatures that cannot be operated by semiconductors generally used in the past. Further, since the compound semiconductor has a large band gap, it is also important as a material for electronic devices having high withstand voltage.

In particular, considering the device application of the compound semiconductor, a structure in which a material different from the Group 3-5 compound semiconductor, such as an electrode and an insulator, is embedded in the compound semiconductor,
This is important because a transmission base transistor, an electrostatic induction transistor, and the like can be manufactured. By the way, as a method of embedding such a dissimilar material in a crystal, regrowth is generally mentioned. The specific procedure for producing a buried structure by regrowth in the compound semiconductor is as follows. That is, first, the crystal surface of the compound semiconductor, which is the underlying layer, is partially covered with a different material for embedding,
By performing crystal growth of the compound semiconductor on this surface, a structure in which the different material is embedded in the compound semiconductor can be produced.

[0004] As a method of partially covering the crystal surface with the dissimilar material, a fine processing technique used for manufacturing a semiconductor device can be used. Specifically, after uniformly forming the heterogeneous material on the crystal surface of the underlayer, a process of forming a pattern using a photoresist or the like is performed to etch the heterogeneous material except for a desired portion, thereby performing etching. Or a method of exposing the crystal surface to the exposed portion.

[0005] Even in such a structure in which different kinds of materials are embedded, it is preferable that the surface be flat as in a normal crystal in an actual device fabrication process. However, in general, when regrowth is performed on a crystal surface partially covered with a heterogeneous material, in a portion not covered with a heterogeneous material,
Unlike normal crystal growth, crystal growth does not proceed uniformly on a heterogeneous material, unlike normal crystal surfaces, because crystal growth does not occur or abnormal crystal growth occurs on different materials . Such non-uniformity in crystal growth due to re-growth tends to gradually increase as re-growth progresses.In order to actually obtain a flat crystal surface, a layer above a layer formed of a different material must be formed. It had to be thick enough. Therefore, in the conventional regrowth method for producing the buried structure, it takes time until the regrown surface becomes a flat structure, and there is a problem as an industrial manufacturing method.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for producing a thin layer of a Group 3-5 compound semiconductor in a regrowth for producing a buried structure, in which the regrown surface quickly becomes a flat structure. 3-5 of the thin layer having the embedded structure
It is an object of the present invention to provide a group III compound semiconductor, a group III-V compound semiconductor device using the group III-V compound semiconductor, and a group III-V compound semiconductor light emitting device.

[0007]

[Means for Solving the Problems] In view of such a situation,
The present inventors have assiduously studied and, as a result, have made the pattern of a heterogeneous material on a crystal surface a specific one. The inventors have found that they can be obtained and have reached the present invention. That is,
The present invention (1) In the formula In _u Ga _v Al _w N (wherein, 0 ≦
u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1) on the layer made of the first group III-V compound semiconductor described above, the above-mentioned first group III-V compound also different semiconductor having a pattern of below the second group III-V compound semiconductor and varies materials, on the group III-V compound semiconductor and the pattern of the first, the general formula in _x Ga _y Al _z N (where 0
≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1)
In the group 3-5 compound semiconductor having a layer made of the second group 3-5 compound semiconductor represented by
Is a line pattern substantially parallel to the [1-100] direction of the group III-V compound semiconductor, and the width of the line pattern is 1
The present invention relates to a Group 3-5 compound semiconductor having a size of not more than μm. Further, the present invention relates to: [2] the general formula In _u Ga _v Al _w N
(Where 0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v
+ W = 1) on the layer made of the first group III-V compound semiconductor, which is different from the above-mentioned first group III-V compound semiconductor, and also the second group III-V compound semiconductor described later. forming a pattern of different materials, then on the group III-V compound semiconductor and the pattern of the first, the general formula in _x Ga _y a
l _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1,
x + y + z = 1) In the method for producing a group 3-5 compound semiconductor that grows a layer composed of the second group 3-5 compound semiconductor represented by (x + y + z = 1), the pattern of [1- The present invention relates to a method for manufacturing a Group 3-5 compound semiconductor in which a line pattern substantially parallel to the [100] direction is formed and the width of the line pattern is 1 μm or less.
Furthermore, the present invention is, (3) the general formula In _u Ga _v Al _w N
(Where 0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v
+ W = 1) on the layer made of the first group III-V compound semiconductor, which is different from the above-mentioned first group III-V compound semiconductor, and also the second group III-V compound semiconductor described later. has a pattern of different materials, on the group III-V compound semiconductor and the pattern of the first, the general formula in _x Ga _y Al _z N
(Where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y
+ Z = 1) in a group III-V compound semiconductor device having a layer made of the second group III-V compound semiconductor, the pattern is [1-10] of the first group III-V compound semiconductor.
The present invention relates to a Group 3-5 compound semiconductor device formed on a Group 3-5 compound semiconductor having a line pattern substantially parallel to the [0] direction. Further, the present invention relates to [4] a general formula In _u
Ga _v Al _w N (where, 0 ≦ u ≦ 1,0 ≦ v ≦ 1,0 ≦ w
.Ltoreq.1, u + v + w = 1) On the layer made of the first group III-V compound semiconductor represented by the following formula: A first semiconductor layer having a pattern made of a material different from that of the compound semiconductor;
A group V compound semiconductor and the general formula In _x
Ga _y Al _z N (where, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z
.Ltoreq.1, x + y + z = 1) In a group III-V compound semiconductor light-emitting device having a layer composed of a second group III-V compound semiconductor represented by the following formula, the pattern is [1] of the first group III-V compound semiconductor. The present invention relates to a Group 3-5 compound semiconductor light emitting device formed on a Group 3-5 compound semiconductor having a line pattern substantially parallel to the [-100] direction.

[0008]

Next, the present invention will be described in detail.
Formula In _x Ga _y Al _z N (where, 0 ≦ x ≦ 1,0 ≦ y
≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) 3-
It is known that the group V compound semiconductor generally grows with a good (0001) plane (c-plane) regardless of the crystal growth method. 3-5 group compound semiconductor of the present invention have the general formula In _u Ga _v Al _w N (where, 0 ≦ u ≦ 1, 0
≦ v ≦ 1,0 ≦ w ≦ 1 , u + v + w = 1) made of a first group III-V compound semiconductor represented by a layer (hereinafter, may be referred underlayer), the general formula In _x Ga _y Al _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z
= 1) between a layer composed of a second group III-V compound semiconductor layer (hereinafter sometimes referred to as a regrowth layer)
A material having a line pattern substantially parallel to the [1-100] direction, which is different from any of the above-described Group 3-5 compound semiconductors (hereinafter, may be referred to as a heterogeneous material), is embedded, and the width of the line pattern is reduced. The thickness is 1 μm or less.

In the present invention, having a line pattern that is substantially parallel to the [1-100] direction means exactly [1-1].
[00] direction, which means that the line shape may be substantially parallel to the [1-100] direction. Specifically, the direction of the line pattern of the dissimilar material in the present invention is preferably within ± 15 degrees, more preferably within ± 10 degrees, and particularly preferably within ± 7 degrees from the [1-100] direction. It is. If the line pattern direction is [1
If the absolute value is more than 15 degrees from the [-100] direction, the effect of the present invention cannot be sufficiently obtained, which is not preferable. Here, in the present invention, the crystal axis direction in the hexagonal system is generally

(Equation 1) Is described as [1-100] for convenience.

The method for producing a group III- _V compound semiconductor of the present invention comprises the general formula In _u Gav Al _w N (where 0 ≦ u ≦ 1,0
≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1), a pattern (hereinafter, also referred to as a mask) made of a different material is formed on the underlayer, and then the underlayer and the In the method of manufacturing a group III-V compound semiconductor in which a growth layer is grown on a mask, [1-10]
0] direction, and the width of the line pattern is 1 μm or less.

Conventionally, regrowth has been attempted in the case of forming a line pattern substantially parallel to the [11-20] direction perpendicular to the [1-100] direction (J. Cryst.
Growth, 144 (1994), p. 133). FIG. 1 shows the transition of the development of the regrowth interface in this case. As shown in FIG. 1, the {1-101} facet from the line pattern grows as the growth proceeds, and the growth rate in the c-axis direction is relatively higher than that in the facet direction. Because it is big, once (000
1) The surface almost disappears. As the growth progresses further, the growth in the facet plane direction progresses, and the regrowth interface separated by each line pattern fuses. As the growth further progresses, the valleys formed by the facet surfaces gradually fill, and finally the (0001) plane is again formed uniformly and flat.

On the other hand, FIG. 2 shows a transition of the present invention in the case of having a line pattern substantially parallel to the [1-100] direction. In this case, when the growth speed in the facet direction and the growth speed in the c-axis direction on the regrown surface are compared, the growth speed in the facet direction is relatively high. For this reason, as the growth in the facet plane direction progresses, (000
1) The surface expands. After the facets grown from both ends of the mask pattern cover the mask pattern, the valleys formed by the facets are gradually filled, and finally the (0001) plane is again formed uniformly and flat. The major difference between the method of the present invention and the conventional method is that, in the conventional method, the (0001) plane temporarily disappears while the flat (0001) plane appears, whereas the method of the present invention is different from the conventional method. According to the method, as the regrowth proceeds, the (0001) plane gradually expands, and the formation of the (0001) plane occurs more rapidly than in the conventional case. In the present invention, it is important that the width of the mask pattern is small in order to quickly obtain the buried structure. As described above, when the conventional method is compared with the method of the present invention, it is understood that a uniform and flat regrowth interface is formed at an earlier stage according to the present invention.

The growth methods that can be used in the present invention include metal organic chemical vapor deposition (hereinafter sometimes referred to as MOVPE), molecular beam epitaxy (hereinafter MBE).
Sometimes referred to as the law. ), Hydride vapor phase epitaxy (hereinafter sometimes referred to as HVPE), and the like. Among them, the MOVPE method is preferable because uniform crystal growth over a large area can be accurately performed.

Next, for the layer made of the first group III- _V compound semiconductor, the general formula Ga _v Al _w N (where 0 ≦ v ≦
1,0 ≦ w ≦ 1, v + w = 1) 3-5 group compound semiconductor represented, for the layer made of the second group III-V compound semiconductor, the general formula Ga _y Al _z N (where 0 ≦ y ≦ 1, 0 ≦
It is particularly preferable to use a Group 3-5 compound semiconductor represented by z ≦ 1, y + z = 1) because high-quality crystals can be grown.

In the present invention, the substrate for crystal growth of a group III-V compound semiconductor is sapphire, ZnO,
GaAs, Si, SiC, NGO (NdGaO ₃ ), spinel (MgAl ₂ O ₄ ), GaN and the like are used. In particular, sapphire is preferable because a large-area high-quality crystal can be obtained. In addition, when a conductive substrate such as SiC, Si, or GaAs is used, the electrodes can be formed on the back surface of the substrate, which may simplify the element manufacturing process and improve the heat radiation efficiency of the element, which is preferable. In the growth using these substrates, ZnO, SiC, G
A method of growing a thin film of aN, AlN, GaAlN or a stacked film thereof as a buffer layer, that is, a so-called two-step growth method is preferable because a highly crystalline group III-V compound semiconductor can be grown.

A pattern (mask) formed on the layer made of the first group III-V compound semiconductor and made of a material different from the first group III-V compound semiconductor and different from the second group III-V compound semiconductor As the material used in (1), any material that is stable even at the regrowth temperature and growth atmosphere can be suitably used, and examples thereof include metals such as SiO ₂ , SiN _x , and tungsten. As a method for forming the mask over the first layer of a Group 3-5 compound semiconductor, an evaporation method, a sputtering method, a chemical vapor deposition method, or the like can be used.

Depending on the material used for the mask, abnormal growth may occur on the mask, making it difficult to finally obtain a flat surface. In such a case, it is preferable to stack a mask made of a more appropriate material on the mask. In particular, as a material for a mask that is unlikely to cause abnormal growth, SiO ₂ , SiN _{x, and the} like can be given. A preferable effect can be obtained by forming a line pattern after laminating materials used for these masks on a mask in which abnormal growth is likely to occur. When a material that is stable at a high temperature but is chemically unstable with respect to the atmosphere of regrowth is used as a mask, a mask made of a stable material is stacked and used again, so that it can be used during regrowth. Unstable materials can be protected and used.

Next, the Group 3-5 compound semiconductor device of the present invention will be described in detail. 3-5 group compound semiconductor device of the present invention have the general formula an In _u Ga _v In Al _w N (wherein, 0 ≦ u ≦
1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1) on the layer made of the first group III-V compound semiconductor, and with the first group III-V compound semiconductor. Unlike having a pattern of below the second group III-V compound semiconductor and varies materials, on the group III-V compound semiconductor and the pattern of the first, the general formula in _x Ga _y Al _z N ( Where 0 ≦ x ≦
1, having a layer made of a second group III-V compound semiconductor represented by the following formula: 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1)
In a Group-V compound semiconductor device, the pattern is formed on a Group-III compound semiconductor that is a line pattern substantially parallel to the [1-100] direction of the first Group-III compound semiconductor. I do.

Specifically, by embedding a metal as a mask, the fabrication of a semiconductor device structure such as a static induction transistor or a transmission base transistor using the embedded metal as an electrode can be performed in a wider range of parameters than in the past. Is possible. As an example of the semiconductor element of the present invention,
FIG. 3 shows a specific structure of the static induction transistor. In addition, it is known that the nitride-based group III-V compound semiconductor contains high-density crystal defects mainly composed of threading dislocations as compared with other group III-V compound semiconductors. That is, since the threading dislocations generated in the base extend in a direction substantially perpendicular to the substrate, even if the crystal growth proceeds, the defects continue to grow to the crystal surface, and are almost not interrupted halfway. However, the effect of improving crystallinity can be expected by suppressing the propagation of defects from the underlayer by the different material by the buried structure in the present invention. FIG. 4 shows how defects are suppressed. When a mask pattern (first mask 2-1 and second mask 2-2) of a different material is once formed on the surface of the crystal, crystal defects do not extend to a further upper layer through this pattern. For this reason, the density of defects contained in the regrown layer on the mask pattern can be reduced as compared with the base layer. Therefore, the flatness of the surface is promptly restored by the regrowth according to the present invention, so that defects from the substrate can be suppressed quickly.

By utilizing the feature that a portion having a small dislocation density is formed by regrowth, the dislocation density can be reduced over the entire surface of the crystal. In order to realize this, there is a method of repeating regrowth twice using a stripe-shaped mask as in the example shown in FIG. By adjusting the position of the second mask so as to cover the portion not masked by the first regrowth, the dislocation density can be reduced in the entire second regrown layer. That is, in the group 3-5 compound semiconductor device of the present invention,
Unlike the first 3-5 group compound semiconductor, the second 3-5
When a pattern made of a material different from that of the group III compound semiconductor is composed of two or more layers, and projected from a direction perpendicular to the first layer made of the group 3-5 compound semiconductor, the first 3-
It is preferable that the surface of the layer made of the group V compound semiconductor is covered without gaps by the projection of the pattern made of two or more layers.

The shape of a mask for obtaining the compound semiconductor having a low defect density will be described below. The shape of the mask is determined by the width of the mask and the distance between the masks (the width of the exposed portion of the underlying layer between the masks). The distance between the masks is preferably 4 μm or less and 100 ° or more,
More preferably, it is not more than 3 μm and not less than 200 °. The width of the mask is preferably from 0.1 μm to 6 μm, more preferably from 0.2 μm to 4 μm. The crystal with a low dislocation density thus formed can be used as a semiconductor element or a light emitting element.

Next, as another example of the semiconductor device of the present invention, a field effect transistor (FET) utilizing a metal semiconductor contact (Schottky contact) is shown in FIG. A buried structure is repeatedly formed twice on the substrate 4 by regrowing a SiO ₂ [1-100] direction stripe mask and non-doped GaN to form a crystal having a low dislocation density, and an electric field effect thereon. The respective electrodes of an n ⁻ -type active layer (electron transit layer) 6, an n ⁺ -type contact layer 7, a source electrode 8, a gate electrode 9, and a drain electrode 10, which are essential to the transistor, are formed. The gate electrode 9 is formed on the exposed n ⁻ -type active layer (electron transit layer) 6 by removing a part of the n ⁺ -type contact layer 7 by etching. By adjusting the gate voltage, the thickness of the charge depletion layer of the Schottky junction is changed, the cross-sectional area of the electron transit channel (the portion between the depletion layer and the underlying layer) is changed, and the current is turned on and off. Can be controlled. That is, the current between the source and the drain is modulated by the gate voltage, and the device performs three-terminal operation. In the FET structure of the present invention, the dislocation density in the electron transit layer is reduced as compared with the conventional structure, so that the electron mobility can be increased and the characteristics of the FET can be improved.

Next, a preferred range of the layer thickness and physical properties of each layer for operating the FET will be described. The regrowth layer under the n ⁻ -type active layer (electron transit layer) 6 needs to have high resistance, and the carrier concentration is preferably 3 × 10 ¹⁶ cm ⁻³ or less. The layer thickness of the n ⁻ -type active layer (electron transit layer) 6 has an appropriate range according to the carrier concentration, and the higher the carrier concentration, the thinner the active layer needs to be.
A preferred range of the carrier concentration is 5 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less.

The carrier concentration of the n ⁺ type contact layer 7 is
In order to obtain sufficient ohmic electrode characteristics, the higher the better, as long as the crystallinity is not impaired. The carrier concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less,
More preferably 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3
It is as follows.

The source electrode and the drain electrode are preferably ohmic electrodes. As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu,
TiAl, CrAu or the like can be suitably used. The gate electrode needs to be a Schottky electrode. As a Schottky electrode material for n-type GaN, Pt, Pd, Ti, Cr, or the like can be suitably used.

Next, as another example of the semiconductor device of the present invention, a high electron mobility transistor (HEMT) shown in FIG.
Will be described. A non-doped (high resistance) GaN layer having a low dislocation density is formed by buried growth twice in the same manner as in the case of the FET described above, and a heterojunction interface 14 essential for HEMT and an n ⁺ -type contact layer are formed thereon. 7, the source electrode 8, the gate electrode 9, and the drain electrode 10 are formed. The heterojunction interface 14 is made of non-doped GaN
A two-dimensional electron gas (electron traveling channel) is formed by forming a Si-doped n ⁻ -type AlGaN layer 13 on the substrate. By adjusting the gate voltage, the thickness of the charge depletion layer of the Schottky junction is changed, and when the charge depletion layer reaches the heterojunction interface, current stops flowing,
If the charge depletion layer does not reach the heterojunction interface, current flows. That is, the current between the source and the drain is modulated by the gate voltage, and the device performs three-terminal operation.

In general, in the HEMT structure, since the electron transit channel is on the non-doped layer side, there is no scattering by ionized impurities, and a higher mobility than that of the FET can be obtained. Further, in the present invention, the crystal quality of the nitride-based compound semiconductor is improved by using the buried growth in the underlayer as compared with the conventional HEMT structure, so that scattering due to dislocations in the electron transit channel is reduced, and high mobility is achieved. We can expect degree.

Thickness of each layer for operating the HEMT,
The preferred range of physical properties will be described. The regrown layer below the heterojunction interface 14 needs to have high resistance, and preferably has a carrier concentration of 3 × 10 ¹⁶ cm ⁻³ or less.

The layer thickness of the n ⁻ -type AlGaN layer 13 has an appropriate range according to the carrier concentration. The higher the carrier concentration, the thinner the layer thickness of the n ⁻ -type AlGaN layer 13 needs to be. A preferable range of the carrier concentration is 5 × 10 ¹⁶
cm ^-3 or more and 3 × 10 ¹⁸ cm ^-3 or less. The n ^- type Al
The preferred range of the AlN mixed crystal ratio of the GaN layer 13 is 0.0
It is 1 or more and 0.5 or less. If the AlN mixed crystal ratio is less than 0.01, a two-dimensional electron gas having a sufficient concentration cannot be obtained,
On the other hand, if it is larger than 0.5, the crystal quality deteriorates and normal operation becomes difficult to perform, which is not preferable.

The carrier concentration of the n ⁺ type contact layer 7 is
In order to obtain sufficient ohmic electrode characteristics, the higher the better, as long as the crystallinity is not impaired. The carrier concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less,
More preferably 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3
It is as follows.

The source electrode and the drain electrode are preferably ohmic electrodes. As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu,
TiAl, CrAu or the like can be suitably used. The gate electrode needs to be a Schottky electrode. As a Schottky electrode material for n-type GaN, Pt, Pd, Ti, Cr, or the like can be suitably used.

Next, another example of the semiconductor device of the present invention will be described.
The static induction transistor (SIT) shown in FIG.
Will be explained. First layer made of Group 3-5 compound semiconductor
(Underlayer) Si-doped n as 1⁺On the GaN layer
Striped TiAu [1-100] direction
A first mask 2-1 is formed, and a first regrowth layer is formed thereon.
A non-doped GaN layer 3-1 is grown and the first mask is grown.
Embed the disk completely. Next, this is made of Pt
Second mask 2 in the form of a stripe in the [1-100] direction
Form 2 The position of the second mask is the same as the position of the first mask.
It is shifted by half a cycle. The second regrowth layer 3-
And growing a non-doped GaN layer as a second mask.
Embed completely. Followed by n⁺Mold contact layer 7
Some Si-doped n⁺A type GaN layer. n ⁺Type contour
An electrode made of TiAu is formed on the semiconductor layer 7. Note that
The mask pattern is a wide surface connected to the stripe
A pattern having a product part is used. This large area
The top is not completely buried and regrowth is over
After exposure, it remains exposed on the surface. Exposed part of this metal
Can be used as an electrode as it is.

In this structure, the metal can be used as a source electrode, a gate electrode, and a drain electrode from above (or from below). In this structure, the electrons travel in the direction of the film thickness, which is different from the FET and HEMT described above. By adjusting the gate voltage, the thickness of the charge depletion layer around the buried gate (Pt, which is the second mask 2-2 in this example) is changed, and the electron travel channel (the adjacent gate The cross-sectional area of the portion 12 between the depletion layer and the depletion layer changes, and the on / off of the current can be controlled. That is, the current between the source and the drain is modulated by the gate voltage, and the device performs three-terminal operation. In this structure, when a conductive substrate is used, a source electrode or a drain electrode can be formed on the back surface of the substrate. In the example of the SIT in FIG. 3, the traveling distance of the electrons is the sum of the thicknesses of the two regrown layers, so that it is possible to perform a shorter and more precise control as compared with the FET and the HEMT. Thus, a transistor having excellent high-frequency operation characteristics can be manufactured.

Next, the preferred ranges of the thicknesses and physical properties of the respective layers for operating the SIT will be described. The carrier concentration of the two regrown layers used in the electron transit channel has an appropriate range according to the distance between the gate electrode stripes, and it is necessary to decrease the carrier concentration as the distance between the gate electrode stripes increases. . A preferable distance between the gate electrode stripes is 0.1 μm or more and 5 μm or less. Accordingly, a preferable carrier concentration is 2 ×
It varies from 10 ¹⁸ cm ^-3 to 1 × 10 ¹⁵ cm ^-3 .

In this SIT, Si-doped n ⁺ -type Ga
Since the underlayer 1 and the n ⁺ -type contact layer 7 which are N layers function as a contact layer, the carrier concentration thereof is
In order to obtain sufficient ohmic electrode characteristics, the higher the better, as long as the crystallinity is not impaired. The carrier concentration is preferably from 1 × 10 ¹⁷ cm ^{−3 to} 1 × 10 ²¹ cm ⁻³ , and more preferably from 1 × 10 ¹⁸ cm ^{−3 to} 1 × 10 ²⁰ c.
m ⁻³ or less.

The source electrode and the drain electrode are preferably ohmic electrodes. As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu,
TiAl, CrAu or the like can be suitably used. Among these, the electrode used as the first regrowth mask is
Au, TiAu, TiAl, or the like can be suitably used because heat resistance is required to withstand the growth temperature during regrowth.
The gate electrode needs to be a Schottky electrode material having heat resistance to withstand the growth temperature at the time of regrowth.
As a Schottky electrode for n-type GaN, Pt,
Pd, Ti, Cr and the like can be suitably used.

Next, the Group 3-5 compound semiconductor light emitting device of the present invention will be described in detail. 3-5 group compound semiconductor light-emitting device of the present invention have the general formula In _u Ga _v Al _w N (wherein,
0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w =
On the layer made of the first group 3-5 compound semiconductor represented by 1), a material different from the first group 3-5 compound semiconductor and different from the second group 3-5 compound semiconductor described later. has a pattern consisting of, on the group III-V compound semiconductor and the pattern of the first, the general formula in _x Ga _y Al _z N (where, 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, x + y + z
= 1), wherein the pattern is [1-10] of the first group III-V compound semiconductor having a layer composed of the second group III-V compound semiconductor.
[0] direction is formed on a group 3-5 compound semiconductor which is a line pattern substantially parallel to the [0] direction.

In the present invention, the dislocation density can be reduced over the entire surface of the crystal by utilizing the feature that a portion having a low dislocation density is formed by regrowth. In order to realize this, there is a method of repeating regrowth twice using a stripe-shaped mask as in the example shown in FIG. By adjusting the position of the second mask so as to cover the portion not masked by the first regrowth, the dislocation density can be reduced in the entire second regrown layer. That is, in the group III-V compound semiconductor light-emitting device of the present invention, a pattern made of a material different from the first group III-V compound semiconductor and different from the second group III-V compound semiconductor comprises two or more layers. , The first 3-5
When projected from a direction perpendicular to the layer made of the group III compound semiconductor, the surface of the layer made of the first group 3-5 compound semiconductor is covered without gaps by the projection of the pattern made of two or more layers. Is preferred.

FIG. 7 shows a light emitting diode (LED) as an example of the light emitting device of the present invention. The buried structure is repeatedly formed twice on the substrate 4 by a SiO ₂ [1-100] direction stripe mask and regrowth of Si-doped n ⁺ -type GaN to form an n-type conductive crystal having a small dislocation density. Make it. On this crystal, an n ⁻ -type GaN layer 15, a quantum well type InGaN light emitting layer 16, an AlGaN protective layer 17,
A g-doped p-type GaN layer 18 is grown to grow a double heterostructure LED structure. Next, a part of the structure is removed by etching to form an exposed portion of the n ⁺ -type GaN layer, and an n-electrode 19 is formed thereon, and a p-electrode 20 is formed on the p-type GaN layer 18. In the LED having this structure, the non-radiative recombination probability due to defects is suppressed, and the luminous efficiency can be increased because the LED is grown on a high-quality crystal having a low dislocation density compared to the conventional LED. Can be lengthened. In this structure, when a conductive substrate is used, an n-electrode can be formed on the back surface of the substrate.

Next, the preferred ranges of the layer thicknesses and physical properties of each layer for operating the LED will be described. The carrier concentration of the layer forming the n-electrode (the second re-growth layer 3-2 in the example of FIG. 7) is determined in order to obtain sufficient ohmic electrode characteristics.
Higher is better as long as the crystal quality is not impaired. The carrier concentration is preferably 1 × 10 ¹⁷ cm ^-3 or more and 1 × 10 ²¹ c
m ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

The In of the quantum well type InGaN light emitting layer 16
The N mixed crystal ratio ranges from 10% to 5 depending on the target emission wavelength.
Determine in the range of 0%. The preferred thickness of the light emitting layer is 5Å
The range is not less than 90 °. The light-emitting layer may be doped with an n-type impurity and / or a p-type impurity, but it is preferable not to dope when light emission from a band edge is obtained. The number of light-emitting layers may be one or more. In this case, a layer between a plurality of light emitting layers (hereinafter, referred to as a layer)
The band gap of the light-emitting layer is determined so as to be larger than the band gap of the light-emitting layer.

AlGa in contact with the light emitting layer closest to the surface side
The N protective layer 17 is a protective layer provided to prevent the InGaN light emitting layer 16 from being thermally degraded. The composition of this layer is I
AlGaN containing no n is preferable because of its high heat resistance.
This protection function depends on the Al mixed crystal ratio and the layer thickness. The higher the Al mixed crystal ratio, the higher the heat resistance, so that the layer thickness required for obtaining a sufficient protective function becomes smaller. The preferred AlN mixed crystal ratio is 10% or more and 50% or less. If it is less than 10%, it is difficult to obtain a sufficient protective function, which is not preferable.
If it is more than 50%, the crystal quality deteriorates, which is not preferable. Further, the preferable thickness of the protective layer is 50 ° or more and 100 ° or more.
0 ° or less, more preferably 100 ° or more and 500
Å It is below.

The carrier concentration of the Mg-doped p-type GaN layer 18 on which the p-electrode is formed is preferably as high as possible without impairing the crystal quality in order to obtain sufficient ohmic electrode characteristics. The carrier concentration is preferably 3 × 10 ¹⁷ cm
^-3 or more and 3 × 10 ²⁰ cm ^-3 or less, more preferably 1
It is not less than × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ .

As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu, TiAl, Cr
Au or the like can be suitably used. As an ohmic electrode material for p-type GaN, NiAu, MgAu,
Au, Pt, ZnAu, CaAu and the like can be suitably used.

Next, as another example of the light emitting device of the present invention,
The laser diode (LD) shown in FIG. 8 will be described. The buried structure is formed on the substrate 1 by repeating the buried structure twice by regrowth of the SiO ₂ [1-100] direction stripe type mask and Si-doped n ⁺ -type GaN, thereby forming an n-type conductive crystal having a small dislocation density. Make it. On this crystal, an n-type AlGaN layer as the lower cladding layer 23, an n-type GaN layer as the lower optical waveguide layer 21, and InGa as the light emitting layer 27
N-type multiple quantum well layer, p-type GaN as upper optical waveguide layer 22
A p-type AlGaN layer as the upper cladding layer 24 and a non-doped GaN layer as the current confinement layer 28 are grown. The light-emitting layer 27 of the InGaN multiple quantum well is made of In _x G
a _1-x N emitting layer and In _y Ga _1-y N barrier layer (where x
> Y, 0 ≦ y <1).

Next, a part of the current constriction layer 28 on the outermost surface is removed in a stripe shape by etching. Next, re-growth is performed on this structure, and a Mg-doped p-type GaN layer 18 is grown. Next, a part of the structure is removed by etching to form an exposed portion of the n ⁺ -type GaN layer, and an n-electrode 19 is formed thereon, and a p-electrode 20 is formed on the p-type GaN layer 18. The LD of this structure grows on a high-quality crystal having a low dislocation density compared to the conventional LD, so that the lifetime can be extended and the probability of non-radiative recombination due to defects can be suppressed. As a result, the luminous efficiency can be increased. In this structure, when a conductive substrate is used, an n-electrode can be formed on the back surface of the substrate.

The thickness of each layer and the preferable range of physical properties for operating the LD will be described. The carrier concentration of the layer forming the n-electrode (the second regrowth layer 3-2 in the example of FIG. 8) is preferably as high as possible in order to obtain sufficient ohmic electrode characteristics as long as the crystal quality is not impaired. The carrier concentration is
It is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less, more preferably 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ^3.
20 cm ^-3 or less.

The InN mixed crystal ratio of the light emitting layer 27 of the multiple quantum well is determined in a range of 10% to 50% according to a target emission wavelength. The preferred thickness of the light emitting layer is 5 ° or more and 90 ° or more.
範 囲 The range is as follows. The light-emitting layer may be doped with an n-type impurity and / or a p-type impurity, but it is preferable not to dope when obtaining light emission from a band edge. The number of light-emitting layers may be one or more. In this case, the composition is determined so that the band gap of the barrier layer between the plurality of light emitting layers is larger than the band gap of the light emitting layer.

The lower optical waveguide layer 21 and the upper optical waveguide layer 22 above and below the light emitting layer, and the lower cladding layers 23 on both sides thereof,
The upper cladding layer 24 adjusts the refractive index so that the order of cladding layer <optical waveguide layer <light emitting layer is satisfied in order to confine the light generated in the light emitting layer in an internal region sandwiched between both cladding layers. . This substantially corresponds to setting the magnitude of the energy gap in the order of the cladding layer> the optical waveguide layer> the light emitting layer. For example, the light emitting layer is InGaN,
The optical waveguide layer may be selected from GaN, and the cladding layer may be selected from AlGaN. The preferred thickness of the cladding layer is 500 ° or more and 500 ° or more.
0 ° or less, and the preferred thickness of the optical waveguide layer is 200 °
Not less than 2000 °. The optical waveguide layer and cladding layer
Generally it is necessary to dope. In the case of doping, the conductivity type is reversed above and below the light emitting layer. In the example of FIG. 8, the lower optical waveguide layer 21 and the lower cladding layer 23 are doped with n-type, and the upper optical waveguide layer 22 and the upper cladding layer 2 are doped.
4 is p-type doped. The doping concentration is preferably higher as long as the crystallinity is not impaired. However, the portion of the optical waveguide layer that is in contact with the light emitting layer may have a lower doping level in order to increase the crystallinity.

The current confinement layer 28 is provided so that a current flows only in a current path formed by etching and a current density flowing in a light emitting layer (light emitting portion) immediately below the current path is increased. Therefore, the resistance of the current confinement layer 28 is
It must be sufficiently high, and the carrier concentration is 3 × 10 ¹⁶ c
It is preferably at most m ⁻³ .

The carrier concentration of the Mg-doped p-type GaN layer 18 on which the p-electrode is formed is preferably as high as possible without impairing the crystal quality in order to obtain sufficient ohmic electrode characteristics. The carrier concentration is preferably 3 × 10 ¹⁷ cm
^-3 or more and 3 × 10 ²⁰ cm ^-3 or less, more preferably 1
It is not less than × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ .

As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu, TiAl, Cr
Au or the like can be suitably used. As an ohmic electrode material for p-type GaN, NiAu, MgAu,
Au, Pt, or the like can be suitably used.

Next, as another example of the light emitting device of the present invention,
The surface emitting laser shown in FIG. 9 will be described. The buried structure is formed on the substrate 1 by repeating the buried structure twice by regrowth of the SiO ₂ [1-100] direction stripe type mask and Si-doped n ⁺ -type GaN, thereby forming an n-type conductive crystal having a small dislocation density. Make it. On this crystal, n-type AlGaN
And a lower reflective layer 25 in which n-type GaN is repeatedly laminated. The thickness of each of the n-type AlGaN and n-type GaN layers is controlled so as to be に な る wavelength of the emission wavelength. On this I
nGaN multiple quantum well light emitting layer 27, p-type AlGaN and p
A non-doped GaN layer, which is an upper reflection layer 26 and a current confinement layer 28 in which type GaN is repeatedly stacked, is grown. The thickness of each of the p-type AlGaN layer and the p-type GaN layer forming the upper reflective layer 26 is controlled so as to be や は り wavelength of the emission wavelength. In addition, the InGaN multiple quantum well light emitting layer 27
Has a structure in which an In _x Ga ₁ -xN light emitting layer and an In _y Ga _{1 -yN} barrier layer (here, x> y, 0 ≦ y <1) are alternately and repeatedly laminated.

Next, the center portion of the uppermost current confinement layer 28 is removed in a circular shape by etching. Next, re-growth is performed on this structure to grow the Mg-doped p-type GaN layer 18. Next, a part of this structure is removed by etching to form an exposed part of the n ⁺ -type GaN layer, on which n
An annular p-electrode 20 is formed on the electrode 19 and the p-type GaN layer 18. In the LD having this structure, compared to the conventional LD,
Since the crystal is grown on a high-quality crystal having a low dislocation density, the lifetime can be prolonged, and the probability of non-radiative recombination due to defects can be suppressed, so that the luminous efficiency can be increased.
In this structure, by using a conductive substrate, an n-electrode can be formed on the back surface of the substrate. In the example above,
Although the upper reflective layer and the p-type contact layer are stacked in this order, the p-type contact layer and the upper reflective layer may be stacked in this order. In this case, the upper reflective layer does not need to be p-type conductive and may be formed by vapor deposition using a material such as CaF or ZnO.

Next, the preferred ranges of the thicknesses and physical properties of the respective layers for operating the surface emitting laser will be described. n
A layer for forming an electrode (the second regrowth layer 3-3 in the example of FIG. 9)
In order to obtain sufficient ohmic electrode characteristics, the carrier concentration in 2) is preferably as high as possible without impairing the crystal quality.
The carrier concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1
× 10 ²¹ cm ^-3 or less, more preferably 1 × 10 ¹⁸
cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.

The InN mixed crystal ratio of the multiple quantum well light emitting layer 27 is determined in a range of 10% to 50% according to a target emission wavelength. The preferred thickness of the light emitting layer is 5 ° or more and 90 ° or more.
範 囲 The range is as follows. The light-emitting layer may be doped with an n-type impurity and / or a p-type impurity, but it is preferable not to dope when obtaining light emission from a band edge. The number of light-emitting layers may be one or more. In this case, the composition is determined so that the band gap of the barrier layer between the plurality of light emitting layers is larger than the band gap of the light emitting layer.

The current confinement layer 28 is provided to allow a current to flow only through a current path formed by etching and to increase the density of a current flowing through a light emitting layer portion (light emitting portion) immediately below the current path. Therefore, the resistance of this layer needs to be sufficiently high, and the carrier concentration is preferably 3 × 10 ¹⁶ cm ⁻³ or less.

The carrier concentration of the Mg-doped p-type GaN layer 18 on which the p-electrode is formed is preferably as high as possible without impairing the crystal quality in order to obtain sufficient ohmic electrode characteristics. The carrier concentration is preferably 3 × 10 ¹⁷ cm
^-3 or more and 3 × 10 ²⁰ cm ^-3 or less, more preferably 1
It is not less than × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ .

As ohmic electrode materials for n-type GaN, Al, In, Au, TiAu, TiAl, Cr
Au or the like can be suitably used. As an ohmic electrode material for p-type GaN, NiAu, MgAu,
Au, Pt, ZnAu, CaAu and the like can be suitably used.

[0060]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto. Example 1 and Comparative Example 1 GaN was grown on a sapphire (0001) surface via an AlN buffer layer by MOVPE, and a SiO ₂ film was deposited thereon as a mask to a thickness of 70 nm by high-frequency sputtering, followed by application of a photoresist. . Next, a He-Cd laser (wavelength: 442 nm)
Was used to perform laser interference exposure to form a pattern on the resist film. The interval between the line patterns is 1.0 μm. Also, the direction of the pattern (the long axis direction of the line)
[1-100] direction (Example 1), and [11-2]
0] direction (Comparative Example 1). After a pattern is formed on the resist, Si is added using buffered hydrofluoric acid (NH ₄ HF ₂ ).
The O ₂ film was wet-etched, and the resist film was removed with acetone to form a substrate for regrowth.

Next, regrowth was performed using the regrowth substrate as a sample. Hydrogen was used as a carrier gas. First, the substrate was placed on a susceptor in a MOVPE growth furnace, and carrier gas and ammonia were respectively supplied to the substrate for 2.5 slm.
While supplying 1.5 slm, the temperature of the substrate was heated to 1070 ° C. by high frequency heating. After the temperature was stabilized, TMG was supplied at a rate of 96 μmol / min for growth, and then the high-frequency heating was stopped, and when the temperature of the substrate reached 400 ° C., the supply of ammonia was stopped. The growth time is 2
Minutes, 7 minutes, 12 minutes, and 30 minutes were produced. Here, slm is a unit of gas flow rate, and 1 slm is 1
This indicates that a gas weighing 1 liter in a standard state flows per minute.

After the regrowth, the sample was cleaved in the direction perpendicular to the line direction of the mask pattern, and the cross-sectional shape was observed with a scanning electron microscope. In Example 1, the direction was perpendicular to the mask pattern and the crystal surface. The growth rate in the [11-20] direction is 76.8 nm / min.
It was found that the growth rate in the axial direction was 33.4 nm / min, the mask pattern was quickly embedded, and the flat c-plane became the growth surface at an early stage. On the other hand, in Comparative Example 1, the direction perpendicular to the mask pattern and the crystal surface was [1].
The growth rate in the [-100] direction is 56.8 nm / min, c
Since the crystal growth speed in the axial direction is 105.8 nm / min and the upward crystal growth speed is high, crystal growth surrounded by the facet plane occurs, and it is found that the C plane observed in the initial stage of the growth gradually decreases. For this reason, it can be seen that a longer crystal growth time is required for the crystal surface to become a flat C-plane than in Example 1.

[0063]

According to the method for producing a Group 3-5 compound semiconductor of the present invention, a flat crystal surface can be promptly obtained even if the thickness of the regrown layer is small. Since the compound semiconductor can be regrown, the industrial value is great. The obtained group III-V compound semiconductor is used as a group III-V compound semiconductor device such as an electrostatic induction transistor, a field effect transistor or a high electron mobility transistor, and a light emitting device such as a light emitting diode, a laser diode or a surface emitting laser. It is preferably used.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a state of regrowth when a mask having a line pattern formed in a [11-20] direction is used, and shows a temporal change in the order of (a), (b), and (c). Some oblique lines have been omitted for easy viewing. ]

FIG. 2 is a cross-sectional view showing a state of regrowth according to the present invention [a change over time is shown in the order of (a) and (b)]. Some oblique lines have been omitted for easy viewing. ]

FIG. 3 is a diagram showing an example of the structure of an electrostatic induction transistor using a buried structure [(a) is a diagram projected from a direction perpendicular to a substrate, and (b) is cut along a line AA ′ in (a)] FIG. 3C shows a side view. ]

FIG. 4 is a cross-sectional view showing suppression of crystal defects using an embedded structure (oblique lines are omitted for easy viewing).

FIG. 5 is a cross-sectional view illustrating a structure example of a field-effect transistor using a buried structure.

FIG. 6 is a cross-sectional view illustrating a structural example of a high electron mobility transistor using a buried structure.

FIG. 7 is a cross-sectional view illustrating a structure example of a light emitting diode using a buried structure.

FIG. 8 is a sectional view showing an example of the structure of a laser diode using an embedded structure.

FIG. 9 is a cross-sectional view showing a structural example of a surface emitting laser using an embedded structure.

[Explanation of symbols]

1. . . 1. Layer (base layer) made of first group 3-5 compound semiconductor . . Unlike the first group 3-5 compound semiconductor, the second
(Mask) made of a material different from that of group 3-5 compound semiconductor of 2-1. First mask 2-2. 2. Second mask . . Layer made of second 3-5 group compound semiconductor (regrown layer) 3-1. First regrowth layer 3-2. 3. second regrowth layer . . Substrate 5. . . Dislocation 6. . . 6. n ^- type active layer (for example, n ^- GaN layer) . . 7. n ⁺ -type contact layer (for example, n ⁺ GaN layer) . . Source electrode 9. . . Gate electrode 10. . Drain electrode 11. . Charge depletion layer 12. . Electronic traveling channel 13. . n ^- type AlGaN layer 14. . Heterojunction interface 15. . n ^- type GaN layer 16. . InGaN light emitting layer 17. . AlGaN protective layer 18. . p-type GaN layer 19. . n-electrode 20. . p electrode 21. . Lower optical waveguide layer 22. . Upper optical waveguide layer 23. . Lower cladding layer 24. . Upper cladding layer 25. . Lower reflective layer 26. . Top reflective layer 27. . Light emitting layer 28. . Current confinement layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/80 H01L 29/80 V 33/00 H01S 3/18 (72) Inventor Hidetada Matsushima 2 Mataho-cho, Nishi-ku, Nagoya-shi, Aichi -1 2-55 (1) Inventor Naoyoshi Maeda 6 Kitahara, Tsukuba, Ibaraki Pref. Within Sumitomo Chemical Co., Ltd. (72) Inventor Yoshinobu Ono 6 Kitahara, Tsukuba, Ibaraki Pref. 6 Sumitomo Chemical Co., Ltd.

Claims (11)

[Claims] 1. A general formula In _u Ga _v Al _w N (where, 0 ≦ u
≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1)
The semiconductor device has a pattern made of a material different from the first group III-V compound semiconductor described above and different from the second group III-V compound semiconductor described later. in the general formula in _x Ga _y Al _z N (where, 0 ≦ x
≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) in a group 3-5 compound semiconductor having a layer made of a second group 3-5 compound semiconductor, the pattern is the first 3
A line pattern substantially parallel to the [1-100] direction of the Group-V compound semiconductor, wherein the width of the line pattern is 1 μm;
A group 3-5 compound semiconductor characterized by the following. 2. The method according to claim 1, wherein the first group III-V compound semiconductor is of the general formula Ga
_v Al _w N (where 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, v + w =
A group 3-5 compound semiconductor represented by 1),
-V compound semiconductor is Ga _y Al _z N (where, 0 ≦ y ≦
3. The compound semiconductor according to claim 1, wherein the compound semiconductor is a Group 3-5 compound semiconductor represented by 1, 0 ≦ z ≦ 1, y + z = 1).
Group 5 compound semiconductor. 3. A general formula In _u Ga _v Al _w N (where, 0 ≦ u
≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1)
A pattern made of a material different from the first group III-V compound semiconductor described above and different from a second group III-V compound semiconductor described later is formed, and then the first group III-V compound semiconductor and the pattern are formed. during on the general formula in _x Ga _y Al _z N (wherein,
0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z =
In the method for producing a group 3-5 compound semiconductor for growing a layer composed of the second group 3-5 compound semiconductor represented by 1),
As the pattern, [1--
[100] A method of manufacturing a Group 3-5 compound semiconductor, wherein a line pattern substantially parallel to the [100] direction is formed, and the width of the line pattern is 1 μm or less. 4. The method for producing a Group 3-5 compound semiconductor according to claim 3, wherein the semiconductor is grown by metal organic chemical vapor deposition. 5. The method according to claim 1, wherein the first group III-V compound semiconductor is of the general formula Ga
_v Al _w N (where 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, v + w =
A group 3-5 compound semiconductor represented by 1),
-V compound semiconductor is Ga _y Al _z N (where, 0 ≦ y ≦
The method for producing a Group 3-5 compound semiconductor according to claim 3, wherein the method is a Group 3-5 compound semiconductor represented by 1, 0 ≦ z ≦ 1, y + z = 1). 6. A general formula In _u Ga _v Al _w N (where, 0 ≦ u
≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1)
The semiconductor device has a pattern made of a material different from the first group III-V compound semiconductor described above and different from the second group III-V compound semiconductor described later. in the general formula in _x Ga _y Al _z N (where, 0 ≦ x
≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) In a 3-5 group compound semiconductor element having a layer made of a second 3-5 group compound semiconductor represented by the following formula: 1
3. A Group 3-5 compound semiconductor element formed on a Group 3-5 compound semiconductor having a line pattern substantially parallel to the [1-100] direction of the Group 3-5 compound semiconductor. 7. A general formula In _u Ga _v Al _w N (where, 0 ≦ u
≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1)
The semiconductor device has a pattern made of a material different from the first group III-V compound semiconductor described above and different from the second group III-V compound semiconductor described later. in the general formula in _x Ga _y Al _z N (where, 0 ≦ x
≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) In a group 3-5 compound semiconductor light emitting device having a layer made of a second group 3-5 compound semiconductor represented by the following formula: A group 3-5 compound semiconductor light-emitting device formed on a group 3-5 compound semiconductor having a line pattern substantially parallel to a [1-100] direction of a first group 3-5 compound semiconductor. In group III-V compound semiconductor device of claim 8 according to claim 6, in the general formula In _u Ga _v Al _w N (wherein, 0 ≦ u ≦
1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1), and is made of a material different from the first group III-V compound semiconductor described later and the second group III-V compound semiconductor described later. has a pattern, on the group III-V compound semiconductor and the pattern of the first, in the general formula in _x Ga _y Al _z N (wherein, 0 ≦ x ≦
1, having a layer made of a second group III-V compound semiconductor represented by the following formula: 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1)
A Group 3-5 compound semiconductor device, wherein the Group 5 compound semiconductor is formed on a conductive substrate. 9. The group III- _V compound semiconductor light emitting device according to claim 7, wherein the general formula In _u Gav Al _w N (where 0 ≦
u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, u + v + w = 1), which is different from the first group III-V compound semiconductor and different from the second group III-V compound semiconductor described later. has a pattern consisting of, on the group III-V compound semiconductor and the pattern of the first, in the general formula in _x Ga _y Al _z N (wherein, 0 ≦
x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) A group 3-5 compound semiconductor having a layer made of a second group 3-5 compound semiconductor is formed on a conductive substrate. A group 3-5 compound semiconductor light-emitting device, wherein: 10. The group III-V compound semiconductor device according to claim 6, wherein the element is different from the first group III-V compound semiconductor.
When a pattern made of a material different from that of the second group III-V compound semiconductor is composed of two or more layers, and when projected from a direction perpendicular to the layer made of the first group III-V compound semiconductor, the first 3. The group 3-5 compound semiconductor element, wherein the surface of the layer made of the group 3-5 compound semiconductor is covered without gaps by projection of a pattern consisting of two or more layers. 11. The group 3-5 compound semiconductor light emitting device according to claim 7, wherein two patterns made of a material different from the first group 3-5 compound semiconductor and different from the second group 3-5 compound semiconductor are used. When projected from a direction perpendicular to the layer composed of the above layers and composed of the first group III-V compound semiconductor, the surface of the layer composed of the first group III-V compound semiconductor is 2
A group 3-5 compound semiconductor light-emitting device, which is covered with no gap by projection of a pattern comprising at least one layer.