JP2020167470A - Image processing device - Google Patents

Abstract

To provide an image processing device realizing scanning conversion with reduced buffer capacity while maintaining transfer efficiency with DRAM.SOLUTION: The image processing device is configured to transmit image data between an external storage and image processing means. The image processing device includes: image data reading means for reading image data from the external storage; image data writing means for writing image data to the external storage; delay giving means for giving a desired delay amount for each line of image data; and image data transfer control means for controlling image data transfer between the external storage and the image processing means. The image data transfer control means controls the image data reading means and the image data writing means to transfer a pixel block having a predetermined number of lines determined by the number of pixels and the amount of pixel shift, where the number of pixels contained in a transfer unit to the external storage is a lateral width of the pixel block.SELECTED DRAWING: Figure 1

Description

The present invention relates to a technique for reading and writing pixel data held in an external storage device by adding or eliminating a predetermined delay for each line.

It is widely practiced to perform various processing on digital image data by a computer. In recent years, the resolution of images has been increasing, and the amount of data handled has increased as compared with the conventional ones.

Among the image processing, there is an error diffusion method in which binarization processing is performed by pseudo-gradation means. When sequential processing is performed according to the scanning order in the error diffusion method, it is necessary to have a large-capacity error buffer according to the number of pixels in the width of the image data. Therefore, as the resolution of the image increases, more error buffers are required. For example, when the error data is 8 bits in CMYK A4 size 600 DPI, a buffer of 230 kbits (= 4COLOR × 7200Pix × 8 bits) is required per line.

Therefore, in order to reduce the capacity of this error buffer, there is a method of error diffusion in an oblique direction (Patent Document 1). In this method, it is not necessary to have an error buffer in the main scanning direction, but it is necessary to perform scanning conversion of pixel data. In Patent Document 2, each line constitutes a FIFO having a different number of stages to realize scanning conversion.

JP-A-10-224627 JP-A-6-98165

In Patent Document 2, scanning conversion is realized by a FIFO (first in, first out) memory for delay according to a line. Since the scanning conversion is performed in the oblique direction, the number of steps to be delayed by the FIFO memory increases as the line height direction progresses. The required buffer capacity increases in proportion to the square of the line height, which increases the circuit cost.

It is also possible to acquire pixel data in the diagonal direction directly from the DRAM. However, when using the commonly used burst transfer, it is necessary to change the row address when scanning diagonally. Therefore, a precharge operation is required every time the row address is converted, which takes time for access and lowers the transfer efficiency.

In view of the above problems, it is an object of the present invention to provide a method for realizing scanning conversion with reduced buffer capacity while maintaining transfer efficiency with DRAM.

An image supply device that transfers image data between an external storage device and an image processing means.
An image data reading means for reading image data from the external storage device,
An image data writing means for writing image data to the external storage device,
A delay giving means for giving a desired delay amount for each line of image data,
It has an image data transfer control means for controlling the image data transfer between the external storage device and the image processing means.
The image data transfer control means widens the number of pixels included in the transfer unit to the external storage device, and transfers a pixel block having a predetermined number of lines determined by the number of pixels and the amount of pixel shift to the reading means and the writing means. An image supply device characterized by being made to.

According to the present invention, it is possible to suppress the buffer capacity provided for each line while maintaining the transfer efficiency with the DRAM.

An example of functional configuration is shown. An example of input image data is shown. Input image data transfer unit (pixel shift amount 2) Input image data transfer unit (pixel shift amount 3) The internal structure of the delay imparting portion is shown (pixel shift amount 2). A flowchart for explaining an operation example is shown. The internal structure of the delay imparting circuit is shown (pixel shift amount 3).

[Example 1]
In the first embodiment, an example using an error diffusion process for converting an N-value image into an M-value image (M <N) will be described.

First, the components will be described.

FIG. 1 is a block diagram showing an example of functional configuration.

In FIG. 1, the image data reading unit 100 reads a divided processing area of N-value image data from an image input device such as a scanner or a digital camera or various storage devices (not shown) such as a hard disk.

The image data writing unit 101 writes the M value image data converted into the M value to an image input device or a storage medium.

Here, a processing area when a certain image is divided into a plurality of areas and processing is performed for each area is called a band area.

The image data transfer control unit 102 instructs the image data reading unit 100 which image block in the band area to read. Further, the delay adding unit 103 is controlled so that the read image block is given a desired delay.

The delay adding unit 103 imparts a desired delay to the image block received from the image data reading unit 100, performs scanning conversion in the oblique direction, and sends the image block to the image processing unit 104 that performs the error diffusion processing in the subsequent stage.

The image processing unit 104 performs error diffusion processing on the image block received from the delay adding unit 103, and converts the image block into M value image data having a relationship of M <N. Further, as for the image data converted into the M value, the M value image data processed by the image processing unit 104 is sent to the delay giving unit 103.

The delay imparting unit 103 imparts a desired delay amount to the image data received from the image processing unit 104, eliminates the delay generated between the lines, returns the oblique scanning to the scanning in the main scanning direction, and returns the image data. It is sent to the writing unit 101.

The image data transfer control unit 102 controls the image data writing unit 101 so that the image block in which the delay between the lines is eliminated is written out at a desired position of various storage media. Further, the delay giving unit 103 is controlled to give a desired delay so that the delay between the lines is eliminated.

Hereinafter, it will be described in detail with reference to the drawings.

FIG. 2 is an image diagram of image data read and written to an external storage device. The image data 200 in the band region of each CMYK color component shown in FIG. 2 is divided into blocks having a width of N bytes and a length of L lines and transferred. The width N bytes of the image block corresponds to the transfer unit to the external storage device. In the case of this embodiment, when the width of the image block is converted into the number of pixels of the image data, the number of pixels is different because the bit width of the data to be read or written to the external storage device is different. Further, the number of lines L is determined by the pixel shift amount required by the image processing unit 104 and the horizontal T pixel as described later, and (pixel shift amount) × (vertical L line + 1) is smaller than (horizontal T pixel). There is no such thing. That is, (vertical L line) is ((horizontal T pixel) / (pixel shift amount)) -1 or more. As shown in FIG. 2, the X-axis direction is the main scanning direction, and the Y-axis direction is the sub-scanning direction.

3 and 4 are used to show the band region on the external storage device. The image data transfer control unit 102 instructs the image data writing unit 101 at the position of the pixel block to be read, and reads the image data.

The band area on the external storage device shown in FIGS. 3 and 4 is defined as X1, X2, ... In order from the coordinate X0 from the beginning (left end in the figure) to the end (right end in the figure) along the main scanning direction. To do. From the beginning (upper end in the figure) to the end (lower end in the figure) along the sub-scanning direction is defined as L1, L2, ... In order from the coordinate L0.

FIG. 3 shows a band area for each pixel block when the number of pixels per transfer unit is 8 and the pixel shift amount is 2. In this case, the number of lines in the pixel block is (horizontal 8 pixels) / (pixel shift amount 2) = 4, and therefore, it will be described as 4 lines here. That is, it is divided into blocks of units of 8 × 4 horizontal pixels and transferred. Further, the pixels shown by the diagonal lines in FIG. 3 are sequentially supplied to the image processing unit 104.

Regarding the pixel shift amount, when the processing of the pixels (X23, L0) is completed in the error diffusion processing performed by the image processing unit 104, the processing of the pixels (X21, L1) of the next line L1 is determined. Similarly, when the pixels (X21, L1) are fixed, the pixels (X19, L2) are fixed, and the pixels (X17, L3) can be further fixed. Further, when the pixels (X17, L3) are determined, the pixels (X22, L4) of the second group can be determined. That is, it shows the positional relationship between the processed pixel and the pixel that can be processed when the processing of the processed pixel is completed in the main scanning direction.

FIG. 4 shows a band area for each pixel block when the number of pixels per transfer unit is 8 and the pixel shift amount is 3. In this case, the number of lines in the pixel block is (horizontal 8 pixels) / (pixel shift amount 3) = 2.667. FIG. 4A shows an example in which the number of lines of the pixel block is fixed at 3. FIG. 4B shows an example in which the number of lines of the pixel block is varied between 2 and 3. The ratio of the number of lines 2 and 3 of the pixel block shown in FIG. 4B is the ratio for realizing the number of lines 2.667 calculated above.

As shown in FIG. 4A, when the number of lines of the pixel block is rounded up to the number of fixed lines, the transfer amount of the pixel block obtained by dividing the band area is constant. Therefore, the image data transfer control unit 102 can simplify the control of the image reading unit 100 and the image writing unit 101. On the other hand, as shown by the pixel blocks A3, B3, C3 and D3 in FIG. 4A, there is a possibility that the data outside the band region is excessively read or written out. In this way, whether the number of lines of the pixel block is fixed or varied is a trade-off relationship between simplification of control and transfer amount. Further, the number of lines in the pixel block may be (horizontal T pixel) / (pixel shift amount) or more, but if the number of lines is increased more than necessary, the lines transferred as described above may not be used. , It is not preferable to set the number of lines larger than necessary.

In reading and writing the image, as shown in FIGS. 3 and 4, pixel blocks of groups having different main scanning directions are read and written in order.

FIG. 5 shows the internal configuration of the delay imparting unit 103 for the pixel block shown in FIG. The area surrounded by the broken line in FIG. 5 is the delay imparting unit 103. The delay adding unit 103 has a configuration in which a different number of FIFO memories is provided for each line, and the delay amount is changed stepwise for each line.

The number of stages of the FIFO memory can be calculated by the following formula.

Number of FIFO stages = Pixel shift amount x (line number-1)
When the pixel shift amount is 2, and based on this calculation formula, the number of FIFO stages is 0 in the first input delay line 501, so that the input is directly input to the image processing unit 104 without giving a delay to the image processing unit 104. .. In the second input delay line 502, the images are input to the image processing unit 104 after being delayed by a predetermined delay time by the two FIFO memories 505. In the third input delay line 503, the four FIFO memories 506 are delayed by twice the predetermined delay time described above, and are input to the image processing unit 104. Hereinafter, in the same manner, in the fourth input delay line 504, the six FIFO memories 507 are delayed by three times the predetermined delay time described above, and are input to the image processing unit 104. Here, a configuration is shown in which data is selected by the selection circuit 511 after a desired delay is given by the FIFO memory, but each input delay line and each output delay line are directly connected to the image processing unit 104 in the image processing unit 104. It may be configured to be connected to 104.

It is desirable to adjust the number of stages of the FIFO memory according to the pixel shift amount. If the number of steps is set to be larger than the pixel shift amount, it is possible to flexibly correspond to the reading position of the image.

First, the input stage 520 of the delay giving unit, in which the image block is scanned and converted in the oblique direction via the delay giving unit 103 and supplied to the image processing unit 104, will be described.

One image block input to the first input delay line 501 arrives at the selection circuit 511. Next, the image block input to the second input delay line 502 arrives immediately after this. Then, an image block arrives at the third input delay line 503 immediately after this. Finally, the image block arrives immediately after the fourth input delay line 504. In this way, the scanning direction is converted from the main scanning direction to the oblique direction.

Next, the output stage 521 of the delay imparting unit, in which the image block subjected to the desired image processing by the image processing unit 104 is supplied to the delay imparting unit 103 and converted to the original main scanning direction, will be described.

In the processing on the output stage side of the delay giving unit, a delay amount obtained by subtracting the delay amount given to the corresponding line of the input stage from the maximum delay amount in the line is given. That is, in the first output delay line 522, a delay amount of 6 is given by subtracting the delay amount 0 of the input stage from the maximum delay amount 6 in the line. In the second output delay line 523, a delay amount of 4 obtained by subtracting the delay amount 2 of the input stage from the maximum delay amount 6 in the line is given. In the third output delay line 524, a delay amount of 2 obtained by subtracting the delay amount 4 of the input stage from the maximum delay amount 6 in the line is given. Similarly, in the fourth output delay line 525, since the subtraction result becomes 0, the delay amount is not added.

First, the image block subjected to image processing by the image processing unit 104 is supplied to each line 522 to 525 of the subsequent stage 521 of the delay imparting unit via the selection circuit 512. The image block input to the first input delay line 501 is selected by the selection circuit 512 and supplied to the first output delay line 522. The first output delay line 522 is delayed by three times the predetermined delay time described above, and is supplied to the image data transfer control unit 102. The image block input to the second input delay line 502 is supplied to the second output delay line 523, and is supplied to the image data transfer control unit 102 with a delay of twice the predetermined delay time described above. Similarly, the third input delay line 503 is delayed by the predetermined delay time described above via the third output delay line 524. The fourth input delay line 504 is supplied to the image data transfer control unit 102 via the fourth output delay line 525 without adding a delay, and is converted to the original main scanning direction.

Hereinafter, an example of processing the pixel block shown in FIG. 4 will be described with reference to the flowchart of FIG.

In the case of the pixel block shown in FIG. 4, the delay imparting unit 103 has the configuration as shown in FIG. 7. First, an example of reading image data from an external storage device will be described.

The image data reading unit 101 reads the image data from the external storage device (S601).

The image data transfer control unit 102 determines the required pixel shift amount from the read image data and the processing content in the image processing unit 104 (S602). Here, the image processing unit 104 shows an example of performing error diffusion processing, and the pixel shift is set to 3.

The image data transfer control unit 102 determines the number of transfer lines based on the pixel shift amount determined in S602 (S603). The number of transfer lines may be (horizontal 8 pixels) / (pixel shift amount 3) = 2.667 lines based on the above-mentioned calculation formula. Here, 3 lines are fixed.

The image data transfer control unit 102 determines the position of the main scan from the pixel shift amount and the number of transfer lines (S604). In this embodiment, as shown in FIG. 4A, in the second group shifted by one in the sub-scanning direction with reference to the calling position D1 in the main scanning direction of the first group, the main scanning direction is set to one. Called from the position C2 after subtracting the image block. Similarly, the third group is called from the position B3 in which the main scanning direction is further subtracted by one image block.

The image data transfer control unit 102 determines whether or not it is necessary to read the error data from the pixel position (S605). The determination is determined by the position of the pixel data to be processed. Here, since the first transfer unit includes the first pixel line, it is determined that it is necessary to read the error data. However, even when the first pixel line is included, if there is no error between regions at the uppermost end of the image, it is determined that reading the error data is unnecessary.

When it is determined that the error data needs to be read, the image processing unit 104 reads the desired error data from the external storage device (S606).

The error data is transferred to the error memory in the image processing unit (S607). The image processing unit 104 acquires the error data and transfers it to the error memory in the image processing unit.

When it is determined that it is not necessary to read the error data, the image data transfer control unit 102 switches the selection circuit 731 of the delay imparting unit 103 (S608).

Next, the image data transfer control unit 102 transfers the pixel block to each input line of the delay imparting unit 103 (S609).

The transferred pixel block is given a desired delay for each delay line by the delay giving unit 103 (S610).

That is, the delay lines corresponding to the first group are 701, 702, and 703, and in the first input delay line 701 of the first group, the image processing unit 104 is directly subjected to the image processing unit 104 without giving a delay. Entered. In the second input delay line 702 of the first group, the images are input to the image processing unit 104 with a delay of three times the predetermined delay time by the three FIFO memories 709. In the third input delay line 703 of the first group, the six FIFO memories 710 are delayed by 6 times the predetermined delay time and are input to the image processing unit 104. Since the pixel shift amount is 3 this time, the delay amount of 3 times is gradually applied to each line based on the first input delay line of the first group. Similarly, in the second group, with reference to the first input delay line 704 of the second group, a delay amount of three times is gradually applied to each line. Similarly, in the third group, with reference to the first input delay line 707 of the third group, a delay amount of three times is gradually applied to each line. The number of FIFO stages is configured based on the above-mentioned formula for calculating the number of FIFO stages. Again, since the pixel shift amount is 3, the number of FIFO stages in the first group is 0, 3, and 6 in order from the first input delay line 801. In the second group, the offset of the delay amount is set to 1 based on the reading position of the pixel in FIG. 4B, and the number of FIFO stages is 1, 4, and 7 in order from the first input delay line 804. Similarly, in the third group, the number of FIFO stages is 2, 5 in order from the first input delay line 807.

The image block to which the delay is given by the delay giving unit 103 is received by the image processing unit 104 (S611). After that, the image processing unit 104 performs error diffusion processing (S612).

When the image processing unit 104 completes the error diffusion process, the image block is transferred to the delay imparting unit 103 (S613).

The pixel block that has passed each input delay line switches the selection circuit 732 so that it passes through the corresponding output delay line.

That is, the pixels that have passed through the first input delay line 701 of the first group switch the selection circuit 732 so that they pass through the first output delay line 723 of the first group.

Similarly, the pixel passing through the input delay line switches the selection circuit 732 so as to pass through the corresponding output delay line.

The transferred pixel block is given a desired delay for each delay line by the delay giving unit 103 (S614).

A delay is given on the output side so as to eliminate the delay difference given in the input stage of the delay giving section for each line. That is, in the first group, since the maximum delay amount on the input side is 6, the FIFO may be configured so that the sum of the delay amount on the input side and the delay amount on the output side is the maximum delay amount 6. For example, regarding the first output delay line 723 of the first group, since no delay is given by the first input delay line 701 of the first group, (maximum delay amount 6)-(delay of the first input line). Since the amount 0) = 6, it is composed of 6 stages of FIFA 716. Similarly, regarding the second output delay line 724 of the first group, since (maximum delay amount 6)-(delay amount 3 of the second input line) = 3, it is composed of three stages of FIFA 717. Similarly, for the third output delay line 725 of the first group, (maximum delay amount 6)-(delay amount 6 of the third input line) = 0, so that the number of FIFO stages is 0. With respect to the second group, the maximum delay amount is 7, so the first output delay line 726 of the second group is a 6-stage FIFA 719. The second output delay line 727 of the second group is a three-stage FIFO 720, and the third output delay line 728 of the second group is a zero-stage FIFO.

Next, the image data transfer control unit 102 determines whether or not it is necessary to write out the error data from the pixel position (S615).

The determination is determined by the position of the pixel data to be processed. Here, since it is necessary to transfer the error data to the first line of the next second transfer unit in the final line of the first transfer unit, it is determined that the error data needs to be written out. Even when the final line is included, if there is no error between the regions at the bottom of the image, it is determined that writing out the error data is unnecessary.

When it is determined that the error data needs to be written out, the image processing unit 104 writes the error data to the external storage device (S616).

Next, the pixel block subjected to the error diffusion processing is written to the external storage device (S617).

Pixel data is converted from N value to M value by error diffusion processing. When the bit width of the pixel data is changed, the grouping of the pixel data to be transferred is changed. That is, the pixel block is defined by the transfer unit × the number of lines, but since the number of pixels included in the transfer unit changes, the pixel block in which the pixel data is included is changed. As a result, the transfer to the external storage device is always performed in a fixed transfer unit, and the transfer efficiency does not decrease depending on the content of the image processing.

The above processing is repeated until all the pixel blocks are processed (S618).

Further, even when the horizontal pixel 6 is input, it can be dealt with. The number of transfer lines may be set to (horizontal 6 pixels) / (pixel shift amount 3) = 2 lines or more based on the above-mentioned calculation formula. Since there are 3 lines here, it can be handled. That is, if the number of transfer lines is prepared according to the maximum width of the expected input image, it is possible to handle an image smaller than the maximum width.

As described above, when the image data is transferred from the external storage device in blocks, a plurality of blocks having a predetermined number of lines are read from regions having different main scanning positions, and a predetermined delay is provided for each line with respect to the pixels of the read multiple blocks. It becomes possible to give an amount and output it.

In this way, by controlling the number of lines to be transferred according to the image data and the error diffusion processing, it is not necessary to provide the FIFO memory according to the band height, so that the buffer capacity can be suppressed.

With the above configuration, it is possible to perform error diffusion image processing when the number of lines of the image block to be transferred is variable, based on the flowchart of FIG.

As described above, by dividing the band region into pixel blocks having different main scanning positions and setting the number of lines of the pixel blocks to be (horizontal T pixel) / (pixel shift amount) or more, the delay amount for the delay imparting circuit is suitable. Can be reduced to. Further, the transfer efficiency can be maintained by determining the number of pixels in the pixel block according to the pixel shift amount and the transfer unit to the external storage device.

The present invention is also realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiment is supplied to the system or device via a network for data communication or various storage media. Then, the computer (or CPU, MPU, etc.) of the system or device reads and executes the program. Further, the program may be recorded and provided on a computer-readable recording medium.

100 Image data reading unit 101 Image data writing unit 102 Image data transfer control unit 103 Delaying unit 104 Image processing unit 108 Image supply unit

Claims (6)

An image processing device that transfers image data between an external storage device and an image processing means.
An image data reading means for reading image data from the external storage device,
An image data writing means for writing image data to the external storage device,
A delay giving means for giving a desired delay amount for each line of image data,
It has an image data transfer control means for controlling the image data transfer between the external storage device and the image processing means.
The image data transfer control means widens the number of pixels included in the transfer unit to the external storage device, and transfers a pixel block having a predetermined number of lines determined by the number of pixels and the amount of pixel shift to the reading means and the writing means. An image processing device characterized by being made to. The image data reading means reads a plurality of the pixel blocks from different main scanning positions of the external storage device, and at the same time,
The image processing apparatus according to claim 1, wherein the delay imparting means imparts a delay amount to each line of the plurality of pixel blocks. The image processing apparatus according to claim 1 or 2, wherein the delay amount of each line is (pixel shift amount) × (line number-1). The delay imparting means imparts a desired delay amount for each line so as to eliminate the delay difference imparted for each line of the plurality of pixel blocks.
The image processing device according to any one of claims 1 to 3, wherein the image data writing means writes out a pixel block in which the delay difference is eliminated to a different main scanning position of the external storage device. The image processing apparatus according to any one of claims 1 to 4, wherein the number of lines of the pixel block is (number of pixels) / (pixel shift amount) or more. The image processing apparatus according to any one of claims 1 to 5, wherein the number of pixels of the pixel block transferred by the reading means and the writing means is different.

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