JP2020167339A - Semiconductor device and semiconductor package - Google Patents

Abstract

To provide a semiconductor device capable of relaxing stress caused by a Cu conductive layer and a semiconductor package including such a semiconductor device.SOLUTION: A semiconductor device 20 includes: a fourth interlayer insulating film 7; a passivation film 2 on the fourth interlayer insulating film 7; and a base portion 221 formed on the passivation film 2 and including a Cu electrode layer 49. The fourth interlayer insulating film 7 and a second film 38 of the passivation film 2 include an SiO2 film. A first film 37 of the passivation film 2 includes an SiN film. The SiN film (first film 37) is sandwiched between the SiO2 films (fourth interlayer insulating film 7, second film 38).SELECTED DRAWING: Figure 17

Description

The present invention relates to a semiconductor device and a semiconductor package including the semiconductor device.

Patent Document 1 includes a semiconductor substrate, a Cu wiring formed on the semiconductor substrate, a plating layer covering the surface and side surfaces of the Cu wiring, and a Cu wire wire-bonded onto the Cu wiring via the plating layer. , Discloses semiconductor devices. The plating layer has a laminated structure of Ni / Pd / Au.
The manufacturing process of this semiconductor device includes, for example, a step of forming Cu wiring on an insulating film covering a semiconductor substrate via a barrier metal film. Each barrier metal film contains a Ti / Cu seed layer formed by a sputtering method. The Cu wiring is formed on the barrier metal film by an electrolytic plating method with the resist film on the barrier metal film as a mask. After plating the Cu wiring, the resist film is removed, and the exposed Ti / Cu seed layer is removed by wet etching. For example, the Cu seed layer is first removed with a mixed solution of hydrogen peroxide solution and nitric acid, and then the Ti film is removed with a mixed solution of hydrogen peroxide solution and ammonia.

JP-A-2010-171386

An object of the present invention is to provide a semiconductor device capable of relieving stress caused by a Cu conductive layer and a semiconductor package including the semiconductor device.

The semiconductor device according to one aspect of the present invention includes a semiconductor layer having a first surface, a first insulating layer covering the first surface of the semiconductor layer, and a second insulation formed on the first insulating layer. The first insulating layer includes a layer, a third insulating layer formed on the second insulating layer, and a Cu conductive layer formed on the third insulating layer and made of a metal containing Cu as a main component. The third insulating layer is made of a material layer softer than the second insulating layer, and sandwiches the second insulating layer.

The semiconductor package according to one aspect of the present invention includes a conductive member having a first surface and a second surface opposite to the first surface, and the semiconductor device flip-chip bonded to the first surface of the conductive member. And a part of the conductive member and a sealing resin covering the semiconductor device.

According to the semiconductor device and the semiconductor package according to one aspect of the present invention, the structure of the insulating layer arranged directly under the Cu conductive layer makes the second insulating layer made of a relatively hard material layer relatively soft. It has a structure sandwiched between a first insulating layer and a third insulating layer made of a material layer. As a result, even if the Cu conductive layer is thermally deformed and stress is generated at the interface between the Cu conductive layer and the third insulating layer, the stress can be relaxed. In particular, it is particularly effective for flip-chip mounting packages because it is susceptible to stress when the semiconductor device is flip-chip bonded to a conductive member. Therefore, it is possible to provide a semiconductor package having excellent reliability.

FIG. 1 is a perspective view of a semiconductor package according to the first embodiment of the present invention. FIG. 2 is a plan view (permeating the sealing resin) of the semiconductor package shown in FIG. FIG. 3 is a plan view of the semiconductor package shown in FIG. 1 (transmitting the semiconductor element and the sealing resin). FIG. 4 is a bottom view of the semiconductor package shown in FIG. FIG. 5 is a front view of the semiconductor package shown in FIG. FIG. 6 is a rear view of the semiconductor package shown in FIG. FIG. 7 is a right side view of the semiconductor package shown in FIG. FIG. 8 is a left side view of the semiconductor package shown in FIG. FIG. 9 is a partially enlarged view of FIG. FIG. 10 is a partially enlarged view of FIG. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG. FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. FIG. 14 is a cross-sectional view taken along the line XIV-XIV of FIG. FIG. 15 is a partially enlarged view (near the first electrode) of FIG. FIG. 16 is a partially enlarged view (near the second electrode) of FIG. FIG. 17 is a diagram for explaining a wiring structure of a semiconductor device. FIG. 18A is a diagram for explaining a part of the manufacturing process of the semiconductor package. FIG. 18B is a diagram showing the next step of FIG. 18A. FIG. 18C is a diagram showing the next step of FIG. 18B. FIG. 18D is a diagram showing the next step of FIG. 18C. FIG. 18E is a diagram showing the next step of FIG. 18D. FIG. 18F is a diagram showing the next step of FIG. 18E. FIG. 18G is a diagram showing the next step of FIG. 18F. FIG. 18H is a diagram showing the next step of FIG. 18G. FIG. 18I is a diagram showing the next step of FIG. 18H. FIG. 18J is a diagram showing the next step of FIG. 18I. FIG. 18K is a diagram showing the next step of FIG. 18J. FIG. 18L is a diagram showing the next step of FIG. 18K. FIG. 18M is a diagram showing the next step of FIG. 18L. FIG. 18N is a diagram showing the next step of FIG. 18M. FIG. 18O is a diagram showing the next step of FIG. 18N. FIG. 18P is a diagram showing the next step of FIG. 18O. FIG. 19 is a diagram for explaining the effect of stress relaxation by the semiconductor device. FIG. 20 is a diagram for explaining the effect of stress relaxation by the semiconductor device.

<Embodiment of the present invention>
First, embodiments of the present invention will be listed and described.
The semiconductor device according to the embodiment of the present invention includes a semiconductor layer having a first surface, a first insulating layer covering the first surface of the semiconductor layer, and a second insulation formed on the first insulating layer. The first insulating layer includes a layer, a third insulating layer formed on the second insulating layer, and a Cu conductive layer formed on the third insulating layer and made of a metal containing Cu as a main component. The third insulating layer is made of a material layer softer than the second insulating layer, and sandwiches the second insulating layer.

According to this configuration, the structure of the insulating layer arranged directly under the Cu conductive layer is a second insulating layer made of a relatively hard material layer, and a first insulating layer and a third insulating layer made of a relatively soft material layer. It has a structure sandwiched between insulating layers. As a result, even if the Cu conductive layer is thermally deformed and stress is generated at the interface between the Cu conductive layer and the third insulating layer, the stress can be relaxed.
In the semiconductor device according to the embodiment of the present invention, the thickness of the third insulating layer may be 50% or less of the total thickness of the second insulating layer and the third insulating layer.

The semiconductor device according to the embodiment of the present invention includes an Al wiring layer that is covered with the first insulating layer and is made of a metal containing Al as a main component, and the thickness of the third insulating layer is the above. It may be 50% or less of the total thickness of the second insulating layer and the third insulating layer.
In the semiconductor device according to the embodiment of the present invention, the Young's modulus (MPa) of the first insulating layer and the third insulating layer measured in accordance with JIS K7161 is higher than the Young's modulus of the second insulating layer. May be small.

In the semiconductor device according to the embodiment of the present invention, the Young's modulus of the first insulating layer may be larger than the Young's modulus of the third insulating layer.
In the semiconductor device according to the embodiment of the present invention, the Young's modulus of the first insulating layer is 60,000 MPa to 80,000 MPa, and the Young's modulus of the second insulating layer is 300,000 MPa to 350,000 MPa. Yes, the Young's modulus of the third insulating layer may be 15,000 MPa to 30,000 MPa.

The semiconductor device according to the embodiment of the present invention includes an Al wiring layer that is covered with the first insulating layer and is made of a metal containing Al as a main component, and the thickness of the third insulating layer is the above. The young ratio is 50% or less of the total thickness of the second insulating layer and the third insulating layer, and the Young ratio measured in accordance with JIS K7161 of the first insulating layer is 60,000 MPa to 80,000 MPa. The young ratio of the second insulating layer may be 300,000 MPa to 350,000 MPa, and the young ratio of the third insulating layer may be 15,000 MPa to 30,000 MPa.

In the semiconductor device according to the embodiment of the present invention, the first insulating layer and the third insulating layer may be made of an oxide film, and the second insulating layer may be made of a nitride film.
In the semiconductor device according to the embodiment of the present invention, the first insulating layer and the third insulating layer may include any one of the SiO ₂ film and the SiO C film.
In the semiconductor device according to the embodiment of the present invention, the Cu conductive layer may have a thickness of 2 μm to 6 μm.

The semiconductor device according to the embodiment of the present invention has a fourth insulating layer formed on the third insulating layer and covering the Cu conductive layer, and the fourth insulating layer extending in the thickness direction and the Cu. It may include a conductive columnar body electrically connected to the conductive layer.
In the semiconductor device according to the embodiment of the present invention, the columnar body may include a Cu columnar body made of a metal containing Cu as a main component.

In the semiconductor device according to the embodiment of the present invention, the columnar body may have a thickness of 20 μm to 60 μm.
The semiconductor device according to the embodiment of the present invention may include a bonding layer formed on the columnar body and used for flip-chip bonding.
In the semiconductor device according to the embodiment of the present invention, the bonding layer is formed on the columnar body, and is formed on the first layer made of a metal containing Ni as a main component and the solder. A second layer made of a metal as a main component may be included, and the second layer may be used for flip-chip bonding.

In the semiconductor device according to the embodiment of the present invention, the second layer may be formed in a substantially spherical shape.
A semiconductor package according to an embodiment of the present invention includes a conductive member having a first surface and a second surface opposite to the first surface, and the semiconductor device flip-chip bonded to the first surface of the conductive member. And a part of the conductive member and a sealing resin covering the semiconductor device.

According to this configuration, the structure of the insulating layer arranged directly under the Cu conductive layer is such that the second insulating layer made of a relatively hard material layer, the first insulating layer made of a relatively soft material layer, and the third one. It has a structure sandwiched between insulating layers. As a result, even if the Cu conductive layer is thermally deformed and stress is generated at the interface between the Cu conductive layer and the third insulating layer, the stress can be relaxed. In particular, it is particularly effective for flip-chip mounting packages because it is susceptible to stress when the semiconductor device is flip-chip bonded to a conductive member. Therefore, it is possible to provide a semiconductor package having excellent reliability.

The semiconductor package according to another embodiment of the present invention includes a conductive member having a first surface and a second surface opposite to the first surface, and a columnar body mounted on the first surface of the conductive member. Includes the semiconductor device connected to the first surface of the conductive member, and a sealing resin covering a part of the conductive member and the semiconductor device.
The semiconductor package according to another embodiment of the present invention has a conductive member having a first surface and a second surface opposite to the first surface, and a columnar body mounted on the first surface of the conductive member. Is formed between the semiconductor device connected to the first surface of the conductive member, the conductive member and the columnar body, and a bonding material made of a metal containing solder as a main component, and one of the conductive members. The unit, the semiconductor device, and a sealing resin that covers the bonding material.

In the semiconductor package according to another embodiment of the present invention, a part of the columnar body may be embedded in the bonding material.
<Detailed Description of Embodiments of the Present Invention>
Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
The semiconductor package A10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 16.

The semiconductor package A10 includes a conductive member 10, a semiconductor device 20, a bonding layer 30, and a sealing resin 40. As shown in FIG. 1, the package format of the semiconductor package A10 is QFN (Quad For Non-Lead Package). The semiconductor device 20 is a flip-chip type LSI. The semiconductor device 20 includes a switching circuit 212A and a control circuit 212B (details will be described later) inside the semiconductor device 20.

In the semiconductor package A10, DC power (voltage) is converted into AC power (voltage) by the switching circuit 212A. The semiconductor package A10 is used, for example, as one element constituting the circuit of a DC / DC converter. Here, FIG. 2 is transparent to the sealing resin 40 for convenience of understanding. FIG. 3 is transparent to the semiconductor device 20 and the sealing resin 40 for convenience of understanding. In these figures, the transmitted semiconductor device 20 and the sealing resin 40 are shown by imaginary lines (dashed-dotted lines), respectively.

In the description of the semiconductor package A10, the thickness direction Z of the conductive member 10 is referred to as "thickness direction Z". The direction orthogonal to the thickness direction Z is called "first direction x". The direction orthogonal to both the thickness direction Z and the first direction x is referred to as a "second direction y".
As shown in FIGS. 1 and 2, the semiconductor package A10 has a square shape when viewed along the thickness direction Z. Further, in the description of the semiconductor package A10, for convenience, the side on which the plurality of second leads 12 (details will be described later) are located in the second direction y is referred to as "one side of the second direction y". The side on which the plurality of first leads 11 (details will be described later) are located in the second direction y is referred to as "the other side of the second direction y".

As shown in FIG. 2, the conductive member 10 supports the semiconductor device 20 and forms a terminal for mounting the semiconductor package A10 on the wiring board. As shown in FIGS. 11 to 14, the conductive member 10 is partially covered with the sealing resin 40. The conductive member 10 has a main surface 101 (first surface) and a back surface 102 (second surface) facing opposite sides in the thickness direction Z. The main surface 101 faces one side of the thickness direction Z and faces the semiconductor device 20.

The semiconductor device 20 is supported by the main surface 101. The main surface 101 is covered with the sealing resin 40. The back surface 102 faces the other side in the thickness direction Z. The conductive member 10 is composed of a single lead frame. The constituent material of the lead frame is, for example, copper (Cu) or a copper alloy. The conductive member 10 includes a plurality of first leads 11, a plurality of second leads 12, and a pair of third leads 13.

As shown in FIGS. 3 and 4, the plurality of first leads 11 have a band shape extending in the second direction y when viewed along the thickness direction Z. The plurality of first leads 11 are arranged along the second direction y. In the example shown by the semiconductor package A10, the plurality of first leads 11 are composed of three terminals, a first input terminal 111A, a second input terminal 11B, and an output terminal 11C.
The plurality of first leads 11 are arranged in the order of the first input terminal 11A, the output terminal 11C, and the second input terminal 11B from one side to the other side in the second direction y. DC power (voltage) to be converted in the semiconductor package A10 is input to the first input terminal 11A and the second input terminal 11B. The first input terminal 11A is a positive electrode (P terminal). The second input terminal 11B is a negative electrode (N terminal). The output terminal 11C outputs AC power (voltage) converted by the switching circuit 212A configured in the semiconductor device 20.

As shown in FIG. 3, the first input terminal 11A is located between the plurality of second leads 12 and the output terminal 11C in the second direction y. The output terminal 11C is located between the first input terminal 11A and the second input terminal 11B in the second direction y. Each of the first input terminal 11A and the output terminal 11C includes a main portion 111 and a pair of side portions 112. As shown in FIGS. 3 and 4, the main portion 111 extends in the first direction x. In the plurality of first leads 11, the semiconductor device 20 is supported by the main surface 101 of the main portion 111.

The pair of side portions 112 are connected to both ends of the main portion 111 in the first direction x. As shown in FIGS. 3, 4, 12, and 13, each of the pair of side portions 112 has a first end surface 112A. The first end surface 112A is connected to both the main surface 101 and the back surface 102 of the first lead 11, and faces the first direction x. The first end surface 112A is exposed from the sealing resin 40.
As shown in FIG. 9, a constricted portion 112B is formed on each of the pair of side portions 112 of the first input terminal 11A and the output terminal 11C. The constricted portion 112B extends from the main surface 101 of the first lead 11 to the back surface 102, and is recessed from both sides in the second direction y toward the inside of the side portion 112. The constricted portion 112B is in contact with the sealing resin 40. Due to the constricted portion 112B, in the first input terminal 11A and the output terminal 11C, the dimension b of each of the pair of first end faces 112A in the second direction y is larger than the dimension B of the back surface 102 of the main portion 111 in the second direction y. It becomes small.

As shown in FIG. 3, the second input terminal 11B is located on the other side of the output terminal 11C in the second direction y. Therefore, the second input terminal 11B is located on the other side of the plurality of first leads 11 in the second direction y. The second input terminal 11B includes a main portion 111, a pair of side portions 112, and a plurality of protruding portions 113.
The plurality of projecting portions 113 project from the other side of the main portion 111 in the second direction y. A sealing resin 40 is filled between two adjacent protrusions 113. As shown in FIG. 12, each of the plurality of protrusions 113 has an auxiliary end face 113A. The sub-end surface 113A is connected to both the main surface 101 and the back surface 102 of the second input terminal 11B, and faces the other side in the second direction y. The secondary end surface 113A is exposed from the sealing resin 40. As shown in FIG. 7, the plurality of sub-end faces 113A are arranged at predetermined intervals along the first direction x.

As shown in FIG. 10, a cut portion 112C is formed in each of the pair of side portions 112 of the second input terminal 11B. The cut portion 112C extends from the main surface 101 of the second input terminal 11B to the back surface 102, and is recessed from the first end surface 112A in the first direction x. As a result, the first end surface 112A is divided into two regions separated from each other in the second direction y. Even with the notch 112C, at the second input terminal 11B, the dimension b of each of the pair of first end faces 112A in the second direction y is smaller than the dimension B of the back surface 102 of the main portion 111 in the second direction y. Become. The dimension b here is the sum of the dimension b1 in the second direction y of one region of the first end surface 112A and the dimension b2 of the second direction y of the other region of the first end surface 112A ( b = b1 + b2). The notch 112C is filled with a sealing resin 40.

As shown in FIGS. 3 and 4, in each of the plurality of first leads 11, the area of the main surface 101 is larger than the area of the back surface 102. In the example shown by the semiconductor package A10, the areas of the back surfaces 102 of the first input terminal 11A and the output terminal 11C are both equal. The area of the back surface 102 of the second input terminal 11B is larger than the area of the back surface 102 of each of the first input terminal 11A and the output terminal 11C.

At each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the main surface 101 of the main portion 111 on which the semiconductor device 20 is supported may be plated with silver (Ag), for example. Further, in each of the first input terminal 11A, the second input terminal 11B, and the output terminal 11C, the back surface 102 exposed from the sealing resin 40, the pair of first end faces 112A, and the plurality of auxiliary end faces 113A are, for example, tin (Sn). ) May be plated. Instead of tin plating, for example, a plurality of metal platings in which nickel (Ni), palladium (Pd), and gold (Au) are laminated in this order may be adopted.

As shown in FIG. 3, the plurality of second leads 12 are located on one side of the plurality of first leads 11 in the second direction y. One of the plurality of second leads 12 is a ground terminal of the control circuit 212B configured in the semiconductor device 20. A power (voltage) for driving the control circuit 212B or an electric signal for transmitting to the control circuit 212B is input to each of the other plurality of second leads 12. As shown in FIGS. 3, 4 and 11, each of the plurality of second leads 12 has a second end face 121. The second end surface 121 is connected to both the main surface 101 and the back surface 102 of the second lead 12, and faces one side of the second direction y. The second end surface 121 is exposed from the sealing resin 40. As shown in FIG. 8, the plurality of second end faces 121 are arranged at predetermined intervals along the first direction.

As shown in FIGS. 3 and 4, in each of the plurality of second leads 12, the area of the main surface 101 is larger than the area of the back surface 102. The areas of the back surfaces 102 of the plurality of second leads 12 are all the same. For example, silver plating may be applied to the back surface 102 of the plurality of second leads 12 on which the semiconductor device 20 is supported. Further, the back surface 102 and the second end surface 121 of the plurality of second leads 12 exposed from the sealing resin 40 may be plated with tin, for example. Instead of tin plating, for example, a plurality of metal platings in which nickel, palladium, and gold are laminated in this order may be adopted.

As shown in FIG. 3, the pair of third leads 13 are located between the first lead 11 (first input terminal 11A) and the plurality of second leads 12 in the second direction y. The pair of third leads 13 are separated from each other in the first direction x. An electric signal or the like to be transmitted to the control circuit 212B configured in the semiconductor device 20 is input to each of the pair of third leads 13.
As shown in FIGS. 3, 4 and 14, each of the pair of third leads 13 has a third end face 131. The third end surface 131 is connected to both the main surface 101 and the back surface 102, and faces the first direction x. The third end surface 131 is exposed from the sealing resin 40. The third end surface 131 is arranged along the second direction y together with the first end surface 112A of the plurality of first leads 11.

As shown in FIGS. 3 and 4, in each of the pair of third leads 13, the area of the main surface 101 is larger than the area of the back surface 102. The main surface 101 of the pair of third leads 13 on which the semiconductor device 20 is supported may be, for example, silver-plated. Further, the back surface 102 and the third end surface 131 of the pair of third leads 13 exposed from the sealing resin 40 may be plated with tin, for example. Instead of tin plating, for example, a plurality of metal platings in which nickel, palladium, and gold are laminated in this order may be adopted.

As shown in FIGS. 11 to 14, the semiconductor device 20 is electrically bonded to the conductive member 10 (a plurality of first leads 11, a plurality of second leads 12, and a pair of third leads 13) by flip-chip bonding. And are supported by these. The semiconductor device 20 is covered with a sealing resin 40. As shown in FIGS. 12 to 18, the semiconductor device 20 has an element body 21, a plurality of electrodes 22, and a surface protective film 23 as an example of the fourth insulating layer of the present invention.

The element body 21 forms the main part of the semiconductor device 20. As shown in FIGS. 15 and 16, the element main body 21 has a semiconductor substrate 211 and a semiconductor layer 212.
As shown in FIGS. 15 and 16, the semiconductor substrate 211 supports the semiconductor layer 212, the plurality of electrodes 22, and the surface protective film 23 below the semiconductor substrate 211. The constituent material of the semiconductor substrate 211 is, for example, Si (silicon) or silicon carbide (SiC).

As shown in FIGS. 11 to 14, the semiconductor layer 212 is laminated on the side of the semiconductor substrate 211 facing the main surface 101 of the conductive member 10. The semiconductor layer 212 includes a plurality of types of p-type semiconductors and n-type semiconductors based on the difference in the amount of elements doped. The semiconductor layer 212 includes a switching circuit 212A and a control circuit 212B conducting the switching circuit 212A. The switching circuit 212A is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), or the like.

In the example shown by the semiconductor package A10, the switching circuit 212A is divided into two regions, a high voltage region (upper arm circuit) and a low voltage region (lower arm circuit). Each region is composed of one n-channel MOSFET. The control circuit 212B includes a gate driver for driving the switching circuit 212A, a bootstrap circuit corresponding to a high voltage region of the switching circuit 212A, and controls for driving the switching circuit 212A normally. .. The semiconductor layer 212 is configured with a wiring layer (described later). The switching circuit 212A and the control circuit 212B are mutually conductive by the wiring layer.

As shown in FIGS. 11 to 14, the plurality of electrodes 22 project from the side of the element body 21 facing the main surface 101 of the conductive member 10 toward the main surface 101 of the conductive member 10. The plurality of electrodes 22 are electrically bonded to the main surface 101 of the conductive member 10. The plurality of electrodes 22 include a plurality of first electrodes 22A and a plurality of second electrodes 22B. The plurality of first electrodes 22A are conductive to the switching circuit 212A of the semiconductor layer 212. In addition, the plurality of first electrodes 22A are electrically bonded to the main surfaces 101 of the plurality of first leads 11. As a result, the plurality of first leads 11 are conducting to the switching circuit 212A. Further, the plurality of second electrodes 22B are conductive to the control circuit 212B of the semiconductor layer 212. In addition, most of the plurality of second electrodes 22B are electrically bonded to the main surface 101 of the plurality of second leads 12. The remaining second electrode 22B is electrically joined to the main surface 101 of the pair of third leads 13. As a result, the plurality of second leads 12 and the pair of third leads 13 are conducting to the control circuit 212B.

As shown in FIGS. 15 and 16, each of the plurality of electrodes 22 has a base portion 221 and a columnar portion 222. The base 221 is conducting to either the switching circuit 212A or the control circuit 212B of the semiconductor layer 212. The columnar portion 222 projects from the base portion 221 toward the main surface 101 of the conductive member 10. The columnar portion 222 has a tip surface 222A and a side surface 222B. The tip surface 222A faces the main surface 101 of the conductive member 10. The side surface 222B is connected to the tip surface 222A and faces a direction orthogonal to the thickness direction Z. In the semiconductor package A10, the columnar portion 222 is formed with a recess 222C that is recessed from the tip surface 222A toward the element body 21.

As shown in FIGS. 15 and 16, the surface protective film 23 covers the side of the element main body 21 facing the main surface 101 of the conductive member 10. In each of the plurality of electrodes 22, the tip surface 222A of the columnar portion 222 is located between the main surface 101 of the conductive member 10 and the surface protective film 23 in the thickness direction Z. In the semiconductor package A10, the surface protective film 23 is in contact with both the base portion 221 and the columnar portion 222 of the plurality of electrodes 22.

As shown in FIGS. 15 and 16, the bonding layer 30 is in contact with both the main surface 101 of the conductive member 10 and the plurality of electrodes 22. The bonding layer 30 has conductivity. As a result, the plurality of electrodes 22 are electrically bonded to the main surface 101 of the conductive member 10. In each of the plurality of electrodes 22, the bonding layer 30 is in contact with both the front end surface 222A and the side surface 222B of the columnar portion 222. In the semiconductor package A10, the bonding layer 30 is also in contact with the recess 222C of the columnar portion 222. Further, the columnar portion 222 of the semiconductor device 20 is embedded in the bonding layer 30. As a result, not only the tip surface 222A and the recess 222C but also a part of the side surface of the columnar portion 222 is covered with the bonding layer 30.

As shown in FIGS. 5 to 8, the sealing resin 40 has a top surface 41, a bottom surface 42, a pair of first side surfaces 431, and a pair of second side surfaces 432. The constituent material of the sealing resin 40 is, for example, a black epoxy resin.
As shown in FIGS. 11 to 14, the top surface 41 faces the same side as the main surface 101 of the conductive member 10 in the thickness direction Z. As shown in FIGS. 5 to 8, the bottom surface 42 faces the side opposite to the top surface 41. As shown in FIG. 4, the back surface 102 of the plurality of first leads 11, the back surface 102 of the plurality of second leads 12, and the back surface 102 of the pair of third leads 13 are exposed from the bottom surface 42.

As shown in FIGS. 7 and 8, the pair of first side surfaces 431 are connected to both the top surface 41 and the bottom surface 42 and face the first direction. The pair of first side surfaces 431 are separated from each other in the second direction y. As shown in FIGS. 12 to 14, from each of the pair of first side surfaces 431, the first end surface 112A of the plurality of first leads 11 and the third end surface 131 of the third lead 13 are the first side surface 431. It is exposed so that it is flush with each other.

As shown in FIGS. 5 and 6, the pair of second side surfaces 432 is connected to any of the top surface 41, the bottom surface 42, and the pair of first side surfaces 431, and faces the second direction y. The pair of second side surfaces 432 are separated from each other in the first direction x. As shown in FIG. 11, from the second side surface 432 located on one side of the second direction y, the second end surface 121 of the plurality of second leads 12 is exposed so as to be flush with the second side surface 432. There is. From the second side surface 432 located on the other side of the second direction y, the plurality of sub-end surfaces 113A of the second input terminal 11B (first lead 11) are exposed so as to be flush with the second side surface 432. ..

The semiconductor package A10 includes a conductive member 10 having a main surface 101, an element body 21, a semiconductor device 20 having a plurality of electrodes 22 electrically bonded to the main surface 101, and a main surface 101 and a plurality of electrodes 22. A bonding layer 30 in contact with both of the above is provided. Each of the plurality of electrodes 22 has a base portion 221 that is in contact with the main surface 101 of the element main body 21 and a columnar portion 222 that protrudes from the base portion 221 toward the main surface 101 and is in contact with the bonding layer 30. As a result, the semiconductor device 20 is electrically bonded to the conductive member 10 by flip-chip bonding.

FIG. 17 is a diagram for explaining the wiring structure of the semiconductor device 20. FIG. 17 shows a semiconductor device 20 before being bonded to the conductive member 10 by flip-chip bonding. Further, in FIG. 17, the semiconductor device 20 is shown in a state in which the columnar portion 222 projects upward. Therefore, the above-mentioned FIGS. 11 to 16 and 17 are upside down.
The semiconductor device 20 includes a multilayer wiring structure 1, a passivation film 2, a base portion 221 of the electrode 22, a surface protective film 23, a columnar portion 222 of the electrode 22, and a bonding layer 30. Note that FIG. 17 shows only one of the plurality of electrodes 22.

The multilayer wiring structure 1 includes a plurality of interlayer insulating films 4 to 7 formed on the element forming surface 3 (first surface) of the semiconductor layer 212, and a plurality of interlayer insulating films 4 to 7 formed in the plurality of interlayer insulating films 4 to 7. Includes electrode layers 14-16. Since the electrode layers 14 to 16 form the multilayer wiring structure 1, they may be referred to as wiring layers 14 to 16, respectively.
The plurality of interlayer insulating films 4 to 7 are a first interlayer insulating film 4 formed on the element forming surface 3 of the semiconductor layer 212 and a second interlayer insulating film 5 formed on the first interlayer insulating film 4. A third interlayer insulating film 6 formed on the second interlayer insulating film 5, and a fourth interlayer insulating film as an example of the first insulating layer of the present invention formed on the third interlayer insulating film 6. 7 and is included. The first interlayer insulating film 4, the second interlayer insulating film 5, and the third interlayer insulating film 6 may include an oxide film (SiO ₂ film) or a nitride film (SiN film), respectively. The material of the fourth interlayer insulating film 7 will be described later.

The plurality of electrode layers 14 to 16 are electrically connected to the switching circuit 212A and the control circuit 212B formed in the semiconductor layer 212 (in FIG. 17, only the switching circuit 212A is shown).
The plurality of electrode layers 14 to 16 are formed on the first electrode layer 14 which is formed on the first interlayer insulating film 4 and is coated on the second interlayer insulating film 5, and is formed on the second interlayer insulating film 5. An example of the Al wiring layer of the present invention formed on the second electrode layer 15 coated with the third interlayer insulating film 6 and the third interlayer insulating film 6 and coated with the fourth interlayer insulating film 7. The third electrode layer 16 is included. The first electrode layer 14, the second electrode layer 15, and the third electrode layer 16 may each contain copper or aluminum.

A first barrier layer 31 is formed on the lower surface of the first electrode layer 14. The first barrier layer 31 suppresses the electrode material constituting the first electrode layer 14 from diffusing into the first interlayer insulating film 4.
A first barrier layer 32 is formed on the upper surface of the first electrode layer 14. The first barrier layer 32 suppresses the electrode material constituting the first electrode layer 14 from diffusing into the second interlayer insulating film 5.
A second barrier layer 33 is formed on the lower surface of the second electrode layer 15. The second barrier layer 33 suppresses the electrode material constituting the second electrode layer 15 from diffusing into the second interlayer insulating film 5.

A second barrier layer 34 is formed on the upper surface of the second electrode layer 15. The second barrier layer 34 suppresses the electrode material constituting the second electrode layer 15 from diffusing into the third interlayer insulating film 6.
A third barrier layer 35 is formed on the lower surface of the third electrode layer 16. The third barrier layer 35 suppresses the electrode material constituting the third electrode layer 16 from diffusing into the third interlayer insulating film 6.
A third barrier layer 36 is formed on the upper surface of the third electrode layer 16. The third barrier layer 36 suppresses the electrode material constituting the third electrode layer 16 from diffusing into the fourth interlayer insulating film 7.

Each of the barrier layers 31 to 36 may have a single layer structure composed of a titanium nitride layer or a titanium layer, or may have a laminated structure including a titanium nitride layer and a titanium layer formed on the titanium nitride layer. You may be. Each of the barrier layers 31 to 36 may be a layer made of the same material as each other, or may be a layer made of different materials.
The passivation film 2 is formed on the multilayer wiring structure 1 so as to cover the multilayer wiring structure 1. More specifically, the passivation film 2 covers the fourth interlayer insulating film 7.

The passivation film 2 may include an oxide film (SiO ₂ film), a BPSG (Boron Phosphorus Silicon Glass) film, or a nitride film (SiN film). In this embodiment, the passivation film 2 is an example of the first film 37 as an example of the second insulating layer of the present invention and the third insulating layer of the present invention laminated in this order from the surface of the fourth interlayer insulating film 7. It has a laminated structure including the second film 38 of the above.

Here, in this embodiment, there is the following relationship between the fourth interlayer insulating film 7, the first film 37 of the passivation film 2, and the second film 38. That is, the fourth interlayer insulating film 7 and the second film 38 are made of a material layer softer than the first film 37, and sandwich the first film 37 which is relatively hard.
More specifically, it is preferable that the Young's modulus (MPa) of the fourth interlayer insulating film 7 and the second film 38 measured according to JIS K7161 is smaller than the Young's modulus of the first film 37. Further, it is preferable that the Young's modulus of the fourth interlayer insulating film 7 is larger than the Young's modulus of the second film 38. For example, the fourth interlayer insulating film 7 Young's modulus may be 60,000 MPa to 80,000 MPa. The Young's modulus of the first film 37 may be 300,000 MPa to 350,000 MPa. The Young's modulus of the second film 38 may be 15,000 MPa to 30,000 MPa.

Examples of the fourth interlayer insulating film 7 and the second film 38 include an oxide film, and examples of the first film 37 include a nitride film. Since the nitride film has a higher density and is denser than the oxide film, it is easier to form harder than the oxide film. Specific examples of the fourth interlayer insulating film 7 and the second film 38 include a SiO ₂ film and a SiOC film, and specific examples of the first film 37 include a SiN film.

Even when the same material film is formed, the fourth interlayer insulating film 7 and the second film 38 can have different hardnesses by changing the film forming conditions. For example, when the fourth interlayer insulating film 7 and the second film 38 composed of the SiO ₂ film are formed by the CVD method, each CVD condition (for example, gas type, temperature, pressure, etc.) is changed to obtain different film qualities. As a result, the fourth interlayer insulating film 7 can be formed of the same type of film having a younger ratio than that of the second film 38. That is, the fourth interlayer insulating film 7 may be made of a SiO ₂ film of the same type as the second film 38 and may have a Young's modulus larger than that of the second film 38.

As for the ratio of the thickness of the passivation film 2, the thickness of the second film 38 is 50% or less of the thickness of the passivation film 2 (total thickness of the first film 37 and the second film 38). Is preferable. That is, the thickness of the relatively soft second film 38 is preferably 50% or less.
A first via 39 penetrating the second interlayer insulating film 5 is formed on the second interlayer insulating film 5 between the upper surface of the first electrode layer 14 and the lower surface of the second electrode layer 15. The first electrode layer 14 is electrically connected to the second electrode layer 15 via the first via 39.

A first via barrier film 43 is formed between the first via 39 and the second interlayer insulating film 5. The first via 39 may contain tungsten. The first via barrier film 43 may contain titanium nitride.
A second via 44 penetrating the third interlayer insulating film 6 is formed on the third interlayer insulating film 6 between the upper surface of the second electrode layer 15 and the lower surface of the third electrode layer 16. The second electrode layer 15 is electrically connected to the third electrode layer 16 via the second via 44.

A second via barrier film 45 is formed between the second via 44 and the third interlayer insulating film 6. The second via 44 may contain tungsten. The second via barrier film 45 may contain titanium nitride.
A third via 46 penetrating the passivation film 2 and the fourth interlayer insulating film 7 is formed on the passivation film 2 and the fourth interlayer insulating film 7 on the third electrode layer 16. The third via 46 is exposed from the passivation film 2 and is electrically connected to the third electrode layer 16.

The exposed surface of the third via 46 is formed flush with the surface of the passivation film 2. A third via barrier film 47 is formed between the third via 46 and the fourth interlayer insulating film 7, and between the third via 46 and the passivation film 2. The third via 46 may contain tungsten. The third via barrier film 47 may contain titanium nitride.
The base portion 221 of the electrode 22 is formed on the passivation film 2 so as to cover the third via 46. The base 221 of the electrode 22 contains a barrier electrode layer 48 formed on the passivation film 2 and a metal containing copper as a main component, and is formed on the main surface of the barrier electrode layer 48. It has a laminated structure including a Cu electrode layer 49 as an example of the layer. The barrier electrode layer 48 suppresses the electrode material constituting the Cu electrode layer 49 from diffusing into the passivation film 2.

Here, the "metal containing copper as a main component" is a metal having the highest mass ratio (mass%) of copper constituting the Cu electrode layer 49 with respect to other components constituting the Cu electrode layer 49. (Hereafter, the same). When the Cu electrode layer 49 is made of an aluminum-copper alloy (Al-Cu alloy), the copper mass ratio R _Cu is higher than the aluminum mass ratio R _Al (R _Cu > R _Al ).
When the Cu electrode layer 49 is made of an aluminum-silicon-copper alloy (Al-Si-Cu alloy), the copper mass ratio R _Cu is higher than the aluminum mass ratio R _Al and the silicon mass ratio R _Si (R _Cu). > R _Al and R _Cu > R _Si ).

The "metal containing copper as a main component" may contain trace impurities, but high-purity copper having a purity of 99.9999% (6N) or more and high-purity copper having a purity of 99.99% (4N) or more. Etc. are also included.
The barrier electrode layer 48 is formed on the passivation film 2 so as to cover the third via 46. The barrier electrode layer 48 is electrically connected to the first electrode layer 14, the second electrode layer 15, and the third electrode layer 16 via the third via 46.

The barrier electrode layer 48 may have a thickness of 100 nm to 500 nm (about 100 nm in this form). The barrier electrode layer 48 may have a single layer structure composed of a single metal layer. The barrier electrode layer 48 may have a laminated structure in which a plurality of metal layers are laminated.
The barrier electrode layer 48 preferably has a coefficient of thermal expansion smaller than the coefficient of thermal expansion of the Cu electrode layer 49. Further, the barrier electrode layer 48 preferably has a rigidity higher than that of the Cu electrode layer 49.

The barrier electrode layer 48 may contain at least one of titanium, titanium nitride, tantalum, tungsten, molybdenum, chromium or ruthenium. According to these metal materials, a barrier electrode layer 48 having a coefficient of thermal expansion (4 μm / m · K to 9 μm / m · K) smaller than the coefficient of thermal expansion of the Cu electrode layer 49 can be realized. When the Cu electrode layer 49 is made of high-purity copper, the coefficient of thermal expansion of the Cu electrode layer 49 is about 16.5 μm / m · K.

The barrier electrode layer 48 may contain at least one of tantalum, tungsten, molybdenum, chromium or ruthenium. According to these metal materials, a barrier electrode layer 48 having a coefficient of thermal expansion (4 μm / m · K to 7 μm / m · K) smaller than the coefficient of thermal expansion of the Cu electrode layer 49 can be realized.
Further, according to these metal materials, the barrier electrode layer 48 having a rigidity (50 Gpa to 180 Gpa) larger than the rigidity of the Cu electrode layer 49 can be realized. When the Cu electrode layer 49 is made of high-purity copper, the rigidity of the Cu electrode layer 49 is about 48 Gpa.

The Cu electrode layer 49 occupies most of the base 221 of the electrode 22. The Cu electrode layer 49 may have a thickness of 2 μm to 6 μm. The Cu electrode layer 49 has an upper surface 49a (first surface), a lower surface 49b (second surface) located on the opposite side of the upper surface 49a, and a side surface 49c connecting the upper surface 49a and the lower surface 49b. The lower surface 49b of the Cu electrode layer 49 is mechanically and electrically connected to the barrier electrode layer 48.

The peripheral edge of the lower surface 49b of the Cu electrode layer 49 is separated from the peripheral edge of the barrier electrode layer 48 inward of the barrier electrode layer 48. The lower surface 49b of the Cu electrode layer 49 is formed to be narrower than the upper surface 49a of the Cu electrode layer 49 in the direction along the surface of the passivation film 2.
More specifically, in the Cu electrode layer 49, a recess in the region on the lower surface 49b side of the side surface 49c is recessed toward the inside of the Cu electrode layer 49 and exposes the upper surface of the edge portion of the barrier electrode layer 48. 50 is formed.

The recess 50 is formed in a convex curved shape that bulges diagonally upward of the Cu electrode layer 49. As a result, the inner surface of the recess 50 is a convex curved surface. Due to the recess 50, the lower surface 49b of the Cu electrode layer 49 is formed to be narrower than the upper surface 49a of the Cu electrode layer 49.
In this embodiment, the side surface 49c of the Cu electrode layer 49 is located outside the peripheral edge (side surface) of the barrier electrode layer 48. Therefore, the peripheral edge (side surface) of the barrier electrode layer 48 is located in the region between the peripheral edge of the lower surface 49b of the Cu electrode layer 49 and the side surface 49c of the Cu electrode layer 49 in this form. The side surface 49c of the Cu electrode layer 49 may be located inside the peripheral edge (side surface) of the barrier electrode layer 48.

The base portion 221 of the electrode 22 includes a pad electrode layer 51 formed on the upper surface 49a of the Cu electrode layer 49. The pad electrode layer 51 is formed on the upper surface 49a of the Cu electrode layer 49 so as to cover the upper surface 49a of the Cu electrode layer 49.
The pad electrode layer 51 includes a first portion 52 that is mechanically and electrically connected to the upper surface 49a of the Cu electrode layer 49, and a second portion 53 that projects laterally from the first portion 52 to the Cu electrode layer 49. Including.

In this embodiment, the pad electrode layer 51 has a laminated structure including a nickel layer 54 formed on the upper surface 49a of the Cu electrode layer 49 and a palladium layer 55 formed on the nickel layer 54. .. The palladium layer 55 is formed with a thickness smaller than the thickness of the nickel layer 54. The palladium layer 55 is a metal having the highest mass ratio (mass%) of palladium constituting the palladium layer 55 with respect to other components constituting the palladium layer 55. In other words, the palladium layer 55 may be a metal containing palladium as a main component. Further, the nickel layer 54 is a metal having the highest mass ratio (mass%) of nickel constituting the nickel layer 54 with respect to other components constituting the nickel layer 54. In other words, the nickel layer 54 may be a metal containing nickel as a main component.

The thickness of the nickel layer 54 may be 0.5 μm to 5 μm. The thickness of the palladium layer 55 may be 0.05 μm to 0.5 μm.
The surface protective film 23 is formed on the passivation film 2. The surface protective film 23 covers the base portion 221 of the electrode 22. The surface protective film 23 is formed with an opening 8 that exposes a part of the base portion 221 of the electrode 22. The surface protective film 23 has electrical insulation properties, and is made of, for example, polyimide.

The columnar portion 222 of the electrode 22 is in contact with the base portion 221 within the opening 8 of the surface protective film 23, and projects from the opening 8 to the opposite side of the base portion 221. The columnar portion 222 of the electrode 22 includes a barrier layer 17 formed on the surface protective film 23 and a Cu columnar body 18 containing a metal containing copper as a main component and formed on the main surface of the barrier layer 17. It has a laminated structure including. The barrier layer 17 suppresses the material constituting the Cu columnar body 18 from diffusing into the surface protective film 23. Here, the "metal containing copper as a main component" constituting the Cu columnar body 18 is the same as the definition of the Cu electrode layer 49 described above.

The barrier layer 17 is formed on the surface protective film 23 so as to cover the base portion 221 in the opening 8 of the surface protective film 23 (so as to be in contact with the palladium layer 55). The barrier layer 17 is electrically connected to the base 221.
The barrier layer 17 may have a thickness of 100 nm to 500 nm (about 100 nm in this form). The barrier layer 17 may have a single-layer structure composed of a single metal layer. The barrier layer 17 may have a laminated structure in which a plurality of metal layers are laminated.

The Cu columnar body 18 may have a thickness of 20 μm to 60 μm. Further, in the columnar portion 222, a columnar body made of a material other than Cu may be applied instead of the Cu columnar body 18.
The bonding layer 30 is formed on the tip surface 222A of the columnar portion 222 of the electrode 22. The joint layer 30 has an overhanging portion 19 that partially projects laterally from the side surface 222B of the columnar portion 222.

The bonding layer 30 has a laminated structure including a first layer 24 formed on the columnar portion 222 and a second layer 25 formed on the first layer 24. In this embodiment, the first layer 24 may include a nickel (Ni) layer and the second layer 25 may include a solder layer.
The nickel layer may be a metal having the highest nickel mass ratio (mass%) with respect to other components constituting the nickel layer. In other words, the first layer 24 may be a metal containing nickel as a main component.

As the solder layer, lead-free solder containing zero or almost no lead is preferable. As the lead-free solder, for example, various materials such as SnAgCu-based, SnZnBi-based, SnCu-based, SnAgInBi-based, and SnZnAl-based can be applied. Further, as shown in FIG. 17, the second layer 25 may be formed in a substantially spherical shape before the flip chip joining.

18A to 18P are diagrams for explaining a part of the manufacturing process of the semiconductor package A10 in the order of the processes. In the following, a case where the Cu electrode layer 49 is made of high-purity copper will be described as an example.
When manufacturing the semiconductor package A10, first, the semiconductor device 20 is manufactured. With reference to FIG. 18A, a semiconductor substrate 211 (semiconductor layer 212) in which the passivation film 2 is formed on the multilayer wiring structure 1 is prepared. A third via 46 penetrating the passivation film 2 and the fourth interlayer insulating film 7 is formed. Next, the barrier electrode layer 48 is formed on the passivation film 2. The barrier electrode layer 48 may be formed by, for example, a sputtering method.

Next, with reference to FIG. 18B, a Cu seed layer 9 is formed on the barrier electrode layer 48. The Cu seed layer 9 may be formed by, for example, a sputtering method. Next, a mask 26 having a predetermined pattern is formed on the Cu seed layer 9. The mask 26 selectively has an opening 26a that exposes a region in the Cu seed layer 9 on which the Cu electrode layer 49 (including the Cu layer 84 in the above-mentioned third example) should be formed.

More specifically, as shown in FIGS. 22 to 24, a mask 26 having an opening 26a corresponding to the planar shape of the base portion 221 and the dummy conductive layer 83 shown in the first to third examples described above is prepared. .. Note that FIG. 22 is a mask 26 for forming the base 221 of the first example, FIG. 23 is the mask 26 for forming the base 221 of the second example, and FIG. 24 is the base 221 of the third example and The mask 26 for forming the dummy conductive layer 83.

Next, with reference to FIG. 18C, the Cu electrode layer 49 is formed. The Cu electrode layer 49 is formed on the surface of the Cu seed layer 9 exposed from the opening 26a of the mask 26. The Cu electrode layer 49 may be formed by an electrolytic copper plating method. The Cu electrode layer 49 is formed up to the middle portion of the opening 26a of the mask 26 in the depth direction. The Cu electrode layer 49 is integrally formed with the Cu seed layer 9.

Next, with reference to FIG. 18D, the nickel layer 54 and the palladium layer 55 are formed in this order on the upper surface 49a of the Cu electrode layer 49. The nickel layer 54 and the palladium layer 55 are each formed on the upper surface 49a of the Cu electrode layer 49 exposed from the opening 26a of the mask 26. The nickel layer 54 and the palladium layer 55 may be formed by an electroless plating method, respectively.

Next, with reference to FIG. 18E, the mask 26 is removed.
Next, referring to FIG. 18F, the unnecessary portion of the Cu seed layer 9 is removed. The Cu seed layer 9 may be removed by wet etching. In this step, a part of the Cu electrode layer 49 is side-etched. Therefore, the side surface 49c of the Cu electrode layer 49 is formed so as to be located inward of the side surface of the pad electrode layer 51.

As a result, the pad electrode layer 51 is formed. The pad electrode layer 51 includes a first portion 52 that is mechanically and electrically connected to the upper surface 49a of the Cu electrode layer 49, and a second portion 53 that projects laterally from the first portion 52 to the barrier electrode layer 48. Including.
Next, referring to FIG. 18G, the unnecessary portion of the barrier electrode layer 48 is removed. The barrier electrode layer 48 may be removed by wet etching. In this step, the barrier electrode layer 48 located directly below the Cu electrode layer 49 is removed by the amount corresponding to the thickness of the barrier electrode layer 48. Therefore, the side surface of the barrier electrode layer 48 is formed so as to be located inward of the side surface 49c of the Cu electrode layer 49.

Next, with reference to FIG. 18H, the corner portion connecting the lower surface 49b and the side surface 49c in the Cu electrode layer 49 is removed. The corners of the Cu electrode layer 49 may be removed by wet etching. The wet etching step is performed until the main surface of the barrier electrode layer 48 is exposed. As a result, a recess 50 is formed in the region of the Cu electrode layer 49 on the lower surface 49b side of the side surface 49c to expose the upper surface of the edge portion of the barrier electrode layer 48.

Next, with reference to FIG. 18I, a surface protective film 23 is formed on the passivation film 2 so as to cover the base portion 221. Next, the surface protective film 23 is patterned to form an opening 8 in the surface protective film 23. Next, the barrier layer 17 is formed on the surface protective film 23. The barrier layer 17 may be formed by, for example, a sputtering method. Next, the Cu seed layer 27 is formed on the barrier layer 17. The Cu seed layer 27 may be formed by, for example, a sputtering method.

Next, with reference to FIG. 18J, a mask 28 having a predetermined pattern is formed on the Cu seed layer 27. The mask 28 selectively has an opening 28a in the Cu seed layer 27 that exposes a region where the Cu columnar body 18 should be formed.
Next, with reference to FIG. 18K, the Cu columnar body 18 is formed. The Cu columnar body 18 is formed on the surface of the Cu seed layer 27 exposed from the opening 28a of the mask 28. The Cu columnar body 18 may be formed by an electrolytic copper plating method. The Cu columnar body 18 is formed up to the middle portion of the opening 28a of the mask 28 in the depth direction. The Cu columnar body 18 is integrally formed with the Cu seed layer 27. Further, the recess 222C of the Cu columnar body 18 is formed by taking over the recess of the opening 8 of the surface protective film 23.

Next, referring to FIG. 18L, the first layer 24 (nickel layer) is formed on the Cu columnar body 18. The first layer 24 is formed on the upper surface of the Cu columnar body 18 exposed from the opening 28a of the mask 28. The first layer 24 may be formed by an electroless plating method.
Next, with reference to FIG. 18M, the mask 28 is removed.
Next, with reference to FIG. 18N, the unnecessary portion of the Cu seed layer 27 is removed. The Cu seed layer 27 may be removed by wet etching. In this step, a part of the Cu columnar body 18 is side-etched. Therefore, the side surface 222B of the Cu columnar body 18 is formed so as to be located inward from the side surface of the first layer 24.

Next, referring to FIG. 18O, the unnecessary portion of the barrier layer 17 is removed. The barrier layer 17 may be removed by wet etching.
Next, with reference to FIG. 18P, a spherical second layer 25 (solder layer) is formed on the first layer 24.
After that, the semiconductor device 20 is flip-bonded to the conductive member 10. Next, the semiconductor device 20 is sealed with the sealing resin 40 together with the conductive member 10. Then, the dicing step of the sealing resin 40 is carried out, and the semiconductor package A10 is cut out. Through the above steps, the semiconductor package A10 is manufactured.

As described above, in the semiconductor device 20, the structure of the insulating layer arranged directly under the Cu electrode layer 49 is such that the first film 37 of the passivation film 2 made of a relatively hard material layer is made of a relatively soft material layer. The structure is sandwiched between the fourth interlayer insulating film 7 and the second film 38 of the passivation film 2. As a result, even if the Cu electrode layer 49 is thermally deformed and stress is generated at the interface between the Cu electrode layer 49 and the passivation film 2, such as when the semiconductor device 20 is flip-chip bonded to the conductive member 10, the stress is relaxed. be able to.

In this regard, the effect of stress relaxation was verified by simulation. The results are shown in FIGS. 19 and 20. FIG. 19 shows the Mises stress applied to the interface (Cu interface) between the Cu electrode layer 49 surrounded by the two-point chain line IXX in FIG. 17 and the second film 38 of the passivation film 2. FIG. 20 shows the Mises stress applied to the third electrode layer 16 (aluminum in the simulation), which is the uppermost layer wiring surrounded by the alternate long and short dash line XX of FIG.

Also, as a simulation condition,
(1) The fourth interlayer insulating film 7 is a SiO ₂ film (Young's modulus = 72,400 MPa),
(2) The first film 37 is a SiN film (Young's modulus = 320,000 MPa),
(3) The second film 38 is a SiO ₂ film (Young's modulus = 20,000 MPa),
(4) Total thickness of the first film 37 and the second film 38 = 1 μm
It was set. In addition, in FIGS. 19 and 20, "TYP" indicates that the second film 38 is absent, that is, the passivation film 2 is formed only of the SiN film.

From FIG. 19, by making the outermost surface of the passivation film 2 a SiO ₂ film, the Mises stress applied to the Cu interface was significantly reduced. In other words, the structure of the insulating layer just below the Cu electrode layer _49, a two-layer structure of SiO 2 + _SiN, by the sandwich structure of SiO 2 + SiN + SiO _2, was found to be alleviated Mises stress on the Cu interface.
Further, if the young ratio of the SiO ₂ film on the outermost surface of the passivation film 2 is set to about 20,000 MPa and the thickness ratio of the SiO ₂ film is 50% or less of the total thickness of the passivation film 2, FIG. As shown, it was found that the Mieses stress on the uppermost layer Al was also reduced.

From the above, in the above-mentioned structure of the semiconductor device 20, even if the Cu electrode layer 49 is thermally deformed and stress is generated at the interface between the Cu electrode layer 49 and the passivation film 2 when the semiconductor device 20 is packaged. , The stress can be relieved.
In particular, when the semiconductor device 20 is flip-chip mounted on the conductive member 10, stress is received from the Cu columnar body 18 and the conductive member 10, so that it is particularly effective for a flip-chip mounting package. This makes it possible to provide the semiconductor package A10 having excellent reliability.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
Further, in the above-described embodiment, only the form in which the semiconductor device 20 is flip-chip bonded is shown, but in the semiconductor device 20, the back surface of the semiconductor substrate 211 is bonded to the conductive member 10, and the pad electrode layer 51 and the conductive member 10 are bonded. Each lead of the above may be bonded by wire bonding.

In addition, various design changes can be made within the scope of the matters described in the claims.

A10 Semiconductor package 2 Passion film 3 Element forming surface 7 Fourth interlayer insulating film 10 Conductive member 16 Third electrode layer 18 Cu columnar body 20 Semiconductor device 23 Surface protective film 24 First layer 25 Second layer 30 Bonding layer 37 First film 38 Second film 40 Encapsulating resin 49 Cu Electrode layer 101 Main surface 102 Back surface 211 Semiconductor substrate 212 Semiconductor layer 221 Base 22 Columnar

Claims (20)

A semiconductor layer having a first surface and
A first insulating layer covering the first surface of the semiconductor layer and
The second insulating layer formed on the first insulating layer and
With the third insulating layer formed on the second insulating layer,
It contains a Cu conductive layer formed on the third insulating layer and made of a metal containing Cu as a main component.
A semiconductor device in which the first insulating layer and the third insulating layer are made of a material layer softer than the second insulating layer and sandwich the second insulating layer. The semiconductor device according to claim 1, wherein the thickness of the third insulating layer is 50% or less of the total thickness of the second insulating layer and the third insulating layer. It is covered with the first insulating layer and includes an Al wiring layer made of a metal containing Al as a main component.
The semiconductor device according to claim 1, wherein the thickness of the third insulating layer is 50% or less of the total thickness of the second insulating layer and the third insulating layer. Any one of claims 1 to 3, wherein the Young's modulus (MPa) of the first insulating layer and the third insulating layer measured in accordance with JIS K7161 is smaller than the Young's modulus of the second insulating layer. The semiconductor device according to the section. The semiconductor device according to claim 4, wherein the Young's modulus of the first insulating layer is larger than the Young's modulus of the third insulating layer. The Young's modulus of the first insulating layer is 60,000 MPa to 80,000 MPa.
The Young's modulus of the second insulating layer is 300,000 MPa to 350,000 MPa.
The semiconductor device according to claim 4 or 5, wherein the Young's modulus of the third insulating layer is 15,000 MPa to 30,000 MPa. It is covered with the first insulating layer and includes an Al wiring layer made of a metal containing Al as a main component.
The thickness of the third insulating layer is 50% or less of the total thickness of the second insulating layer and the third insulating layer.
The Young's modulus measured according to JIS K7161 of the first insulating layer is 60,000 MPa to 80,000 MPa.
The Young's modulus of the second insulating layer is 300,000 MPa to 350,000 MPa.
The semiconductor device according to claim 1, wherein the Young's modulus of the third insulating layer is 15,000 MPa to 30,000 MPa. The semiconductor device according to any one of claims 1 to 7, wherein the first insulating layer and the third insulating layer are made of an oxide film, and the second insulating layer is made of a nitride film. The semiconductor device according to claim 8, wherein the first insulating layer and the third insulating layer include any one of a SiO ₂ film and a SiO C film, and the second insulating layer contains a SiN film. The semiconductor device according to any one of claims 1 to 9, wherein the Cu conductive layer has a thickness of 2 μm to 6 μm. A fourth insulating layer formed on the third insulating layer and covering the Cu conductive layer,
The semiconductor device according to any one of claims 1 to 10, wherein the fourth insulating layer extends in the thickness direction and includes a conductive columnar body electrically connected to the Cu conductive layer. The semiconductor device according to claim 11, wherein the columnar body includes a Cu columnar body made of a metal containing Cu as a main component. The semiconductor device according to claim 11 or 12, wherein the columnar body has a thickness of 20 μm to 60 μm. The semiconductor device according to any one of claims 11 to 13, comprising a bonding layer formed on the columnar body and used for flip-chip bonding. The bonding layer includes a first layer formed on the columnar body and made of a metal containing Ni as a main component, and a second layer formed on the first layer and made of a metal containing solder as a main component. Including
The semiconductor device according to claim 14, wherein the second layer is used for flip-chip bonding. The semiconductor device according to claim 15, wherein the second layer is formed in a substantially spherical shape. A conductive member having a first surface and a second surface opposite to the first surface,
The semiconductor device according to any one of claims 11 to 16, which is flip-chip bonded to the first surface of the conductive member.
A semiconductor package including a part of the conductive member and a sealing resin covering the semiconductor device. A conductive member having a first surface and a second surface opposite to the first surface,
The semiconductor device according to any one of claims 11 to 16, which is mounted on the first surface of the conductive member and the columnar body is connected to the first surface of the conductive member.
A semiconductor package including a part of the conductive member and a sealing resin covering the semiconductor device. A conductive member having a first surface and a second surface opposite to the first surface,
The semiconductor device according to any one of claims 11 to 14, which is mounted on the first surface of the conductive member and the columnar body is connected to the first surface of the conductive member.
A bonding material formed between the conductive member and the columnar body and made of a metal containing solder as a main component,
A semiconductor package including a part of the conductive member, the semiconductor device, and a sealing resin covering the bonding material. The semiconductor package according to claim 19, wherein a part of the columnar body is embedded in the bonding material.

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