JP2020155640A - Module and manufacturing method thereof - Google Patents

Module and manufacturing method thereof Download PDF

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JP2020155640A
JP2020155640A JP2019053665A JP2019053665A JP2020155640A JP 2020155640 A JP2020155640 A JP 2020155640A JP 2019053665 A JP2019053665 A JP 2019053665A JP 2019053665 A JP2019053665 A JP 2019053665A JP 2020155640 A JP2020155640 A JP 2020155640A
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terminal
metal layer
layer
insulating layer
wiring
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Inventor
貴之 高野
Takayuki Takano
貴之 高野
裕一 笹島
Yuichi Sasajima
裕一 笹島
敏文 近藤
Toshifumi Kondo
敏文 近藤
修 水口
Osamu Mizuguchi
修 水口
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Fpc Connection Co Ltd
Taiyo Yuden Co Ltd
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Fpc Connection Co Ltd
Taiyo Yuden Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

To easily form a wiring having different thickness.SOLUTION: A module includes a first insulating layer, a first electronic component mounted on the lower surface of the first insulating layer and having a first terminal and a second terminal on the upper surface, a first metal layer that is provided on the inner surface of a first through hole penetrating the first insulating layer and the upper surface of the first insulating layer, and is connected to the first terminal and the second terminal of the first electronic component through the first through hole, a second insulating layer, a second metal layer attached to the lower surface of the second insulating layer, a conductive bonding layer that joins the upper surface of the first metal layer and the lower surface of the second metal layer, a first wiring that is connected to the first terminal and includes the first metal layer, the conductive bonding layer, and the second metal layer, and a second wiring that is connected to the second terminal and includes the first metal layer and does not include the second metal layer.SELECTED DRAWING: Figure 4

Description

本発明はモジュールおよびその製造方法に関し、例えば電子部品を搭載するモジュールおよびその製造方法に関する。 The present invention relates to a module and a manufacturing method thereof, for example, a module for mounting an electronic component and a manufacturing method thereof.

パワー半導体デバイスと制御デバイスが搭載されたモジュールにおいて、パワー半導体に接続される配線を厚くすることが知られている（例えば特許文献１）。 It is known that in a module in which a power semiconductor device and a control device are mounted, the wiring connected to the power semiconductor is thickened (for example, Patent Document 1).

米国特許出願公開第２００７／０２３５８１０号明細書U.S. Patent Application Publication No. 2007/0235810

電子部品に大電流を供給する配線と微小電流を供給する配線とでは厚さを異ならせることが好ましい。しかしながら、簡単な方法で厚い配線と薄い配線を形成することは難しい。 It is preferable that the wiring that supplies a large current to the electronic component and the wiring that supplies a minute current have different thicknesses. However, it is difficult to form thick wiring and thin wiring by a simple method.

本発明は、上記課題に鑑みなされたものであり、厚さの異なる配線を容易に形成することを目的とする、 The present invention has been made in view of the above problems, and an object of the present invention is to easily form wirings having different thicknesses.

本発明は、第１絶縁層と、前記第１絶縁層の下面に搭載され、上面に第１端子および第２端子を有する第１電子部品と、前記第１絶縁層を貫通する第１貫通孔の内面および前記第１絶縁層の上面に設けられ、前記第１貫通孔を介し前記第１電子部品の前記第１端子および前記第２端子と接続する第１金属層と、第２絶縁層と、前記第２絶縁層の下面に貼られた第２金属層と、前記第１金属層の上面と前記第２金属層の下面とを接合する導電性接合層と、前記第１端子と接続し、前記第１金属層、前記導電性接合層および前記第２金属層を含む第１配線と、前記第２端子と接続し、前記第１金属層を含み前記第２金属層を含まない第２配線と、を備えるモジュールである。 The present invention includes a first insulating layer, a first electronic component mounted on the lower surface of the first insulating layer and having a first terminal and a second terminal on the upper surface, and a first through hole penetrating the first insulating layer. A first metal layer provided on the inner surface and the upper surface of the first insulating layer and connected to the first terminal and the second terminal of the first electronic component through the first through hole, and a second insulating layer. , The second metal layer attached to the lower surface of the second insulating layer, the conductive bonding layer for joining the upper surface of the first metal layer and the lower surface of the second metal layer, and the first terminal are connected to each other. , The first wiring including the first metal layer, the conductive bonding layer and the second metal layer, and a second wiring including the first metal layer and not including the second metal layer connected to the second terminal. It is a module that includes wiring.

上記構成において、前記第１金属層はめっき金属層であり、前記第２金属層は圧延金属層またはめっき金属層である構成とすることができる。 In the above configuration, the first metal layer may be a plated metal layer, and the second metal layer may be a rolled metal layer or a plated metal layer.

上記構成において、前記第２金属層は、前記第２絶縁層より厚い構成とすることができる。 In the above configuration, the second metal layer can be thicker than the second insulating layer.

上記構成において、前記第２金属層は、前記第１金属層より厚い構成とすることができる。 In the above configuration, the second metal layer can be thicker than the first metal layer.

上記構成において、前記第１電子部品は下面に第３端子を有し、前記モジュールは、第３絶縁層と、前記第３絶縁層の上面に設けられ前記第３端子に接続する第３金属層と、を備える構成とすることができる。 In the above configuration, the first electronic component has a third terminal on the lower surface, and the module has a third insulating layer and a third metal layer provided on the upper surface of the third insulating layer and connected to the third terminal. And can be configured to include.

上記構成において、前記第１絶縁層の下面に搭載された第２電子部品および第３電子部品を備え、前記第１配線は、前記第１端子と前記第２電子部品の上面に設けられた第４端子とを接続し、前記第２配線は、前記第２端子と前記第３電子部品の上面に設けられた第５端子とを接続する構成とすることができる。 In the above configuration, a second electronic component and a third electronic component mounted on the lower surface of the first insulating layer are provided, and the first wiring is provided on the first terminal and the upper surface of the second electronic component. The 4 terminals may be connected, and the second wiring may be configured to connect the second terminal and the fifth terminal provided on the upper surface of the third electronic component.

上記構成において、前記第２絶縁層の上面に設けられ、前記第２絶縁層を貫通する第２貫通孔を介し前記第２金属層と接続された第４金属層を備える構成とすることができる。 In the above configuration, a fourth metal layer provided on the upper surface of the second insulating layer and connected to the second metal layer through a second through hole penetrating the second insulating layer can be provided. ..

上記構成において、前記第１電子部品は、トランジスタを含み、前記第１端子は前記トランジスタの制御端子以外の端子であり、前記第２端子は前記トランジスタの制御端子である構成とすることができる。 In the above configuration, the first electronic component may include a transistor, the first terminal may be a terminal other than the control terminal of the transistor, and the second terminal may be a control terminal of the transistor.

上記構成において、前記第１電子部品の上面と前記第１絶縁層の下面とを接合する樹脂接着層を備え、前記第１貫通孔は前記樹脂接着層を貫通する構成とすることができる。 In the above configuration, a resin adhesive layer for joining the upper surface of the first electronic component and the lower surface of the first insulating layer may be provided, and the first through hole may be configured to penetrate the resin adhesive layer.

本発明は、第１絶縁層を貫通する貫通孔の内面および前記第１絶縁層の上面に、前記第１絶縁層の下面に搭載された電子部品の上面に設けられた第１端子および第２端子に前記貫通孔を介し接続する第１金属層を形成する工程と、前記第１端子と接続し、前記第１金属層、導電性接合層および第２絶縁層の下面に貼られた第２金属層を含む第１配線と、前記第２端子と接続し、前記第１金属層を含み前記第２金属層を含まない第２配線と、が形成されるように、前記第１金属層の上面と前記第２金属層の下面とを前記導電性接合層を用い接合する工程と、を含むモジュールの製造方法である。 In the present invention, the first terminal and the second terminal provided on the inner surface of the through hole penetrating the first insulating layer and the upper surface of the first insulating layer, and on the upper surface of the electronic component mounted on the lower surface of the first insulating layer. A step of forming a first metal layer connected to the terminal via the through hole, and a second portion connected to the first terminal and attached to the lower surfaces of the first metal layer, the conductive bonding layer, and the second insulating layer. The first metal layer is connected so that the first wiring including the metal layer and the second wiring including the first metal layer and not including the second metal layer are formed by connecting to the second terminal. This is a method for manufacturing a module, which includes a step of joining an upper surface and a lower surface of the second metal layer using the conductive bonding layer.

本発明によれば、厚さの異なる配線を容易に形成することができる。 According to the present invention, wirings having different thicknesses can be easily formed.

図１（ａ）から図１（ｃ）は、実施例１に係るモジュールの製造方法を示す断面図（その１）である。1 (a) to 1 (c) are cross-sectional views (No. 1) showing a method of manufacturing a module according to the first embodiment. 図２（ａ）および図２（ｂ）は、実施例１に係るモジュールの製造方法を示す断面図（その２）である。2 (a) and 2 (b) are cross-sectional views (No. 2) showing a method of manufacturing the module according to the first embodiment. 図３（ａ）および図３（ｂ）は、実施例１に係るモジュールの製造方法を示す断面図（その３）である。3 (a) and 3 (b) are cross-sectional views (No. 3) showing a method of manufacturing the module according to the first embodiment. 図４（ａ）および図４（ｂ）は、実施例１に係るモジュールの製造方法を示す断面図（その４）である。4 (a) and 4 (b) are cross-sectional views (No. 4) showing a method of manufacturing the module according to the first embodiment. 図５は、実施例１に係るモジュールの製造方法を示す断面図（その５）である。FIG. 5 is a cross-sectional view (No. 5) showing a method of manufacturing the module according to the first embodiment. 図６は、実施例１に係るモジュールの製造方法を示す断面図（その６）である。FIG. 6 is a cross-sectional view (No. 6) showing a method of manufacturing the module according to the first embodiment. 図７は、実施例１に係るモジュールの製造方法を示す断面図（その７）である。FIG. 7 is a cross-sectional view (No. 7) showing a method of manufacturing the module according to the first embodiment. 図８は、実施例１に係るモジュールの平面図である。FIG. 8 is a plan view of the module according to the first embodiment. 図９は、実施例１に係るモジュールの平面図である。FIG. 9 is a plan view of the module according to the first embodiment. 図１０（ａ）および図１０（ｂ）は、実施例２に係るモジュールの製造方法を示す断面図（その１）である。10 (a) and 10 (b) are cross-sectional views (No. 1) showing a method of manufacturing the module according to the second embodiment. 図１１は、実施例２に係るモジュールの製造方法を示す断面図（その２）である。FIG. 11 is a cross-sectional view (No. 2) showing a method of manufacturing the module according to the second embodiment. 図１２は、実施例２に係るモジュールの平面図である。FIG. 12 is a plan view of the module according to the second embodiment.

以下、図面を参照し本発明の実施例について説明する。 Hereinafter, examples of the present invention will be described with reference to the drawings.

図１（ａ）から図７は、実施例１に係るモジュールの製造方法を示す断面図である。図１（ａ）に示すように、絶縁層１０の下面に接着剤１６を塗布する。絶縁層１０はポリイミド層等の樹脂層であり可撓性を有する。絶縁層１０の厚さは例えば７．５μｍから１２５μｍである。接着剤１６は例えばエポキシ樹脂接着剤等の樹脂接着剤である。接着剤１６は耐熱性および低誘電特性に優れた樹脂材料が好ましい。接着剤１６の塗布は、例えばスピンコート法、スプレコート法、インクジェット法またはスクリーン印刷法を用いる。接着剤１６の厚さは硬化後で例えば５μｍから５０μｍである。なお、予め接着剤１６が形成された絶縁層１０を用意してもよい。接着剤１６は、後述する電子部品４０、４２、シム４６および４８が配置される領域に対応して、選択的に塗布されていてもよい。 1 (a) to 7 are cross-sectional views showing a method of manufacturing a module according to the first embodiment. As shown in FIG. 1A, the adhesive 16 is applied to the lower surface of the insulating layer 10. The insulating layer 10 is a resin layer such as a polyimide layer and has flexibility. The thickness of the insulating layer 10 is, for example, 7.5 μm to 125 μm. The adhesive 16 is a resin adhesive such as an epoxy resin adhesive. The adhesive 16 is preferably a resin material having excellent heat resistance and low dielectric properties. The adhesive 16 is applied, for example, by using a spin coating method, a spray coating method, an inkjet method, or a screen printing method. The thickness of the adhesive 16 is, for example, 5 μm to 50 μm after curing. The insulating layer 10 on which the adhesive 16 is formed in advance may be prepared. The adhesive 16 may be selectively applied corresponding to the regions where the electronic components 40, 42, shims 46 and 48, which will be described later, are arranged.

図１（ｂ）に示すように、絶縁層１０および接着剤１６を貫通する貫通孔１２を形成する。貫通孔１２は、例えばレーザ光を照射することにより形成する。貫通孔１２の大きさは、例えば３０μｍから５００μｍである。 As shown in FIG. 1B, a through hole 12 penetrating the insulating layer 10 and the adhesive 16 is formed. The through hole 12 is formed by, for example, irradiating a laser beam. The size of the through hole 12 is, for example, 30 μm to 500 μm.

図１（ｃ）に示すように、接着剤１６の下面に電子部品４０および４２、シム４６および４８を配置する。電子部品４０の上面には、端子５１および５２が設けられ、電子部品４０の下面には端子５３が設けられている。電子部品４２の上面には端子５４および５６が設けられている。 As shown in FIG. 1 (c), the electronic components 40 and 42 and the shims 46 and 48 are arranged on the lower surface of the adhesive 16. Terminals 51 and 52 are provided on the upper surface of the electronic component 40, and terminals 53 are provided on the lower surface of the electronic component 40. Terminals 54 and 56 are provided on the upper surface of the electronic component 42.

電子部品４０は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）、バイポーラトランジスタまたはＦＥＴ（Field Effect Transistor）等のトランジスタである。トランジスタには、Ｓｉ、ＧａＮまたはＳｉＣ等の半導体が用いられる。電子部品４０は、例えばベアチップまたはベアチップが実装されたパッケージである。ベアチップが実装されたパッケージは、ＷＬＰ（Wafer Level Package）またはＳＩＰ（Single Inline Package）等のパッケージである。 The electronic component 40 is, for example, a transistor such as an IGBT (Insulated Gate Bipolar Transistor), a bipolar transistor, or a FET (Field Effect Transistor). A semiconductor such as Si, GaN or SiC is used as the transistor. The electronic component 40 is, for example, a bare chip or a package on which a bare chip is mounted. The package on which the bare chip is mounted is a package such as WLP (Wafer Level Package) or SIP (Single Inline Package).

電子部品４２は、例えば集積回路であり、電子部品４０を制御するコントローラであり、例えばベアチップまたはベアチップが実装されたパッケージである。端子５１〜５４および５６は、電子部品４０および４２の例えばベアチップまたはパッケージの表面に設けられたＣｕ（銅）、Ａｕ（金）、Ａｇ（銀）またはＡｌ（アルミニウム）等の金属を主材料とした金属層からなるパッドである。電子部品４０が縦型トランジスタの場合、ソース端子およびドレイン端子の一方が上面に設けられ、ソース端子およびドレイン端子の他方が下面に設けられる。シム４６および４８はＣｕ層等の金属層である。 The electronic component 42 is, for example, an integrated circuit, a controller for controlling the electronic component 40, and is, for example, a bare chip or a package on which a bare chip is mounted. The terminals 51 to 54 and 56 are mainly made of a metal such as Cu (copper), Au (gold), Ag (silver) or Al (aluminum) provided on the surface of the electronic components 40 and 42, for example, a bare chip or a package. It is a pad made of a metal layer. When the electronic component 40 is a vertical transistor, one of the source terminal and the drain terminal is provided on the upper surface, and the other of the source terminal and the drain terminal is provided on the lower surface. The shims 46 and 48 are metal layers such as a Cu layer.

熱処理することにより、接着剤１６を硬化させ電子部品４０、４２、シム４６および４８と絶縁層１０とを接合する。熱処理は例えば１５０℃から３００℃の温度で実施する。接着剤１６上に電子部品４０、４２、シム４６および４８を配置する前に熱処理し、接着剤１６のタック性を高めてもよい。端子５１〜５４および５６は貫通孔１２に露出する。 The heat treatment cures the adhesive 16 and joins the electronic components 40, 42, shims 46 and 48 and the insulating layer 10. The heat treatment is carried out at a temperature of, for example, 150 ° C to 300 ° C. The electronic components 40, 42, shims 46 and 48 may be heat-treated before being placed on the adhesive 16 to improve the tackiness of the adhesive 16. The terminals 51 to 54 and 56 are exposed in the through hole 12.

図２（ａ）に示すように、絶縁層１０の上面、貫通孔１２の内面に金属層１４を形成する。金属層１４の形成方法を説明する。絶縁層１０の上面、貫通孔１２の内面にシード層を形成する。シード層は、例えばスパッタリング法または無電解めっき法を用い形成する。シード層は、例えば絶縁層１０側からＴｉ、Ｃｒ、Ｎｉを主材料とする層およびＣｕを主材料とする層等の金属層である。シード層の上面にめっき層を形成する。めっき層は例えばＣｕ層等の金属層である。めっき層は、例えばシード層に電流を供給することによる電解めっき法を用い形成する。シード層およびめっき層により金属層１４が形成される。金属層１４の厚さは例えば数μｍから１２５μｍであり、貫通孔１２が埋め込まれる厚さとする。 As shown in FIG. 2A, a metal layer 14 is formed on the upper surface of the insulating layer 10 and the inner surface of the through hole 12. A method of forming the metal layer 14 will be described. A seed layer is formed on the upper surface of the insulating layer 10 and the inner surface of the through hole 12. The seed layer is formed by, for example, a sputtering method or an electroless plating method. The seed layer is, for example, a metal layer such as a layer containing Ti, Cr, and Ni as the main material and a layer containing Cu as the main material from the insulating layer 10 side. A plating layer is formed on the upper surface of the seed layer. The plating layer is a metal layer such as a Cu layer. The plating layer is formed by using, for example, an electrolytic plating method in which an electric current is supplied to the seed layer. The metal layer 14 is formed by the seed layer and the plating layer. The thickness of the metal layer 14 is, for example, several μm to 125 μm, and is the thickness at which the through hole 12 is embedded.

図２（ｂ）に示すように、金属層１４の上面に接合層２８を塗布する。接合層２８は、Ｃｕ粒子またはＡｇ粒子等の金属粒子等が含まれるＣｕペーストまたはＡｇペーストである。金属粒子の粒径が１μｍ未満のナノペーストでもよい。金属粒子は合金からなる粒子でもよい。接合層２８の塗布は、例えば印刷法、ディスペンス法またはインクジェット法を用いる。接合層２８は低温で焼結される金属でもよい。 As shown in FIG. 2B, the bonding layer 28 is applied to the upper surface of the metal layer 14. The bonding layer 28 is a Cu paste or Ag paste containing metal particles such as Cu particles or Ag particles. A nanopaste having a metal particle size of less than 1 μm may be used. The metal particles may be particles made of an alloy. The bonding layer 28 is applied by, for example, a printing method, a dispensing method or an inkjet method. The bonding layer 28 may be a metal that is sintered at a low temperature.

図３（ａ）に示すように、絶縁層２０の一方主面に金属層２４が形成された支持基板を準備する。絶縁層２０はポリイミド層等の樹脂層である。金属層２４は、例えばＣｕ層である。支持基板は、例えば銅張積層（ＣＣＬ：Copper Clad Laminate）基板であり、金属層２４は圧延された圧延金属層である。絶縁層２０の厚さは例えば７．５μｍから１２５μｍであり、金属層２４の厚さは例えば１０μｍから５０μｍである。 As shown in FIG. 3A, a support substrate having a metal layer 24 formed on one main surface of the insulating layer 20 is prepared. The insulating layer 20 is a resin layer such as a polyimide layer. The metal layer 24 is, for example, a Cu layer. The support substrate is, for example, a copper-clad laminate (CCL: Copper Clad Laminate) substrate, and the metal layer 24 is a rolled rolled metal layer. The thickness of the insulating layer 20 is, for example, 7.5 μm to 125 μm, and the thickness of the metal layer 24 is, for example, 10 μm to 50 μm.

絶縁層２０の全面に金属層２４を形成し、その後金属層２４を、フォトリソグラフィ法およびエッチング法を用いパターニングしてもよい。プレス等の機械加工により形成した金属層２４を絶縁層２０に張り付けてもよい。絶縁層２０と金属層２４との間に接着剤等が設けられていてもよい。接着剤は絶縁層２０の主面全体に形成されていてもよいし、絶縁層２０の主面のうち金属層２４が設けられた箇所に選択的に形成されていてもよい。 A metal layer 24 may be formed on the entire surface of the insulating layer 20, and then the metal layer 24 may be patterned by a photolithography method and an etching method. The metal layer 24 formed by machining such as pressing may be attached to the insulating layer 20. An adhesive or the like may be provided between the insulating layer 20 and the metal layer 24. The adhesive may be formed on the entire main surface of the insulating layer 20, or may be selectively formed on the main surface of the insulating layer 20 where the metal layer 24 is provided.

図３（ｂ）に示すように、絶縁層２０を貫通する貫通孔２２を形成する。貫通孔２２の形成方法は図１（ｂ）の貫通孔１２の形成方法と同様である。絶縁層２０の上面及び貫通孔２２の上面に金属層２６を形成する。金属層２６の形成方法は図２（ａ）の金属層１４の形成方法と同様にめっき法により形成される。これにより、金属層２６は貫通孔２２を介し金属層２４と接続する。金属層２４は例えば主にＣｕ層である。金属層２６の厚さは例えば数μｍから１２５μｍであり、貫通孔１２が埋め込まれる厚さとする。 As shown in FIG. 3B, a through hole 22 penetrating the insulating layer 20 is formed. The method for forming the through hole 22 is the same as the method for forming the through hole 12 in FIG. 1 (b). A metal layer 26 is formed on the upper surface of the insulating layer 20 and the upper surface of the through hole 22. The metal layer 26 is formed by a plating method in the same manner as the method for forming the metal layer 14 in FIG. 2 (a). As a result, the metal layer 26 is connected to the metal layer 24 via the through hole 22. The metal layer 24 is, for example, mainly a Cu layer. The thickness of the metal layer 26 is, for example, several μm to 125 μm, and is the thickness at which the through hole 12 is embedded.

図４（ａ）に示すように、図２（ｂ）の接合層２８の上面上に金属層２４の下面を接触させる。熱処理することで、接合層２８を焼成する。これにより、金属層１４と２４とが熱的、機械的かつ電気的に接合される。接合層２８の厚さは焼成後で例えば５μｍから５０μｍである。熱処理温度は例えば１５０℃から３００℃であり、絶縁層１０、２０、接着剤１６および絶縁層２０下の接着層が軟化または熱分解しない程度の温度とする。以上により、金属層１４、接合層２８および金属層２４により厚い配線８０および枠体８６が形成される。端子５１および５６は配線８０により金属層２６と電気的に接続される。端子５２と５４とは配線８２により電気的に接続される。枠体８６は、絶縁層１０および２０の周縁に設けられ、絶縁層１０および２０を支持する。 As shown in FIG. 4A, the lower surface of the metal layer 24 is brought into contact with the upper surface of the bonding layer 28 of FIG. 2B. By heat treatment, the bonding layer 28 is fired. As a result, the metal layers 14 and 24 are thermally, mechanically and electrically joined. The thickness of the bonding layer 28 is, for example, 5 μm to 50 μm after firing. The heat treatment temperature is, for example, 150 ° C. to 300 ° C., and is set to such a temperature that the insulating layers 10 and 20, the adhesive 16 and the adhesive layer under the insulating layer 20 do not soften or thermally decompose. As described above, the thick wiring 80 and the frame 86 are formed by the metal layer 14, the bonding layer 28, and the metal layer 24. The terminals 51 and 56 are electrically connected to the metal layer 26 by the wiring 80. The terminals 52 and 54 are electrically connected by wiring 82. The frame 86 is provided on the periphery of the insulating layers 10 and 20 and supports the insulating layers 10 and 20.

図４（ｂ）に示すように、絶縁層１０と２０との間の空間を樹脂６０を用い封止する。樹脂６０は、例えば熱硬化型樹脂または熱可塑性樹脂である。 As shown in FIG. 4B, the space between the insulating layers 10 and 20 is sealed with the resin 60. The resin 60 is, for example, a thermosetting resin or a thermoplastic resin.

図５に示すように、絶縁基板３０の上面および下面には金属層３４および３６が設けられている。絶縁基板３０は、例えばセラミックス基板である。金属層３４および３６は例えばＣｕ層である。絶縁基板３０、金属層３４および３６は電子部品４０の熱を放出するヒートシンクとして機能する。金属層３４上面に接合層３８を塗布する。接合層３８の材料は例えばＡｇペースト、Ｃｕペースト等の金属ペーストまたはロウ材である。金属ペーストの金属粒子は合金でもよい。 As shown in FIG. 5, metal layers 34 and 36 are provided on the upper surface and the lower surface of the insulating substrate 30. The insulating substrate 30 is, for example, a ceramic substrate. The metal layers 34 and 36 are, for example, Cu layers. The insulating substrate 30, the metal layers 34 and 36 function as a heat sink that releases heat from the electronic component 40. The bonding layer 38 is applied to the upper surface of the metal layer 34. The material of the bonding layer 38 is, for example, a metal paste such as Ag paste or Cu paste, or a brazing material. The metal particles of the metal paste may be an alloy.

図６に示すように、接合層３８の上面に電子部品４０、シム４６および４８の下面を接触させる。熱処理することで、接合層３８を焼成する。これにより、電子部品４０、シム４６および４８と金属層２４が熱的、機械的かつ電気的に接合される。接合層２８の厚さは焼成後で例えば５μｍから５０μｍである。熱処理温度は例えば１５０℃から３００℃であり、絶縁層１０、２０および接着剤１６が軟化または熱分解しない程度の温度とする。端子５３は、金属層３４、シム４６、配線８０を介し金属層２６に電気的に接続される。 As shown in FIG. 6, the upper surface of the bonding layer 38 is brought into contact with the lower surfaces of the electronic components 40, shims 46 and 48. The joint layer 38 is fired by heat treatment. As a result, the electronic components 40, shims 46 and 48 and the metal layer 24 are thermally, mechanically and electrically joined. The thickness of the bonding layer 28 is, for example, 5 μm to 50 μm after firing. The heat treatment temperature is, for example, 150 ° C. to 300 ° C., which is such that the insulating layers 10 and 20 and the adhesive 16 do not soften or thermally decompose. The terminal 53 is electrically connected to the metal layer 26 via the metal layer 34, the shim 46, and the wiring 80.

図７に示すように、絶縁層１０と絶縁基板３０との間の空間を樹脂６２により封止する。樹脂６２は、例えば熱硬化型樹脂または熱可塑性樹脂である。以上により実施例１に係るモジュールが完成する。 As shown in FIG. 7, the space between the insulating layer 10 and the insulating substrate 30 is sealed with the resin 62. The resin 62 is, for example, a thermosetting resin or a thermoplastic resin. With the above, the module according to the first embodiment is completed.

図４（ｂ）において封止樹脂６０を設けず、図７において、封止樹脂６０および樹脂６２を設けてもよい。 The sealing resin 60 may not be provided in FIG. 4B, and the sealing resin 60 and the resin 62 may be provided in FIG. 7.

図８および図９は、実施例１に係るモジュールの平面図である。図８は、貫通孔２２、金属層２４および２６を図示している。図９は、貫通孔１２、金属層１４、電子部品４０、４２、端子５１−５２、５４、５６、配線８０および８２を図示している。 8 and 9 are plan views of the module according to the first embodiment. FIG. 8 illustrates the through holes 22, the metal layers 24 and 26. FIG. 9 illustrates through holes 12, metal layers 14, electronic components 40, 42, terminals 51-52, 54, 56, wires 80 and 82.

図８および図９に示すように、電子部品４０ａおよび４０ｂおよび電子部品４２が設けられている。電子部品４０ａの上面には端子５１ａおよび５２ａが設けられ、電子部品４０ｂの上面には端子５１ｂおよび５２ｂが設けられている。電子部品４０ａおよび４０ｂは例えばパワー半導体素子であり縦型のトランジスタである。端子５１ａおよび５１ｂはソース端子であり、端子５２ａおよび５２ｂはゲート端子である。 As shown in FIGS. 8 and 9, electronic components 40a and 40b and electronic components 42 are provided. Terminals 51a and 52a are provided on the upper surface of the electronic component 40a, and terminals 51b and 52b are provided on the upper surface of the electronic component 40b. The electronic components 40a and 40b are, for example, power semiconductor elements and vertical transistors. The terminals 51a and 51b are source terminals, and the terminals 52a and 52b are gate terminals.

電子部品４２の上面には端子５４および５６が設けられている。電子部品４２は、トランジスタを制御する制御回路を有する。制御回路は、外部からの制御信号に基づき、トランジスタのゲート端子にゲート信号を出力する。端子５４は、端子５２ａおよび５２ｂにトランジスタのゲート信号を出力する端子である。端子５６は外部から制御信号を受信する端子である。 Terminals 54 and 56 are provided on the upper surface of the electronic component 42. The electronic component 42 has a control circuit that controls a transistor. The control circuit outputs a gate signal to the gate terminal of the transistor based on the control signal from the outside. The terminal 54 is a terminal that outputs a transistor gate signal to the terminals 52a and 52b. The terminal 56 is a terminal that receives a control signal from the outside.

金属層２６は、ソースパッドＰｓ、ドレインパッドＰｄおよび制御パッドＰｇを形成する。端子５１ａおよび５１ｂは貫通孔１２を介し配線８０ａに電気的に接続される。配線８０ａは貫通孔２２を介しソースパッドＰｓに電気的に接続される。端子５２ａおよび５２ｂは、貫通孔１２および配線８２ａを介し端子５４に電気的に接続される。端子５６は、貫通孔１２、２２および配線８０ｂおよび８２ｂを介し制御パッドＰｇに電気的に接続される。 The metal layer 26 forms a source pad Ps, a drain pad Pd, and a control pad Pg. The terminals 51a and 51b are electrically connected to the wiring 80a via the through hole 12. The wiring 80a is electrically connected to the source pad Ps via the through hole 22. The terminals 52a and 52b are electrically connected to the terminal 54 via the through hole 12 and the wiring 82a. The terminal 56 is electrically connected to the control pad Pg via the through holes 12, 22 and the wirings 80b and 82b.

電子部品４０ａおよび４０ｂの下面に設けられた端子５３は接合層３８、金属層３４、シム４６および配線８０ｃを介しドレインパッドＰｄに電気的に接続される。ドレインパッドＰｄには例えばグランド電位が供給される。 The terminals 53 provided on the lower surfaces of the electronic components 40a and 40b are electrically connected to the drain pad Pd via the bonding layer 38, the metal layer 34, the shim 46, and the wiring 80c. For example, a ground potential is supplied to the drain pad Pd.

トランジスタでは、ソース端子およびドレイン端子には大きな電流が流れる。ゲート端子は、ソース電流とドレイン端子との間の電流のスイッチングを行うゲート信号が入力する。このため、ソース端子のパッド面積は大きく、ゲート端子のパッド面積は小さい。ソース端子に接続される配線は、平面寸法は大きくてもよいが厚いことが要求される。ゲート端子に接続される配線は、薄くてもよいが平面寸法は小さいことが要求される。 In a transistor, a large current flows through the source terminal and the drain terminal. A gate signal that switches the current between the source current and the drain terminal is input to the gate terminal. Therefore, the pad area of the source terminal is large and the pad area of the gate terminal is small. The wiring connected to the source terminal may have a large planar dimension, but is required to be thick. The wiring connected to the gate terminal may be thin, but the plane size is required to be small.

実施例１では、配線８０ａはソースパッドＰｓとソース端子である端子５１ａおよび５１ｂとの間の電流の供給用の配線である。配線８０ｃはドレインパッドＰｄとドレイン端子である端子５３との間の電流の供給用の配線である。配線８２ａは制御回路の制御端子である端子５４とゲート端子である端子５２ａおよび５２ｂとの間の制御電圧または制御電流の供給用の配線である。配線８０ｂは、制御パッドＰｇと端子５６とを接続する配線であり、比較的大きな電流が流れる。 In the first embodiment, the wiring 80a is a wiring for supplying a current between the source pad Ps and the terminals 51a and 51b which are the source terminals. The wiring 80c is a wiring for supplying a current between the drain pad Pd and the terminal 53 which is a drain terminal. The wiring 82a is a wiring for supplying a control voltage or a control current between the terminal 54 which is a control terminal of the control circuit and the terminals 52a and 52b which are gate terminals. The wiring 80b is a wiring that connects the control pad Pg and the terminal 56, and a relatively large current flows through the wiring 80b.

実施例１では、ソース端子に接続される配線８０ａ、ドレイン端子に接続される配線８０ｃ、端子５６に接続される配線８０ｂを金属層１４と２４とで形成し、ゲート端子に接続される配線８２ａを金属層１４のみで形成する。これにより、簡単な工程で厚い配線８０ａから８０ｃと薄い配線８２を形成できる。 In the first embodiment, the wiring 80a connected to the source terminal, the wiring 80c connected to the drain terminal, and the wiring 80b connected to the terminal 56 are formed by the metal layers 14 and 24, and the wiring 82a connected to the gate terminal. Is formed only by the metal layer 14. Thereby, the thick wiring 80a to 80c and the thin wiring 82 can be formed by a simple process.

図１０（ａ）から図１１は、実施例２に係るモジュールの製造方法を示す断面図である。図１０（ａ）に示すように、図２（ｂ）および図３（ｂ）と同様に、絶縁層１０および２０を準備する。絶縁層１０の下面にシムは設けられていない。電子部品４０の下面に端子は設けられていない。電子部品４０が横型トランジスタの場合、ソース端子、ドレイン端子およびゲート端子はいずれも上面に設けられる。 10 (a) to 11 are cross-sectional views showing a method of manufacturing the module according to the second embodiment. As shown in FIG. 10 (a), the insulating layers 10 and 20 are prepared in the same manner as in FIGS. 2 (b) and 3 (b). No shim is provided on the lower surface of the insulating layer 10. No terminal is provided on the lower surface of the electronic component 40. When the electronic component 40 is a horizontal transistor, the source terminal, drain terminal, and gate terminal are all provided on the upper surface.

図１０（ｂ）に示すように、図４（ａ）と同様に接合層２８を用い金属層２４の下面と金属層１４の上面とを接合する。配線８０および枠体８６は各々金属層１４および２４を備え、配線８２は金属層１４を備え、金属層２４は備えていない。 As shown in FIG. 10B, the lower surface of the metal layer 24 and the upper surface of the metal layer 14 are joined by using the bonding layer 28 in the same manner as in FIG. 4A. The wiring 80 and the frame 86 include metal layers 14 and 24, respectively, and the wiring 82 includes a metal layer 14 and no metal layer 24.

図１１に示すように、図４（ｂ）と同様に、絶縁層１０と２０との間の空間を樹脂６０で封止する。これにより、実施例２に係るモジュールが完成する。 As shown in FIG. 11, the space between the insulating layers 10 and 20 is sealed with the resin 60 as in FIG. 4 (b). As a result, the module according to the second embodiment is completed.

図１２は、実施例２に係るモジュールの平面図である。図１２は、貫通孔１２、金属層１４、電子部品４０、４２、端子５１、５２、５４、５６、配線８０、８２および枠体８６を図示している。 FIG. 12 is a plan view of the module according to the second embodiment. FIG. 12 illustrates a through hole 12, a metal layer 14, electronic components 40, 42, terminals 51, 52, 54, 56, wirings 80, 82 and a frame 86.

図１２に示すように、電子部品４０ａおよび４０ｂおよび電子部品４２が設けられている。電子部品４０ａの上面には端子５１ａ、５１ｃおよび５２ａが設けられ、電子部品４０ｂの上面には端子５１ｂ、５１ｄおよび５２ｂが設けられている。電子部品４０ａおよび４０ｂは例えばパワー半導体素子でありトランジスタである。端子５１ａおよび５１ｂはソース端子であり、端子５１ｃおよび５１ｄはドレイン端子であり、端子５２ａおよび５２ｂはゲート端子である。 As shown in FIG. 12, electronic components 40a and 40b and electronic components 42 are provided. Terminals 51a, 51c and 52a are provided on the upper surface of the electronic component 40a, and terminals 51b, 51d and 52b are provided on the upper surface of the electronic component 40b. The electronic components 40a and 40b are, for example, power semiconductor elements and transistors. The terminals 51a and 51b are source terminals, the terminals 51c and 51d are drain terminals, and the terminals 52a and 52b are gate terminals.

端子５１ａと５１ｂとは配線８０ａにより電気的に接続され、絶縁層２０の上面のソースパッド（不図示）に電気的に接続される。端子５１ｃと５１ｄとは配線８０ｃにより電気的に接続され、絶縁層２０の上面のドレインパッド（不図示）に電気的に接続される。端子５２ａと５２ｂとは配線８２ａにより端子５４に電気的に接続される。その他の構成は実施例１と同じであり説明を省略する。 The terminals 51a and 51b are electrically connected by wiring 80a, and are electrically connected to a source pad (not shown) on the upper surface of the insulating layer 20. The terminals 51c and 51d are electrically connected by wiring 80c, and are electrically connected to a drain pad (not shown) on the upper surface of the insulating layer 20. The terminals 52a and 52b are electrically connected to the terminal 54 by the wiring 82a. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

実施例２のようにソース端子とドレイン端子とは電子部品４０の上面に設けられていてもよい。 As in the second embodiment, the source terminal and the drain terminal may be provided on the upper surface of the electronic component 40.

実施例１および２によれば、図２（ａ）のように、絶縁層１０（第１絶縁層）を貫通する貫通孔１２（第１貫通孔）の内面および絶縁層１０の上面に、金属層１４（第１金属層）を形成する。金属層１４は、絶縁層１０の下面に搭載された電子部品４０（第１電子部品）の上面に設けられた端子５１（第１端子）および端子５２（第２端子）に貫通孔１２を介し接続する。 According to Examples 1 and 2, as shown in FIG. 2A, metal is formed on the inner surface of the through hole 12 (first through hole) penetrating the insulating layer 10 (first insulating layer) and the upper surface of the insulating layer 10. Layer 14 (first metal layer) is formed. The metal layer 14 passes through a through hole 12 through a terminal 51 (first terminal) and a terminal 52 (second terminal) provided on the upper surface of the electronic component 40 (first electronic component) mounted on the lower surface of the insulating layer 10. Connecting.

図４（ａ）のように、金属層１４の上面と絶縁層２０（第２絶縁層）の下面に貼られた金属層２４（第２金属層）の下面とを接合層２８（導電性接合層）を用い接合する。これにより、配線８０（第１配線）は、端子５１と接続し、金属層１４、接合層２８および金属層２４を含むように形成され、配線８２（第２配線）は、端子５２と接続し、金属層１４を含み金属層２４を含まないように形成される。 As shown in FIG. 4A, the upper surface of the metal layer 14 and the lower surface of the metal layer 24 (second metal layer) attached to the lower surface of the insulating layer 20 (second insulating layer) are joined to the bonding layer 28 (conductive bonding). Layer) is used for joining. As a result, the wiring 80 (first wiring) is connected to the terminal 51 and is formed so as to include the metal layer 14, the bonding layer 28 and the metal layer 24, and the wiring 82 (second wiring) is connected to the terminal 52. , The metal layer 14 is included and the metal layer 24 is not included.

これにより、厚い配線８０と薄い配線８２を簡単な方法で形成できる。 Thereby, the thick wiring 80 and the thin wiring 82 can be formed by a simple method.

金属層１４はめっき金属層であり、金属層２４は圧延金属層またはめっき金属層である。ＣＣＬ等ですでに形成された金属層２４が貼り付けられた絶縁層２０を用いることで、金属層１４を形成するための工程時間が削減できる。特に、配線８０の厚さを１００μｍ以上、好ましくは２００μｍとする場合、工程時間が長くなる。そこで、ＣＣＬ等のめっき金属層または圧延金属層に追加でめっきを形成することにより、厚い配線８０を簡単に形成できる。配線８０を厚くするため、金属層２４は金属層１４より厚いことが好ましい。金属層２４の厚さは金属層１４の厚さの２倍以上がより好ましく、５倍以上がさらに好ましい。また、金属層２４は、絶縁層２０より厚いことが好ましい。金属層２４の厚さは絶縁層２０の厚さの２倍以上がより好ましく、５倍以上がさらに好ましい。 The metal layer 14 is a plated metal layer, and the metal layer 24 is a rolled metal layer or a plated metal layer. By using the insulating layer 20 to which the metal layer 24 already formed by CCL or the like is attached, the process time for forming the metal layer 14 can be reduced. In particular, when the thickness of the wiring 80 is 100 μm or more, preferably 200 μm, the process time becomes long. Therefore, the thick wiring 80 can be easily formed by additionally forming plating on the plated metal layer such as CCL or the rolled metal layer. In order to make the wiring 80 thicker, the metal layer 24 is preferably thicker than the metal layer 14. The thickness of the metal layer 24 is more preferably twice or more, more preferably five times or more the thickness of the metal layer 14. Further, the metal layer 24 is preferably thicker than the insulating layer 20. The thickness of the metal layer 24 is more preferably twice or more, more preferably five times or more the thickness of the insulating layer 20.

接着剤１６（樹脂接着層）は、電子部品４０および４２の上面と絶縁層１０の下面とを接合する。貫通孔１２は接着剤１６を貫通する。これにより、電子部品４０および４２は簡単に絶縁層１０に接合できる。 The adhesive 16 (resin adhesive layer) joins the upper surfaces of the electronic components 40 and 42 and the lower surface of the insulating layer 10. The through hole 12 penetrates the adhesive 16. As a result, the electronic components 40 and 42 can be easily joined to the insulating layer 10.

実施例１の図７のように、電子部品４０は下面に端子５３（第３端子）を有する。絶縁基板３０（第３絶縁層）は、上面に設けられ端子５３に接続する金属層３４（第３金属層）を備える。これにより、電子部品４０の下面の端子５３に電気的に接続することができる。 As shown in FIG. 7 of the first embodiment, the electronic component 40 has a terminal 53 (third terminal) on the lower surface. The insulating substrate 30 (third insulating layer) includes a metal layer 34 (third metal layer) provided on the upper surface and connected to the terminal 53. As a result, it can be electrically connected to the terminal 53 on the lower surface of the electronic component 40.

図９のように、絶縁層１０の下面に電子部品４０ａ（第１電子部品）、電子部品４０ｂ（第２電子部品）および電子部品４２（第３電子部品）が搭載されている。配線８０ａ（第１配線）は、端子５１ａと電子部品４０ｂの上面に設けられた端子５１ｂ（第４端子）とを接続する。配線８２ａ（第２配線）は、端子５２と電子部品４２の上面に設けられた端子５４（第５端子）とを接続する。これにより、大きな電流の流れる電子部品間の接続に厚い配線８０ａを用い、小さな電流が流れる電子部品間の接続に薄い配線８２ａを用いることがきる。 As shown in FIG. 9, an electronic component 40a (first electronic component), an electronic component 40b (second electronic component), and an electronic component 42 (third electronic component) are mounted on the lower surface of the insulating layer 10. The wiring 80a (first wiring) connects the terminal 51a and the terminal 51b (fourth terminal) provided on the upper surface of the electronic component 40b. The wiring 82a (second wiring) connects the terminal 52 and the terminal 54 (fifth terminal) provided on the upper surface of the electronic component 42. As a result, it is possible to use the thick wiring 80a for the connection between the electronic components through which a large current flows and the thin wiring 82a for the connection between the electronic components through which a small current flows.

金属層２６（第４金属層）は、絶縁層２０の上面に設けられ、絶縁層２０を貫通する貫通孔２２（第２貫通孔）を介し金属層２４と接続されている。これにより、配線８０を介し、端子５１を金属層２６に電気的に接続することができる。 The metal layer 26 (fourth metal layer) is provided on the upper surface of the insulating layer 20 and is connected to the metal layer 24 via a through hole 22 (second through hole) penetrating the insulating layer 20. As a result, the terminal 51 can be electrically connected to the metal layer 26 via the wiring 80.

電子部品４０は、トランジスタを含み、端子５１はトランジスタの制御端子以外の端子であり、端子５２はトランジスタの制御端子である。これにより、大きな電流の流れる制御端子以外の端子（電流が流入する端子および／または電流が流出する端子）に厚い配線８０を接続でき、小さな電流の流れる制御端子に薄い配線８２を接続できる。制御端子は、ゲート端子またはベース端子であり、制御端子以外の端子はソース端子、ドレイン端子、エミッタ端子またはコレクタ端子である。 The electronic component 40 includes a transistor, the terminal 51 is a terminal other than the control terminal of the transistor, and the terminal 52 is a control terminal of the transistor. As a result, the thick wiring 80 can be connected to terminals other than the control terminal through which a large current flows (terminal in which current flows and / or terminal in which current flows out), and thin wiring 82 can be connected to the control terminal through which a small current flows. The control terminal is a gate terminal or a base terminal, and terminals other than the control terminal are a source terminal, a drain terminal, an emitter terminal or a collector terminal.

以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。 Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

１０、２０ 絶縁層
１２、２２ 貫通孔
１４、２４、２６、３４、３６ 金属層
１６ 接着剤
２８、３８ 接合層
３０ 絶縁基板
４０、４０ａ、４０ｂ、４２ 電子部品
５１−５４、５６、５１ａ−５１ｄ 端子
６０、６２ 樹脂
８０、８２ 配線 10, 20 Insulation layer 12, 22 Through hole 14, 24, 26, 34, 36 Metal layer 16 Adhesive 28, 38 Bonding layer 30 Insulation substrate 40, 40a, 40b, 42 Electronic components 51-54, 56, 51a-51d Terminal 60, 62 Resin 80, 82 Wiring

Claims (10)

第１絶縁層と、
前記第１絶縁層の下面に搭載され、上面に第１端子および第２端子を有する第１電子部品と、
前記第１絶縁層を貫通する第１貫通孔の内面および前記第１絶縁層の上面に設けられ、前記第１貫通孔を介し前記第１電子部品の前記第１端子および前記第２端子と接続する第１金属層と、
第２絶縁層と、
前記第２絶縁層の下面に貼られた第２金属層と、
前記第１金属層の上面と前記第２金属層の下面とを接合する導電性接合層と、
前記第１端子と接続し、前記第１金属層、前記導電性接合層および前記第２金属層を含む第１配線と、
前記第２端子と接続し、前記第１金属層を含み前記第２金属層を含まない第２配線と、
を備えるモジュール。 With the first insulating layer
A first electronic component mounted on the lower surface of the first insulating layer and having a first terminal and a second terminal on the upper surface,
It is provided on the inner surface of the first through hole penetrating the first insulating layer and the upper surface of the first insulating layer, and is connected to the first terminal and the second terminal of the first electronic component through the first through hole. The first metal layer to be used
With the second insulating layer
The second metal layer attached to the lower surface of the second insulating layer and
A conductive bonding layer that joins the upper surface of the first metal layer and the lower surface of the second metal layer,
A first wiring that is connected to the first terminal and includes the first metal layer, the conductive bonding layer, and the second metal layer.
A second wiring that is connected to the second terminal and includes the first metal layer and does not include the second metal layer.
Module with. 前記第１金属層はめっき金属層であり、前記第２金属層は圧延金属層またはめっき金属層である請求項１に記載のモジュール。 The module according to claim 1, wherein the first metal layer is a plated metal layer, and the second metal layer is a rolled metal layer or a plated metal layer. 前記第２金属層は、前記第２絶縁層より厚い請求項１または２に記載のモジュール。 The module according to claim 1 or 2, wherein the second metal layer is thicker than the second insulating layer. 前記第２金属層は、前記第１金属層より厚い請求項１から３のいずれか一項に記載のモジュール。 The module according to any one of claims 1 to 3, wherein the second metal layer is thicker than the first metal layer. 前記第１電子部品は下面に第３端子を有し、
前記モジュールは、
第３絶縁層と、
前記第３絶縁層の上面に設けられ前記第３端子に接続する第３金属層と、
を備える請求項１から４のいずれか一項に記載のモジュール。 The first electronic component has a third terminal on the lower surface and has a third terminal.
The module
With the third insulating layer
A third metal layer provided on the upper surface of the third insulating layer and connected to the third terminal,
The module according to any one of claims 1 to 4. 前記第１絶縁層の下面に搭載された第２電子部品および第３電子部品を備え、
前記第１配線は、前記第１端子と前記第２電子部品の上面に設けられた第４端子とを接続し、
前記第２配線は、前記第２端子と前記第３電子部品の上面に設けられた第５端子とを接続する請求項１から４のいずれか一項に記載のモジュール。 A second electronic component and a third electronic component mounted on the lower surface of the first insulating layer are provided.
The first wiring connects the first terminal and the fourth terminal provided on the upper surface of the second electronic component.
The module according to any one of claims 1 to 4, wherein the second wiring connects the second terminal and the fifth terminal provided on the upper surface of the third electronic component. 前記第２絶縁層の上面に設けられ、前記第２絶縁層を貫通する第２貫通孔を介し前記第２金属層と接続された第４金属層を備える請求項１から６のいずれか一項に記載のモジュール。 Any one of claims 1 to 6 including a fourth metal layer provided on the upper surface of the second insulating layer and connected to the second metal layer through a second through hole penetrating the second insulating layer. The module described in. 前記第１電子部品は、トランジスタを含み、前記第１端子は前記トランジスタの制御端子以外の端子であり、前記第２端子は前記トランジスタの制御端子である請求項１から７のいずれか一項に記載のモジュール。 The first electronic component includes a transistor, the first terminal is a terminal other than the control terminal of the transistor, and the second terminal is a control terminal of the transistor according to any one of claims 1 to 7. Described module. 前記第１電子部品の上面と前記第１絶縁層の下面とを接合する樹脂接着層を備え、
前記第１貫通孔は前記樹脂接着層を貫通する請求項１から８のいずれか一項に記載のモジュール。 A resin adhesive layer for joining the upper surface of the first electronic component and the lower surface of the first insulating layer is provided.
The module according to any one of claims 1 to 8, wherein the first through hole penetrates the resin adhesive layer. 第１絶縁層を貫通する貫通孔の内面および前記第１絶縁層の上面に、前記第１絶縁層の下面に搭載された電子部品の上面に設けられた第１端子および第２端子に前記貫通孔を介し接続する第１金属層を形成する工程と、
前記第１端子と接続し、前記第１金属層、導電性接合層および第２絶縁層の下面に貼られた第２金属層を含む第１配線と、前記第２端子と接続し、前記第１金属層を含み前記第２金属層を含まない第２配線と、が形成されるように、前記第１金属層の上面と前記第２金属層の下面とを前記導電性接合層を用い接合する工程と、
を含むモジュールの製造方法。 The penetration through the inner surface of the through hole penetrating the first insulating layer and the upper surface of the first insulating layer, and the first terminal and the second terminal provided on the upper surface of the electronic component mounted on the lower surface of the first insulating layer. The process of forming the first metal layer connected through the holes and
The first wiring including the first metal layer, the conductive bonding layer, and the second metal layer attached to the lower surface of the second insulating layer, which is connected to the first terminal, and the second terminal are connected to the second terminal. The upper surface of the first metal layer and the lower surface of the second metal layer are joined by using the conductive bonding layer so that a second wiring containing one metal layer and not including the second metal layer is formed. And the process to do
How to manufacture a module, including.
JP2019053665A 2019-03-20 2019-03-20 Module and manufacturing method thereof Pending JP2020155640A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4020533A2 (en) 2020-12-25 2022-06-29 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing same
WO2022162875A1 (en) * 2021-01-29 2022-08-04 サンケン電気株式会社 Semiconductor power module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4020533A2 (en) 2020-12-25 2022-06-29 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing same
US11742272B2 (en) 2020-12-25 2023-08-29 Shinko Electric Industries Co., Ltd. Semiconductor device
WO2022162875A1 (en) * 2021-01-29 2022-08-04 サンケン電気株式会社 Semiconductor power module

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