JP2020144637A - Detection device, generation device, detection system, detection method, and detection program - Google Patents

Abstract

To provide a detection device and the like that enable detection of a bit error by means of a smaller-scale code generating circuit.SOLUTION: The detection device comprises: a receiving side exclusive OR generation unit to generate a second exclusive OR between a first exclusive OR obtained by first reception via a data path and second information obtained by second reception via the data path or information derived from the second information; and an output unit to output an inspection result regarding an inspection by the second exclusive OR of first information obtained by third reception via the data path. Each piece of data of the first exclusive OR is generated from a redundant code generated from the first information prior to transmission regarding the third reception and the second information prior to transmission regarding the second reception or the information derived from the second information prior to transmission regarding the second reception.SELECTED DRAWING: Figure 4

Description

The present invention relates to bit error detection.

When the input digital information passes through the data path, a bit error may occur in which the received information is different from the transmitted information due to wiring defects or signal fluctuations that occur in the data path. Then, in order to detect a bit error, a bit error detection method is generally used in which a redundant code generated on the transmitting side is separately sent to the receiving side through a data path, and the receiving side verifies the correctness of the received information. ing.

FIG. 1 is a conceptual diagram showing the configuration of a bit error detection system 500, which is an example of a general bit error detection system that verifies the presence or absence of bit errors in received information by using a redundant code. In the present specification, the bit error detection system means a system that detects that a bit error has occurred when a bit error occurs in the information sent from the transmitting side to the receiving side via the data path. To do.

In FIG. 1, it is assumed that two types of digital information, information A [31: 0] and information B [6: 0], are sent from the transmitting side 191 to the receiving side 291 via the data path 301. There is.

In addition, a of [a: b] attached to the information is the maximum value of a value representing a bit position (hereinafter, referred to as "maximum bit"), and b is a value representing the minimum value of a value representing a bit position (hereinafter, "maximum bit"). Hereinafter, it is referred to as “minimum bit”), and this point is the same in each of the figures after FIG. The value obtained by subtracting the minimum bit from the maximum bit and adding 1 is the bit length (bit width). Hereinafter, the fact that the bit length is a bit (a is an integer) may be simply referred to as "a bit". Information A is 32-bit information having a minimum bit of 0 and a maximum bit of 31. Information B is 7-bit information having a minimum bit of 0 and a maximum bit of 6.

The bit error detection system 500 includes a transmitting side data processing unit 101 and a receiving side data processing unit 201. The transmission side data processing unit 101 includes code generation units 1061 and 1062. The receiving side data processing unit 201 includes bit error detection units 2261 and 2262.

The information A is sent from the transmitting side 191 to the receiving side 291 via the data path 301, and is input to the code generation unit 1061 of the transmitting side 191. The information A is sent from the transmitting side 191 to the receiving side 291 by the communication line 801 and is input to the code generation unit 1061 by the communication line 802. Each of the communication lines 801 and 802 is a wiring group consisting of 32 wirings. Then, the data of each bit position of the information A is sent to the receiving side 291 through different wirings at the same timing, and is input to the code generation unit 1061.

The code generation unit 1061 generates, for example, a 7-bit redundant code from the input 32-bit information A data. The 7-bit redundant code corresponds to the case where the redundant code is ECC (Error Correction Code) of Non-Patent Documents 1 and 2. Hereinafter, when the redundant code is other than the ECC of Non-Patent Documents 1 and 2, the bit length of the redundant code may be another value. The ECC of Non-Patent Documents 1 and 2 enables the receiving side to determine whether or not there is a bit error in the received information depending on whether or not the decrypted data of the received information by the ECC becomes zero.

The bit error detection unit 2261 decodes 32-bit information A with a 7-bit redundant code. The decoding method is based on the method corresponding to the code generated by the code generation unit 1061. Then, the bit error detection unit 2261 decodes the information A with a redundant code. Then, the bit error detection unit 2261 determines whether or not a bit error has occurred in the information A by inspecting the decoded data. When the redundant code is the ECC of Non-Patent Documents 1 and 2, the decoding performed by the bit error detection unit 2261 is to obtain the product of the data obtained by adding the ECC to the information A and the inspection matrix. Then, the bit error detection unit 2261 determines that a bit error has occurred in the information A when the product of the data obtained by adding ECC to the information A and the inspection matrix does not become a zero matrix. Then, the bit error detection unit 2261 outputs the determination result.

The same applies to the information B, and the information B is sent from the transmitting side 191 to the receiving side 291 via the data path 301, and is input to the code generation unit 1062 on the transmitting side 191. The information B is sent from the transmitting side 191 to the receiving side 291 by the communication line 806, and is input to the code generation unit 1062 by the communication line 807. Each of the communication lines 806 and 807 is a wiring group consisting of seven wires. Then, the data at each bit position of the information B is sent to the receiving side 291 through different wirings of the communication lines 806 and 807 at the same timing, and is input to the code generation unit 1062.
The code generation unit 1061 of the transmission side data processing unit 101 generates a 7-bit redundant code from the information B having a bit length of 7. Then, the bit error detection unit 2262 decodes the received information B with the similarly received redundant code. Then, the bit error detection unit 2062 examines whether or not the product of the data obtained by adding ECC to the information A and the inspection matrix becomes a zero matrix, and determines whether or not a bit error has occurred.

When the bit error detection units 2061 and 2062 determine the occurrence of a bit error, the case where the redundant code generated by the code generation units 1061 and 1062 is changed in the data path 301 is included. In that case, the bit error detection units 2061 and 2062 erroneously detect the bit error even if the bit error does not occur in the information A and B.

Next, the data based on AXI ^TM, the common bit error detection system for verifying the ECC data in the non-patent document 1 and 2 in the case of sending via a data path will be described. Here, AXI ^TM is a standard for buses proposed by ARM ^TM and is well known (see Non-Patent Document 3).

2, the data conforming to AXI ^TM, bit error detection system 500 is an example of a typical bit error detection system for verifying the ECC data in the non-patent document 1 and 2 in the case of sending via a data path It is a conceptual diagram which shows the structure.

The bit error detection system 500 includes a transmitting side data processing unit 101 and a receiving side data processing unit 201. The transmission side data processing unit 101 includes ECC code generation units 1063 to 1065. Further, the receiving side data processing unit 201 includes bit error detecting units 2063 to 2065. The description of the data path 301 shown in FIG. 2 is the same as the description of the data path shown in FIG.

A total of eight types of information are sent from the transmitting side 191 to the receiving side 291. These eight types of information are ARADDR, ARID, ARSIDZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT and ARUSER. The contents of this information is known and defined in AXI ^TM (see Non-Patent Document 3). The communication line to which each information is sent is a wiring group consisting of a number of wires corresponding to the bit width of each information. The data at each bit position of each information is sent at the same timing through different wiring of the communication line.

The ARADDR is sent from the transmitting side 191 to the receiving side 291 and is input to the ECC code generation unit 1063 of the transmitting side 191. The ECC code generator 1063 generates ARADDR_ECC, which is a 7-bit ECC redundant code, from 32-bit ARADDR. ARADDR_ECC is sent to the bit error detection unit 2063 via the data path 301.

The bit error detection unit 2063 decodes the ARADDR sent from the transmitting side 191 by the ARADDR_ECC sent from the ECC code generation unit 1063. The decoding is to obtain the product of the data obtained by adding ARADDR_ECC to ARADDR and the inspection matrix corresponding to ECC. Then, the bit error detection unit 2063 checks whether or not the product is a zero matrix, and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in ARADDR.

Further, ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE and ARPROT are sent from the transmitting side 191 to the receiving side 291. These are also input to the ECC code generation unit 1064. The ECC code generation unit 1064 generates set data in which ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, and ARPROT are combined in this order. Here, it is assumed that the bit width of the set data does not exceed 32 bits. When the bit width of the set data is smaller than 32 bits, the code generation unit 1046 adds 0 bits to the set data to generate 32-bit transmitter set data. Then, the ECC code generation unit 1064 generates ARNFO_ECC, which is a 7-bit ECC redundant code, from the 32-bit transmission side set data. ARNFO_ECC is sent from the transmitting side 191 to the bit error detecting unit 2064 of the receiving side 291.

The bit error detection unit 2064 sequentially combines ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, and ARPROT sent from the transmitting side 191. Then, the bit error detection unit 2064 further generates 32-bit receiving side set data in which 0 bits are added as needed. Then, the bit error detection unit 2064 decodes the receiving side set data by the ARNFO_ECC sent from the ECC code generation unit 1064. In the decoding, the product of the data obtained by adding ARNFO_ECC to the receiving side set data and the inspection matrix corresponding to the ECC is obtained. Then, the bit error detection unit 2064 checks whether or not the product is a zero matrix, and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in the receiving side set data.

Further, an n-bit ARUSER is sent from the transmitting side 191 to the receiving side 291. It is assumed that n is a number of 32 or less. ARUSER is also input to the ECC code generator 1065. When the bit width of ARUSER is smaller than 32 bits, the code generation unit 105 adds 0 bits to ARUSER to generate 32-bit second transmitter set data. Then, the ECC code generation unit 1064 generates ARUSER_ECC, which is a 7-bit ECC redundant code, from the 32-bit second transmission side correction set data. ARUSER_ECC is sent from the transmitting side 191 to the bit error detecting unit 2065 of the receiving side 291.

The bit error detection unit 2065 generates 32-bit second receiving side set data in which 0 bits are added to the ARUSER sent from the transmitting side 191 as needed. Then, the bit error detection unit 2065 decodes the second receiving side set data by the ARUER_ECC sent from the ECC code generation unit 1065. The decoding is to obtain the product of the data obtained by adding ARCHER_ECC to the second receiving side set data and the inspection matrix corresponding to ECC. Then, the bit error detection unit 2065 checks whether or not the product is a zero matrix, and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in the second receiving side set data.

Patent Document 1 discloses a data storage device that generates a new redundant code that includes auxiliary data related to data without increasing the bit length of the redundant code, and detects auxiliary data from the new redundant code.

Japanese Unexamined Patent Publication No. 07-253934

CortexTM-R4 and Cortex-R4F Technical Reference Manual Revisions: r1p3, 8.2.2. Error checking and correction, arm, [searched on February 20, 2019], Internet (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363fj/index. html) Introduction to Coding Theory (14th), Application of Coding Theory to Computer Technology, Journal of Television Society Vol. 45, No9, pp. 1089-1094 (1991). AMBATM AXITM and ACETM Protocol Specification, AX13TM, AX14TM and AX14-LiteTM, ACE and ACE-LiteTM, ARM, [Search February 20, 2019], Internet (http://www.ttp://www. courses / fall15 / eel4720_5721 / labs / refs / AXI4_speciation.pdf)

The bit error detection system 500 shown in FIG. 2 includes three code generators on the transmitting side and three bit error detecting units on the receiving side, and the number of them is larger than that shown in FIG. It is increasing. In FIG. 2, the range of data for detecting bit errors is expanded as compared with FIG. 1, but if the range of data for detecting bit errors is expanded in this way, it is redundant in a general bit error detection system. The scale of the circuit required for code generation and decoding increases. An increase in the circuit scale leads to an increase in cost.

An object of the present invention is to provide a detection device or the like that enables detection of a bit error with a smaller code generation circuit.

The detection device of the present invention is the first of the first exclusive OR received via the data path and the second information received second via the data path or the information derived from the second information. (Ii) The receiving side exclusive OR generator that generates the exclusive OR, and the output that outputs the inspection result related to the inspection by the second exclusive OR of the first information received third via the data path. Each data of the first exclusive OR is provided with a redundant code generated from the first information before the transmission related to the third reception and before the transmission related to the second reception. It is generated by the second information or the information derived from the second information before the transmission related to the second reception.

The detection device and the like of the present invention enable detection of bit errors with a smaller code generation circuit.

It is a conceptual diagram which shows the configuration example (the 1) of the general bit error detection system. It is a conceptual diagram which shows the configuration example (the 2) of the general bit error detection system. It is a conceptual diagram which shows the configuration example (the 1) of the bit error detection system of this embodiment. It is a conceptual diagram which shows the configuration example (the 2) of the bit error detection system of this embodiment. It is a conceptual diagram which shows the structural example of the transmission side data conversion part. It is a conceptual diagram which shows the structural example of the receiving side data conversion part. It is a conceptual diagram which shows the input data example (the 1) to the transmission side EXOR circuit. It is a conceptual diagram which shows the input data example (the 1) to the receiving side EXOR circuit. It is a conceptual diagram which shows the power example (the 2) of the data to the transmission side EXOR circuit. It is a conceptual diagram which shows the input data example (the 2) to the receiving side EXOR circuit. It is a conceptual diagram which shows the power example (the 3) of the data to the transmission side EXOR circuit. It is a conceptual diagram which shows the input data example (the 3) to the receiving side EXOR circuit. It is a conceptual diagram which shows the power example (the 4) of the data to the transmission side EXOR circuit. It is a conceptual diagram which shows the input data example (the 4) to the receiving side EXOR circuit. It is a block diagram which shows the structure of the minimum detection apparatus of embodiment.

The bit error detection system of the present embodiment generates the first exclusive OR of the redundant code generated from the first information and the second information on the transmitting side. Here, the first and second information are information sent from the transmitting side to the receiving side via the data path. Then, the bit error detection system generates a second exclusive OR based on the first exclusive OR received on the receiving side and the second information also received. Then, the bit error detection system decodes the data at each bit position of the received first information by the second exclusive OR. The bit error detection system further checks whether the relationship between the decrypted data and the received first information is set for the redundant code.

In the above case, if a bit error occurs in the first information in the data path, the received first information data is different from that before transmission. Further, when a bit error occurs in the second data after reception, the second exclusive OR is different from the redundant code. Therefore, the relationship between the decrypted data and the first information is different from that set for the redundant code. Therefore, in the bit error detection system, the relationship between the first information after decoding and the first information before decoding is set regardless of whether a bit error occurs in either the first information or the second information. By detecting the difference, it is possible to detect that a bit error has occurred.

Here, the bit error detection system of the present embodiment does not generate or decode the redundant code for the second information. Therefore, the bit error detection system of the present embodiment does not require a configuration for generating and decoding a redundant code for the second information. That is, the bit error detection system of the present embodiment can detect a bit error by configuring a smaller code generation circuit and decoding circuit.

Hereinafter, the details of the bit error detection system of the present embodiment will be described with reference to the drawings.

FIG. 3 is a conceptual diagram showing the configuration of the bit error detection system 500, which is an example of the bit error detection system of the present embodiment. The explanations of the information A and B and the data path 301 in FIG. 3 are the same as those in FIG. 1 except for the following explanations.

The information A is the above-mentioned first information used for generating the redundant code. Further, the information B is the above-mentioned second information that generates an exclusive OR with the redundant code.

The bit error detection system 500 includes a transmitting side data processing unit 101 and a receiving side data processing unit 201.

The transmission side data processing unit 101 includes a code generation unit 1061 and a transmission side data conversion unit 118. The transmission side data conversion unit 118 includes transmission side EXOR circuits 1210 to 1216.

The receiving side data processing unit 201 includes a receiving side data conversion unit 218 and a bit error detecting unit 2061. The receiving side data conversion unit 218 includes receiving side EXOR circuits 2210 to 2216.

The information A is sent from the transmitting side 191 to the receiving side 291 via the data path 301, and is input to the code generation unit 1061 on the transmitting side 191. The information A is sent from the transmitting side 191 to the receiving side 291 by the communication line 801 and is input to the code generation unit 1061 by the communication line 802. Each of the communication lines 801 and 802 is a wiring group consisting of 32 wirings. Then, the data at each bit position of the information A is sent to the receiving side 291 through different wirings of the communication lines 801 and 802 at the same timing, and is input to the code generation unit 1061.

On the other hand, the information B is sent from the transmitting side 191 to the receiving side 291 via the data path 301, and is input to each EXOR circuit of the transmitting side data conversion unit 118 on the transmitting side 191. Information B is sent from the transmitting side 191 to the receiving side 291 by the communication line 806. The communication line 806 is a wiring group consisting of seven wirings. Then, the data at each bit position of the information B is sent to the receiving side 291 through different wirings of the communication line 806 at the same timing. Further, the communication line 807 on the left side of the position 991 and the seven wires on the right side are simply different notations of the same wiring.

The code generation unit 1061 generates a 7-bit redundant code from the input 32-bit information A, similarly to the code generation unit 1061 shown in FIG. The 7-bit redundant code corresponds to the case where the redundant code is ECC of Non-Patent Documents 1 and 2. When the redundant code is other than the ECC of Non-Patent Documents 1 and 2, the bit width of the redundant code may be another value.

The code generation unit 1061 inputs the data of each bit position of the generated 7-bit redundant code to the transmitting side EXOR circuits 1210 to 1216 at the same timing. The timing is, for example, a clock timing. When the number of integers in [] is one, the integer represents the bit position of the target data.

Each of the transmitting EXOR circuits 1210 to 1216 outputs the first exclusive OR, which is the exclusive OR of the two input data. Since the configuration of the circuit that outputs the exclusive OR of the input data is well known, the description thereof is omitted here. The first exclusive OR output from the transmitting side EXOR circuits 1210 to 1216 is sent to the receiving side 291 via the data path 301.

The first exclusive OR sent to the receiving side 291 is input to each of the receiving side EXOR circuits 2210 to 2216 at the same timing.

The information A sent to the receiving side 291 is sent to the outside and is also input to the bit error detection unit 2061. The external device is, for example, another device that uses information A. On the other hand, the information B sent to the receiving side 291 is sent to the outside and input to each of the receiving side EXOR circuits 2210 to 2216. The external device is, for example, another device that uses information B. The communication line 808 on the left side of the position 992 and the seven wires on the right side represent the same wiring in different notations.

The receiving EXOR circuits 2210 to 2216 output the second exclusive OR, which is the exclusive OR of the two data input at the same timing.

The second exclusive OR output from the receiving EXOR circuits 2210 to 2216 is input to the bit error detection unit 2061.

Like the communication line 801 the communication line 803 is a wiring group consisting of 32 wires. Then, the data of each bit position of the information A is input to the bit error detection unit 2061 through different wirings of the communication line 803 at the same timing.

The bit error detection unit 2061 decodes the input information A by the code consisting of the input second exclusive OR. Then, the bit error detection unit 2061 determines whether or not the decoding information is set for the redundant code generated by the code generation unit 1061. The bit error detection unit 2061 outputs the determination result to the outside.

Here, the following three cases are assumed as the case where the bit error detection unit 2061 detects the bit error.

In the above case, first, the information A is changed in the data path 301.

In the above case, the second is the case where the information B is changed in the data path. In this case, for the first exclusive OR derived by each transmitting side EXOR circuit, even if the second exclusive OR is further derived by each receiving side EXOR circuit, the second exclusive OR is code-generated. It does not return to the redundant code generated by part 1061. Therefore, the decrypted information A is not set for the redundant code generated by the code generation unit 1061.

In the above case, the third is the case where the first exclusive OR sent from the transmitting side 191 to the receiving side 291 is changed in the data path 301. In this case, even if the information A and B do not have a bit error, the bit error is detected by false detection.

The bit error detection system 500 shown in FIG. 3 can detect any bit error of the information A and B depending on the first and second cases.

Further, in the configuration of FIG. 1, there are two code generation units 1061 and 1062, and the bit error detection unit is also two bit error detection units 2061 and 2062. On the other hand, in the configuration of FIG. 3, there is one code generation unit 1061 and one bit error detection unit 2061. Therefore, the bit error detection system 500 shown in FIG. 3 can simplify the circuit configuration for generating and decoding the redundant code.

In the configuration of FIG. 3, as the third case, there may be a erroneous detection of a bit error due to a bit error in the data path 301 of the first exclusive OR. This corresponds to erroneous detection of a bit error due to a bit error in the data path 301 of the redundant code in the configuration of FIG. However, the number of bits of the first exclusive OR sent in the configuration of FIG. 3 is 7, which is less than the number of bits of the redundant code sent in the configuration of FIG. 1. Therefore, the probability of occurrence of the bit error of the first exclusive OR in the configuration of FIG. 3 is considered to be smaller than that of the configuration of FIG. Therefore, the configuration of FIG. 3 can reduce the probability of erroneous detection of a bit error as compared with the configuration of FIG.

FIG. 4 shows a bit error detection system 500 which is an example of the bit error detection system of the present embodiment in which the data in the case of transmitting the data conforming to AXI via the data path is verified by the ECC of Non-Patent Documents 1 and 2. It is a conceptual diagram which shows the structure of.

The bit error detection system 500 includes a transmitting side data processing unit 101 and a receiving side data processing unit 201. The transmission side data processing unit 101 includes an ECC code generation unit 106 and a transmission side data conversion unit 118. Further, the receiving side data processing unit 201 includes a bit error detecting unit 206 and a receiving side data conversion unit 218.

A total of eight types of information are sent from the transmitting side 191 to the receiving side 291. These eight types of information are ARADDR, ARID, ARSIDZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT and ARUSER. The contents of this information is known and defined in AXI ^TM. The communication line to which each information is sent is a wiring group consisting of a number of wires corresponding to the bit width of each information. The data at each bit position of each information is sent at the same timing through different wiring of the communication line.

Of these, ARADDR is information on the generator of the ECC redundant code, and is the first information described above. Further, ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, ARPROT, and ARUSER are the above-mentioned second information that does not generate a redundant code.

The first information, ARADDR, is sent from the transmitting side 191 to the receiving side 291 and is input to the ECC code generation unit 106 on the transmitting side 191. The ECC code generator 106 generates ARADDR_ECC, which is a 7-bit ECC redundant code, from 32-bit ARADDR. ARADDR_ECC is input to the transmission side data conversion unit 118.

Second information, ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, ARPROT, and ARUSER, are also input to the transmission side data conversion unit 118.

The transmitting side data conversion unit 118 derives the 7-bit ARADDR_ECC which is the exclusive OR of each bit of the 7-bit ARADDR_ECC and the data constituting the second information or the reduced data of the second information. A configuration example of the transmission side data conversion unit 118 will be described later with reference to FIGS. 5, 7, 9, 11, and 13. An example of inputting degenerate data will be described later with reference to FIGS. 11 and 13.

ARADDR_ECC is sent to the receiving side 291 via the data path 301.

AR_ECC and the second information are input to the receiving side data conversion unit 218 of the receiving side 291. The second information is ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, ARPROT and ARUSER as described above.

The receiving side data conversion unit 218 is a 7-bit second exclusive sum which is an exclusive logical sum of each bit of the 7-bit AR_ECC and the data at each bit position constituting the second information or the reduced data of the second information. Derivation of the logical sum. At the time of the derivation, each bit of AR_ECC and the data of that bit used for performing the exclusive OR calculation with ARADDR_ECC by the transmitting side data conversion unit 118 after passing through the data path 301. An exclusive OR operation between and is performed. The second exclusive OR is input to the bit error detection unit 206. A configuration example of the receiving side data conversion unit 218 will be described later with reference to FIGS. 6, 8, 10, 12, and 14.

In addition to the second exclusive OR, ARADDR, which is the first information after passing through the data path 301, is input to the bit error detection unit 206.

The bit error detection unit 206 decodes ARADDR, which is the first information, using the input 7-bit second exclusive OR as the decoding code. The decoding is to obtain the product of the data obtained by adding the second exclusive OR to ARADDR and the check matrix corresponding to ECC. Then, the bit error detection unit 206 checks whether or not the product is a zero matrix, and outputs the result. The case where the product is not a zero matrix is either a case where a bit error has occurred in the first ARADDR or a case where the second exclusive OR is not equal to the ECC generated by the ECC code generator 106. Then, when the second exclusive OR is not equal to the ECC generated by the ECC code generation unit 106, a case where a bit error occurs in the second information is included. Therefore, when the bit error detection unit 206 outputs a determination result that the product is not a zero matrix, a case where a bit error occurs in any of the first information and the second informatization is included.

FIG. 5 is a conceptual diagram showing a configuration example of the transmission side data conversion unit 118 shown in FIG.

The transmission side data conversion unit 118 includes transmission side EXOR circuits 1210 to 1216.

The data at each bit position of the 7-bit ARADDR_ECC is input to each of the transmitting side EXOR circuits 1210 to 1216. The number at the end of the code of the transmitting side EXOR circuit 1210 to 1216 corresponds to the bit position in ARADDR_ECC of the input data.

On the other hand, for the data at each bit position of the second information, the selection of the input transmission side EXOR circuit is arbitrary. An example of such selection will be described later with reference to FIGS. 7, 9 and 13.

Further, the predetermined data range of the second information may be converted into degenerate data and input to the transmitting side EXOR circuit. An example in which those predetermined data ranges are converted into degenerate data and input to the transmitting side EXOR circuit will be described later with reference to FIGS. 11 and 13.

Further, the number of data input to one transmitting side EXOR circuit at the same timing is arbitrary of 1 or more. When the number of data is 1, only the data at a certain bit position of ARADDR_ECC is input.

Further, when the data assumed to be input to the transmitting side EXOR circuit is only the data at a certain bit position of ARADDR_ECC, the transmitting side EXOR circuit may not be provided.

Each transmitting EXOR circuit outputs AR_ECC, which is the exclusive OR of the data input at the same timing.

AR_ECC is sent to the receiving side data conversion unit 218 of the receiving side 291 via the data path 301 shown in FIG.

FIG. 6 is a conceptual diagram showing a configuration example of the receiving side data conversion unit 218 shown in FIG. The receiving side data conversion unit 218 shown in FIG. 6 corresponds to the case where the transmitting side data conversion unit 118 shown in FIG. 4 is shown in FIG.

The receiving side data conversion unit 218 includes receiving side EXOR circuits 2210 to 2216.

The data at each bit position of the 7-bit AR_ECC is input to each of the receiving side EXOR circuits 2210 to 2216 at the same timing. Here, the number at the end of the code of the receiving side EXOR circuits 2210 to 2216 corresponds to the bit position in AR_ECC of the input data.

On the other hand, the numbers at the end of the codes of the receiving side EXOR circuits 2210 to 2216 into which the data of each bit position of the second information are input are those of the transmitting side EXOR circuits 1210 to 1216 in which the data is input in FIG. It is the same.

An example of the data input to the receiving EXOR circuit will be described later with reference to FIGS. 8, 10 and 14.

Further, in FIG. 5, when a predetermined data range of the second information is converted into degenerate data and input to the transmitting side EXOR circuit, the data range is set to the same degenerate data on the receiving side and the corresponding receiving side. It is input to the EXOR circuit. An example in which a predetermined data range is converted into degenerate data and input to the corresponding receiving-side EXOR circuit will be described later with reference to FIGS. 12 and 14.

If it is assumed that there is no corresponding XOR circuit on the transmitting side, there is no EXOR circuit on the receiving side.

Each receiving EXOR circuit outputs the second exclusive OR, which is the exclusive OR for the data input at the same timing.

The second exclusive OR is input to the bit error detection unit 206 shown in FIG.

Hereinafter, examples of input data to the transmitting side EXOR circuit of FIG. 5 and the receiving side EXOR circuit of FIG. 6 will be described with reference to FIGS. 7 to 14.

FIG. 7 is a conceptual diagram showing an example of input data (No. 1) to the transmission side EXOR circuit shown in FIG. FIG. 7 shows an input example for only ARSIDE and ARLEN among the second information shown in FIG.

As described above, the data at each bit position of ARADDR_ECC, which is the ECC redundant code generated from ARADDR [31: 0], is input to each transmitting side EXOR circuit. In the example of FIG. 7, the rightmost number of the code of the transmitting side EXOR circuit matches the value representing the bit position of the input ARADDR_ECC. Further, in the example of FIG. 7, the bit position of the data other than ARADDR_ECC input to each transmitting side EXOR circuit also matches the rightmost number of the code of the transmitting side EXOR circuit. From each of the transmitting side EXOR circuits, AR_ECC in which the rightmost number of the code representing the transmitting side EXOR circuit is a value representing a bit position is output.

In FIG. 7, the number of data input to one transmitting side EXOR circuit at the same timing is 2 or 3, but 4 or more data may be input at the same timing.

FIG. 8 is a conceptual diagram showing an example of input data (No. 1) to the receiving side EXOR circuit shown in FIG. FIG. 8 shows an example of input data to the receiving side EXOR circuit shown in FIG. 6, corresponding to the case where the input data to the transmitting side EXOR circuit shown in FIG. 5 is that of FIG. 7. In the configuration shown in FIG. 8, each ARADDR_ECC is replaced with AR_ECC at the same bit position, and the transmitting side EXOR circuits 1210 to 1213 are replaced with the receiving side EXOR circuits 2210 to 2213, respectively. The configuration shown in FIG. 8 further replaces AR_ECC at each bit position with ARADDR_ECC at the same bit position in the configuration shown in FIG. 7.

FIG. 9 is a conceptual diagram showing an example (No. 2) of input data to the transmitting side EXOR circuit shown in FIG. FIG. 9 shows an input example of only ARSIDE and ARLEN among the second information shown in FIG.

As described above, the data at each bit position of ARADDR_ECC, which is the ECC redundant code generated from ARADDR [31: 0], is input to each transmitting side EXOR circuit. The rightmost number of the code of the transmitting EXOR circuit coincides with the input bit position of ARADDR_ECC. On the other hand, the bit positions of the data other than ARADDR_ECC input to each transmitting side EXOR circuit do not always match the rightmost number of the code of the transmitting side EXOR circuit. From each of the transmitting side EXOR circuits, AR_ECC in which the rightmost number of the code representing the transmitting side EXOR circuit is a value representing a bit position is output.

In FIG. 9, the number of data input to one transmitting side EXOR circuit at the same timing is 2, but 3 or more data may be input at the same timing.

FIG. 10 is a conceptual diagram showing an example of input data (No. 2) to the receiving side EXOR circuit shown in FIG. FIG. 10 shows an example of input data to the receiving side EXOR circuit shown in FIG. 6 corresponding to the case where the input data to the transmitting side EXOR circuit shown in FIG. 5 is that of FIG. In the configuration shown in FIG. 10, each ARADDR_ECC is replaced with AR_ECC at the same bit position, and the transmitting side EXOR circuits 1210 to 1216 are replaced with the receiving side EXOR circuits 2210 to 2216, respectively. The configuration shown in FIG. 10 further replaces each AR_ECC in the configuration shown in FIG. 9 with ARADDR_ECC at the same bit position.

FIG. 11 is a conceptual diagram showing an example of input data (No. 3) to the transmitting side EXOR circuit shown in FIG. FIG. 11 shows an input example of only ARUSER among the second information shown in FIG.

Each of ARUSER [0] to [n-1] is input to the degenerate unit 131 at the same timing. The degenerate unit 131 generates 1-bit degenerate data from the input ARUSER [0] to [n-1]. The degenerate data is, for example, a known parity code. The configuration of the degenerate portion that generates the parity code from a plurality of data is known. The degenerate data generated by the degenerate unit 131 is input to the transmission side EXOR circuit 1214 at the same timing as ARADDR_ECC [4].

The transmitting EXOR circuit 1214 outputs AR_ECC [4], which is the exclusive OR of ARADDR_ECC [4] and degenerate data.

In FIG. 11, the degenerate data is generated from ARUSER [0] to [n-1], but even if the degenerate data is generated from any of the second information and input to the transmitting side EXOR circuit. Good.

Further, degenerate data may be generated from a combination of two or more pieces of information selected from the second information and input to the transmitting side EXOR circuit.

Further, the number of degenerate data is 2 bits or more, and each of them may be input to the transmitting side EXOR circuit.

When the degenerate data is input to the transmission side EXOR circuit, the input timing of the information input to the transmission side circuit is adjusted according to the input timing of the degenerate data.

FIG. 12 is a conceptual diagram showing an example of input data (No. 3) to the receiving side EXOR circuit shown in FIG. FIG. 12 shows an example of input data to the receiving side EXOR circuit shown in FIG. 6, corresponding to the case where the input data to the transmitting side EXOR circuit shown in FIG. 5 is that of FIG. In FIG. 11, ARADDR_ECC [4] is replaced with AR_ECC [4], the transmitting side EXOR circuit 1214 is replaced with the receiving side EXOR circuit 2214, and AR_ECC [4] is replaced with ARADDR_ECC [4]. ..

FIG. 13 is a conceptual diagram showing an example of input data (No. 4) to the transmitting side EXOR circuit shown in FIG. FIG. 9 shows an example of input data when all the second information shown in FIG. 5 is input to any of the transmitting side EXOR circuits.

As described above, the data at each bit position of ARADDR_ECC, which is the ECC redundant code generated from ARADDR [31: 0], is input to each transmitting side EXOR circuit. The rightmost number of the code of the transmitting EXOR circuit coincides with the input bit position of ARADDR_ECC.

Further, the number of data input to each transmitting side EXOR circuit at the same timing is 4 or 3.

Further, for ARID [0] to [m-1], the degenerate data generated by the degenerate unit 1311 is input to the transmission side EXOR circuit 1210. Further, for ARUSER [0] to [n-1], the degenerate data generated by the degenerate unit 1312 is input to the transmission side EXOR circuit 1215.

From each of the transmitting side EXOR circuits, AR_ECC having the rightmost number of the code representing the transmitting side EXOR circuit as the bit position is output.

In FIG. 13, the number of data input to one transmitting side EXOR circuit at the same timing is 3 or 4, but 5 or more data are input to one transmitting side EXOR circuit at the same timing. It doesn't matter.

Further, the timing at which each data is input to the transmitting side EXOR circuit is adjusted by a buffer or the like (not shown) so as to be the same timing.

FIG. 14 is a conceptual diagram showing an example of input data (No. 4) to the receiving side EXOR circuit shown in FIG. FIG. 14 shows the input data to the receiving side EXOR circuit shown in FIG. 6, which corresponds to the case where the input data to the transmitting side EXOR circuit shown in FIG. 5 is that of FIG. In the configuration shown in FIG. 14, each ARADDR_ECC is replaced with AR_ECC at the same bit position, and the transmitting side EXOR circuits 1210 to 1213 are replaced with the receiving side EXOR circuits 2210 to 2213, respectively. The configuration shown in FIG. 14 further replaces each AR_ECC in the configuration shown in FIG. 13 with ARADDR_ECC at the same bit position.

As described above, in the bit error detection system 500 of the present embodiment, first, on the transmitting side 191, each of the redundant codes generated from the data of each bit position of the first information and the data of each bit position of the second information Alternatively, the first exclusive logical sum with the data selected from the reduced data is generated. At this time, the bit error detection system 500 makes the data of all bit positions of the second information used for generating the first exclusive OR. The first and second information and the first exclusive OR are sent to the receiving side 291 via the data path 301.

Then, the bit error detection system 500 receives a second data between the data at each bit position of the first exclusive OR received by the receiving side 291 and the data of the second information or the reduced data also received. Generate an exclusive OR. Here, the data of the second information is used on the transmitting side 191 to generate the data of the bit position. Then, the bit error detection system 500 decodes the data at each bit position of the received first information by the second exclusive OR. The bit error detection system 500 further determines whether or not the decrypted data is set for the redundant code generated by the code generator.

At that time, if a bit error occurs in the data path 301 in which the data having the first information is changed, the decrypted data is different from the set data.

On the other hand, when a bit error occurs in which the second data after reception is different from the second data before transmission, the second exclusive OR is different from the redundant code. Therefore, the decrypted data is different from the set data.

As described above, when the decrypted data is different from the set data, a case where a bit error occurs in the first information and the second information is included. As a result, the bit error detection system of the present embodiment can detect that a bit error has occurred in either the first information or the second information.
[effect]
The bit error detection system of the present embodiment generates a redundant code for the first information when the first information and the second information are sent from the transmitting side to the receiving side, but the redundant code for the second information. Does not generate. Therefore, the second data is not decrypted by the redundant code on the receiving side. Therefore, the bit error detection system can detect bit errors with a smaller code generation circuit and decoding circuit as compared with a general bit error detection system as shown in FIGS. 1 and 2. For example, in the bit error detection system of FIG. 3, the number of code generation units and bit error detection units is halved, whereas the number of code generation units and bit error detection units is two each in FIG. 1 for monitoring data for the same data range. It is one. Further, the bit error detection system of FIG. 4 is one-third of each of the three bit error detection systems of FIG. 2 that monitors bit errors in the same data range.

When the decrypted data does not become the one set for the redundant code, the case where the first exclusive OR is changed in the data path may be included. In that case, the bit error detection system causes an erroneous detection in which the bit error detection system detects a bit error even if the bit error in which the data of the first and second information is changed in the data path does not occur. obtain. However, in the general bit error detection system described in the section of the prior art, erroneous detection of a bit error may occur due to the redundant code sent from the transmitting side to the receiving side being changed in the data path. The number of data of the first exclusive OR that the bit error detection system of the present embodiment sends from the transmitting side to the receiving side is received from the transmitting side by the general bit error detecting system described in the section of the prior art. It is less than the number of redundant code data sent to the side. Therefore, the bit error detection system of the present embodiment has a smaller number of transmitted data that cause erroneous detection as compared with the general bit error detection system described in the section of the prior art, and therefore has a probability of erroneous detection. Is small.

The bit error detection system of the present embodiment may use degenerate data obtained by degenerating the data included in the second information as the data used to generate the first exclusive OR. .. In that case, when there is a lot of data as the second information, the number of data of the second information for deriving the exclusive OR in combination with one data of the redundant code or the first exclusive OR can be reduced. In the above case, the generation of the first exclusive OR information and the second exclusive OR information becomes easier accordingly.

In the above description, the case where ECC of Non-Patent Documents 1 and 2 is mainly used as the redundant code for bit error detection has been described. However, the redundant code of the embodiment may be any one that can verify the fact when a bit error occurs in the redundant code or the original data. Such redundant codes include, for example, CRC (Cyclic Redundancy Check) and Reed-Solomon type redundant codes.

FIG. 15 is a block diagram showing the configuration of the detection device 201x, which is the minimum detection device of the embodiment.

The detection device 201x includes a receiving side exclusive OR generation unit 221x and an output unit 206x.

The receiving side exclusive OR generator 221x is derived from the first exclusive OR received first via the data path and the second received second information or the second information via the data path. Generate a second exclusive OR with the information.

The output unit 206x outputs the inspection result related to the inspection by the second exclusive OR of the first information received thirdly via the data path, and each data of the first exclusive OR is the first. (Iii) From the redundant code generated from the first information before the transmission related to the reception and the second information before the transmission related to the second reception or the second information before the transmission related to the second reception. It is generated by the information to be derived.

When the detection device 201x is used, the redundant code for the second information is not generated. Therefore, there is no need for a configuration that generates a redundant code for the second information. Therefore, the detection device 201x enables detection of bit errors with a smaller code generation circuit.

Therefore, the detection device 201x exhibits the effects described in the section [Effects of the Invention] according to the above configuration.

The detection device 201x shown in FIG. 15 is, for example, the receiving side data processing unit 201 shown in FIG. 3 or FIG.

Further, the receiving side exclusive OR generation unit 221x is, for example, the receiving side data conversion unit 218 shown in FIG. 3 or FIG.

Further, the output unit 206x is, for example, a part of the bit error detection unit 206 shown in FIG. 3 or FIG. 4 that outputs a bit error detection result.

Further, the data path is, for example, the data path 301 shown in FIG. 3 or FIG.

Further, the first exclusive OR is, for example, the above-mentioned first exclusive OR, for example, AR_ECC shown in FIGS. 4 to 14.

Further, the second exclusive OR is, for example, the above-mentioned second exclusive OR.

Further, the first information is, for example, information A shown in FIG. 3 and ARADDR shown in FIGS. 4, 5, 7, 7, 9, 11 and 13.

Further, the second information is, for example, the above-mentioned second information, and the information B shown in FIG. 3 and the ARID, ARCIZE, ARLEN, ARBURST, ARLOCK, ARCACE, and ARPROT shown in FIGS. 4, 5, and 13. And at least part of ARUSER.

Further, the first reception is, for example, reception of the first exclusive OR on the receiving side shown in FIGS. 3 and 4.

Further, the second reception is, for example, reception of the second information on the receiving side shown in FIGS. 3 and 4.

Further, the third reception is, for example, reception of the first information on the receiving side shown in FIGS. 3 and 4.

Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and further modifications, substitutions, and adjustments can be made without departing from the basic technical idea of the present invention. Can be added. For example, the composition of the elements shown in each drawing is an example for facilitating the understanding of the present invention, and is not limited to the composition shown in these drawings.

Further, a part or all of the above-described embodiment may be described as in the following appendix, but is not limited to the following.
(Appendix 1)
Generates a second exclusive OR of the first exclusive OR received via the data path and the second received second information or information derived from the second information via the data path. The receiving side exclusive OR generator and
An output unit that outputs the inspection result related to the inspection by the second exclusive OR of the first information received thirdly via the data path, and the output unit.
With
Each data of the first exclusive OR includes a redundant code generated from the first information before the transmission related to the third reception, and the second information or the second information before the transmission related to the second reception. It is generated by the information derived from the second information before the transmission related to the second reception.
Detection device.
(Appendix 2)
The detection device according to Appendix 1, wherein the inspection is for whether or not the decrypted data of the first information by the redundant code is set for the redundant code.
(Appendix 3)
The detection device according to Appendix 1 or Appendix 2, wherein the information derived from the second information includes degenerate data generated from at least a part of the data of the second information.
(Appendix 4)
The detection device according to Appendix 3, wherein the degenerate data is a parity code generated from at least a part of the data of the second information.
(Appendix 5)
Addendum 1 to 4 that the data of the redundant code from which the arbitrary data of the first exclusive OR is generated is different from the data of the redundant code which is the source of other data of the first exclusive OR. The detector according to any one of the following.
(Appendix 6)
The data of the second information of the generation source of the arbitrary data of the first exclusive OR is different from the data of the second information of the generation source of other data of the first exclusive OR, Appendix 1 to The detection device according to any one of Appendix 5.
(Appendix 7)
Described in any one of Appendix 1 to Appendix 6, wherein the data of the second information from which the arbitrary data of the first exclusive OR is generated may be two or more data different from each other. Detection device.
(Appendix 8)
Described in any one of Appendix 1 to Appendix 7, wherein the data of the second information from which the arbitrary data of the first exclusive OR is generated may be three or more data different from each other. Detection device.
(Appendix 9)
Described in any one of Appendix 1 to Appendix 8, wherein the data of the second information from which the arbitrary data of the first exclusive OR is generated may be four or more data different from each other. Detection device.
(Appendix 10)
Of Appendix 1 to Appendix 9, the number of data of the data from which the data having the first exclusive OR is generated is different from the number of data of the data from which the other data of the first exclusive OR is generated. The detector according to any one.
(Appendix 11)
A second exclusive OR of the first exclusive OR received via the data path and the second exclusive OR received second via the data path is generated, and the second exclusive OR is generated via the data path. (3) Decrypted data obtained by decoding the received first information by the second exclusive OR is generated, and the relationship between the decoded data and the third received first information via the data path is a redundant code. When there is a detection device that outputs the judgment result as to whether or not it is set for
A code generator that generates the redundant code from the first information before transmission related to the third reception, and
A transmission-side exclusive OR generator that generates each data of the first exclusive OR by the redundant code and the second information before transmission related to the second reception.
To prepare
Generator.
(Appendix 12)
A generator that generates each data of the first exclusive OR by the redundant code generated from the first information before the third transmission and the second information before the second transmission.
A second exclusive OR is generated between the first exclusive OR received first via the data path and the second information received related to the second transmission via the data path, and the data is generated. Decrypted data obtained by decoding the first information received in relation to the third transmission via the route by the second exclusive OR is generated, and the decoded data and the third transmission are transmitted via the data path. A detection device that outputs a determination result as to whether or not the relationship with the first information received is set for the redundant code.
To prepare
Detection system.
(Appendix 13)
Each data of the first exclusive OR is generated by the redundant code generated from the first information before the third transmission and the second information before the second transmission.
A second exclusive OR is generated between the first exclusive OR received first via the data path and the second information received related to the second transmission via the data path. Decrypted data obtained by decoding the first information received according to the third transmission via the data path by the second exclusive OR is generated, and the decoded data and the third transmission via the data path are generated. Outputs the determination result as to whether or not the relationship with the first information received according to the above is set for the redundant code.
Detection method.
(Appendix 14)
A process of generating each data of the first exclusive OR by a redundant code generated from the first information before the third transmission and the second information before the second transmission.
A process of generating a second exclusive OR of the first exclusive OR received via the data path and the second information received related to the second transmission via the data path. A process of generating decoded data obtained by decoding the first information received according to the third transmission via the data path by the second exclusive OR, and via the decoded data and the data path. A detection program that causes a computer to execute a process of outputting a determination result as to whether or not the relationship with the received first information related to the third transmission is set for the redundant code.

101 Transmission side data processing unit 1061, 1062 Code generation unit 106, 1063, 1064, 1065 ECC code generation unit 118 Transmission side data conversion unit 1210, 1211, 1212, 1213, 1214, 1215, 1216 Transmission side EXOR circuit 191 Transmission side 201 Receiving side data processing unit 201x detector 2061, 2062, 2063, 2064, 2065 bit error detecting unit 206x output unit 218 Receiving side data conversion unit 221x receiving side exclusive OR generator 2210, 2211, 2212, 2213, 2214, 2215 , 2216 Receiving side EXOR circuit 291 Receiving side 301 Data path 500-bit error detection system

Claims (10)

Generates a second exclusive OR of the first exclusive OR received via the data path and the second received second information or information derived from the second information via the data path. The receiving side exclusive OR generator and
An output unit that outputs the inspection result related to the inspection by the second exclusive OR of the first information received thirdly via the data path, and the output unit.
With
Each data of the first exclusive OR includes a redundant code generated from the first information before the transmission related to the third reception, and the second information or the second information before the transmission related to the second reception. It is generated by the information derived from the second information before the transmission related to the second reception.
Detection device. The detection device according to claim 1, wherein the inspection is for whether or not the decrypted data of the first information by the redundant code is set for the redundant code. The detection device according to claim 1 or 2, wherein the information based on the second information includes degenerate data generated from at least a part of the data of the second information. The detection device according to claim 3, wherein the degenerate data is a parity code generated from at least a part of the data of the second information. Claims 1 to claim that the data of the redundant code from which the arbitrary data of the first exclusive OR is generated is different from the data of the redundant code which is the generator of other data of the first exclusive OR. Item 4. The detection device according to any one of item 4. The data of the second information of the generation source of arbitrary data of the first exclusive OR is different from the data of the second information of the generation source of other data of the first exclusive OR, claim 1. The detection device according to any one of claims 5. A second exclusive OR of the first exclusive OR received via the data path and the second exclusive OR received second via the data path is generated, and the second exclusive OR is generated via the data path. (3) Decrypted data obtained by decoding the received first information by the second exclusive OR is generated, and the relationship between the decoded data and the third received first information via the data path is a redundant code. When there is a detection device that outputs the judgment result as to whether or not it is set for
A code generator that generates the redundant code from the first information before transmission related to the third reception, and
A transmission-side exclusive OR generator that generates each data of the first exclusive OR by the redundant code and the second information before transmission related to the second reception.
To prepare
Generator. A generator that generates each data of the first exclusive OR by the redundant code generated from the first information before the third transmission and the second information before the second transmission.
A second exclusive OR is generated between the first exclusive OR received first via the data path and the second information received related to the second transmission via the data path, and the data is generated. Decrypted data obtained by decoding the first information received in relation to the third transmission via the route by the second exclusive OR is generated, and the decoded data and the third transmission are transmitted via the data path. A detection device that outputs a determination result as to whether or not the relationship with the first information received is set for the redundant code.
To prepare
Detection system. Each data of the first exclusive OR is generated by the redundant code generated from the first information before the third transmission and the second information before the second transmission.
A second exclusive OR is generated between the first exclusive OR received first via the data path and the second information received related to the second transmission via the data path. Decrypted data obtained by decoding the first information received according to the third transmission via the data path by the second exclusive OR is generated, and the decoded data and the third transmission via the data path are generated. Outputs the determination result as to whether or not the relationship with the first information received according to the above is set for the redundant code.
Detection method. A process of generating each data of the first exclusive OR by a redundant code generated from the first information before the third transmission and the second information before the second transmission.
A process of generating a second exclusive OR of the first exclusive OR received via the data path and the second information received related to the second transmission via the data path. A process of generating decoded data obtained by decoding the first information received according to the third transmission via the data path by the second exclusive OR, and via the decoded data and the data path. A detection program that causes a computer to execute a process of outputting a determination result as to whether or not the relationship with the received first information related to the third transmission is set for the redundant code.

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