JP6714119B1 - Detecting device, generating device, detecting system, detecting method, and detecting program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection device and the like capable of detecting a bit error with a smaller code generation circuit. A detection device includes a first exclusive OR that is first received through a data path and second information that is second received through the data path or information derived from the second information. A receiving-side exclusive-OR generating unit that generates a second exclusive-OR, and an inspection result related to an inspection by the second exclusive-OR of the first information that is third-received via the data path. An output unit, wherein each data of the first exclusive OR is a redundant code generated from the first information before the transmission related to the third reception, and before the transmission related to the second reception. Of the second information or information derived from the second information before the transmission related to the second reception. [Selection diagram]

Description

The present invention relates to bit error detection.

When the input digital information passes through the data path, a bit error in which the received information differs from the transmitted information may occur due to a wiring defect or a signal fluctuation occurring in the data path. Then, in order to detect a bit error, a redundant code generated on the transmitting side is separately sent to the receiving side through a data path, and the receiving side verifies the correctness of the received information. ing.

FIG. 1 is a conceptual diagram showing the configuration of a bit error detection system 500 which is an example of a general bit error detection system that verifies the presence or absence of a bit error in received information using a redundant code. In the present specification, the bit error detection system means a system that detects the occurrence of a bit error when the bit error occurs in the information sent from the transmission side to the reception side via the data path. To do.

In FIG. 1, it is assumed that two types of digital information, information A [31:0] and information B [6:0], are sent from the transmission side 191 to the reception side 291 via the data path 301. There is.

In addition, a of [a:b] attached to the information is a maximum value (hereinafter, referred to as “maximum bit”) of a value that represents a bit position, and b is a value that represents a minimum value of a value that represents a bit position ( Hereinafter, it is referred to as a "minimum bit"), and this point is the same in each of the drawings starting from FIG. The value obtained by subtracting the minimum bit from the maximum bit and adding 1 is the bit length (bit width). Hereinafter, a bit length of a bits (a is an integer) may be simply referred to as “a bits”. The information A is 32-bit information in which the minimum bit is 0 and the maximum bit is 31. The information B is 7-bit information in which the minimum bit is 0 and the maximum bit is 6.

The bit error detection system 500 includes a transmission side data processing unit 101 and a reception side data processing unit 201. The transmission side data processing unit 101 includes code generation units 1061 and 1062. The reception side data processing unit 201 includes bit error detection units 2261 and 2262.

The information A is sent from the transmission side 191 to the reception side 291 via the data path 301 and is input to the code generation unit 1061 of the transmission side 191. The information A is sent from the transmission side 191 to the reception side 291 via the communication line 801, and is input to the code generation unit 1061 via the communication line 802. Each of the communication lines 801 and 802 is a wiring group including 32 wirings. Then, the data at each bit position of the information A is sent to the reception side 291 through the different wiring at the same timing and is also input to the code generation unit 1061.

The code generation unit 1061 generates, for example, a 7-bit redundancy code from the input 32-bit information A data. The 7-bit redundant code corresponds to the case where the redundant code is the ECC (Error Correction Code) of Non-Patent Documents 1 and 2. Hereinafter, when the redundant code is other than the ECC of Non-Patent Documents 1 and 2, the bit length of the redundant code may have other values. The ECCs of Non-Patent Documents 1 and 2 enable the receiving side to determine the presence/absence of a bit error in the received information depending on whether or not the decoded data obtained by ECC of the received information becomes zero.

The bit error detection unit 2261 decodes the 32-bit information A with the 7-bit redundancy code. The decoding method is based on the method corresponding to the code generated by the code generation unit 1061. Then, the bit error detection unit 2261 decodes the information A with the redundant code. Then, the bit error detection unit 2261 determines whether or not a bit error has occurred in the information A by examining the decoded data. When the redundant code is the ECC of Non-Patent Documents 1 and 2, the decoding performed by the bit error detection unit 2261 is to obtain the product of the data obtained by adding the ECC to the information A and the check matrix. Then, if the product of the data obtained by adding ECC to the information A and the check matrix does not become a zero matrix, the bit error detection unit 2261 determines that a bit error has occurred in the information A. Then, the bit error detection unit 2261 outputs the determination result.

The same applies to the information B, and the information B is sent from the transmission side 191 to the reception side 291 via the data path 301 and is input to the code generation unit 1062 at the transmission side 191. The information B is sent from the transmission side 191 to the reception side 291 via the communication line 806, and is input to the code generation unit 1062 via the communication line 807. Each of the communication lines 806 and 807 is a wiring group including seven wirings. Then, the data at each bit position of the information B is sent to the reception side 291 through different wirings of the communication lines 806 and 807 at the same timing, and is also input to the code generation unit 1062.
The code generation unit 1061 of the transmission side data processing unit 101 generates a 7-bit redundant code from the information B having a bit length of 7. Then, the bit error detection unit 2262 decodes the received information B with the redundant code also received. Then, the bit error detection unit 2062 checks whether or not the product of the data obtained by adding ECC to the information A and the check matrix is a zero matrix, and determines whether or not a bit error has occurred.

When the bit error detection units 2061 and 2062 determine the occurrence of a bit error, the redundant code generated by the code generation units 1061 and 1062 is changed in the data path 301. In that case, even if no bit error has occurred in the information A and B, the bit error detection units 2061 and 2062 erroneously detect the bit error.

Next, a general bit error detection system for verifying the data in the case of sending the data conforming to AXI ^™ through the data path by the ECC of Non-Patent Documents 1 and 2 will be described. Here, AXI ^™ is a standard regarding a bus proposed by ARM ^™ and is well known (see Non-Patent Document 3).

FIG. 2 shows a bit error detection system 500 which is an example of a general bit error detection system for verifying the data in the case of sending data conforming to AXI ^™ through a data path by the ECC of Non-Patent Documents 1 and 2. It is a conceptual diagram showing a structure.

The bit error detection system 500 includes a transmission side data processing unit 101 and a reception side data processing unit 201. The transmission side data processing unit 101 includes ECC code generation units 1063 to 1065. The receiving side data processing unit 201 also includes bit error detection units 2063 to 2065. The description of the data path 301 shown in FIG. 2 is the same as the description of the data path shown in FIG.

A total of eight types of information are sent from the transmitting side 191 to the receiving side 291. These eight types of information are ARADDR, ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT, and ARUSER. The contents of these pieces of information are defined in AXI ^™ and are publicly known (see Non-Patent Document 3). The communication line to which each information is sent is a wiring group including a number of wirings corresponding to the bit width of each information. The data at each bit position of each information is sent at the same timing through different wirings of communication lines.

The ARADDR is sent from the transmission side 191 to the reception side 291 and is input to the ECC code generation unit 1063 of the transmission side 191. The ECC code generation unit 1063 generates ARADDR_ECC, which is a 7-bit ECC redundancy code, from 32-bit ARADDR. The ARADDR_ECC is sent to the bit error detection unit 2063 via the data path 301.

The bit error detection unit 2063 decodes the ARADDR sent from the transmission side 191, using the ARADDR_ECC sent from the ECC code generation unit 1063. The decoding is to obtain a product of data obtained by adding ARADDR_ECC to ARADDR and a check matrix corresponding to the ECC. Then, the bit error detection unit 2063 checks whether the product is a zero matrix and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in ARADDR.

Further, ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE and ARPROT are sent from the transmission side 191 to the reception side 291. These are also input to the ECC code generation unit 1064. The ECC code generation unit 1064 generates group data in which ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, and ARPROT are combined in order. Here, the bit width of the set data does not exceed 32 bits. When the bit width of the group data is smaller than 32 bits, the code generation unit 1046 adds 0 bit to the group data to generate 32-bit transmission group data. Then, the ECC code generation unit 1064 generates ARNFO_ECC which is a 7-bit ECC redundancy code from the 32-bit transmission side set data. The ARNFO_ECC is sent from the transmission side 191 to the bit error detection unit 2064 of the reception side 291.

The bit error detection unit 2064 combines the ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE and ARPROT sent from the transmitting side 191 in order. Then, the bit error detection unit 2064 further generates 32-bit receiving-side set data with 0 bits added as needed. Then, the bit error detection unit 2064 decodes the reception side set data by the ARNFO_ECC sent from the ECC code generation unit 1064. The decoding is to obtain the product of the data obtained by adding ARNFO_ECC to the reception side set data and the check matrix corresponding to the ECC. Then, the bit error detection unit 2064 checks whether the product is a zero matrix, and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in the reception side set data.

Further, n-bit ARUSER is sent from the transmitting side 191 to the receiving side 291. It is assumed that n is 32 or less. ARUSER is also input to the ECC code generation unit 1065. When the bit width of ARUSER is smaller than 32 bits, the code generation unit 105 adds 0 bit to ARUSER to generate 32-bit second transmission side set data. Then, the ECC code generation unit 1064 generates ARUSER_ECC, which is a 7-bit ECC redundancy code, from the 32-bit second transmission side correction set data. ARUSER_ECC is sent from the transmission side 191 to the bit error detection unit 2065 of the reception side 291.

The bit error detection unit 2065 generates 32-bit second receiving side set data in which 0 bits are added to the ARUSER sent from the sending side 191 as necessary. Then, the bit error detection unit 2065 decodes the second reception side set data by the ARUER_ECC sent from the ECC code generation unit 1065. The decoding is to obtain the product of the data obtained by adding ARUER_ECC to the second receiving side set data and the check matrix corresponding to the ECC. Then, the bit error detection unit 2065 checks whether the product is a zero matrix and outputs the result. The case where the product is not a zero matrix corresponds to the case where a bit error occurs in the second receiving side set data.

Note that Patent Document 1 discloses a data storage device that generates a new redundant code in which auxiliary data related to data is included without increasing the bit length of the redundant code and detects the auxiliary data from the new redundant code.

JP, 07-253934, A

CortexTM-R4 and Cortex-R4F Technical Reference Manual Revision: r1p3, 8.2.2. Error checking and correction, arm, [search on February 20, 2019], Internet (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363fj/index. html) Introduction to Code Theory (14th), Application of Code Theory to Computer Technology, Television Society Journal Vol. 45, No. 9, pp. 1089-1094 (1991). AMBATM AXITM and ACETM Protocol Specification, AX13TM, AX14TM and AX14-LiteTM, ACE and ACE-LiteTM, ARM, [February 20, 2019 search], Internet (http://st.utw.ce.tw.ce. courses/fall15/eel4720_ 5721/labs/refs/AXI4_specification.pdf)

The bit error detection system 500 shown in FIG. 2 includes three code generation units on the transmission side and three bit error detection units on the reception side, and the numbers thereof are smaller than those in the case shown in FIG. It is increasing. Although the range of the data for detecting the bit error is expanded in FIG. 2 as compared with the case of FIG. 1, the expansion of the range of the data for detecting the bit error is redundant in a general bit error detection system. The scale of the circuit required for code generation and decoding increases. The increase in the circuit scale leads to an increase in cost.

It is an object of the present invention to provide a detection device and the like that can detect a bit error with a smaller code generation circuit.

The detection apparatus of the present invention comprises a first exclusive OR that is first received through a data path and second information that is secondly received through the data path or information derived from the second information. (2) a receiving-side exclusive-OR generating unit that generates an exclusive-OR, and an output that outputs a check result related to a check by the second exclusive-OR of the first information third received via the data path And a redundancy code generated from the first information before the transmission related to the third reception, and a data before the transmission related to the second reception. Information derived from the second information or the second information before the transmission related to the second reception.

The detection device and the like of the present invention enable detection of bit errors with a smaller code generation circuit.

It is a conceptual diagram showing the structural example (the 1) of a general bit error detection system. It is a conceptual diagram showing the structural example (the 2) of a general bit error detection system. It is a conceptual diagram showing the structural example (the 1) of the bit error detection system of this embodiment. It is a conceptual diagram showing the structural example (the 2) of the bit error detection system of this embodiment. It is a conceptual diagram showing the structural example of a transmission side data conversion part. It is a conceptual diagram showing the structural example of a receiving side data conversion part. It is a conceptual diagram showing the input data example (the 1) to the transmission side EXOR circuit. It is a conceptual diagram showing the input data example (the 1) to a receiving side EXOR circuit. It is a conceptual diagram showing the force example (the 2) of the data to the transmission side EXOR circuit. It is a conceptual diagram showing the input data example (the 2) to the receiving side EXOR circuit. It is a conceptual diagram showing the force example (the 3) of the data to the transmission side EXOR circuit. It is a conceptual diagram showing the input data example (the 3) to a receiving side EXOR circuit. It is a conceptual diagram showing the force example (the 4) of the data to the transmission side EXOR circuit. It is a conceptual diagram showing the input data example (the 4) to the receiving side EXOR circuit. It is a block diagram showing the composition of the minimum detection device of an embodiment.

The bit error detection system of the present exemplary embodiment generates, on the transmission side, a first exclusive OR of the redundant code generated from the first information and the second information. Here, the first and second information are information sent from the transmitting side to the receiving side via the data path. Then, the bit error detection system generates a second exclusive logical sum from the first exclusive logical sum received at the receiving side and the second information also received. Then, the bit error detection system decodes the received data of each bit position of the first information by the second exclusive OR. The bit error detection system further checks whether or not the relation between the decoded data and the received first information is set for the redundant code.

In the above case, when a bit error occurs in the first information in the data path, the received data of the first information is different from that before the transmission. Further, when a bit error occurs in the second data after reception, the second exclusive OR is different from the redundant code. Therefore, the relationship between the decoded data and the first information is different from that set for the redundant code. Therefore, in the bit error detection system, even if a bit error occurs in any of the first information and the second information, the relationship between the first information after decoding and the first information before decoding is set. By detecting the difference, it can be detected that a bit error has occurred.

Here, the bit error detection system of this embodiment does not generate or decode a redundant code for the second information. Therefore, the bit error detection system of this embodiment does not require a configuration for generating and decoding a redundant code for the second information. That is, the bit error detection system according to the present embodiment can detect bit errors with a configuration of a smaller-scale code generation circuit and decoding circuit.

Hereinafter, the bit error detection system of the present embodiment will be described in detail with reference to the drawings.

FIG. 3 is a conceptual diagram showing the configuration of a bit error detection system 500 which is an example of the bit error detection system of this embodiment. The description of the information A and B and the data path 301 in FIG. 3 is the same as the case of FIG. 1 except for the following description.

The information A is the above-mentioned first information used for generating the redundant code. The information B is the above-mentioned second information that generates an exclusive OR with the redundant code.

The bit error detection system 500 includes a transmission side data processing unit 101 and a reception side data processing unit 201.

The transmission side data processing unit 101 includes a code generation unit 1061 and a transmission side data conversion unit 118. The transmission side data conversion unit 118 includes transmission side EXOR circuits 1210 to 1216.

The reception side data processing unit 201 includes a reception side data conversion unit 218 and a bit error detection unit 2061. The reception side data conversion unit 218 includes reception side EXOR circuits 2210 to 2216.

The information A is sent from the transmitting side 191 to the receiving side 291 via the data path 301, and is input to the code generating section 1061 at the transmitting side 191. The information A is sent from the transmission side 191 to the reception side 291 via the communication line 801, and is input to the code generation unit 1061 via the communication line 802. Each of the communication lines 801 and 802 is a wiring group including 32 wirings. Then, the data at each bit position of the information A is sent to the reception side 291 through different wirings of the communication lines 801 and 802 at the same timing, and is also input to the code generation unit 1061.

On the other hand, the information B is sent from the transmission side 191 to the reception side 291 via the data path 301, and is also input to each EXOR circuit of the transmission side data conversion unit 118 at the transmission side 191. The information B is sent from the transmission side 191 to the reception side 291 via the communication line 806. The communication line 806 is a wiring group including seven wirings. Then, the data at each bit position of the information B is sent to the receiving side 291 through the different wiring of the communication line 806 at the same timing. Further, the communication line 807 on the left side of the position 991 and the seven wirings on the right side are the same ones, but are simply represented by different notations.

The code generation unit 1061 generates a 7-bit redundant code from the input 32-bit information A, similarly to the code generation unit 1061 shown in FIG. The 7-bit redundant code corresponds to the case where the redundant code is the ECC of Non-Patent Documents 1 and 2. When the redundant code is other than the ECC of Non-Patent Documents 1 and 2, the bit width of the redundant code may have another value.

The code generation unit 1061 inputs the data of each bit position of the generated 7-bit redundant code to the transmission side EXOR circuits 1210 to 1216 at the same timing. The timing is, for example, clock timing. If there is one integer in [], the integer represents the bit position of the target data.

Each of the transmission side EXOR circuits 1210 to 1216 outputs the first exclusive OR which is the exclusive OR of the two input data. Since the configuration of the circuit that outputs the exclusive OR of the input data is well known, its description is omitted here. The first exclusive ORs output from the transmission side EXOR circuits 1210 to 1216 are sent to the reception side 291 via the data path 301.

The first exclusive-OR sent to the receiving side 291 is input to each of the receiving side EXOR circuits 2210 to 2216 at the same timing.

The information A sent to the receiving side 291 is sent to the outside and also input to the bit error detection unit 2061. The outside is, for example, another device that uses the information A. On the other hand, the information B sent to the receiving side 291 is sent to the outside and also input to each of the receiving side EXOR circuits 2210 to 2216. The outside is, for example, another device that uses the information B. Note that the communication line 808 on the left side of the position 992 and the seven wirings on the right side are the same as each other but are represented by different notations.

The EXOR circuits 2210 to 2216 on the receiving side output the second exclusive OR which is the exclusive OR of the two data input at the same timing.

The second exclusive ORs output from the reception side EXOR circuits 2210 to 2216 are input to the bit error detection unit 2061.

Like the communication line 801, the communication line 803 is a wiring group including 32 wires. Then, the data at each bit position of the information A is input to the bit error detection unit 2061 through different wirings of the communication line 803 at the same timing.

The bit error detection unit 2061 decodes the input information A by the code including the input second exclusive OR. Then, the bit error detection unit 2061 determines whether the decoding information is set for the redundant code generated by the code generation unit 1061. The bit error detection unit 2061 outputs the determination result to the outside.

Here, there are three possible cases in which the bit error detection unit 2061 detects a bit error.

In the above case, first, the information A is changed in the data path 301.

The second case is the case where the information B is changed in the data path. In this case, even if the second exclusive OR is further derived by each receiving EXOR circuit with respect to the first exclusive OR derived by each transmitting EXOR circuit, the second exclusive OR is code-generated. It does not return to the redundant code generated by the unit 1061. Therefore, the information A after decoding is not set for the redundant code generated by the code generation unit 1061.

In the above case, thirdly, there is a case where the first exclusive OR sent from the transmitting side 191 to the receiving side 291 is changed in the data path 301. In this case, even if the information A and B have no bit error, the bit error is detected incorrectly.

The bit error detection system 500 shown in FIG. 3 can detect any bit error of the information A and B according to the first and second cases.

Further, in the configuration of FIG. 1, the code generation units are two code generation units 1061 and 1062, and the bit error detection units are also two bit error detection units 2061 and 2062. On the other hand, in the configuration of FIG. 3, there is one code generation unit 1061 and one bit error detection unit 2061. Accordingly, the bit error detection system 500 shown in FIG. 3 can simplify the circuit configuration for generating and decoding the redundant code.

In the configuration of FIG. 3, as the third case, there may be erroneous detection of a bit error due to a bit error in the data path 301 of the first exclusive OR. This corresponds to erroneous detection of a bit error due to a bit error in the redundant code data path 301 in the configuration of FIG. However, the number of bits of the first exclusive-OR bit sent by the configuration of FIG. 3 is 7 is smaller than the number of bits of the redundant code sent by the configuration of FIG. Therefore, it is considered that the probability of occurrence of the bit error of the first exclusive OR in the configuration of FIG. 3 is smaller than that of the configuration of FIG. Therefore, the configuration of FIG. 3 can reduce the occurrence probability of erroneous detection of a bit error as compared with the configuration of FIG.

FIG. 4 is a bit error detection system 500 which is an example of the bit error detection system of the present embodiment, which verifies the data in the case of sending the data complying with AXI through a data path by the ECC of Non-Patent Documents 1 and 2. It is a conceptual diagram showing the structure of.

The bit error detection system 500 includes a transmission side data processing unit 101 and a reception side data processing unit 201. The transmission side data processing unit 101 includes an ECC code generation unit 106 and a transmission side data conversion unit 118. Further, the reception side data processing section 201 includes a bit error detection section 206 and a reception side data conversion section 218.

A total of eight types of information are sent from the transmitting side 191 to the receiving side 291. These eight types of information are ARADDR, ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT, and ARUSER. The contents of these pieces of information are defined in AXI ^™ and are publicly known. The communication line for transmitting each information is a wiring group including a number of wirings corresponding to the bit width of each information. The data at each bit position of each information is sent at the same timing through different wirings of communication lines.

Among these, ARADDR is the information of the generation source of the ECC redundant code and is the above-mentioned first information. Further, ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT and ARUSER are the above-mentioned second information that is not a source of the redundant code.

The ARADDR, which is the first information, is sent from the transmission side 191 to the reception side 291 and is input to the ECC code generation unit 106 at the transmission side 191. The ECC code generation unit 106 generates ARADDR_ECC, which is a 7-bit ECC redundancy code, from 32-bit ARADDR. The ARADDR_ECC is input to the transmission side data conversion unit 118.

Second information ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT and ARUSER are also input to the transmission side data conversion unit 118.

The transmission-side data conversion unit 118 derives a 7-bit ARADDR_ECC that is an exclusive OR of each bit of the 7-bit ARADDR_ECC and the data forming the second information or the degenerate data of the second information. A configuration example of the transmission side data conversion unit 118 will be described later with reference to FIGS. 5, 7, 9, 11, and 13. An example of inputting the degenerate data will be described later with reference to FIGS. 11 and 13.

The ARADDR_ECC is sent to the receiving side 291 via the data path 301.

The AR_ECC and the second information are input to the reception side data conversion unit 218 of the reception side 291. The second information is ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, ARPROT and ARUSER, as described above.

The reception-side data conversion unit 218 has a 7-bit second exclusive OR that is an exclusive OR of each bit of the 7-bit AR_ECC and the data at each bit position forming the second information or the degenerate data of the second information. Derive OR. At the time of the derivation, each bit of AR_ECC and the data used when the data of the bit is subjected to the exclusive OR operation of the transmission side data conversion unit 118 with ARADDR_ECC after passing through the data path 301. , And are exclusive-ORed. The second exclusive OR is input to the bit error detection unit 206. A configuration example of the reception side data conversion unit 218 will be described later with reference to FIGS. 6, 8, 10, 12, and 14.

In addition to the second exclusive OR, the bit error detection unit 206 receives ARADDR, which is the first information after passing through the data path 301.

The bit error detection unit 206 decodes ARADDR, which is the first information, by using the input 7-bit second exclusive OR as the decoding code. The decoding is to obtain the product of the data obtained by adding the second exclusive OR to the ARADDR and the check matrix corresponding to the ECC. Then, the bit error detection unit 206 checks whether the product is a zero matrix and outputs the result. If the product is not a zero matrix, it means that either a bit error has occurred in the ARADDR or the second exclusive OR is not equal to the ECC generated by the ECC code generation unit 106. When the second exclusive OR is not equal to the ECC generated by the ECC code generation unit 106, a case where a bit error occurs in the second information is included. Therefore, when the bit error detection unit 206 outputs the determination result that the product is not the zero matrix, the case where the bit error occurs in any of the first information and the second information is included.

FIG. 5 is a conceptual diagram showing a configuration example of the transmission side data conversion unit 118 shown in FIG.

The transmission side data conversion unit 118 includes transmission side EXOR circuits 1210 to 1216.

The data at each bit position of 7-bit ARADDR_ECC is input to each of the transmission side EXOR circuits 1210 to 1216. The numbers at the end of the codes of the transmission side EXOR circuits 1210 to 1216 correspond to the bit positions in the ARADDR_ECC of the input data.

On the other hand, for the data at each bit position of the second information, the selection of the input EXOR circuit on the transmission side is arbitrary. An example of the selection will be described later with reference to FIGS. 7, 9 and 13.

Further, the predetermined data range of the second information may be converted into degenerate data and input to the transmission side EXOR circuit. An example in which those predetermined data ranges are degenerated data and input to the transmission side EXOR circuit will be described later with reference to FIGS. 11 and 13.

Further, the number of data input to one transmission side EXOR circuit at the same timing is one or more. The case where the number of data is 1 is a case where only the data at a certain bit position of ARADDR_ECC is input.

If the data supposed to be input to the transmission side EXOR circuit is only the data at a certain bit position of ARADDR_ECC, the transmission side EXOR circuit may be omitted.

Each transmission side EXOR circuit outputs AR_ECC which is the exclusive OR of the data input at the same timing.

The AR_ECC is sent to the reception side data conversion unit 218 of the reception side 291 via the data path 301 shown in FIG.

FIG. 6 is a conceptual diagram showing a configuration example of the reception side data conversion unit 218 shown in FIG. The reception side data conversion unit 218 shown in FIG. 6 corresponds to the case where the transmission side data conversion unit 118 shown in FIG. 4 is the one shown in FIG.

The reception side data conversion unit 218 includes reception side EXOR circuits 2210 to 2216.

Data of each bit position of 7-bit AR_ECC is input to each of the reception side EXOR circuits 2210 to 2216 at the same timing. Here, the numbers at the end of the codes of the receiving side EXOR circuits 2210 to 2216 correspond to the bit positions in the AR_ECC of the input data.

On the other hand, the numbers at the end of the reference numerals of the receiving side EXOR circuits 2210 to 2216 to which the respective data at the respective bit positions of the second information are input are the same as those of the transmitting side EXOR circuits 1210 to 1216 to which the data are input in FIG. Is the same.

An example of the data input to the receiving side EXOR circuit will be described later with reference to FIGS. 8, 10 and 14.

Further, in FIG. 5, when the predetermined data range of the second information is degenerated data and is input to the transmitting side EXOR circuit, the data range is also changed to the same degenerated data on the receiving side and the corresponding receiving side. It is input to the EXOR circuit. An example in which a predetermined data range is converted to degenerate data and input to the corresponding receiving side EXOR circuit will be described later with reference to FIGS. 12 and 14.

If it is assumed that there is no corresponding EXOR circuit on the transmitting side, the EXOR circuit on the receiving side does not exist.

Each reception side EXOR circuit outputs the second exclusive OR which is the exclusive OR of the data input at the same timing.

The second exclusive OR is input to the bit error detection unit 206 shown in FIG.

Hereinafter, examples of input data to the transmission side EXOR circuit of FIG. 5 and the reception side EXOR circuit of FIG. 6 will be described with reference to FIGS. 7 to 14.

FIG. 7 is a conceptual diagram showing an example (part 1) of input data to the transmission side EXOR circuit shown in FIG. FIG. 7 shows an input example of only ARSIZE and ARLEN of the second information shown in FIG.

As described above, the data of each bit position of ARADDR_ECC, which is the ECC redundancy code generated from ARADDR[31:0], is input to each transmission side EXOR circuit. In the example of FIG. 7, the rightmost number of the code of the transmission side EXOR circuit matches the value indicating the bit position of the input ARADDR_ECC. Further, in the example of FIG. 7, the bit positions of the data other than ARADDR_ECC input to each transmission side EXOR circuit also match the rightmost number of the code of the transmission side EXOR circuit. From each of the transmission side EXOR circuits, AR_ECC in which the rightmost numeral of the code representing the transmission side EXOR circuit is used as a value indicating a bit position is output.

Note that, in FIG. 7, the number of data input to one transmission side EXOR circuit at the same timing is 2 or 3, but four or more data may be input at the same timing.

FIG. 8 is a conceptual diagram showing an example (part 1) of input data to the EXOR circuit on the receiving side shown in FIG. FIG. 8 shows an example of input data to the reception side EXOR circuit shown in FIG. 6 corresponding to the case where the input data to the transmission side EXOR circuit shown in FIG. 5 is that of FIG. 7. In the configuration shown in FIG. 8, each ARADDR_ECC of the configuration shown in FIG. 7 is replaced with an AR_ECC of the same bit position, and the transmission side EXOR circuits 1210 to 1213 are replaced with reception side EXOR circuits 2210 to 2213, respectively. The configuration shown in FIG. 8 is obtained by further replacing the AR_ECC at each bit position of the configuration shown in FIG. 7 with the ARADDR_ECC at the same bit position.

FIG. 9 is a conceptual diagram showing an example (No. 2) of input data to the transmitting side EXOR circuit shown in FIG. FIG. 9 shows an input example of only ARSIZE and ARLEN of the second information shown in FIG.

As described above, the data of each bit position of ARADDR_ECC, which is the ECC redundancy code generated from ARADDR[31:0], is input to each transmission side EXOR circuit. The rightmost number of the code of the transmission side EXOR circuit matches the bit position of the input ARADDR_ECC. On the other hand, the bit position of the data other than ARADDR_ECC input to each transmission side EXOR circuit does not necessarily match the rightmost number of the code of the transmission side EXOR circuit. From each of the transmission side EXOR circuits, AR_ECC in which the rightmost numeral of the code representing the transmission side EXOR circuit is used as a value indicating a bit position is output.

Note that in FIG. 9, the number of data input to one transmission side EXOR circuit at the same timing is two, but three or more data may be input at the same timing.

FIG. 10 is a conceptual diagram showing an example (part 2) of input data to the receiving side EXOR circuit shown in FIG. FIG. 10 shows an example of input data to the reception side EXOR circuit shown in FIG. 6, which corresponds to the case where the input data to the transmission side EXOR circuit shown in FIG. In the configuration shown in FIG. 10, each ARADDR_ECC in the configuration shown in FIG. 9 is replaced with an AR_ECC at the same bit position, and the transmission side EXOR circuits 1210 to 1216 are replaced with reception side EXOR circuits 2210 to 2216, respectively. The configuration shown in FIG. 10 is obtained by further replacing each AR_ECC of the configuration shown in FIG. 9 with ARADDR_ECC at the same bit position.

FIG. 11 is a conceptual diagram showing an example (part 3) of input data to the transmission side EXOR circuit shown in FIG. FIG. 11 shows an input example of only ARUSER among the second information shown in FIG.

Each of ARUSER[0] to [n-1] is input to the degeneration unit 131 at the same timing. The degeneration unit 131 generates 1-bit degenerate data from the input ARUSER[0] to [n-1]. The degenerate data is, for example, a known parity code. The configuration of the degeneration unit that generates a parity code from a plurality of data is publicly known. The degenerated data generated by the degeneration unit 131 is input to the transmission side EXOR circuit 1214 at the same timing as ARADDR_ECC[4].

The transmission side EXOR circuit 1214 outputs AR_ECC[4] which is the exclusive OR of ARADDR_ECC[4] and the degenerated data.

In FIG. 11, the degenerate data is generated from ARUSER[0] to [n−1], but the degenerate data is generated from any of the second information and is input to the transmission side EXOR circuit. Good.

In addition, degenerate data may be generated from a combination of two or more pieces of information selected from the second information and input to the transmission side EXOR circuit.

Further, the number of degenerate data may be 2 bits or more, and each may be input to the transmission side EXOR circuit.

When the degenerate data is input to the transmission side EXOR circuit, the input timing of the information input to the transmission side circuit is adjusted according to the input timing of the degenerated data.

FIG. 12 is a conceptual diagram showing an example (part 3) of input data to the receiving side EXOR circuit shown in FIG. FIG. 12 shows an example of input data to the reception side EXOR circuit shown in FIG. 6, which corresponds to the case where the input data to the transmission side EXOR circuit shown in FIG. FIG. 12 is a diagram in which ARADDR_ECC[4] is replaced with AR_ECC[4], the transmission side EXOR circuit 1214 is replaced with a reception side EXOR circuit 2214, and AR_ECC[4] is replaced with ARADDR_ECC[4] in FIG. 11. ..

FIG. 13 is a conceptual diagram showing an example (part 4) of input data to the transmission side EXOR circuit shown in FIG. FIG. 9 shows an example of input data when all the second information shown in FIG. 5 is input to any of the transmitting side EXOR circuits.

As described above, the data of each bit position of ARADDR_ECC, which is the ECC redundancy code generated from ARADDR[31:0], is input to each transmission side EXOR circuit. The rightmost number of the code of the transmission side EXOR circuit matches the bit position of the input ARADDR_ECC.

Further, the number of data input to each transmission side EXOR circuit at the same timing is 4 or 3.

For ARIDs [0] to [m−1], the degenerate data generated by the degenerating unit 1311 is input to the transmission side EXOR circuit 1210. For ARUSER[0] to [n−1], the degenerate data generated by the degenerating unit 1312 is input to the transmission side EXOR circuit 1215.

From each of the transmission side EXOR circuits, AR_ECC whose bit position is the rightmost digit of the code representing the transmission side EXOR circuit is output.

Note that in FIG. 13, the number of data input to one transmission side EXOR circuit at the same timing is 3 or 4, but 5 or more data is input to one transmission side EXOR circuit at the same timing. I don't mind.

Further, the timing at which each data is input to the transmission side EXOR circuit is adjusted by a buffer (not shown) or the like so as to have the same timing.

FIG. 14 is a conceptual diagram showing an example (No. 4) of input data to the receiving side EXOR circuit shown in FIG. FIG. 14 shows the input data to the receiving side EXOR circuit shown in FIG. 6 corresponding to the case where the input data to the transmitting side EXOR circuit shown in FIG. 5 is that of FIG. In the configuration shown in FIG. 14, each ARADDR_ECC of the configuration shown in FIG. 13 is replaced with an AR_ECC of the same bit position, and the transmission side EXOR circuits 1210 to 1213 are replaced with reception side EXOR circuits 2210 to 2213, respectively. The configuration shown in FIG. 14 is obtained by further replacing each AR_ECC of the configuration shown in FIG. 13 with ARADDR_ECC at the same bit position.

As described above, in the bit error detection system 500 of the present embodiment, first, on the transmission side 191, each redundant code generated from the data at each bit position of the first information and the data at each bit position of the second information. Alternatively, the first exclusive OR with the data selected from the degenerate data is generated. At this time, the bit error detection system 500 causes the data at all bit positions of the second information to be used for generating the first exclusive OR. The first and second information and the first exclusive OR are sent to the receiving side 291 via the data path 301.

Then, the bit error detection system 500 makes a second difference between the data of each bit position of the first exclusive OR that is received by the receiving side 291 and the data of the second information or the degenerate data that is also received. Generate exclusive OR. Here, the data of the second information is used for generating data of the bit position on the transmitting side 191. Then, the bit error detection system 500 decodes the received data at each bit position of the first information by the second exclusive OR. The bit error detection system 500 further determines whether or not the decoded data is set for the redundant code generated by the code generation unit.

At that time, if a bit error occurs in which the data having the first information is changed in the data path 301, the decoded data is different from the set data.

On the other hand, when a bit error occurs in which the second data after reception is different from the second data before transmission, the second exclusive OR is different from the redundancy code. Therefore, the decoded data is different from the set data.

As described above, when the decoded data is different from the set data, a case where a bit error occurs in the first information and the second information is included. As a result, the bit error detection system of this embodiment can detect that a bit error has occurred in either the first information or the second information.
[effect]
The bit error detection system of the present embodiment generates a redundant code for the first information when the first information and the second information are sent from the transmitting side to the receiving side, but for the second information, the redundant code is generated. Is not generated. Therefore, the second data is not decrypted by the redundant code on the receiving side. Therefore, the bit error detection system can detect the bit error with a smaller-scale code generation circuit and decoding circuit as compared with a general bit error detection system as shown in FIGS. 1 and 2. For example, in the bit error detection system of FIG. 3, the number of code generation units and the number of bit error detection units are each two in the case shown in FIG. It is one. Also, the bit error detection system of FIG. 4 is one in each of the three thirds of the bit error detection system of FIG. 2 that monitors bit errors in the same data range.

When the decoded data is not the one set for the redundancy code, a case may be included where the first exclusive OR is changed in the data path. In that case, the bit error detection system may generate an erroneous detection in which the bit error detection system detects a bit error even if the bit error in which the data of the first and second information is changed in the data path does not occur. obtain. However, in the general bit error detection system described in the section of the prior art, the redundant code sent from the transmission side to the reception side may be changed in the data path, resulting in erroneous detection of bit errors. Then, the number of data of the first exclusive logical sum sent from the transmitting side to the receiving side by the bit error detecting system of the present embodiment is the same as that of the general bit error detecting system described in the section of the prior art. Less than the number of redundant code data to be sent to the side. Therefore, the bit error detection system of the present embodiment has a smaller probability of occurrence of erroneous detection as compared with the general bit error detection system described in the section of the prior art because the number of sending data that causes erroneous detection is small. Is small.

The bit error detection system of this embodiment may use, as the data used to generate the first exclusive OR, the degenerated data obtained by degenerating the data contained in the second information. .. In that case, when there are many data as the second information, the number of data of the second information for deriving the exclusive OR by combining with the redundant code or one data of the first exclusive OR can be reduced. In the above case, the first exclusive OR information and the second exclusive OR information can be easily generated correspondingly.

In the above description, the case where the ECCs of Non-Patent Documents 1 and 2 are mainly used as the redundant code for bit error detection has been described. However, the redundant code of the embodiment may be any one as long as it can be verified if a bit error occurs in the redundant code or the original data. Such a redundant code includes, for example, a CRC (Cyclic Redundancy Check) or a Reed-Solomon type redundant code.

FIG. 15 is a block diagram showing the configuration of a detection device 201x which is the minimum detection device of the embodiment.

The detection device 201x includes a reception-side exclusive-OR generation unit 221x and an output unit 206x.

The receiving-side exclusive-OR generation unit 221x is derived from the first exclusive-OR received first via the data path and the second information or the second information second-received via the data path. Generate a second exclusive OR with the information.

The output unit 206x outputs the inspection result of the inspection by the second exclusive OR of the first information third received via the data path, and each data of the first exclusive OR outputs the data of the first exclusive OR. From the redundant code generated from the first information before the transmission related to the third reception, and the second information before the transmission related to the second reception or the second information before the transmission related to the second reception It is generated by the information that is guided.

When the detection device 201x is used, the redundant code for the second information is not generated. Therefore, there is no need for a configuration for generating a redundant code for the second information. Therefore, the detection device 201x enables detection of bit errors with a smaller code generation circuit.

Therefore, the detection device 201x has the effects described in the section [Effects of the Invention] due to the above configuration.

The detection device 201x illustrated in FIG. 15 is, for example, the reception-side data processing unit 201 illustrated in FIG. 3 or 4.

Further, the reception side exclusive OR generation section 221x is, for example, the reception side data conversion section 218 shown in FIG. 3 or 4.

The output unit 206x is, for example, a unit that outputs the detection result of the bit error in the bit error detection unit 206 illustrated in FIG. 3 or 4.

The data path is, for example, the data path 301 shown in FIG. 3 or 4.

Further, the first exclusive OR is, for example, the above-mentioned first exclusive OR, and is, for example, AR_ECC shown in FIGS. 4 to 14.

The second exclusive OR is, for example, the second exclusive OR described above.

The first information is, for example, information A shown in FIG. 3 and ARADDR shown in FIGS. 4, 5, 7, 9, 11 and 13.

Further, the second information is, for example, the second information described above, and the information B shown in FIG. 3 and the ARID, ARSIZE, ARLEN, ARBURST, ARLOCK, ARCACHE, and ARPROT shown in FIGS. 4, 5, and 13. And at least part of ARUSER.

The first reception is, for example, reception of the first exclusive OR on the reception side shown in FIGS. 3 and 4.

Further, the second reception is, for example, reception of the second information on the reception side shown in FIGS. 3 and 4.

The third reception is, for example, reception of the first information on the reception side shown in FIGS. 3 and 4.

Although the respective embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and further modifications, replacements, and adjustments can be made without departing from the basic technical idea of the present invention. Can be added. For example, the configuration of the elements shown in each drawing is an example for helping understanding of the present invention, and is not limited to the configuration shown in these drawings.

Further, a part or all of the above-described exemplary embodiment may be described as the following supplementary notes, but is not limited to the following.
(Appendix 1)
Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information second received via the data path or information derived from the second information A receiving side exclusive OR generating unit,
An output unit that outputs a check result related to a check by the second exclusive OR of the first information third received via the data path,
Equipped with
Each data of the first exclusive OR, the redundant code generated from the first information before transmission related to the third reception, and the second information before transmission related to the second reception or the Information derived from the second information before the transmission related to the second reception, and is generated by
Detection device.
(Appendix 2)
The detection device according to appendix 1, wherein the inspection is for whether or not the decoded data of the redundant code of the first information is set for the redundant code.
(Appendix 3)
The detection device described in Appendix 1 or Appendix 2, wherein the information derived from the second information includes degenerate data generated from at least a part of the data of the second information.
(Appendix 4)
The detection device according to attachment 3, wherein the degenerate data is a parity code generated from at least a part of the data of the second information.
(Appendix 5)
The data of the redundant code of the generation source of the arbitrary data of the first exclusive OR is different from the data of the redundant code of the generation source of the other data of the first exclusive OR. The detection device described in any one of the above.
(Appendix 6)
Note that data of the second information that is a generation source of arbitrary data of the first exclusive OR is different from data of the second information that is a generation source of other data of the first exclusive OR. The detection device described in any one of Appendix 5.
(Appendix 7)
The data of the second information, which is a generation source of the arbitrary data of the first exclusive OR, may be two or more data different from each other, and is described in any one of appendices 1 to 6. Detection device.
(Appendix 8)
The data of the second information, which is a generation source of the arbitrary data of the first exclusive OR, may be three or more data different from each other, and is described in any one of appendices 1 to 7. Detection device.
(Appendix 9)
The data of the second information, which is the generation source of the arbitrary data of the first exclusive OR, may be four or more data different from each other, and is described in any one of appendices 1 to 8. Detection device.
(Appendix 10)
Among the appendixes 1 to 9, the number of pieces of data that is the generation source of the data having the first exclusive OR is different from the number of pieces of data that is the generation source of the other data of the first exclusive OR. The detection device described in any one.
(Appendix 11)
A second exclusive OR of the first exclusive OR received first via the data path and the second information second received via the data path is generated, and the second exclusive OR is generated via the data path. (3) Generated decoded data by decoding the received first information by the second exclusive OR, and the relationship between the decoded data and the third received first information via the data path is a redundant code. When there is a detection device that outputs a determination result as to whether or not the
A code generation unit that generates the redundant code from the first information before transmission related to the third reception,
Each data of the first exclusive OR, the transmission-side exclusive OR generator, which generates the redundant code and the second information before transmission related to the second reception,
With
Generator.
(Appendix 12)
Each data of the first exclusive OR, the generation device for generating the redundant code generated from the first information before the third transmission and the second information before the second transmission,
Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; Generates decoded data by decoding the first information received by the third transmission via the second exclusive OR, and transmits the decoded data to the third transmission via the data path. A detection device, which outputs a determination result as to whether the relationship with the received first information is set for the redundant code,
With
Detection system.
(Appendix 13)
Each data of the first exclusive OR is generated by the redundant code generated from the first information before the third transmission and the second information before the second transmission,
Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; Decoded data obtained by decoding the first information received by the third transmission via the data path by the second exclusive OR, and generating the decoded data and the third transmission via the data path Output a determination result as to whether the relationship with the received first information according to is set for the redundant code,
Detection method.
(Appendix 14)
A process of generating each data of the first exclusive OR with the redundant code generated from the first information before the third transmission and the second information before the second transmission,
A process of generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; A process of generating decoded data by decoding the first information received by the third transmission via the data path by the second exclusive OR, and via the decoded data and the data path A detection program that causes a computer to execute a process of outputting a determination result as to whether the relationship with the received first information related to the third transmission is set for the redundant code.

101 transmission side data processing section 1061, 1062 code generation section 106, 1063, 1064, 1065 ECC code generation section 118 transmission side data conversion section 1210, 1211, 1212, 1213, 1214, 1215, 1216 transmission side EXOR circuit 191 transmission side 201 Reception side data processing unit 201x Detection device 2061, 2062, 2063, 2064, 2065 Bit error detection unit 206x Output unit 218 Reception side data conversion unit 221x Reception side exclusive OR generation unit 2210, 2211, 2212, 2213, 2214, 2215 , 2216 Receiver EXOR circuit 291 Receiver 301 Data path 500-bit error detection system

Claims (10)

Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received second via the data path or information derived from the second information A receiving side exclusive OR generating unit,
An output unit that outputs a test result related to a test by the second exclusive OR of the first information third received via the data path,
Equipped with
Each data of the first exclusive OR, the redundant code generated from the first information before transmission related to the third reception, and the second information before transmission related to the second reception or the Information derived from the second information before the transmission related to the second reception, and
Detection device. The detection device according to claim 1, wherein the check is for whether or not the decoded data obtained by the second exclusive OR of the first information is set for the redundant code. The detection device according to claim 1, wherein the information derived from the second information includes degenerate data generated from at least a part of the data of the second information. The detection device according to claim 3, wherein the degenerate data is a parity code generated from at least a part of the data of the second information. The data of the redundant code of the generation source of the arbitrary data of the first exclusive OR is different from the data of the redundant code of the generation source of the other data of the first exclusive OR. Item 6. The detection device according to any one of items 4. 2. The data of the second information, which is the origin of the arbitrary data of the first exclusive OR, is different from the data of the second information, which is the origin of the other data of the first exclusive OR. The detection device according to claim 5. A second exclusive OR of the first exclusive OR received first via the data path and the second information second received via the data path is generated, and the second exclusive OR is generated via the data path. (3) Generated decoded data by decoding the received first information by the second exclusive OR, and the relationship between the decoded data and the third received first information via the data path is a redundant code. When there is a detection device that outputs a determination result as to whether or not it is set for, a code generation unit that generates the redundant code from the first information before transmission related to the third reception,
Each data of the first exclusive OR, the transmission-side exclusive OR generator, which generates the redundant code and the second information before transmission related to the second reception,
With
Generator. Each data of the first exclusive OR, the generation device for generating the redundant code generated from the first information before the third transmission and the second information before the second transmission,
Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; Generates decoded data by decoding the first information received by the third transmission via the second exclusive OR, and transmits the decoded data to the third transmission via the data path. A detection device, which outputs a determination result as to whether the relationship with the received first information is set for the redundant code,
With
Detection system. Each data of the first exclusive OR is generated by the redundant code generated from the first information before the third transmission and the second information before the second transmission,
Generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; Decoded data obtained by decoding the first information received by the third transmission via the data path by the second exclusive OR, and generating the decoded data and the third transmission via the data path Output a determination result as to whether or not the relationship with the received first information according to is set for the redundant code,
Detection method. A process of generating each data of the first exclusive OR with the redundant code generated from the first information before the third transmission and the second information before the second transmission,
A process of generating a second exclusive OR of the first exclusive OR received first via the data path and the second information received by the second transmission via the data path; , A process of generating decoded data obtained by decoding the first information received by the third transmission via the data path by the second exclusive OR, and via the decoded data and the data path A detection program that causes a computer to execute a process of outputting a determination result as to whether the relationship with the received first information related to the third transmission is set for the redundant code.

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