JP2020134635A - Liquid crystal display device - Google Patents

Abstract

To suppress generation of a gradation discontinuous region in a display image as well as to suppress occurrence of a failure in the display quality in a liquid crystal display device constituted by stacking a plurality of display panels.SOLUTION: A liquid crystal display device includes: a first display panel; a second display panel; and an image processing unit for acquiring an n-bit input image data and generating a first image data and a second image data based on the input image data. The image processing unit generates a gamma-processed image data having a greater bit number than the n-bit by using the input image data, and performs an extension processing of extending a gradation expression in n bits on the image data generated by using the gamma-processed image data or on the gamma-processed image data, within a limited gradation range.SELECTED DRAWING: Figure 6

Description

The present invention relates to a liquid crystal display device.

Conventionally, as a technique for improving the contrast of a liquid crystal display device, a technique has been proposed in which two display panels are superposed and an image is displayed on each display panel based on input image data (for example, Patent Document 1). reference). Specifically, for example, of the two display panels arranged on the display surface side and the back side, the color image is displayed on the display panel arranged on the display surface side, and the display panel arranged on the back side is used. By displaying a black-and-white image, the contrast is improved.

Japanese Unexamined Patent Publication No. 2008-191269

In the above-mentioned conventional liquid crystal display device, when the gradation expression is insufficient, a streak-like gradation discontinuity region may occur in the display image. In addition, when an expansion process for expanding the gradation expression is executed in order to suppress the occurrence of such a gradation discontinuity region, there is a problem that the display image has a problem of poor display quality such as flicker and display unevenness. It was.

The present disclosure has been made in view of the above circumstances, and an object of the present invention is to suppress the occurrence of a gradation discontinuous region in a display image and to display the liquid crystal display device configured by superimposing a plurality of display panels. The purpose is to achieve both suppression of the occurrence of poor quality.

In order to solve the above problems, the liquid crystal display device according to the present disclosure is a liquid crystal display device in which a plurality of display panels are overlapped and arranged, and an image is displayed on each of the display panels, and the first image is displayed. The first display panel to be displayed, the second display panel arranged on the back side of the first display panel and displaying the second image, and the input image data are acquired, and based on the input image data. The image processing unit includes an image processing unit that generates a first image data corresponding to the first image and a second image data corresponding to the second image, and the image processing unit is the input. The image data is used to generate gamma-processed image data having a number of bits larger than n bits, and the image data generated using the gamma-processed image data or the gamma-processed image data is ordered by n bits. Extended processing for expanding the tone expression is performed within a limited gradation range.

According to the liquid crystal display device according to the present disclosure, in a liquid crystal display device configured by superimposing a plurality of display panels, the occurrence of a gradation discontinuous region in a display image and the occurrence of poor display quality are suppressed. Can be compatible with each other.

FIG. 1 is a schematic plan view showing a schematic configuration of a liquid crystal display device according to the first embodiment. FIG. 2 is a schematic plan view showing a schematic configuration of a first display panel according to the first embodiment. FIG. 3 is a schematic plan view showing a schematic configuration of a second display panel according to the first embodiment. FIG. 4 is a schematic cross-sectional view showing the AA'cross sections of FIGS. 2 and 3. FIG. 5 is a schematic plan view showing another example of the pixel arrangement of the liquid crystal display device according to the first embodiment. FIG. 6 is a schematic block diagram showing the configuration of the image processing unit according to the first embodiment. FIG. 7 is a schematic block diagram showing another configuration example of the image processing unit according to the first embodiment. FIG. 8 is a schematic block diagram showing another configuration example of the image processing unit according to the first embodiment. FIG. 9 is a schematic block diagram showing another configuration example of the image processing unit according to the first embodiment. FIG. 10 is a schematic block diagram showing another configuration example of the image processing unit according to the first embodiment. FIG. 11 is a graph showing the output gradations of the first image data and the second image data with respect to the input gradation of the input image data in the first embodiment. FIG. 12 is a schematic diagram showing an example of dithering processing. FIG. 13 is a schematic diagram showing an example of the dithering process. FIG. 14 is a schematic diagram showing an example of frame rate control processing.

The first embodiment of the present disclosure will be described below with reference to the drawings. The liquid crystal display device according to the present embodiment controls a plurality of display panels for displaying images, a plurality of drive circuits (plurality of source drivers, a plurality of gate drivers) for driving the respective display panels, and each drive circuit. Image processing is performed on the input image data input from the outside, and the image processing unit that outputs the image data to each timing controller and the plurality of display panels are irradiated with light from the back side. Includes backlight and. The number of display panels is not limited and may be two or more. Further, the plurality of display panels are arranged so as to be overlapped with each other in the front-rear direction when viewed from the observer side, and each of them displays an image. In the following, a liquid crystal display device 10 including two display panels will be described as an example.

FIG. 1 is a schematic view showing a schematic configuration of a liquid crystal display device 10 according to the present embodiment. As shown in FIG. 1, the liquid crystal display device 10 includes a first display panel 100 arranged on the display surface side of the entire liquid crystal display device 10 and a second display panel 100 arranged on the back side of the first display panel 100. A display panel 200, a first timing controller 140 for controlling a first source driver 120 and a first gate driver 130 provided on the first display panel 100, and a second display panel 200 provided on the second display panel 200. A second timing controller 240 that controls the second source driver 220 and the second gate driver 230, and an image processing unit 300 that outputs image data to the first timing controller 140 and the second timing controller 240 are included. I'm out. The first display panel 100 displays the first image (color image in the present embodiment) corresponding to the first image data generated based on the input image data in the first image display area 110, and the second The display panel 200 displays a second image (black and white image in this embodiment) corresponding to the second image data generated based on the input image data in the second image display area 210. The image processing unit 300 receives the input image data Data transmitted from an external system (not shown), executes image processing described later, and then outputs the first image data DAT1 to the first timing controller 140. Then, the second image data DAT2 is output to the second timing controller 240. Further, the image processing unit 300 outputs a control signal (omitted in FIG. 1) such as a synchronization signal to the first timing controller 140 and the second timing controller 240. The first image data DAT1 is the image data for the first image display, and the second image data DAT2 is the image data for the second image display. The backlight (omitted in FIG. 1) is arranged on the back side of the second display panel 200. The specific configuration of the image processing unit 300 will be described later. In this embodiment, an example in which the first image is a color image will be described, but the first image may be a black-and-white image.

FIG. 2 is a schematic diagram showing a schematic configuration of the first display panel 100, and FIG. 3 is a schematic diagram showing a schematic configuration of the second display panel 200. FIG. 4 is a cross-sectional view corresponding to the lines AA'of FIGS. 2 and 3.

The configuration of the first display panel 100 will be described with reference to FIGS. 2 and 4. As shown in FIG. 4, the first display panel 100 is arranged on the back side, that is, the thin film transistor substrate 101 arranged on the backlight 400 side, and on the display surface side of the thin film transistor substrate 101, and faces the thin film transistor substrate 101. It includes a color filter substrate 102 and a liquid crystal layer 103 arranged between the thin film transistor substrate 101 and the color filter substrate 102. The polarizing plate 104 is arranged on the back side of the first display panel 100, that is, the backlight 400 side, and the polarizing plate 105 is arranged on the display surface side.

As shown in FIG. 2, the thin film transistor substrate 101 extends a plurality of data lines 111 extending in the first direction (for example, the column direction) and a second direction (for example, the row direction) different from the first direction. A plurality of gate lines 112 are formed, and a thin film transistor 113 is formed in the vicinity of each intersection of the plurality of data lines 111 and the plurality of gate lines 112. When the first display panel 100 is viewed in a plane, an area surrounded by two adjacent data lines 111 and two adjacent gate lines 112 is defined as one sub-pixel 114, and the sub-pixel 114 is defined as one sub-pixel 114. A plurality of them are arranged in the row direction and the column direction. The plurality of data lines 111 are arranged at equal intervals in the row direction, and the plurality of gate lines 112 are arranged at equal intervals in the column direction. A pixel electrode 115 is formed for each sub-pixel 114 on the thin film transistor substrate 101, and one common electrode (not shown) common to the plurality of sub-pixels 114 is formed. The drain electrode constituting the thin film transistor 113 is electrically connected to the data line 111, the source electrode is electrically connected to the pixel electrode 115, and the gate electrode is electrically connected to the gate wire 112.

As shown in FIG. 4, a plurality of colored portions 102a are formed on the color filter substrate 102 corresponding to each sub-pixel 114. Each colored portion 102a is surrounded by a black matrix 102b that blocks the transmission of light, and is formed in a rectangular shape, for example. Further, the plurality of colored portions 102a are formed of a red material, a red portion that transmits red light, a green portion that transmits green light, and a blue material. It includes a blue part that transmits blue light. The red part, the green part, and the blue part are repeatedly arranged in this order in the row direction, the colored parts of the same color are arranged in the column direction, and the black matrix 102b is formed at the boundary portion of the colored parts 102a adjacent to each other in the row direction and the column direction. Is formed. As shown in FIG. 2, the plurality of sub-pixels 114 corresponding to the colored portions 102a correspond to the red sub-pixel 114R corresponding to the red portion, the green sub-pixel 114G corresponding to the green portion, and the blue portion. The blue sub-pixel 114B and the like are included. In the first display panel 100, one red sub-pixel 114R, one green sub-pixel 114G, and one blue sub-pixel 114B are included to form one pixel 124, and a plurality of pixels 124 are arranged in a matrix. Has been done.

The first timing controller 140 has a well-known configuration. For example, the first timing controller 140 is based on the first image data DAT1 output from the image processing unit 300 and the first control signal CS1 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.). Generates image data DA1 and various timing signals (data start pulse DSP1, data clock DCK1, gate start pulse GSP1, gate clock GCK1) for controlling the drive of the first source driver 120 and the first gate driver 130. (See Fig. 2). The first timing controller 140 outputs the first image data DA1, the data start pulse DSP1, and the data clock DCK1 to the first source driver 120, and outputs the gate start pulse GSP1 and the gate clock GCK1 to the first source driver 120. Output to the gate driver 130.

The first source driver 120 is a driver driven by n bits (n = 10 in this embodiment), and is converted to the first image data DA1 based on the data start pulse DSP1 and the data clock DCK1. The corresponding data signal (data voltage) is output to the data line 111. The first gate driver 130 is a driver driven by n bits (n = 10 in this embodiment), and outputs a gate signal (gate voltage) based on the gate start pulse GSP1 and the gate clock GCK1. Output to the gate line 112.

A data voltage is supplied to each data line 111 from the first source driver 120, and a gate voltage is supplied to each gate line 112 from the first gate driver 130. A common voltage is supplied to the common electrode from a common driver (not shown). When the gate voltage (gate-on voltage) is supplied to the gate line 112, the thin film transistor 113 connected to the gate line 112 is turned on, and the data voltage is supplied to the pixel electrode 115 via the data line 111 connected to the thin film transistor 113. Will be done. An electric field is generated by the difference between the data voltage supplied to the pixel electrode 115 and the common voltage supplied to the common electrode. An image is displayed by driving the liquid crystal by this electric field and controlling the light transmittance of the backlight 400. In the first display panel 100, a color image display is performed by supplying a desired data voltage to the data lines 111 connected to the pixel electrodes 115 of the red sub-pixel 114R, the green sub-pixel 114G, and the blue sub-pixel 114B, respectively. Will be done. A well-known configuration can be applied to the first display panel 100.

Next, the configuration of the second display panel 200 will be described with reference to FIGS. 3 and 4. As shown in FIG. 4, the second display panel 200 includes a thin film transistor substrate 201 arranged on the back side, that is, the backlight 400 side, and a color filter substrate 202 arranged on the display surface side and facing the thin film transistor substrate 201. , The liquid crystal layer 203 arranged between the thin film transistor substrate 201 and the color filter substrate 202. The polarizing plate 204 is arranged on the back side of the second display panel 200, that is, the backlight 400 side, and the polarizing plate 205 is arranged on the display surface side. A diffusion sheet 301 is arranged between the polarizing plate 104 of the first display panel 100 and the polarizing plate 205 of the second display panel 200.

As shown in FIG. 3, the thin film transistor substrate 201 is formed with a plurality of data lines 211 extending in the column direction and a plurality of gate lines 212 extending in the row direction, and the plurality of data lines 211 and a plurality of data lines 211 are formed. A thin film transistor 213 is formed in the vicinity of each intersection with the gate line 212. Looking at the second display panel 200 in a plane, an area surrounded by two adjacent data lines 211 and two adjacent gate lines 212 is defined as one pixel 214, and the pixel 214 is in the row direction. And a plurality of them are arranged in the column direction. The plurality of data lines 211 are arranged at equal intervals in the row direction, and the plurality of gate lines 212 are arranged at equal intervals in the column direction. A pixel electrode 215 is formed for each pixel 214 on the thin film transistor substrate 201, and one common electrode (not shown) common to a plurality of pixels 214 is formed. The drain electrode constituting the thin film transistor 213 is electrically connected to the data line 211, the source electrode is electrically connected to the pixel electrode 215, and the gate electrode is electrically connected to the gate wire 212. Each sub-pixel 114 of the first display panel 100 and each pixel 214 of the second display panel 200 are arranged in a one-to-one relationship with each other, and overlap each other in a plan view. For example, each of the red sub-pixel 114R, the green sub-pixel 114G, and the blue sub-pixel 114B constituting the pixel 124 shown in FIG. 2 and each of the three pixels 214 shown in FIG. 3 overlap in a plan view. As shown in FIG. 5, the three sub-pixels 114 (red sub-pixel 114R, green sub-pixel 114G, blue sub-pixel 114B) of the first display panel 100 (see FIG. 5A) and the second One pixel 214 (see FIG. 5B) of the display panel 200 may overlap with each other in a plan view.

As shown in FIG. 4, the color filter substrate 202 is formed with a black matrix 202b that blocks light transmission at a position corresponding to a boundary portion of each pixel 214. A colored portion is not formed in the region 202a surrounded by the black matrix 202b, and for example, an overcoat film is formed.

The second timing controller 240 has a well-known configuration. For example, the second timing controller 240 has a second timing controller 240 based on the second image data DAT2 output from the image processing unit 300 and the second control signal CS2 (clock signal, vertical synchronization signal, horizontal synchronization signal, etc.). Generates image data DA2 and various timing signals (data start pulse DSP2, data clock DCK2, gate start pulse GSP2, gate clock GCK2) for controlling the drive of the second source driver 220 and the second gate driver 230. (See Fig. 3). The second timing controller 240 outputs the second image data DA2, the data start pulse DSP2, and the data clock DCK2 to the second source driver 220, and outputs the gate start pulse GSP2 and the gate clock GCK2 to the second source driver 220. Output to the gate driver 230.

The second source driver 220 is a driver driven by n bits (n = 10 in this embodiment), and is converted to the second image data DA2 based on the data start pulse DSP2 and the data clock DCK2. The corresponding data voltage is output to the data line 211. The second gate driver 230 is a driver driven by n bits (n = 10 in this embodiment), and transfers the gate voltage to the gate line 212 based on the gate start pulse GSP2 and the gate clock GCK2. Output.

A data voltage is supplied to each data line 211 from the second source driver 220, and a gate voltage is supplied to each gate line 212 from the second gate driver 230. A common voltage is supplied to the common electrode from the common driver. When the gate voltage (gate-on voltage) is supplied to the gate line 212, the thin film transistor 213 connected to the gate line 212 is turned on, and the data voltage is supplied to the pixel electrode 215 via the data line 211 connected to the thin film transistor 213. Will be done. An electric field is generated by the difference between the data voltage supplied to the pixel electrode 215 and the common voltage supplied to the common electrode. An image is displayed by driving the liquid crystal by this electric field and controlling the light transmittance of the backlight 400. A black-and-white image is displayed on the second display panel 200. A well-known configuration can be applied to the second display panel 200.

FIG. 6 is a block diagram showing a specific configuration of the image processing unit 300. The image processing unit 300 includes a second image data generation unit 320, a gamma processing circuit 321, a gradation table 324, a reciprocal multiplication circuit 311 and a first discrimination circuit 312, and a first processing circuit 313. A second discriminant circuit 322 and a second processing circuit 323 are included. The image processing unit 300 performs image processing described later based on the input image data Data of n bits (n = 10 in the present embodiment), and the first image displayed by the first display panel 100. The n-bit first image data DAT1 corresponding to the above and the n-bit second image data DAT2 corresponding to the second image displayed by the second display panel 200 are generated. Further, the image processing unit 300 sets the combined gamma value (γ value) of the display image obtained by combining the first image and the second image to a desired value (in this embodiment, γ = 2.2. ), The first gradation of the first image data DAT1 and the second gradation of the second image data DAT2 are determined.

The n-bit input image data Data transmitted from the external system is input to the second image data generation circuit 320 and the reciprocal multiplication circuit 311 of the image processing unit 300. The input image data Data includes, for example, luminance information (gradation information) and color information. The color information is information for designating a color. For example, when the input image data Data is 10 bits, each color of a plurality of colors including red, green, and blue can be represented by a value of 0 to 1023. The plurality of colors include at least red, green and blue, and may further include white and / or yellow. In the following, as an example, the case where the plurality of colors are red, green, and blue will be mentioned. In the following, the color information of the input image data Data will be referred to as "RGB value" ([R value, G value, B value]). For example, when the color corresponding to the input image data Data is "white", the red value (R value) is represented by [1023], the green value (G value) is represented by [1023], and the blue value. (B value) is represented by [1023]. That is, the "RGB value" is represented by [1023, 1023, 1023]. When the color corresponding to the input image data Data is "red", the "RGB value" is represented by [1023, 0, 0], and when the color corresponding to the input image data Data is "black", the "RGB value" is displayed. Is represented by [0,0,0].

When the second image data generation circuit 320 acquires the 10-bit input image data Data, the values of each color indicating the color information of the input image data Data (here, RGB values: [R value, G value, B value]). The input image data Data is converted into black-and-white image data by using the maximum value (R value, G value or B value) among them. Specifically, the second image data generation circuit 320 sets the maximum value of the RGB values of the RGB values corresponding to the pixel of interest 214 to the value of the pixel of interest 214, thereby converting the input image data Data into black and white. Convert to image data. The second image data generation circuit 320 outputs the input image data Data converted into black and white image data to the gamma processing circuit 321.

The gamma processing circuit 321 performs gamma processing on the input image data Data with reference to the gradation table 324 corresponding to m bits larger than n bits (m = 12 in this embodiment). Generates m-bit gamma-processed image data. For example, the gamma processing circuit 321 uses a second gamma value γ2 set based on the second gamma characteristic corresponding to the second display panel 200 to adjust the gradation of 10-bit image data to a 12-bit image. Convert to data gradation. The gamma processing circuit 321 outputs the gamma-processed image data subjected to the gamma processing to the reciprocal multiplication circuit 311, the second discrimination circuit 322, and the second processing circuit 323.

The reciprocal multiplication circuit 311 multiplies the acquired input image data Data by the reciprocal of the gamma-processed image data acquired from the gamma processing circuit 321 to m bits (in this embodiment, m = 12). Generates image data that has been multiplied by the reciprocal of.

When the first discriminating circuit 312 acquires the reciprocal-multiplied image data from the reciprocal multiplication circuit 311, the first discriminating circuit 312 determines whether or not the gradation of the reciprocal-multiplied image data is within a limited gradation range. The method of setting the limited gradation range and the method of discriminating the first discriminating circuit 312 will be described below with reference to FIG. The limited gradation range does not mean the entire gradation range, and for example, in the case of 10-bit gradation, it means only a part of the gradation range from 0 to 1023. ..

FIG. 11 is a diagram showing output gradations of the first image data DAT1 and the second image data DAT2 with respect to the input gradation of the input image data Data in the present embodiment. The solid line shown in FIG. 11 shows the gradation characteristic of the first image data DAT1, and the alternate long and short dash line shown in FIG. 11 shows the gradation characteristic of the second image data DAT2. In FIG. 11, the input image data Data, the first image data DAT1, and the second image data DAT2 are n-bit image data (n = 10 in this embodiment), respectively.

As shown in FIG. 11, in the gradation range A in which the input gradation is 1 to 256, the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation. In such a range, there is a high possibility that the gradation expression is insufficient in the first image data DAT1. That is, it can be seen that the gradation region in the displayed image is likely to have a gradation discontinuity region.

Further, as shown in FIG. 11, in the gradation range B in which the input gradation is 128 to 256, the increase amount of the output gradation of the second image data DAT2 is 2.5 or less with respect to the increase amount of the input gradation. It has become. In such a range, there is a high possibility that the gradation expression is insufficient in the second image data DAT2. That is, it can be seen that the gradation region in the displayed image is likely to have a gradation discontinuity region.

Therefore, the following examples can be given as an example of setting the first input gradation range as the limited gradation range and an example of discrimination of the first discrimination circuit 312.

(Discrimination example 1 of the first discrimination circuit 312)
As described above, in the gradation range A in which the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation, the gradation expression is insufficient in the first image data DAT1. Probability is high. Therefore, it is desirable to positively perform the first expansion process described later in this range. Therefore, in the discrimination example 1, the first input gradation range as the limited gradation range is set to the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. The input gradation range A in which the amount of increase is less than 1 is set. Then, in the first discrimination circuit 312, the gradation obtained by converting the gradation of the reciprocal-multiplied image data of m bits (m = 12 in the present embodiment) into n bits is the first input. Output of the first image data DAT1 corresponding to the gradation range A discrimination result indicating whether or not the data is included in the gradation range is output.

In the present embodiment, since the m-bit is 12 bits and the n-bit is 10-bit, it is necessary to divide the m-bit reciprocal-multiplied image data by 4 in order to convert it into n-bit. In the example shown in FIG. 11, in the first input gradation range in which the input gradation is 1 to 256, the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation. It has become. The output gradation of the first image data DAT1 in the first input gradation range is 164 to 256. Therefore, when the value obtained by dividing the gradation of the reciprocal-multiplied image data by 4 is included in the gradation range of 164 to 256, that is, when the gradation of the reciprocal-multiplied image data is included in the range of 656 to 1024. The first discrimination circuit 312 outputs a discrimination result (for example, 1) indicating that the gradation of the reciprocal-multiplied image data is within a limited gradation range. The first discrimination circuit 312 may discriminate using the gradation of the image data that has been multiplied by the reciprocal of m bits.

(Discrimination Example 2 of the First Discrimination Circuit 312)
As described above, in the gradation range A in which the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation, the gradation expression is insufficient in the first image data DAT1. Probability is high. Further, in the gradation range C in which the increase amount of the output gradation of the second image data DAT2 is less than 2.5 with respect to the increase amount of the input gradation, the gradation expression is insufficient in the second image data DAT2. Probability is high. Therefore, it is desirable to positively perform the first expansion process described later for the gradation range B that satisfies these two conditions. Therefore, in the discrimination example 2, the first input gradation range as the limited gradation range is set to the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. Input in which the amount of increase is less than 1 and the amount of increase in the output gradation of the second image data DAT2 is less than 2.5 with respect to the amount of increase in the input gradation of the input image data Data. Set to the gradation range B. Then, in the first discrimination circuit 312, the gradation obtained by converting the gradation of the reciprocal-multiplied image data of m bits (m = 12 in the present embodiment) into n bits is the first input. Output of the first image data DAT1 corresponding to the gradation range A discrimination result indicating whether or not the data is included in the gradation range is output.

In the present embodiment, since the m-bit is 12 bits and the n-bit is 10-bit, it is necessary to divide the m-bit reciprocal-multiplied image data by 4 in order to convert it into n-bit. In the example shown in FIG. 11, in the first input gradation range in which the input gradation is 128 to 256, the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. The amount of increase is less than 1, and the amount of increase in the output gradation of the second image data DAT2 is less than 2.5 with respect to the amount of increase in the input gradation of the input image data Data. The output gradation of the first image data DAT1 corresponding to the first input gradation range is 181 to 256. Therefore, when the value obtained by dividing the gradation of the reciprocal-multiplied image data by 4 is included in the gradation range of 181 to 256, that is, when the gradation of the reciprocal-multiplied image data is included in the range of 724 to 1024. The first discrimination circuit 312 outputs a discrimination result (for example, 1) indicating that the gradation of the reciprocal-multiplied image data is within a limited gradation range.

When the first processing circuit 313 acquires the reciprocal-multiplied image data of m bits from the reciprocal multiplication circuit 311, the first reciprocal-multiplied image data is used to generate the n-bit first image data DAT1. Further, the first processing circuit 313 performs a first expansion process for expanding the gradation expression by n bits for the image data that has been multiplied by the reciprocal of m bits according to the discrimination result of the first discrimination circuit 312. Do.

For example, when the first processing circuit 313 acquires a determination result (for example, 1) indicating that the gradation of the reciprocal-multiplied image data is in a limited gradation range from the first determination circuit 312, 12 The image data that has been multiplied by the reciprocal of the bits is converted into the first image data DAT1 of 10 bits, and the gradation is expanded by the average in the area direction using a predetermined dither pattern. By the above dithering process, the 12-bit gradation of the input image data Data can be pseudo-expressed by 10 bits. FIG. 12 is a diagram showing an example of dithering processing. FIG. 12 shows a case where 10-bit gradation data is converted into 8-bit gradation data. The error diffusion method may be used for the dithering process. FIG. 13 is a diagram showing an example of dithering processing by the error diffusion method. According to the error diffusion method, the quality of an image can be improved by performing feedback processing that diffuses the error generated by the conversion process to 8-bit gradation data to surrounding pixels. Well-known techniques can be applied to the dithering process and the error diffusion method. The first processing circuit 313 outputs the 10-bit image data subjected to the expansion processing to the first timing controller 140 as the first image data DAT1.

With such a configuration, it is possible to suppress the occurrence of the gradation discontinuous region in the display image and the occurrence of the flicker at the same time. That is, the first processing circuit 313 converts the m-bit reciprocal-multiplied image data into the n-bit first image data DAT1 and expands the gradation by averaging in the area direction using a predetermined dither pattern. .. Therefore, it is possible to suppress the occurrence of a gradation discontinuous region in the display image. Further, in the first expansion process by the first processing circuit 313, a determination result (for example, 1) indicating that the gradation of the image data to which the reciprocal has been multiplied is in a limited gradation range from the first determination circuit 312. Since it is configured to be performed only when the above is acquired, it is possible to suppress the occurrence of flicker in the displayed image. Therefore, according to the liquid crystal display device 10 according to the present disclosure, it is possible to suppress the occurrence of the gradation discontinuous region in the display image and the occurrence of the flicker at the same time.

When the first processing circuit 313 obtains a determination result (for example, 0) from the first determination circuit 312 indicating that the gradation of the reciprocal-multiplied image data is not within the limited gradation range, For example, the value of the lowest (mn) bit in the reciprocal-multiplied image data of m bits is truncated or the value of the lowest (mn + 1) bit is not performed without performing the first expansion process described above. By adding 1 to, the reciprocal-multiplied image data of m bits is converted into the first image data DAT1 of n bits and output. In the present embodiment, the first processing circuit 313 has the lowest 3 bits in the inversely multiplied image data when the value of the lowest 2 bits in the m-bit inversely multiplied image data is equal to or more than a predetermined value. 1 is added to the eyes, and if the value of the lowest 2 bits is less than the predetermined value, it is truncated without adding 1 to the lowest 3 bits to add the n-bit first image data DAT1. Convert and output.

Further, in the present embodiment, as described above, the image processing unit 300 includes the second discrimination circuit 322 and the second processing circuit 323.

The second discrimination circuit 322 determines whether or not the gradation of the gamma-processed image data output from the gamma processing circuit 321 is within a limited gradation range. The following examples can be given as examples of setting the limited gradation range and discriminating the second discriminating circuit 322.

(Discrimination example 1 of the second discrimination circuit 322)
As described above, in the gradation range A in which the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation, the gradation expression is insufficient in the first image data DAT1. Probability is high. Therefore, with respect to this range, at least the gamma-processed image data used for generating the second image data DAT2 is positively subjected to the second expansion processing described later to obtain the first image and the second image. It is desirable to suppress the occurrence of gradation discontinuous regions in the composite image of. Therefore, in the discrimination example 1, the second input gradation range as the limited gradation range is set to the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. The gradation range A is set so that the amount of increase is less than 1. Then, in the second discrimination circuit 322, the gradation obtained by converting the gradation of the gamma-processed image data of m bits (m = 12 in the present embodiment) into n bits is the input of the second input. Output of the second image data DAT2 corresponding to the gradation range A discrimination result indicating whether or not the data is included in the gradation range is output. The second discrimination circuit 322 may discriminate using the gradation of m-bit gamma-processed image data.

In the present embodiment, since the m-bit is 12 bits and the n-bit is 10-bit, it is necessary to divide the m-bit gamma-processed image data by 4 in order to convert it into n-bit. In the example shown in FIG. 11, in the second input gradation range in which the input gradation is 1 to 256, the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation. It becomes. The output gradation of the second image data DAT2 corresponding to the second input gradation range is 6 to 1023. Therefore, when the value obtained by dividing the gradation of the gamma-processed image data by 4 is included in the gradation range of 6 to 1023, that is, when the gradation of the gamma-processed image data is included in the range of 24 to 4092. The second discrimination circuit 322 outputs a discrimination result (for example, 1) indicating that the gradation of the gamma-processed image data is in the output gradation range corresponding to the second input gradation range.

(Discrimination example 2 of the second discrimination circuit 322)
As described above, in the gradation range A in which the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation, the gradation expression is insufficient in the first image data DAT1. Probability is high. Further, in the gradation range C in which the increase amount of the output gradation is less than 2.5 with respect to the increase amount of the input gradation, there is a high possibility that the gradation expression is insufficient in the second image data DAT2. Therefore, it is desirable to positively perform the second expansion process described later for the gradation range B that satisfies these two conditions. Therefore, in the discrimination example 2, the second input gradation range as the limited gradation range is set to the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. Input in which the amount of increase is less than 1 and the amount of increase in the output gradation of the second image data DAT2 is less than 2.5 with respect to the amount of increase in the input gradation of the input image data Data. Set to the gradation range B. Then, in the second discrimination circuit 322, the gradation obtained by converting the gradation of the gamma-processed image data of m bits (m = 12 in the present embodiment) into n bits is the input of the second input. Output of the second image data DAT2 corresponding to the gradation range A determination result indicating whether or not the gradation range is included is output.

In the present embodiment, since the m-bit is 12 bits and the n-bit is 10-bit, it is necessary to divide the m-bit reciprocal-multiplied image data by 4 in order to convert it into n-bit. In the example shown in FIG. 11, in the second input gradation range in which the input gradation is 128 to 256, the output gradation of the first image data DAT1 with respect to the increase amount of the input gradation of the input image data Data. The amount of increase is less than 1, and the amount of increase in the output gradation of the second image data DAT2 is less than 2.5 with respect to the amount of increase in the input gradation of the input image data Data. The output gradation of the second image data DAT2 corresponding to the second input gradation range is 724 to 1023. Therefore, when the value obtained by dividing the gradation of the gamma-processed image data by 4 is included in the gradation range of 724 to 1023, that is, when the gradation of the gamma-processed image data is included in the range of 2896 to 4092. The second discrimination circuit 322 outputs a discrimination result (for example, 1) indicating that the gradation of the gamma-processed image data is in the output gradation range corresponding to the second input gradation range.

When the second processing circuit 323 acquires m-bit gamma-processed image data from the gamma-processing circuit 321, the second processing circuit 323 uses the gamma-processed image data to generate n-bit second image data DAT2. Further, the second processing circuit 323 performs a second expansion process of expanding the gradation expression by n bits on the m-bit gamma-processed image data according to the discrimination result of the second discrimination circuit 322. Do.

For example, when the second processing circuit 323 obtains a discrimination result (for example, 1) indicating that the gradation of the gamma-processed image data is in a limited gradation range from the second discrimination circuit 322, 12 The bit gamma-processed image data is converted into the 10-bit second image data DAT2, and the gradation is expanded by averaging in the area direction using a predetermined dither pattern. By the above dithering process, the 12-bit gradation of the input image data Data can be pseudo-expressed by 10 bits. The second processing circuit 323 outputs the 10-bit image data subjected to the expansion processing to the second timing controller 240 as the second image data DAT2.

In this way, since the second processing circuit 323 performs the second expansion processing for expanding the gradation expression by n bits on the m-bit gamma-processed image data, the gradation discontinuity region in the display image is performed. It is possible to further suppress the occurrence of. Further, the second processing circuit 323 only obtains a discrimination result (for example, 1) indicating that the gradation of the gamma-processed image data is in a limited gradation range from the second discrimination circuit 322. Since the configuration is such that the second expansion process is performed, it is possible to further suppress the occurrence of the gradation discontinuous region while suppressing the occurrence of flicker in the displayed image.

When the second processing circuit 323 obtains a determination result (for example, 0) from the second discrimination circuit 322 that the gradation of the gamma-processed image data is not within the limited gradation range, Without performing the second expansion process described above, for example, the value of the lowest (mn) bit in the m-bit gamma-processed image data is truncated, or the value of the lowest (mn + 1) bit. By adding 1 to, the m-bit gamma-processed image data is converted into the n-bit second image data DAT2 and output. In the present embodiment, the second processing circuit 323 has the lowest 3 bits in the gamma-processed image data when the value of the lowest 2 bits in the m-bit gamma-processed image data is equal to or more than a predetermined value. 1 is added to the eyes, and if the value of the lowest 2 bits is less than the predetermined value, it is truncated without adding 1 to the lowest 3 bits to add 1 to the n-bit second image data DAT2. Convert and output.

The expansion process for expanding the gradation expression in the first processing circuit 313 and the second processing circuit 323 is not limited to the dithering process described above, and may be, for example, a frame rate control process. FIG. 14 is a diagram showing an example of frame rate control processing. For example, when 10-bit image data representing 65 gradations is expressed by 8-bit image data, 65 gradations are expressed by averaging in the time axis direction (for example, for 4 frames). A well-known method can be applied to the frame rate control process.

In the configuration shown in FIG. 6, the configuration in which the image processing unit 300 includes the second discrimination circuit 322 and the second processing circuit 323 has been described as an example, but the image processing unit 300 is the second discrimination circuit. An output circuit that does not have 322 and a second processing circuit 323, converts the gamma-processed image data from the gamma processing circuit 321 into 10 bits, and outputs it as the second image data DAT2 to the second timing controller 240. May be provided separately. However, as described above, by configuring the image processing unit 300 to include the second discrimination circuit 322 and the second processing circuit 323, the occurrence of a gradation discontinuous region is generated while suppressing the occurrence of flicker in the displayed image. It is desirable because it can further suppress the above.

As shown in FIG. 7, the image processing unit 300 may further include a filter circuit 325 that performs smoothing processing on the gamma-processed image data output by the gamma processing circuit 321.

When the filter circuit 325 acquires the gamma-processed image data, the filter circuit 325 performs a smoothing process on the gamma-processed image data by using an average value filter common to all pixels 214 in each frame. For example, in the filter circuit 325, for each pixel 214, a pixel region consisting of 11 vertical pixels and 11 horizontal pixels centered on the pixel 214 is set as the filter size, and the average value of the brightness within this filter size is defined as the brightness of the pixel 214. Perform the processing to be performed. The filter size is not limited to the 11 × 11 pixel region, but is set to a common filter size for all pixels 214 in each frame. Further, the filter shape is not limited to a square shape and may be a circular shape. According to the smoothing process, the high frequency component is deleted, so that the change in brightness can be smoothed. The filter circuit 325 outputs the smoothed gamma-processed image data to the reciprocal multiplication circuit 311 and the second discrimination circuit 322, and the second processing circuit 323.

In this case, the reciprocal multiplication circuit 311 may multiply the input image data Data by the reciprocal of the gamma-processed image data subjected to the smoothing process to generate the reciprocal-multiplied image data of m bits.

Further, in the second discrimination circuit 322, the gradation of the gamma-processed image data subjected to the smoothing processing is set to the output gradation range of the second image data DAT2 corresponding to the second input gradation range. It may be determined whether or not there is. The discrimination method by the second discrimination circuit 322 is as described above.

In the example shown in FIG. 7, in the second discrimination circuit 322, the gradation of the gamma-processed image data subjected to the smoothing processing corresponds to the second input gradation range. An example of determining whether or not the image data is within the output gradation range of the DAT2 has been shown. As shown in FIG. 8, the gamma-processed image before the second determination circuit 322 is input to the filter circuit 325. It may be configured to determine whether or not the gradation of the data is within the output gradation range of the second image data DAT2 corresponding to the second input gradation range. Further, the second discrimination circuit 322 may be configured to determine whether or not the gradation of the input image data Data is within the second input gradation range. In that case, since the input image data Data is n bits, it is not necessary to convert the gradation of the m-bit gamma-processed image data into n bits.

In the examples shown in FIGS. 6 and 7, the gradation of the reciprocal-multiplied image data output by the reciprocal multiplication circuit 311 in the first discrimination circuit 312 corresponds to the first input gradation range. An example of determining whether or not the data is within the output gradation range of the image data DAT1 of 1 is shown. However, as shown in FIG. 8, the first determination circuit 312 sets the gradation of the input image data Data to the first. It may be configured to determine whether or not it is within the input gradation range of. In that case, the method of setting the first input gradation range may be set in the same manner as described above. Further, in determining whether or not the input image data Data is in the first input gradation range, since the input image data Data is n bits, the gradation of the image data that has been multiplied by the inverse of m bits is n. There is no need for processing such as converting to bits.

In the examples shown in FIGS. 6 to 8, the image processing unit 300 includes the reciprocal multiplication circuit 311, and the reciprocal multiplication circuit 311 multiplies the input image data by the reciprocal of the gamma-processed image data to m bits. Although an example of generating reciprocal-multiplied image data of is shown, the present disclosure is not limited thereto.

In the example shown in FIG. 9, the image processing unit 300A includes a second image data generation unit 320A, a second gamma processing circuit 321A, a second gradation table 324A, and a first gamma processing circuit 311A. , The first gradation table 314A, the first discrimination circuit 312A, the first processing circuit 313A, the second discrimination circuit 322A, and the second processing circuit 323A are included. That is, in the example shown in FIG. 9, the image processing unit 300A does not include the reciprocal multiplication circuit 311 but includes the first gamma processing circuit 311A and the first gradation table 314A. In the example shown in FIG. 9, the second gamma processing circuit 321A and the second gradation table 324A have the same configuration as the gamma processing circuit 321 and the gradation table 324 shown in FIG. The explanation is omitted. In the example shown in FIG. 9, the gamma processing performed by the second gamma processing circuit 321A is set as the second gamma processing, and the image data output by the second gamma processing circuit 321A is the second gamma-processed image. Let it be data. Further, since the second discrimination circuit 322A and the second processing circuit 323A have the same configurations as the second discrimination circuit 322 and the second processing circuit 323 shown in FIG. 6 and the like, the description thereof will be omitted. ..

In the example shown in FIG. 9, the first gamma processing circuit 311A corresponds to the first p-bit (p = 14 in the present embodiment) larger than n bits with respect to the input image data Data. The first gamma processing is performed with reference to the gradation table 314A of the above, and the first gamma-processed image data of p bits is generated. For example, the first gamma processing circuit 311A uses the first gamma value γ1 set based on the first gamma characteristic corresponding to the first display panel 100 to adjust the gradation of 10-bit image data to 14. Converts to the gradation of bit image data. The first gamma processing circuit 311A outputs the gamma-processed image data subjected to the first gamma processing to the first discrimination circuit 312A and the first processing circuit 313A.

Here, a method for setting the first gamma value γ1 and the second gamma value γ2 described above will be described. For example, for the first gamma value γ1 and the second gamma value γ2, the combined gamma value of the composite image obtained by combining the first image which is a color image and the second image which is a black-and-white image is 2.2. Is set to. For example, when both the first gamma characteristic of the first display panel 100 and the second gamma characteristic of the second display panel 200 have a gamma value of 2.2, the brightness of the first display panel 100 is set to Lm and the second. Assuming that the brightness of the display panel 200 is Ls, the combined brightness is represented by Lm × Ls. The combined brightness Lm × Ls is expressed by the input image data Data, the first gamma value γ1, and the second gamma value γ2 by the following equation.
Lm × Ls = (Data ^ γ1) ^ 2.2 × (Data ^ γ2) ^ 2.2
= Data ^ (γ1 × 2.2) × Data ^ (γ2 × 2.2)
= Data ^ (γ1 × 2.2 + γ2 × 2.2)
Therefore, if the first gamma value γ1 and the second gamma value γ2 are set so that (γ1 + γ2) = 1, the synthetic gamma value can be set to 2.2.

In the example shown in FIG. 9, in the first discrimination circuit 312A, the gradation of the first gamma-processed image data corresponds to the output gradation range of the first image data DAT1 corresponding to the first input gradation range. Determine if it is in. The method of setting the first input gradation range is the same as the example shown with reference to FIG. 6 and the like. That is, the method of setting the first input gradation range is, for example, an input gradation in which the amount of increase in the output gradation of the first image data DAT1 is less than 1 with respect to the amount of increase in the input gradation of the input image data Data. The input gradation range in which the increase amount of the output gradation of the first image data DAT1 is less than 1 with respect to the increase amount of the input gradation of the range A and the input image data Data, and the input of the input image data Data. It is possible to set by the input gradation range B or the like in which the increase amount of the output gradation of the second image data DAT2 is less than 2.5 with respect to the increase amount of the gradation.

In the present embodiment, since the p-bit is 14 bits and the n-bit is 10 bits, it is necessary to divide the first gamma-processed image data of the p-bit by 16 in order to convert it into n-bits. is there. Therefore, when the value obtained by dividing the gradation of the first gamma-processed image data by 16 is included in the output gradation range corresponding to the first input gradation range described above, the first discrimination circuit 312A A determination result (for example, 1) indicating that the gradation of the first gamma-processed image data is in a limited gradation range is output. On the contrary, when the value obtained by dividing the gradation of the first gamma-processed image data by 16 is not included in the output gradation range corresponding to the first input gradation range described above, the first discrimination circuit 312A Outputs a determination result (for example, 0) indicating that the gradation of the first gamma-processed image data is not within the limited gradation range.

The first processing circuit 313A uses the p-bit first gamma-processed image data to generate n-bit first image data DAT1. Further, the first processing circuit 313A is a first that extends the gradation expression by n bits with respect to the p-bit first gamma-processed image data according to the discrimination result of the first discrimination circuit 312A. Perform extended processing.

As shown in FIG. 10, the image processing unit 300A may further include a filter circuit 325A that performs smoothing processing on the second gamma-processed image data output by the second gamma processing circuit 321A. Good. In that case, the second discrimination circuit 322A outputs the second image data DAT2 in which the gradation of the second gamma-processed image data subjected to the smoothing processing corresponds to the second input gradation range. It may be configured to determine whether or not it is in the gradation range, and the gradation of the second gamma-processed image data before the second discrimination circuit 322A is input to the filter circuit 325 is the second. It may be configured to determine whether or not it is within the output gradation range of the second image data DAT2 corresponding to the input gradation range of. Further, the second discrimination circuit 322A may be configured to determine whether or not the gradation of the input image data Data is within the second input gradation range. In that case, since the input image data Data is n bits, it is not necessary to convert the gradation of the second gamma-processed image data of m bits into n bits.

In the example shown in FIGS. 9 and 10, the gradation of the first gamma-processed image data output by the first discrimination circuit 312A by the first gamma-processing circuit 311A is the first input floor. An example of determining whether or not the data is within the output gradation range of the first image data DAT1 corresponding to the adjustment range has been shown, but the first determination circuit 312A has the input image data Data having the first gradation. It may be configured to determine whether or not it is within the input gradation range. In that case, the method of setting the first input gradation range may be set in the same manner as described above. Further, in determining whether or not the input image data Data is in the first input gradation range, since the input image data Data is n bits, the gradation of the p-bit first gamma-processed image data. Is not required to be converted into n bits.

In the present embodiment, the number of bits of the input image data Data and the number of bits of the first image data DAT1 and the second image data DAT2 are the same n bits. Disclosure is not limited to that. That is, the gradation expression is expanded by n bits by using image data having a bit number larger than the number of bits of the first image data DAT1 and the second image data DAT2 (for example, m-bit gamma-processed image data). In the case of a configuration in which the first expansion process and the second expansion process are performed, the number of bits of the input image data Data and the number of bits of the first image data DAT1 and the second image data DAT2 need to be the same. Absent.

In the liquid crystal display device 10 according to the present embodiment, the configuration in which the first display panel 100 is arranged on the display surface side and the second display panel 200 is arranged on the back side is illustrated, but the first display The panel 100 may be arranged on the back side, and the second display panel 200 may be arranged on the display surface side. Further, the first display panel 100 and the second display panel 200 may both be configured to display a black-and-white image, or both may be configured to display a color image.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and there are also embodiments appropriately modified by those skilled in the art from the above embodiments without departing from the spirit of the present invention. Needless to say, it is included in the technical scope of the present invention.

10 LCD display device, 100 1st display panel, 101 thin film substrate, 102 color filter substrate, 102a colored part, 102b black matrix, 103 liquid crystal layer, 104 polarizing plate, 105 polarizing plate, 111 data line, 112 gate line, 113 Thin film, 114 subpixels, 114R red subpixels, 114G green subpixels, 114B blue subpixels, 115 pixel electrodes, 124 pixels, 120 first source driver, 130 first gate driver, 140 first timing controller, 200 Second display panel, 201 thin film substrate, 202 color filter substrate, 202a region, 202b black matrix, 203 liquid crystal layer, 204 polarizing plate, 205 polarizing plate, 211 data line, 212 gate line, 213 thin film, 214 pixels, 215 pixels Electrode, 220 2nd source driver, 230 2nd gate driver, 240 2nd timing controller, 300 image processing unit, 300A image processing unit, 301 diffusion sheet, 320 2nd image data generation unit, 321 gamma processing circuit 324 Gradation table, 311 Inverse multiplication circuit, 312 First discrimination circuit, 313 First processing circuit, 322 Second discrimination circuit, 323 Second processing circuit, 325 Filter circuit, 320A Second image data generation Unit, 321A gamma processing circuit, 324A gradation table, 311A first gamma processing circuit, 314A first gradation table, 312A first discrimination circuit, 313A first processing circuit, 320 second image data generation circuit , 322A 2nd discrimination circuit, 323A 2nd processing circuit, 325A filter circuit, 400 backlight, Data input image data, DAT1 1st image data, CS1 1st control signal, DA1 1st image data, DSP1 data Start pulse, DCK1 data clock, GSP1 gate start pulse, GCK1 gate clock, DAT2 second image data, CS2 second control signal, DA2 second image data, DSP2 data start pulse, DCK2 data clock, GSP2 gate start pulse, GCK2 gate clock.

Claims (14)

A liquid crystal display device in which a plurality of display panels are superposed and arranged, and an image is displayed on each of the display panels.
The first display panel that displays the first image and
A second display panel arranged on the back side of the first display panel and displaying a second image, and
Image processing that acquires input image data and generates first image data corresponding to the first image and second image data corresponding to the second image based on the input image data. Including the part
The image processing unit
Using the input image data, gamma-processed image data having a number of bits larger than n bits is generated.
An expansion process for expanding the gradation expression with the n bits is performed on the image data generated by using the gamma-processed image data or the gamma-processed image data within a limited gradation range.
Liquid crystal display device. The image processing unit
A gamma processing circuit that performs gamma processing on the input image data with reference to a gradation table corresponding to an m bit larger than the n bits and generates the gamma processed image data of the m bits.
A reciprocal multiplication circuit that multiplies the input image data by the reciprocal of the gamma-processed image data to generate the reciprocal-multiplied image data of the m bits.
A first discriminating circuit that determines whether or not the gradation of the input image data or the gradation of the image data that has been reciprocally multiplied is within the limited gradation range.
A first processing circuit that generates the first image data of the n bits using the reciprocal multiplied image data of the m bits, and a first processing circuit.
Including
The first processing circuit is a first expansion process for expanding the gradation expression with the n bits for the reciprocal-multiplied image data of the m bits according to the discrimination result of the first discrimination circuit. I do,
The liquid crystal display device according to claim 1. The limited gradation range is a first input gradation range in which the increase amount of the output gradation of the first image data is less than 1 with respect to the increase amount of the input gradation of the input image data.
The first discrimination circuit
The gradation obtained by converting the gradation of the m-bit inversely multiplied image data into the n bits is included in the output gradation range of the first image data corresponding to the first input gradation range. When it is determined that the gradation of the input image data is included in the first input gradation range.
The first processing circuit performs the first expansion processing.
The liquid crystal display device according to claim 2. The limited gradation range is an input gradation range in which the amount of increase in the output gradation of the first image data is less than 1 with respect to the amount of increase in the input gradation of the input image data. It is the first input gradation range in which the increase amount of the output gradation of the second image data is 2.5 or less with respect to the increase amount of the input gradation of the input image data.
The first discrimination circuit
The gradation obtained by converting the gradation of the m-bit inversely multiplied image data into the n bits is included in the output gradation range of the first image data corresponding to the first input gradation range. When it is determined that the gradation of the input image data is included in the first input gradation range.
The first processing circuit performs the first expansion processing.
The liquid crystal display device according to claim 2. The image processing unit
A second discriminating circuit that determines whether or not the gradation of the input image data or the gradation of the gamma-processed image data is within the limited gradation range.
A second processing circuit that generates the n-bit second image data using the m-bit gamma-processed image data, and a second processing circuit.
Including
The second processing circuit is a second expansion process for expanding the gradation expression with the n bits for the gamma-processed image data of the m bits according to the discrimination result of the second discrimination circuit. I do,
The liquid crystal display device according to claim 2. The limited gradation range is a second input gradation range in which the amount of increase in the output gradation of the first image data is less than 1 with respect to the amount of increase in the input gradation of the input image data.
The second discrimination circuit
When the gradation obtained by converting the gradation of the gamma-processed image data of the m-bit into the n-bit is included in the output gradation range of the second image data corresponding to the second input gradation range. When it is determined, or when it is determined that the gradation of the input image data is included in the second input gradation range,
The second processing circuit performs the second expansion processing.
The liquid crystal display device according to claim 5. The limited gradation range is an input gradation range in which the amount of increase in the output gradation of the first image data is less than 1 with respect to the amount of increase in the input gradation of the input image data. It is the second input gradation range in which the increase amount of the output gradation of the second image data is less than 2.5 with respect to the increase amount of the input gradation of the input image data.
The second discrimination circuit
When the gradation obtained by converting the gradation of the gamma-processed image data of the m-bit into the n-bit is included in the output gradation range of the second image data corresponding to the second input gradation range. When it is determined, or when it is determined that the gradation of the input image data is included in the second input gradation range,
The second processing circuit performs the second expansion processing.
The liquid crystal display device according to claim 5. The image processing unit
The input image data is subjected to the first gamma processing with reference to the first gradation table corresponding to the p bits larger than the n bits, and the first gamma-processed image data of the p bits is generated. The first gamma processing circuit to do
The input image data is subjected to the second gamma processing with reference to the second gradation table corresponding to the m bits larger than the n bits, and the second gamma processed image data of the m bits is generated. The second gamma processing circuit to do
A first discriminating circuit that determines whether or not the gradation of the input image data or the gradation of the first gamma-processed image data is within the limited gradation range.
A first processing circuit that generates the n-bit first image data using the p-bit first gamma-processed image data, and a first processing circuit.
Including
The first processing circuit extends the gradation expression by the n bits with respect to the first gamma-processed image data of the p bits according to the discrimination result of the first discrimination circuit. Extend processing of
The liquid crystal display device according to claim 1. The limited gradation range is a first input gradation range in which the increase amount of the output gradation of the first image data is less than 1 with respect to the increase amount of the input gradation of the input image data.
The first discrimination circuit
The output gradation range of the first image data in which the gradation obtained by converting the gradation of the first gamma-processed image data of the p-bit into the n-bit corresponds to the first input gradation range. When it is determined that the input image data is included in the first input gradation range, or when it is determined that the gradation of the input image data is included in the first input gradation range.
The first processing circuit performs the first expansion processing.
The liquid crystal display device according to claim 8. The limited gradation range is an input gradation range in which the amount of increase in the output gradation of the first image data is less than 1 with respect to the amount of increase in the input gradation of the input image data. It is the first input gradation range in which the increase amount of the output gradation of the second image data is less than 2.5 with respect to the increase amount of the input gradation of the input image data.
The first discrimination circuit
The output gradation range of the first image data in which the gradation obtained by converting the gradation of the first gamma-processed image data of the p-bit into the n-bit corresponds to the first input gradation range. When it is determined that the input image data is included in the first input gradation range, or when it is determined that the gradation of the input image data is included in the first input gradation range.
The first processing circuit performs the first expansion processing.
The liquid crystal display device according to claim 8. The image processing unit
A second discriminating circuit that determines whether or not the gradation of the input image data or the gradation of the second gamma-processed image data is within the limited gradation range.
A second processing circuit that generates the n-bit second image data using the m-bit second gamma-processed image data, and a second processing circuit.
Including
The second processing circuit is an extension process for expanding the gradation expression with the n bits for the second gamma-processed image data of the m bits according to the discrimination result of the second discrimination circuit. I do,
The liquid crystal display device according to claim 8. The limited gradation range is a second input gradation range in which the increase amount of the output gradation of the first image data is less than 1 with respect to the increase amount of the input gradation of the input image data.
The second discrimination circuit
The gradation obtained by converting the gradation of the second gamma-processed image data of the m-bit into the n-bit becomes the output gradation range of the second image data corresponding to the second input gradation range. When it is determined that it is included, or when it is determined that the gradation of the input image data is included in the second input gradation range.
The second processing circuit performs the second expansion processing.
The liquid crystal display device according to claim 11. The limited gradation range is an input gradation range in which the amount of increase in the output gradation of the first image data is less than 1 with respect to the amount of increase in the input gradation of the input image data. It is the second input gradation range in which the increase amount of the output gradation of the second image data is less than 2.5 with respect to the increase amount of the input gradation of the input image data.
The second discrimination circuit
The gradation obtained by converting the gradation of the second gamma-processed image data of the m-bit into the n-bit becomes the output gradation range of the second image data corresponding to the second input gradation range. When it is determined that the input image data is included, or when it is determined that the gradation of the input image data is included in the second input gradation range.
The second processing circuit performs the second expansion processing.
The liquid crystal display device according to claim 11. The number of bits of the input image data is n bits.
The liquid crystal display device according to any one of claims 1 to 13.

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