JP2020127073A - Solid-state imaging element, imaging device, and method for controlling solid-state imaging element - Google Patents

Abstract

To reduce noise due to jitter in a solid-state imaging element with a single-slope ADC arranged therein.SOLUTION: A solid-state imaging element includes a reference signal generation unit, a filter circuit, and an analog-digital converter. The reference signal generation unit generates a predetermined reference signal in synchronization with a predetermined clock signal. The filter circuit passes a specific frequency component of jitter of the clock signal. The analog-digital converter converts an analog signal into a digital signal using the specific frequency component and the reference signal.SELECTED DRAWING: Figure 14

Description

The present technology relates to a solid-state imaging device, an imaging device, and a method for controlling a solid-state imaging device. More specifically, the present invention relates to a solid-state image sensor that converts an analog signal into a digital signal in synchronization with a clock signal, an image pickup apparatus, and a method for controlling the solid-state image sensor.

2. Description of the Related Art Conventionally, a single slope type ADC (Analog to Digital Converter) has been widely used because of its simple structure for AD (Analog to Digital) conversion of an analog signal in an imaging device or the like. A single-slope ADC is generally provided with a comparator that compares a reference signal and an analog signal and a counter that counts until the comparison result is inverted. For example, a solid-state imaging device has been proposed in which a single-slope ADC is arranged for each column and a DAC (Digital to Analog Converter) that supplies a reference signal to these ADCs is provided (see, for example, Patent Document 1). .. In this solid-state image pickup device, the DAC and the counter in the ADC operate in synchronization with the same clock signal.

JP, 2013-126015, A

In the above-mentioned conventional technique, the solid-state image sensor can perform AD conversion of an analog signal on a row-by-row basis by the ADC arranged in each column. However, if jitter occurs in the clock signal that operates the DAC or the counter, noise (horizontal pulling noise, etc.) occurs in the digital signal after AD conversion due to the jitter, and the image quality of the image data composed of those digital signals is It may decrease. Although noise due to jitter can be suppressed by adding a circuit or element for reducing jitter to a PLL (Phase Locked Loop) as a supply source of a clock signal, the circuit area and power consumption of the PLL increase. Therefore, it is not preferable. As described above, the above solid-state image sensor has a problem that it is difficult to reduce noise due to jitter.

The present technology is created in view of such a situation, and an object thereof is to reduce noise due to jitter in a solid-state imaging device in which a single slope type ADC is arranged.

The present technology has been made to solve the above-described problems, and a first aspect thereof is a reference signal generation unit that generates a predetermined reference signal in synchronization with a predetermined clock signal, and the clock signal. A solid-state image sensor including a filter circuit that allows passage of a specific frequency component of the jitter, and an analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal, and It is a control method. As a result, the analog signal is converted into a digital signal by the specific frequency component of the jitter and the reference signal.

Further, in the first aspect, the specific frequency component is a high frequency component exceeding a predetermined upper limit frequency of the clock signal, and the reference signal generating unit satisfies a predetermined lower limit frequency of the jitter. A low-frequency component that does not exist is passed through, and the analog-digital converter compares the reference signal added with the high-frequency component with the analog signal and outputs a comparison result, until the comparison result is inverted. A counter that counts the count value in synchronization with the clock signal over the period and outputs the count value as the digital signal. This brings about the effect that the analog signal is added to the digital signal by the reference signal to which the high frequency component is added.

Further, in the first aspect, the filter circuit detects an edge of the clock signal and outputs the detected signal as a detection signal, and alternately outputs a high level and a low level in synchronization with the detection signal. And a toggle circuit for switching. As a result, the high frequency component of the edge passes through the edge detection circuit.

In the first aspect, a switched capacitor circuit that charges and discharges a capacitor in synchronization with the clock signal, a resistor connected in series to the capacitor, and a signal input via the resistor are synchronized. A toggle circuit that alternately outputs a high level and a low level, and a switch that opens and closes a path between the resistor and the toggle circuit in synchronization with the clock signal may be provided. This brings about the effect that the high frequency component of the edge passes through the switched capacitor register circuit.

Further, in the first aspect, the specific frequency component is a low frequency component that is less than a predetermined lower limit frequency of the clock signal, and the reference signal generation unit includes at least a part of the specific frequency component. , The analog-digital converter is a comparator for comparing the reference signal and the analog signal and outputting a comparison result, and the specific frequency component of the specific frequency component over a period until the comparison result is inverted. A counter that counts the count value in synchronization with the signal and outputs the count value as the digital signal may be provided. As a result, the analog signal is converted into a digital signal in synchronization with the low frequency component signal.

A second aspect of the present technology is to provide a reference signal generation unit that generates a predetermined reference signal in synchronization with a predetermined clock signal, a filter circuit that passes a specific frequency component of the jitter of the clock signal, An image pickup apparatus comprising: an analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal; and a signal processing unit that performs predetermined signal processing on the digital signal. As a result, the analog signal is converted into a digital signal by the specific frequency component of the jitter and the reference signal, and the signal processing is performed.

In addition, a third aspect of the present technology includes a timing control unit that outputs a predetermined clock signal, a reference signal generation unit that generates a predetermined reference signal in synchronization with the clock signal, and a jitter of the clock signal. A solid-state imaging device comprising: a filter circuit that passes a specific frequency component; and an analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal. As a result, the analog signal is converted into a digital signal by the specific frequency component of the jitter and the reference signal.

Further, in the third aspect, the specific frequency component is a high frequency component exceeding a predetermined upper limit frequency of the clock signal, and the reference signal generating unit satisfies a predetermined lower limit frequency of the jitter. A low-frequency component that does not exist is passed through, and the analog-digital converter compares the reference signal added with the high-frequency component with the analog signal and outputs a comparison result, until the comparison result is inverted. A counter that counts the count value in synchronization with the clock signal over the period and outputs the count value as the digital signal. This brings about the effect that the analog signal is added to the digital signal by the reference signal to which the high frequency component is added.

Further, in the third aspect, the filter circuit may be arranged between the timing control unit and the comparator. This brings about the effect that filtering is performed between the timing control unit and the comparator.

Further, in the third aspect, the specific frequency component is a low frequency component that is less than a predetermined lower limit frequency of the clock signal, and the reference signal generation unit includes at least a part of the specific frequency component. , The analog-digital converter is a comparator that outputs the comparison result by comparing the reference signal and the analog signal, and the specific frequency component of the specific frequency component over a period until the comparison result is inverted. A counter that counts the count value in synchronization with the signal and outputs the count value as the digital signal may be provided. As a result, the analog signal is converted into a digital signal in synchronization with the low frequency component signal.

Further, in the third aspect, the filter circuit may be arranged between the timing control unit and the counter. This brings about the effect that filtering is performed between the timing control unit and the comparator.

It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. It is a figure showing an example of a layered structure of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of an analog digital conversion part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a reference signal supply part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of DAC in a 1st embodiment of this art. It is an example of an equivalent circuit of the DAC in the first embodiment of the present technology. It is a circuit diagram showing an example of 1 composition of a filter circuit in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a comparator in a 1st embodiment of this art. It is a figure for demonstrating the characteristic of the impulse DAC in 1st Embodiment of this technique. It is a graph which shows an example of a waveform of a clock signal and a detection signal in a 1st embodiment of this art. It is a figure for demonstrating the characteristic of the reference signal supply part in 1st Embodiment of this technique. It is an enlarged view of a figure showing a characteristic of a reference signal supply part in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of an analog digital conversion part in a 1st embodiment of this art and a comparative example. It is a flow chart which shows an example of operation of the solid-state image sensing device in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a filter circuit in a 2nd embodiment of this art. It is a circuit diagram showing an example of composition of a switched capacitor register circuit in a 2nd embodiment of this art. It is a graph which shows an example of a waveform of a clock signal and a current signal in a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of an analog digital conversion part in a 3rd embodiment of this art. It is a block diagram showing a schematic example of composition of a vehicle control system. It is explanatory drawing which shows an example of the installation position of an imaging part.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (an example in which a filter circuit that passes high frequency components is provided)
2. Second embodiment (an example in which a switched capacitor register circuit is used to provide a filter circuit for passing high frequency components)
3. Third embodiment (an example in which a filter circuit that passes low frequency components is provided)
4. Application example to mobile

<1. First Embodiment>
[Example of configuration of imaging device]
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The image pickup apparatus 100 is an apparatus for picking up image data, and includes an optical unit 110, a solid-state image pickup element 200, and a DSP (Digital Signal Processing) circuit 120. Furthermore, the image pickup apparatus 100 includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As the imaging device 100, for example, a digital camera such as a digital still camera, a smartphone having an imaging function, a personal computer, a vehicle-mounted camera, or the like is assumed.

The optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200. The solid-state imaging device 200 is to generate image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC. Here, the vertical synchronization signal VSYNC is a periodic signal of a predetermined frequency that indicates the timing of image pickup. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209.

The DSP circuit 120 executes predetermined image processing on the image data from the solid-state image sensor 200. The DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150.

The display unit 130 displays image data. As the display unit 130, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed. The operation unit 140 generates an operation signal according to the operation of the user.

The bus 150 is a common path for the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 to exchange data with each other.

The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.

[Configuration example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection part such as a via. In addition to vias, Cu-Cu bonding or bumps may be used for connection.

FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a row scanning circuit 210, a pixel array section 220, a timing control section 240, a constant current source circuit 250, an analog/digital conversion section 300, a horizontal transfer scanning section 260, and a signal processing section 270.

For example, the pixel array section 220 is arranged on the light receiving chip 201, and the other circuits (the row scanning circuit 210 and the like) are arranged on the circuit chip 202. The circuits arranged in each of the light receiving chip 201 and the circuit chip 202 are not limited to this configuration. For example, it is possible to arrange up to the comparator in the analog-digital conversion unit 300 on the light receiving chip 201, and arrange the subsequent stage on the circuit chip 202.

In the pixel array unit 220, a plurality of pixels 230 are arranged in a two-dimensional lattice shape. The pixel 230 generates an analog pixel signal by photoelectric conversion and supplies the analog pixel signal to the analog-digital conversion unit 300. Hereinafter, a set of pixels 230 arranged in the horizontal direction is referred to as a “row”, and a set of pixels 230 arranged in the direction perpendicular to the row is referred to as a “column”.

The row scanning circuit 210 sequentially selects and drives rows to output pixel signals.

The timing control unit 240 controls the operation timings of the row scanning circuit 210, the analog-digital conversion unit 300, and the horizontal transfer scanning unit 260 in synchronization with the vertical synchronization signal VSYNC.

In the constant current source circuit 250, a constant current source is arranged for each column. Each constant current source is connected to the vertical signal line in the corresponding column.

The analog-to-digital converter 300 converts, for each column, the pixel signal of that column into a digital signal. The analog-digital conversion unit 300 outputs a digital signal for each column to the signal processing unit 270.

The horizontal transfer scanning unit 260 controls the analog-digital conversion unit 300 to sequentially output the pixel signals in the row.

The signal processing unit 270 performs predetermined signal processing such as dark current correction and demosaic processing on the digital signal. The signal processing unit 270 supplies the image data composed of the processed signal to the DSP circuit 120 via the signal line 209.

[Example of configuration of analog-digital converter]
FIG. 4 is a block diagram illustrating a configuration example of the analog-digital conversion unit 300 according to the first embodiment of the present technology. A reference signal supply unit 340, a plurality of comparators 310, a plurality of counters 320, and a plurality of latches 330 are arranged in the analog-digital conversion unit 300.

The comparator 310, the counter 320, and the latch 330 are provided for each column. If the number of columns is N (N is an integer), N comparators 310, counters 320, and latches 330 are provided for each N.

The reference signal supply unit 340 generates the reference signal RMP in synchronization with the clock signal ADCK from the timing control unit 240 and supplies the reference signal RMP to each of the comparators 310. The clock signal ADCK is generated, for example, by using a PLL to multiply the frequency of the vertical synchronization signal VSYNC. Further, a DAC control signal for controlling the waveform and generation timing of the reference signal RMP is input to the reference signal supply unit 340. The DAC control signal is generated by the timing control unit 240, for example.

The comparator 310 compares the reference signal RMP with the pixel signal Vsig from the corresponding column. The comparator 310 supplies the comparison result COMP to the counter 320.

The counter 320 counts the count value over a period until the comparison result COMP is inverted. The counter 320 outputs a digital signal indicating the count value to the latch 330 and holds it. Further, a counter control signal for controlling the counting operation is input to the counter 320.

The latch 330 holds the digital signal of the corresponding column. The latch 330 outputs a digital signal to the signal processing unit 270 under the control of the horizontal transfer scanning unit 260.

The comparator 310 and the counter 320 described above convert an analog pixel signal into a digital signal. That is, the comparator 310 and the counter 320 function as an ADC. An ADC having a simple structure including a comparator and a counter is called a single slope ADC.

In addition to the AD conversion, the analog-digital conversion unit 300 also performs CDS (Correlated Double Sampling) processing for obtaining the difference between the reset level and the signal level for each column. Here, the reset level is the level of the pixel signal when the pixel 230 is initialized, and the signal level is the level of the pixel signal at the end of the exposure. For example, the CDS process is realized by the counter 320 performing one of down-counting and up-counting when converting the reset level and performing the other of down-counting and up-counting when converting the signal level. Note that the counter 320 may be configured to perform only up-counting, and a circuit for performing CDS processing may be added at the subsequent stage.

[Example of Configuration of Reference Signal Supply Unit]
FIG. 5 is a block diagram showing a configuration example of the reference signal supply unit 340 according to the first embodiment of the present technology. The DAC 350, the filter circuit 360, and the resistor 341 are arranged in the reference signal supply unit 340.

The DAC 350 generates a predetermined current signal as the reference signal DACOUT in synchronization with the clock signal ADCK according to the DAC control signal. For example, a sawtooth wave ramp signal is generated as the reference signal DACOUT.

The filter circuit 360 passes a specific frequency component of the jitter of the clock signal ADCK. The filter circuit 360 generates a fixed width pulse signal FWP (Fixed Width Pulse) including the frequency component.

The resistor 341 converts a signal obtained by analog-adding the fixed-width pulse signal FWP to the reference signal DACOUT (current signal) into a voltage signal. This voltage signal is supplied to the comparator 310 as the reference signal RMP.

[DAC configuration example]
FIG. 6 is a block diagram showing a configuration example of the DAC 350 according to the first embodiment of the present technology. The DAC 350 is provided with a counter 351, M (M is an integer of 2 or more) toggle circuits 352, and a capacitor 356. Each of the toggle circuits 352 includes a current source 353 and switches 354 and 355.

The counter 351 counts the count value in synchronization with the clock signal ADCK. The counter 351 decodes the count value and generates an M-bit signal. For example, the larger the count value is, the more the bit value of the logical value “1” is decoded into a signal. Of these M bits, the m-th bit (m is an integer from 0 to M−1) is input to the m-th toggle circuit 352.

For example, in the initial state, all M bits are set to the logical value "0". When the count value is a decimal number "1", the logical value "1" is set only in the 0th bit, and when the count value is a decimal number "2", the 0th bit and the 1st bit are set. The logical value "1" is set. Hereinafter, the larger the count value, the larger the number of bits of the logical value "1".

Further, the counter 351 performs either an M-bit initialization process or a counting process in accordance with the DAC control signal.

The toggle circuit 352 alternately outputs a high level current and a low level current according to the bit from the counter 351. In the toggle circuit 352, the current source 353 supplies a constant current. The switch 354 opens and closes the path between the current source 353 and the ground terminal according to the bit from the counter 351. The switch 355 opens and closes the path between the current source 353 and the output terminal of the DAC 350 according to the bit from the counter 351.

The corresponding bit also causes one of the switches 354 and 355 to transition to the open state and the other to transition to the closed state. For example, when the bit of the logical value "0" is input, the switch 354 shifts to the closed state and the switch 355 shifts to the open state. On the other hand, when the bit of the logical value "1" is input, the switch 354 shifts to the open state and the switch 355 shifts to the closed state.

The capacitor 356 is inserted between the output terminal of the DAC 350 and the ground terminal.

With the above configuration, the counter 351 counts when the reset level is converted, and the larger the count value, the larger the sum of the output currents from the M toggle circuits 352. Then, when the conversion of the reset level is completed, the counter 351 initializes the M bits. Similar processing is performed when converting the signal level. As a result, the sawtooth-shaped reference signal DACOUT is generated.

Note that the circuit in the DAC 350 is not limited to the circuit illustrated in the figure as long as it can generate the sawtooth reference signal RMP.

FIG. 7 is an example of an equivalent circuit of the DAC 350 according to the first embodiment of the present technology. The M toggle circuits 352 can be replaced with a variable current source 357 and a resistor 358 as illustrated in the figure.

The variable current source 357 generates a current whose current amount changes according to the count value of the counter 351. The resistor 358 is inserted between the variable current source 357 and the ground terminal. Further, the capacitor 356 is inserted between the connection point of the variable current source 357 and the resistor 358 and the ground terminal. Further, the reference signal DACOUT is output from the connection point of the variable current source 357 and the resistor 358.

The resistor 358 and the capacitor 356 form a low pass filter. This low-pass filter passes low-frequency components of the jitter of the clock signal ADCK that are less than a predetermined lower limit frequency.

[Example of filter circuit configuration]
FIG. 8 is a circuit diagram showing a configuration example of the filter circuit 360 according to the first embodiment of the present technology. The filter circuit 360 includes an edge detection circuit 370 and a toggle circuit 380.

The edge detection circuit 370 detects an edge (for example, a rising edge) of the clock signal ADCK and outputs it as a detection signal. The edge detection circuit 370 includes a delay circuit 371 and an AND (logical product) gate 372.

The delay circuit 371 delays the clock signal ADCK by a constant delay time. The delay circuit 371 outputs the delayed clock signal ADCK.

The AND gate 372 outputs a logical product of the clock signal ADCK before delay and the inverted value of the clock signal ADCK after delay as a detection signal to the toggle circuit 380.

With the above configuration, the rising edge of the clock signal ADCK is detected. The width of this rising edge corresponds to the delay time of the delay circuit 371.

The toggle circuit 380 alternately outputs a high level current and a low level current according to the detection signal from the edge detection circuit 370. The toggle circuit 380 includes a current source 381 and switches 382 and 383.

The current source 381 supplies a constant current. The switch 382 opens and closes the path between the current source 381 and the ground terminal according to the detection signal from the edge detection circuit 370. The switch 383 opens and closes the path between the current source 381 and the output terminal of the filter circuit 360 according to the detection signal from the edge detection circuit 370.

With the above configuration, the filter circuit 360 generates the fixed width pulse signal FWP. Further, the filter circuit 360 functions as a high-pass filter that passes a high frequency component exceeding a predetermined upper limit frequency in the jitter of the clock signal ADCK. Details of the principle of functioning as a high-pass filter will be described later.

The filter circuit 360 is not limited to the circuit illustrated in the figure as long as it functions as a high pass filter.

[Example of configuration of comparator]
FIG. 9 is a circuit diagram showing a configuration example of the comparator 310 according to the first embodiment of the present technology. The comparator 310 includes pMOS (p-channel metal oxide semiconductor) 311 and 312, nMOS (n-channel MOS) 313 and 315, a resistor 314 and a current source 316. Further, the comparator 310 further includes a resistor 317 and a capacitor 318.

The pMOS transistors 311 and 312 are connected in parallel to the power supply terminal. Further, the gate of the pMOS transistor 311 is connected to its drain and the gate of the pMOS transistor 312.

The nMOS transistor 313 is inserted between the pMOS transistor 311 and the current source 316. The reference signal RMP from the reference signal supply unit 340 is input to the gate of the nMOS transistor 313.

The nMOS transistor 315 is inserted between the pMOS transistor 312 and the current source 316. The pixel signal Vsig from the pixel 230 is input to the gate of the nMOS transistor 315. The connection point between the pMOS transistor 312 and the nMOS transistor 315 is connected to the output terminal of the comparator 310.

Both ends of the resistor 314 are connected to the source and drain of the nMOS transistor 315.

The current source 316 is inserted between the common node of the nMOS transistors 313 and 315 and the ground terminal.

The resistor 317 and the capacitor 318 are connected in parallel between the connection point of the pMOS transistor 312 and the nMOS transistor 315 and the power supply terminal.

With the configuration described above, the comparator 310 compares the reference signal RMP and the pixel signal Vsig, and outputs the comparison result COMP. Further, the resistor 317 and the capacitor 318 form a low-pass filter. This low-pass filter passes low frequency components of the jitter of the clock signal ADCK.

Here, the reason why the above-described filter circuit 360 functions as a high-pass filter will be considered. In general, jitter can be divided into a PWM (Pulse Width Modulation) component and a PDM (Pulse Delay Modulation) component. Of these, the PDM component is known to be a high frequency component obtained by passing the jitter through a high pass filter. The derivation process is described in "O. Oliaei, "State-Space Analysis of Clock Jitter in CT Oversampling Data Converters" IEEE TCASII, vol. 50, no. 1, pp. 31-37, Jan. 2003". .. Also, "M. Anderson, L. Sundstrom, "DT Modeling of Clock Phase-Noise Effects in LP CT ΔΣ ADCs with RZ Feedback" IEEE TCASII, Vol. 56, No. 7, Jul 2009, pp. 530-534. It is also described in.

In order to simply understand that the PDM component is a high frequency component, it is easy to consider an impulse DAC that is a virtual DAC that outputs an impulse.

FIG. 10 is a diagram for explaining the characteristics of the impulse DAC according to the first embodiment of the present technology. In the figure, a is a graph showing an example of the waveform of the reference signal DACOUT output from the impulse DAC. In the same figure, b is a graph showing an example of the waveform of the reference signal DACOUT due to jitter. In the figure, c is a graph showing an example of time integration of the reference signal DACOUT due to jitter. In the same figure, d is a graph showing an example of the spectrum of the time integration of the reference signal DACOUT due to jitter. In the figure, e is a graph showing an example of the time derivative of the spectrum due to the jitter.

Further, the vertical axis of a in the figure shows the level of the reference signal DACOUT, and the horizontal axis shows time. In the figure, the vertical axis of b indicates the level of the reference signal DACOUT due to jitter, and the horizontal axis indicates time. The vertical axis of c in the figure shows the value of time integration, and the horizontal axis shows time. In the figure, the vertical axis of d shows the spectrum value, and the horizontal axis shows the frequency. In the figure, the vertical axis of e shows the value of time differentiation, and the horizontal axis shows the frequency.

In such an impulse DAC, an ideal output waveform without jitter (hatched portion) and an output waveform in the presence of jitter (white portion) are considered as illustrated in a of the figure. The output waveform in the presence of jitter is an ideal output waveform translated in parallel along the time axis by the amount of jitter.

Next, consider the output component of the impulse DAC added by the jitter, as illustrated in b in FIG. This can be achieved by subtracting the ideal waveform from the output waveform when there is the jitter.

If it is left as it is, the handling is troublesome, so next, consider a waveform obtained by time-integrating the waveform of b in the same figure as illustrated in c of the same figure. This waveform is an output waveform of an RZ (Return to Zero)-DAC with a pulse width of a jitter value, in other words, a waveform obtained by directly converting the jitter as a time axis signal into a voltage or current signal. Therefore, the spectrum of this waveform is the same as the spectrum of the jitter itself.

If the jitter is white noise, the spectrum of this waveform will also be white noise, as illustrated by d in the figure.

In order to restore the previous time integration to its original value, a first-order derivative of this is the spectrum of the output component (b in the figure) of the impulse DAC due to the jitter. Considering white jitter, this is a spectrum of high-frequency components that have passed through a first-order high-pass filter, as illustrated by e in the figure. As described using a to e in the figure, the PDM component of the jitter is the high frequency component of the jitter obtained by the high pass filter.

In CT (Continuous-Time)-delta sigma ADC, there is known a method of using SCR (Switched Capacitor Resistor)-DAC which will be described later in order to suppress the PWM component due to the jitter and use only the PDM component. However, this method has a large variation in characteristics, and is not compatible with the DAC 350 having the current steering configuration in view of the purpose of use for jitter cancellation.

Then, returning to the understanding of the principle of realizing the PDM component, it seems that SCR-DAC is not the only solution and is not necessarily the most natural idea. On the contrary, using the edge detection circuit 370 using the delay circuit 371 for generating the fixed delay is the simplest method of realizing the PDM. In reality, the jitter due to the delay circuit 371 can be made sufficiently smaller than the jitter of the clock signal ADCK.

FIG. 11 is a graph showing an example of waveforms of the clock signal and the detection signal in the first embodiment of the technology. In the figure, a is a graph showing an example of the waveform of the clock signal ADCK. In the same figure, b is a graph showing an example of the waveform of the detection signal of the edge detection circuit 370.

As illustrated in b in the figure, the rising edge of the clock signal ADCK in a in the figure is detected as a detection signal. The width of this edge corresponds to the delay time of the delay circuit 371.

The same consideration as the impulse DAC described above is performed for the reference signal supply unit 340 using the edge detection circuit 370.

FIG. 12 is a diagram for explaining the characteristics of the reference signal supply unit 340 according to the first embodiment of the present technology. In the figure, a is a graph showing an example of the waveform of the reference signal RMP output from the reference signal supply unit 340. B in the figure is a graph showing an example of the waveform of the reference signal RMP due to jitter. In the figure, c is a graph showing an example of time integration of the reference signal RMP due to jitter. In the figure, d is a graph showing an example of the spectrum of the time integration of the reference signal RMP due to the jitter. In the figure, e is a graph showing an example of the time derivative of the spectrum due to the jitter.

It is captured why the time integration (c in the figure) of the output component of the reference signal supply unit 340 added by the jitter has the same spectrum as the jitter as in the case of the impulse DAC.

FIG. 13 is an enlarged view of the diagram showing the characteristic of the reference signal supply unit 340 according to the first embodiment of the present technology. A in FIG. 13 is an enlarged view of one pulse of a in FIG. 13B is an enlarged view of a waveform regarding one pulse of b in FIG. 13C is an enlarged view of a waveform regarding one pulse of c in FIG. FIG. 13D is an enlarged view of the waveform for one pulse of c in FIG.

Let dT be the pulse width of the fixed-width pulse signal FWP and t _PDM be the jitter amount, and consider the time integration of the output component of the reference signal supply unit 340 added by the jitter with respect to one pulse. As illustrated in c in FIG. 13, the time integration has a trapezoidal waveform in which both the amplitude and the pulse width depend on the jitter amount, and the area A is represented by the following formula.
A=0.5×I×t _PDM ² +I×t _PDM ×(dT−t _PDM )
+0.5×I×t _PDM ²
=I×t _PDM ×dT
In the above equation, I indicates the level of the reference signal RMP, and the unit is, for example, ampere (A). The unit of the pulse width dT and the jitter amount t _PDM is, for example, seconds (s).

From the above equation, the area A is directly proportional to the amount of jitter. That is, it can be approximated by a pulse whose amplitude is directly proportional to the amount of jitter. From this, it is understood that the spectrum of the time integration of the output component of the reference signal supply unit 340 added by the jitter has the same spectrum as the jitter, as in the case of the impulse DAC.

As described above, the reference signal supply unit 340 that uses the fixed width pulse signal FWP is also referred to as FWP RZ-DAC. This FWP RZ-DAC is considered to be very suitable for use in jitter cancellation, as compared with the SCR-DAC described later. This is because the current steering configuration in the DAC 350 illustrated in FIG. 6 can be used as it is.

Further, in the CT-delta sigma ADC, by considering why the FWP RZ-DAC method is not so effective, the difference from the application to the jitter cancellation will be considered. In a word, it is the difference between using as a literal DAC as in the case of a CT-delta sigma ADC, or as a toggle circuit with no input data, such as in a jitter cancellation application.

When used as a DAC, naturally, the first important factor is the transfer characteristic of input data rather than the transfer characteristic of jitter. In the FWP RZ-DAC, this gain is proportional to the pulse width dT, but it is difficult to set the pulse width dT accurately because it is composed of logic gates. In addition, the PVT (Process, Supply Voltage, and Temperature) characteristic becomes very large. To solve these problems, for example, a major modification such as DLL (Delay-Locked Loop) addition is required. In addition, since a long logic gate string is generally required to realize a large delay time, it tends to be a jitter source itself. If the delay time is to be kept small as a countermeasure, the output current value I of the DAC must be increased correspondingly in order to make the gains the same. When increasing the output current value I, a large through/BW (Band Width) characteristic is required for the amplifier of the loop filter of the CT-delta sigma ADC.

On the other hand, when applied to the jitter cancellation, there is no input data and the filter circuit 360 only performs a simple toggle operation. Therefore, the output signal corresponding to the above data becomes a simple offset and is removed by the CDS processing. The most important in this case is the transfer function of jitter, which, as we have seen, is independent of pulse width. Therefore, it is considered that the pulse width does not need to be set accurately, the PVT dependency does not have to be suppressed, and the pulse width need not have a large value. As described above, it can be understood that the problem when applied to the CT-delta sigma ADC is significantly alleviated.

FIG. 14 is a block diagram showing a configuration example of an analog-digital conversion unit in the first embodiment of the present technology and a comparative example. In the figure, a is a block diagram showing a configuration example of the analog-digital conversion unit 300 of the first embodiment. In the same figure, b is a block diagram showing one configuration example of the analog-digital conversion unit of the comparative example in which the filter circuit 360 is not provided. The circuit composed of the comparator 310 and the counter 320 constitutes the analog-digital converter 305.

As illustrated in a in the figure, the DAC 350 generates a predetermined reference signal DACOUT in synchronization with the clock signal ADCK. Further, the DAC 350 passes the low frequency component of the jitter of the clock signal ADCK. The DAC 350 is an example of the reference signal generation unit described in the claims.

Further, the filter circuit 360 passes the high frequency component of the jitter of the clock signal ADCK and outputs the fixed width pulse signal FWP.

The analog-digital converter 305 converts the analog pixel signal Vsig into a digital signal using the reference signal DACOUT and the fixed-width pulse signal FWP (that is, the high frequency component).

The comparator 310 in the analog-digital converter 305 compares the reference signal RMP obtained by adding the fixed-width pulse signal FWP to the reference signal DACOUT with the pixel signal Vsig, and outputs the comparison result COMP. Further, the comparator 310 passes the low frequency component of the jitter of the clock signal ADCK.

The counter 320 counts the count value in synchronization with the clock signal ADCK until the comparison result COMP is inverted, and outputs the count value as a digital signal. The counter 320 cancels the jitter of the signal from the comparator 310 (that is, the comparison result COMP) and the jitter of the clock signal ADCK not passing through the comparator 310 or the like.

Here, there are two paths from the timing control unit 240 to the counter 320, one is a path passing through the DAC 350, the filter circuit 360 and the comparator 310, and the other is a path not passing through them. As described above, since the DAC 350 and the comparator 310 have the characteristics of the low-pass filter and the filter circuit 360 has the characteristics of the high-pass filter, the transfer characteristic of the former path is close to that of the latter path. As a result, the cancellation of the jitter in the counter 320 is strengthened, and the noise of the digital signal due to the jitter is reduced.

On the other hand, as illustrated in b in the figure, when the filter circuit 360 is not provided, the path passing through the DAC 350 and the comparator 310 has the characteristic of a low-pass filter, but the path not passing through them does not have the characteristic. .. Therefore, the counter 320 does not sufficiently cancel the jitter, and for example, the high frequency component of the jitter remains without being removed. Therefore, in the comparative example, noise due to jitter occurs. In the configuration in which the ADC is arranged for each column, horizontal drawing noise or the like occurs.

By reducing the jitter of the PLL itself that is the source of the jitter, noise due to the jitter can be suppressed, but it is necessary to add a large capacity to the PLL, which increases the circuit area and power consumption of the PLL. Absent.

[Operation example of solid-state image sensor]
FIG. 15 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

The row scanning circuit 210 in the solid-state image sensor 200 selects a row to read (step S901). Further, the reference signal supply unit 340 supplies the reference signal RMP (step S902). The analog-digital converter 305 performs AD conversion for each column (step S903). The row scanning circuit 210 determines whether AD conversion of all rows is completed (step S904).

When the AD conversion of all rows has not been completed (step S904: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. On the other hand, when the AD conversion of all rows is completed (step S904: Yes), the solid-state imaging device 200 executes image processing on the image data and ends the operation for capturing the image data. When a plurality of pieces of image data are continuously imaged, the processing of steps S901 to S904 is repeatedly executed in synchronization with the vertical synchronization signal VSYNC.

As described above, according to the first embodiment of the present technology, since the DAC 350 that passes the low frequency component of the jitter of the clock signal and the filter circuit 360 that passes the high frequency component of the jitter are provided, these components are The added reference signal RMP can be supplied. As a result, both the jitter of the reference signal RMP passing through the DAC 350 and the jitter of the clock signal not passing through the DAC 350 include high frequency components and low frequency components, and the counter 320 can cancel them. it can. Therefore, noise due to jitter can be reduced.

Further, when the noise is constant, the allowable amount of jitter is increased by adding the filter circuit 360, so that the circuit area of the PLL or the like and the power consumption can be reduced.

<2. Second Embodiment>
In the above-described first embodiment, the high-pass filter is realized by adding the edge detection circuit 370. However, as the delay time is lengthened, the number of elements forming the delay circuit 371 in the edge detection circuit 370 increases. , The circuit scale increases. The solid-state image sensor 200 of the second embodiment differs from that of the first embodiment in that a switched capacitor register circuit is used instead of the edge detection circuit 370.

FIG. 16 is a circuit diagram showing a configuration example of the filter circuit 360 according to the second embodiment of the present technology. The filter circuit 360 of the second embodiment is different from that of the first embodiment in that a switched capacitor register circuit 390 is provided instead of the edge detection circuit 370. As described above, the reference signal supply unit 340 in which the switched capacitor register circuit 390 is arranged is also called an SCR-DAC.

FIG. 17 is a circuit diagram showing a configuration example of the switched capacitor register circuit 390 according to the second embodiment of the present technology. This switched capacitor register circuit 390 includes a switched capacitor circuit 391, a resistor 395, an nMOS transistor 396 and a pMOS transistor 397. The switched capacitor circuit 391 includes a pMOS transistor 392, a capacitor 393 and an nMOS transistor 394.

The pMOS transistor 392 and the nMOS transistor 394 are connected in series between the terminal of the reference voltage +V _{ref and} the terminal of the inverted value thereof, −V _ref . The clock signal ADCK is input to the gates of the pMOS transistor 392 and the nMOS transistor 394.

The capacitor 393 is inserted between the connection point of the pMOS transistor 392 and the nMOS transistor 394 and the terminal of the common voltage V _CM .

The nMOS transistor 396 and the pMOS transistor 397 are connected in parallel between the resistor 395 and the toggle circuit 380. A signal xADCK which is the inverted clock signal ADCK is input to the gate of the nMOS transistor 396, and a clock signal ADCK is input to the gate of the pMOS transistor 397.

The resistor 395 is inserted between the connection point of the nMOS transistor 394 and the pMOS transistor 392 in the switched capacitor circuit 391 and the connection point of the nMOS transistor 396 and the pMOS transistor 397.

With the above configuration, the switched capacitor circuit 391 charges and discharges the capacitor 393 in synchronization with the clock signal ADCK. The switch composed of the nMOS transistor 396 and the pMOS transistor 397 opens and closes the path between the resistor 395 and the toggle circuit 380 in synchronization with the clock signal ADCK. A current signal I _out is output from the switched capacitor register circuit 390.

As illustrated in the figure, since the switched capacitor register circuit 390 does not need the delay circuit 371, the circuit scale of the filter circuit 360 is reduced as compared with the case where the edge detection circuit 370 provided with the delay circuit 371 is used. can do.

FIG. 18 is a graph showing an example of waveforms of a clock signal and a current signal according to the second embodiment of the present technology. In the figure, a is a graph showing an example of the waveform of the clock signal ADCK. B in the same figure is a graph showing an example of the waveform of the current signal I _out .

In the figure, the vertical axis of a is the level of the clock signal ADCK, and the horizontal axis is time. The vertical axis of b in the figure is the level of the current signal I _out , and the horizontal axis is time.

The switched capacitor register circuit 390 suppresses the PWM component of the clock signal ADCK and can obtain only the PDM component (high frequency component).

As described above, in the second embodiment of the present technology, the circuit scale of the filter circuit 360 is reduced because the switched capacitor register circuit 390 having no delay circuit is provided in the filter circuit 360 instead of the edge detection circuit 370. can do.

<3. Third Embodiment>
In the above-described first embodiment, the filter circuit 360 that passes the high frequency component of the jitter is added to reduce the noise due to the jitter, but a filter circuit that passes the low frequency component of the jitter may be used. .. The solid-state image sensor 200 according to the third embodiment is different from that according to the first embodiment in that a filter circuit that passes low frequency components of jitter is added.

FIG. 19 is a block diagram showing a configuration example of the analog-digital conversion unit 300 according to the third embodiment of the present technology. The analog-digital conversion unit 300 of the third embodiment differs from that of the first embodiment in that a filter circuit 361 is provided instead of the filter circuit 360.

The filter circuit 361 passes the low frequency component of the jitter of the clock signal ADCK. For example, DLL or PLL is used as the filter circuit 361. The filter circuit 361 supplies the signal of the low frequency component to the counter 320.

Further, the counter 320 of the third embodiment counts the count value in synchronization with the signal from the filter circuit 361.

There are two paths from the timing control unit 240 to the counter 320, one path is through the DAC 350 and the comparator 310, and the other path is through the filter circuit 361. As described above, since the DAC 350 and the comparator 310 have the characteristics of the low-pass filter and the filter circuit 361 also has the characteristics of the low-pass filter, the transfer characteristic of the former path is close to that of the latter path. As a result, the cancellation of the jitter in the counter 320 is strengthened, and the noise of the digital signal due to the jitter is reduced.

As described above, according to the third embodiment of the present technology, each of the DAC 350 and the filter circuit 361 outputs the low-frequency component of jitter to the counter 320, and thus the counter 320 can cancel those components. it can.

<4. Application to mobiles>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.

FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a voice image output unit 12052, and an in-vehicle network I/F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, and a steering angle of the vehicle. It functions as a steering mechanism for adjustment and a control device such as a braking device that generates a braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a winker, or a fog lamp. In this case, the body system control unit 12020 may receive radio waves or signals of various switches transmitted from a portable device that substitutes for a key. The body system control unit 12020 receives input of these radio waves or signals and controls the vehicle door lock device, power window device, lamp, and the like.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the imaging unit 12031 is connected to the vehicle outside information detection unit 12030. The vehicle exterior information detection unit 12030 causes the image capturing unit 12031 to capture an image of the vehicle exterior and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light. The imaging unit 12031 can output the electric signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects in-vehicle information. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.

The microcomputer 12051 calculates a control target value of the driving force generation device, the steering mechanism, or the braking device based on the information inside or outside the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes functions of ADAS (Advanced Driver Assistance System) including avoidance or impact mitigation of a vehicle, follow-up traveling based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, vehicle lane departure warning, and the like. It is possible to perform cooperative control for the purpose.

Further, the microcomputer 12051 controls the driving force generation device, the steering mechanism, the braking device, or the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's It is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information on the outside of the vehicle acquired by the outside information detecting unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio image output unit 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or audibly notifying information to a passenger of the vehicle or the outside of the vehicle. In the example of FIG. 20, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior. The image capturing unit 12101 provided on the front nose and the image capturing unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 included in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that FIG. 21 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, and the imaging range 12114 indicates The imaging range of the imaging part 12104 provided in a rear bumper or a back door is shown. For example, by overlaying image data captured by the image capturing units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera including a plurality of image capturing elements, or may be an image capturing element having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). In particular, the closest three-dimensional object on the traveling path of the vehicle 12100, which travels in the substantially same direction as the vehicle 12100 at a predetermined speed (for example, 0 km/h or more), can be extracted as a preceding vehicle by determining it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation of the driver.

For example, the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to convert three-dimensional object data regarding a three-dimensional object into another three-dimensional object such as a two-wheeled vehicle, an ordinary vehicle, a large vehicle, a pedestrian, and a utility pole. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or more than the set value and there is a possibility of collision, the microcomputer 12051 outputs the audio through the audio speaker 12061 and the display unit 12062. A driver can be assisted for collision avoidance by outputting an alarm to the driver and by performing forced deceleration or avoidance steering through the drive system control unit 12010.

At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the imaging units 12101 to 12104. To recognize such a pedestrian, for example, a procedure of extracting a feature point in an image captured by the image capturing units 12101 to 12104 as an infrared camera and a pattern matching process on a series of feature points indicating the contour of an object are performed to determine whether the pedestrian is a pedestrian. Is performed by the procedure for determining. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 causes the recognized pedestrian to have a rectangular contour line for emphasis. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon indicating a pedestrian or the like at a desired position.

The example of the vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, noise due to jitter can be reduced and a more easily captured image can be obtained, so that fatigue of the driver can be reduced.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a correspondence relationship. Similarly, the matters specifying the invention in the claims and the matters having the same names in the embodiments of the present technology have a correspondence relationship. However, the present technology is not limited to the embodiment, and can be embodied by making various modifications to the embodiment without departing from the scope of the invention.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, or as a program for causing a computer to execute the series of procedures or a recording medium storing the program. You can catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be present.

In addition, the present technology may have the following configurations.
(1) A reference signal generator that generates a predetermined reference signal in synchronization with a predetermined clock signal,
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An analog-to-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal.
(2) The specific frequency component is a high frequency component exceeding a predetermined upper limit frequency in the clock signal,
The reference signal generation unit passes a low frequency component of the jitter that is less than a predetermined lower limit frequency,
The analog-digital converter,
A comparator that outputs the comparison result by comparing the analog signal with the reference signal to which the high frequency component is added;
The solid-state imaging device according to claim 2, further comprising a counter that counts a count value in synchronization with the clock signal and outputs the count value as the digital signal over a period until the comparison result is inverted.
(3) The filter circuit is
An edge detection circuit that detects an edge of the clock signal and outputs it as a detection signal,
The toggle circuit that alternately outputs a high level and a low level in synchronization with the detection signal, and the solid-state imaging device according to (2).
(4) The filter circuit is
A switched capacitor circuit that charges and discharges a capacitor in synchronization with the clock signal,
A resistor connected in series with the capacitor,
A toggle circuit that alternately outputs a high level and a low level in synchronization with a signal input via the resistor,
The solid-state imaging device according to (2), further including a switch that opens and closes a path between the resistor and the toggle circuit in synchronization with the clock signal.
(5) The specific frequency component is a low frequency component of the clock signal that is less than a predetermined lower limit frequency,
The reference signal generation unit passes at least a part of the specific frequency component,
The analog-digital converter,
A comparator for comparing the reference signal and the analog signal and outputting a comparison result;
The solid according to (1), further comprising: a counter that counts a count value in synchronization with the signal of the specific frequency component and outputs the count value as the digital signal over a period until the comparison result is inverted. Image sensor.
(6) A reference signal generation procedure for generating a predetermined reference signal in synchronization with a predetermined clock signal,
A filtering procedure for passing a specific frequency component of the jitter of the clock signal,
An analog-digital conversion procedure for converting an analog signal into a digital signal using the specific frequency component and the reference signal.
(7) A reference signal generator that generates a predetermined reference signal in synchronization with a predetermined clock signal,
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An image pickup apparatus comprising: an analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal; and a signal processing unit that performs predetermined signal processing on the digital signal.
(8) A timing control unit that outputs a predetermined clock signal,
A reference signal generator that generates a predetermined reference signal in synchronization with the clock signal;
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal,
A solid-state image sensor comprising:
(9) The specific frequency component is a high frequency component exceeding a predetermined upper limit frequency in the clock signal,
The reference signal generation unit passes a low frequency component of the jitter that is less than a predetermined lower limit frequency,
The analog-digital converter,
A comparator that outputs the comparison result by comparing the analog signal with the reference signal to which the high frequency component is added;
The solid-state imaging device according to (8), further comprising: a counter that counts a count value in synchronization with the clock signal and outputs the count value as the digital signal over a period until the comparison result is inverted.
(10) The solid-state imaging device according to (9), wherein the filter circuit is arranged between the timing control unit and the comparator.
(11) The specific frequency component is a low frequency component of the clock signal that is less than a predetermined lower limit frequency,
The reference signal generation unit passes at least a part of the specific frequency component,
The analog-digital converter,
A comparator for comparing the reference signal and the analog signal and outputting a comparison result;
The solid according to (8), further comprising: a counter that counts a count value in synchronization with the signal of the specific frequency component and outputs the count value as the digital signal over a period until the comparison result is inverted. Image sensor.
(12) The solid-state imaging device according to (11), wherein the filter circuit is arranged between the timing control unit and the counter.

100 image pickup device 110 optical unit 120 DSP circuit 130 display unit 140 operation unit 150 bus 160 frame memory 170 storage unit 180 power supply unit 200 solid-state imaging device 201 light receiving chip 202 circuit chip 210 row scanning circuit 220 pixel array unit 230 pixels 240 timing control unit 250 constant current source circuit 260 horizontal transfer scanning unit 270 signal processing unit 300 analog-digital conversion unit 305 analog-digital converter 310 comparator 311, 312, 392, 397 pMOS transistor 313, 315, 394, 396 nMOS transistor 314, 317, 341 358, 395 Resistor 316, 353, 381 Current source 318, 356, 393 Capacitor 320, 351 Counter 330 Latch 340 Reference signal supply unit 350 DAC
352, 380 Toggle circuit 354, 355, 382, 383 Switch 357 Variable current source 360, 361 Filter circuit 370 Edge detection circuit 371 Delay circuit 372 AND (logical product) gate 390 Switched capacitor register circuit 391 Switched capacitor circuit 12031 Imaging unit

Claims (12)

A reference signal generator that generates a predetermined reference signal in synchronization with a predetermined clock signal;
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An analog-to-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal. The specific frequency component is a high frequency component exceeding a predetermined upper limit frequency of the clock signal,
The reference signal generation unit passes a low frequency component of the jitter that is less than a predetermined lower limit frequency,
The analog-digital converter,
A comparator that outputs the comparison result by comparing the analog signal with the reference signal to which the high frequency component is added;
The solid-state imaging device according to claim 1, further comprising a counter that counts a count value in synchronization with the clock signal and outputs the count value as the digital signal over a period until the comparison result is inverted. The filter circuit is
An edge detection circuit that detects an edge of the clock signal and outputs it as a detection signal,
The solid-state imaging device according to claim 2, further comprising a toggle circuit that alternately outputs a high level and a low level in synchronization with the detection signal. The filter circuit is
A switched capacitor circuit that charges and discharges a capacitor in synchronization with the clock signal,
A resistor connected in series with the capacitor,
A toggle circuit that alternately outputs a high level and a low level in synchronization with a signal input via the resistor,
The solid-state imaging device according to claim 2, further comprising a switch that opens and closes a path between the resistor and the toggle circuit in synchronization with the clock signal. The specific frequency component is a low frequency component that is less than a predetermined lower limit frequency of the clock signal,
The reference signal generation unit passes at least a part of the specific frequency component,
The analog-digital converter,
A comparator for comparing the reference signal and the analog signal and outputting a comparison result;
The solid-state imaging device according to claim 1, further comprising a counter that counts a count value in synchronization with the signal of the specific frequency component and outputs the count value as the digital signal over a period until the comparison result is inverted. element. A reference signal generation procedure for generating a predetermined reference signal in synchronization with a predetermined clock signal,
A filtering procedure for passing a specific frequency component of the jitter of the clock signal,
An analog-digital conversion procedure for converting an analog signal into a digital signal using the specific frequency component and the reference signal. A reference signal generator that generates a predetermined reference signal in synchronization with a predetermined clock signal;
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An image pickup apparatus comprising: an analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal; and a signal processing unit that performs predetermined signal processing on the digital signal. A timing control unit for outputting a predetermined clock signal,
A reference signal generator that generates a predetermined reference signal in synchronization with the clock signal;
A filter circuit that passes a specific frequency component of the jitter of the clock signal,
An analog-digital converter that converts an analog signal into a digital signal using the specific frequency component and the reference signal,
A solid-state image sensor comprising: The specific frequency component is a high frequency component exceeding a predetermined upper limit frequency of the clock signal,
The reference signal generation unit passes a low frequency component of the jitter that is less than a predetermined lower limit frequency,
The analog-digital converter,
A comparator that outputs the comparison result by comparing the analog signal with the reference signal to which the high frequency component is added;
9. The solid-state imaging device according to claim 8, further comprising a counter that counts a count value in synchronization with the clock signal and outputs the count value as the digital signal for a period until the comparison result is inverted. The solid-state imaging device according to claim 9, wherein the filter circuit is arranged between the timing control unit and the comparator. The specific frequency component is a low frequency component that is less than a predetermined lower limit frequency of the clock signal,
The reference signal generation unit passes at least a part of the specific frequency component,
The analog-digital converter,
A comparator for comparing the reference signal and the analog signal and outputting a comparison result;
The solid-state imaging device according to claim 8, further comprising: a counter that counts a count value in synchronization with the signal of the specific frequency component and outputs the count value as the digital signal over a period until the comparison result is inverted. element. The solid-state imaging device according to claim 11, wherein the filter circuit is arranged between the timing control unit and the counter.

Images