WO2020090311A1

WO2020090311A1 - Solid-state imaging element

Info

Publication number: WO2020090311A1
Application number: PCT/JP2019/038136
Authority: WO
Inventors: 弘博朱
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2018-10-30
Filing date: 2019-09-27
Publication date: 2020-05-07

Abstract

In this solid-state imaging element which compares a variation in the amount of light and a threshold value, time required to adjust the threshold value is shortened. The solid-state imaging element is provided with a voltage comparison unit and a counting unit. In the solid-state imaging element, the voltage comparison unit compares an analog signal corresponding to a variation in incident light and a predetermined voltage indicating the boundary of a predetermined voltage range and outputs the comparison result as a voltage comparison result. Furthermore, in the solid-state imaging element, the counting unit counts a counter value each time a voltage comparison result indicating that the analog signal is out of the voltage range is outputted.

Description

Solid-state image sensor

The present technology relates to a solid-state image sensor. More specifically, the present invention relates to a solid-state image sensor that detects that the amount of change in light amount exceeds a threshold value.

Conventionally, a synchronous solid-state image sensor that captures image data (frame) in synchronization with a synchronization signal such as a vertical synchronization signal has been used in an imaging device or the like. In this general synchronous type solid-state image sensor, image data can be acquired only at every cycle (for example, 1/60 seconds) of a synchronous signal, so that higher-speed processing can be performed in fields such as traffic and robots. It will be difficult to respond when requested. Therefore, an asynchronous solid-state imaging device has been proposed, which is provided with a detection circuit that detects in real time as an address event that the amount of change in the light amount of the pixel exceeds a threshold value for each pixel address (for example, Patent Document 1). reference.). As described above, the solid-state image sensor that detects an address event for each pixel is called a DVS (Dynamic Vision Sensor). The detection circuit in the DVS detects the presence / absence of an address event by comparing a voltage signal corresponding to the amount of change in incident light with a threshold voltage indicating a threshold value.

Japanese Patent Publication No. 2016-533140

The asynchronous solid-state image sensor (that is, DVS) described above generates and outputs data much faster than the synchronous solid-state image sensor. Therefore, for example, in the traffic field, the process of recognizing an image of a person or an obstacle is executed at high speed. However, when adjusting the threshold for the purpose of improving the detection accuracy, there is a problem that it takes a certain amount of time to complete the adjustment. This is because when the threshold voltage indicating the threshold is changed, it takes time for the changed voltage to stabilize.

The present technology was created in view of such a situation, and it is an object of the present invention to reduce the time required for adjusting the threshold in a solid-state image sensor that compares the amount of change in light quantity with the threshold.

The present technology has been made to solve the above-mentioned problems, and the first aspect thereof is to compare an analog signal according to the amount of change of incident light with a predetermined voltage indicating a boundary of a predetermined voltage range. And a voltage comparison unit that outputs the comparison result as a voltage comparison result, and a counting unit that counts a count value each time the voltage comparison result indicating that the analog signal is out of the voltage range is output. A solid-state image sensor and its control method. This brings about the effect that the count value corresponding to the amount of change of the incident light is counted.

Further, in the first aspect, a control circuit that supplies a predetermined control signal is further included, and the counting unit selects and outputs any one of a plurality of bits indicating the count value according to the control signal. Good. This brings about the effect that the bit corresponding to the threshold value is output as the detection signal.

Further, in the first aspect, the predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range, and the counting unit is configured such that the analog signal is higher than the upper limit voltage. An upper limit counter that counts the count value each time the voltage comparison result indicating high is output, and a count value each time the voltage comparison result indicating that the analog signal is lower than the lower limit voltage is output. And a lower limit counter for performing the operation. This brings about the effect that the count value according to the increase amount of the incident light and the count value according to the decrease amount are counted.

Further, in the first aspect, the predetermined voltage is a variable voltage that fluctuates to one of an upper limit voltage and a lower limit voltage that are different from each other, and the counting unit compares the voltage according to a polarity signal indicating a value of the variable voltage. And a lower limit switch for opening and closing a path between the voltage comparison unit and the lower limit counter according to the polarity signal. This brings about the effect that the variable voltage and the analog signal are compared.

Further, in the first aspect, a reference signal comparison unit that compares a pixel signal according to the light amount of the incident light with a predetermined reference signal and outputs a comparison result as a reference signal comparison result is further provided. The unit may include a selection unit that selects one of the voltage comparison result and the reference signal comparison result, and a counter that counts the count value based on the selected comparison result. This brings about the effect that image data is captured.

In the first aspect, the predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range, and the voltage comparison result is a comparison result with the upper limit voltage. Including the upper limit side comparison result and the lower limit voltage comparison result indicating the lower limit voltage, the counter includes a front stage counter and a rear stage counter, the selection unit, the upper limit side comparison result and the lower limit side. A pre-stage selector that selects one of the comparison results and the reference signal comparison result and supplies it to the pre-stage counter, and the other of the upper limit side comparison result and the lower limit side comparison result and the output bit of the front stage counter. It may be provided with a rear stage selector that selects one of them and supplies it to the rear stage counter. This brings about the effect that the count value having a size obtained by adding the respective numbers of bits of the front-stage counter and the rear-stage counter is counted.

Also, in the first aspect, the counter may further include a backup counter. This brings about the effect that the count value of the size obtained by adding the respective numbers of bits of the front-stage counter, the rear-stage counter, and the spare counter is enlarged.

Further, in the first aspect, the spare counter further includes a switch that counts a count value based on an output bit of the rear stage counter and opens / closes a path between the rear stage selector and the spare counter. Good. This brings about the effect that the count value of the size obtained by adding the respective numbers of bits of the front-stage counter, the rear-stage counter, and the spare counter is enlarged.

Further, in the first aspect, the spare counter may be inserted between the pre-stage selector and the reference signal comparison unit. This brings about the effect that the count value of the size obtained by adding the respective numbers of bits of the front-stage counter, the rear-stage counter, and the spare counter is enlarged.

Further, in the first aspect, the control circuit that supplies a predetermined threshold value and the counting unit output the count value each time the voltage comparison result indicating that the analog signal is out of the voltage range is output. May be provided, and a threshold value comparing unit that compares the count value with the threshold value. This brings about the effect that an address event is detected by comparing the count value with the threshold value.

Further, in the first aspect, the predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range, and the counter has the analog signal higher than the upper limit voltage. When the voltage comparison result indicating that is output is output, one of increment processing and decrement processing is performed on the count value, and the voltage comparison result indicating that the analog signal is lower than the lower limit voltage is output. In this case, the other one of the increment processing and the decrement processing may be performed on the count value. This brings about the effect that the increment value and the decrement value cancel each other out.

Further, in the first aspect, the predetermined voltage is a variable voltage that fluctuates to one of an upper limit voltage and a lower limit voltage different from each other, and the counter is configured to compare the polarity signal indicating the value of the variable voltage with the voltage comparison result. One of the increment processing and the decrement processing may be performed based on This brings about the effect that the variable voltage and the analog signal are compared.

In the first aspect, the voltage comparison unit is arranged in each of the plurality of pixels, the counting unit is arranged in a pixel block in which the plurality of pixels are arranged, and the counting unit is arranged in the plurality of pixels. A comparison result processing unit that processes the voltage comparison result corresponding to each pixel and a counter that counts the count value based on the processing result of the comparison result processing unit may be provided. This brings about an effect that the counting unit is shared by a plurality of pixels.

Further, in the first aspect, the predetermined voltage is a variable voltage that changes to either an upper limit voltage or a lower limit voltage different from each other, and the comparison result processing unit outputs the voltage comparison result corresponding to the upper limit voltage. An upper limit side comparison result processing unit for processing, and a lower limit side comparison result processing unit for processing the voltage comparison result corresponding to the lower limit voltage, the counting unit, the voltage according to a polarity signal indicating the value of the variable voltage. An upper limit switch that opens and closes a path between a comparison unit and the upper limit comparison result processing unit, and a lower limit switch that opens and closes a path between the voltage comparison unit and the lower limit comparison result processing unit according to the polarity signal. And may be further provided. This brings about the effect that the variable voltage and the analog signal are compared.

In the first aspect, the comparison result processing unit may output the exclusive OR of the voltage comparison results corresponding to each of the plurality of pixels as the processing result. This brings about the effect that the count value is counted based on the exclusive OR.

Further, in the first aspect, the comparison result processing unit may output a logical sum of the voltage comparison results corresponding to each of the plurality of pixels as the processing result. This brings about the effect that the count value is counted based on the logical sum.

Further, in the first aspect, the comparison result processing unit may select any one of the voltage comparison results corresponding to each of the plurality of pixels and output it as the processing result. This brings about the effect that the count value is counted based on the selected comparison result.

Further, in the first aspect, the voltage comparison unit includes a current-voltage conversion unit that converts a photocurrent into a voltage signal, a differentiation circuit that differentiates the voltage signal and outputs the analog signal, and the analog signal. A comparator that compares the predetermined voltage may be provided. This brings about the effect that the comparison result of the differential signal of the voltage signal and the predetermined voltage is output.

The first aspect may further include an initialization control unit that controls the differentiating circuit to set the analog signal to a predetermined initial value each time the count value is counted. This brings about the effect that the analog signal is initialized every time counting is performed.

Further, in the first aspect, a transfer unit may be further provided that transfers a signal indicating a result of comparison between the count value and a predetermined threshold value, transfers the signal, and then initializes the count value. .. This brings about the effect that the count value is initialized at the time of transfer.

It is a block diagram showing an example of 1 composition of an imaging device in a 1st embodiment of this art. It is a figure showing an example of a layered structure of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a pixel in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of a voltage comparison part in a 1st embodiment of this art. It is a graph which shows an example of the input-output characteristic of the comparator in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of an upper limit side counter and a lower limit side counter in a 1st embodiment of this art. It is a graph which shows an example of the relation between the amount of change of the amount of light and a count value in a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of an initialization control part in a 1st embodiment of this art. It is a figure showing an example of connection of an initialization control part in a 1st embodiment of this art. It is a figure showing another example of connection of the initialization control part in a 1st embodiment of this art. It is a flow chart which shows an example of operation of the solid-state image sensing device in a 1st embodiment of this art. It is a figure which shows the control example of the voltage comparison part and control circuit in the 1st modification of 1st Embodiment of this technique. It is a block diagram showing an example of 1 composition of a counter in a 1st modification of a 1st embodiment of this art. It is a top view showing an example of 1 composition of a pixel array part in a 2nd modification of a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a pixel block in the 2nd modification of a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 2nd modification of a 1st embodiment of this art. It is a circuit diagram showing an example of 1 composition of an upper limit side comparison result processing part in the 2nd modification of a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 3rd modification of a 1st embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a modification of a 2nd embodiment of this art. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 3rd embodiment of this art. It is a block diagram showing an example of 1 composition of a pixel in a 3rd embodiment of this art. It is a circuit diagram showing an example of 1 composition of a voltage comparison part in a 3rd embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 3rd embodiment of this art. It is a circuit diagram showing an example of 1 composition of a reference signal comparison part in a 3rd embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 1st modification of a 3rd embodiment of this art. It is a block diagram showing an example of 1 composition of a counter in a 2nd modification of a 3rd embodiment of this art. It is a block diagram showing an example of 1 composition of a counter which arranged a backup counter in the former paragraph in the 2nd modification of a 3rd embodiment of this art. It is a block diagram showing an example of composition of an imaging device concerning a 4th embodiment of this art. It is a block diagram showing a schematic example of composition of a vehicle control system. It is explanatory drawing which shows an example of the installation position of an imaging part.

Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.
1. First embodiment (example of counting based on a comparison result)
2. Second embodiment (example of incrementing or decrementing a count value based on a comparison result)
3. Third Embodiment (Example of Counting Based on Comparison Result with Reference Signal or Comparison Result with Voltage)
4. Fourth embodiment (scan method)
5. Application example to mobile

<1. First Embodiment>
[Example of configuration of imaging device]
FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology. The image pickup apparatus 100 includes an image pickup lens 110, a solid-state image pickup device 200, a recording unit 120, and a control unit 130. As the imaging device 100, a camera mounted on an industrial robot, a vehicle-mounted camera, or the like is assumed.

The image pickup lens 110 collects incident light and guides it to the solid-state image pickup device 200. The solid-state image sensor 200 photoelectrically converts incident light to detect the presence or absence of an address event, and generates the detection result. Here, the address event includes an on event and an off event, and the detection result includes a 1-bit on-event detection result and a 1-bit off-event detection result. The on-event means that the amount of change in the amount of incident light exceeds a predetermined upper limit threshold. On the other hand, the off-event means that the amount of change in the light amount is below a predetermined lower limit threshold. The solid-state imaging device 200 processes the detection result of the address event, and outputs the data indicating the processing result to the recording unit 120 via the signal line 209. The solid-state image sensor 200 may detect only one of the on event and the off event.

The recording unit 120 records the data from the solid-state image sensor 200. The control unit 130 controls the solid-state imaging device 200 to detect the presence or absence of an address event.

[Configuration example of solid-state image sensor]
FIG. 2 is a diagram showing an example of a laminated structure of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a circuit chip 202 and a light receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via a connection part such as a via. In addition to vias, Cu-Cu bonding or bumps may be used for connection.

FIG. 3 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology. The solid-state imaging device 200 includes a control circuit 211, a signal processing unit 212, an arbiter 213, and a pixel array unit 214. In the pixel array unit 214, a plurality of pixels 300 are arranged in a two-dimensional lattice shape.

The control circuit 211 controls an upper limit threshold and a lower limit threshold for detecting an address event.

The pixel 300 detects the presence or absence of an address event. When the pixel 300 detects an address event, the pixel 300 supplies the arbiter 213 with a request for transfer of a detection signal indicating a detection result. Then, upon receiving the response to the request, the pixel 300 supplies the detection signal to the signal processing unit 212.

The arbiter 213 arbitrates a request from each pixel block and sends a response to the pixel 300 based on the arbitration result.

The signal processing section 212 executes predetermined signal processing such as image recognition processing on the detection signal from the pixel array section 214. The signal processing unit 212 supplies data indicating the processing result to the recording unit 120 via the signal line 209.

[Example of pixel configuration]
FIG. 4 is a block diagram showing a configuration example of the pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a voltage comparison unit 400, a counting unit 310, a transfer unit 380, and an initialization control unit 390.

The voltage comparison unit 400 compares an analog differential signal according to the amount of change of incident light with a predetermined voltage (upper limit voltage or lower limit voltage) indicating a boundary of a predetermined voltage range, and the comparison result COMP is counted by the counting unit 310. Is output to. The differential signal is an example of the analog signal described in the claims.

The counting unit 310 counts the count value every time the comparison result COMP indicating that the differential signal is out of the voltage range is output. The counting unit 310 generates a detection signal DET indicating the detection result of the address event from the count value and supplies it to the transfer unit 380.

The transfer unit 380 transfers the detection signal DET, supplies the reset signal RST to the counting unit 310 after the transfer, and controls the count value to the initial value. The transfer unit 380 supplies a request for transfer of the detection signal DET to the arbiter 213 when an address event is detected. Then, when receiving the response to the request, the transfer unit 380 supplies the detection signal to the signal processing unit 212 and the reset signal RST to the counting unit 310.

The initialization control unit 390 supplies the auto-zero signal XAZ to the voltage comparison unit 400 every time the count value is counted by the comparison result COMP to control the differential signal to the initial value.

[Configuration Example of Voltage Comparator]
FIG. 5 is a circuit diagram showing a configuration example of the voltage comparison unit 400 according to the first embodiment of the present technology. The voltage comparison section 400 includes a logarithmic response section 410, a buffer 420, a differentiating circuit 430, and a comparator 440.

The logarithmic response unit 410 generates a photocurrent by photoelectric conversion and logarithmically converts the photocurrent into a voltage. The logarithmic response unit 410 includes a photoelectric conversion element 411 and a current / voltage conversion unit 416.

The photoelectric conversion element 411 generates photoelectric current by photoelectric conversion of incident light. The current-voltage converter 416 logarithmically converts the photocurrent into the pixel voltage Vp. The current-voltage converter 416 includes N-

type transistors

412 and 415, a capacitor 413, and a P-type transistor 414. As the N-type transistor 412, the P-type transistor 414, and the N-type transistor 415, for example, a MOS (Metal-Oxide-Semiconductor) transistor is used.

The source of the N-type transistor 412 is connected to the cathode of the photoelectric conversion element 411, and the drain is connected to the power supply terminal. The P-type transistor 414 and the N-type transistor 415 are connected in series between the power supply terminal and the reference terminal of a predetermined reference potential (ground potential or the like). The connection point between the P-type transistor 414 and the N-type transistor 415 is connected to the gate of the N-type transistor 412 and the input terminal of the buffer 420. The connection point between the N-type transistor 412 and the photoelectric conversion element 411 is connected to the gate of the N-type transistor 415.

Further, a predetermined bias voltage V _blog is applied to the gate of the P-type transistor 414. The capacitor 413 is inserted between the gate of the N-type transistor 412 and the gate of the N-type transistor 415.

Further, for example, the photoelectric conversion element 411 is arranged on the light receiving chip 201, and the circuit at the subsequent stage is arranged on the circuit chip 202. It should be noted that the circuits and elements arranged in each of the light receiving chip 201 and the circuit chip 202 are not limited to this configuration. For example, the photoelectric conversion element 411, the N-

type transistors

412 and 415, and the capacitor 413 can be arranged in the light receiving chip 201, and the circuit at the subsequent stage can be arranged in the circuit chip 202.

The buffer 420 outputs the input pixel voltage to the differentiating circuit 430. With this buffer 420, the driving force for driving the subsequent stage can be improved. Further, the buffer 420 can ensure the isolation of noise associated with the switching operation in the subsequent stage.

The buffer 420 also includes P-

type transistors

421 and 422. For example, MOS transistors are used as these transistors.

In the buffer 420, P-

type transistors

421 and 422 are connected in series between the power supply terminal and the reference potential terminal. The gate of the P-type transistor 422 is connected to the logarithmic response unit 410, and the connection point of the P-

type transistors

421 and 422 is connected to the differentiating circuit 430. A predetermined bias voltage V _bsf is applied to the gate of the P-type transistor 421.

The differentiating circuit 430 obtains the amount of change in the pixel voltage Vp by differentiating operation. The change amount of the pixel voltage Vp indicates the change amount of the light amount. The differentiating circuit 430 supplies the differential signal Vout indicating the amount of change in the light amount to the comparator 440.

Also, the differentiating circuit 430 includes

capacitors

431 and 434, P-

type transistors

432 and 433, and an N-type transistor 435. For example, a MOS transistor is used as the transistor in the differentiating circuit 430.

The P-type transistor 433 and the N-type transistor 435 are connected in series between the power supply terminal and the reference potential terminal. A predetermined bias voltage V _bdiff is input to the gate of the N-type transistor 435. These transistors function as an inverting circuit in which the gate of the P-type transistor 433 serves as the input terminal 491 and the connection point of the P-type transistor 433 and the N-type transistor 435 serves as the output terminal 492.

The capacitor 431 is inserted between the buffer 420 and the input terminal 491. The capacitor 431 supplies to the input terminal 491 a current according to the time differentiation (in other words, the amount of change) of the pixel voltage Vp from the buffer 420. Further, the capacitor 434 is inserted between the input terminal 491 and the output terminal 492.

The P-type transistor 432 opens and closes the path between the input terminal 491 and the output terminal 492 according to the auto-zero signal XAZ from the initialization control unit 390. The initialization control unit 390 sets the auto-zero signal XAZ to a low level from a high level and instructs initialization, for example, every time the count value is counted. Then, the P-type transistor 432 shifts to the ON state according to the auto-zero signal XAZ, and sets the differential signal Vout to the initial value.

The comparator 440 compares the differential signal Vout with a predetermined voltage (upper limit voltage or lower limit voltage) indicating the boundary of a certain voltage range. The comparator 440 includes P-

type transistors

441 and 443 and N-

type transistors

442 and 444. For example, MOS transistors are used as these transistors.

In the comparator 440, the P-type transistor 441 and the N-type transistor 442 are connected in series between the power supply terminal and the reference terminal, and the P-type transistor 443 and the N-type transistor 444 are also connected in series between the power supply terminal and the reference terminal. Connected. The gates of the P-

type transistors

441 and 443 are connected to the differentiating circuit 430. The upper limit voltage V _high is applied to the gate of the N-type transistor 442, and the lower limit voltage V _low is applied to the gate of the N-type transistor 444.

The connection point of the P-type transistor 441 and the N-type transistor 442 is connected to the counting unit 310, and the voltage at this connection point is output as the comparison result COMP + with the upper limit voltage. The connection point of the P-type transistor 443 and the N-type transistor 444 is also connected to the counting unit 310, and the voltage at this connection point is output as the comparison result COMP- with the lower limit voltage. With such a connection, the comparator 440 outputs the high level comparison result COMP + when the differential signal Vout is higher than the upper limit voltage V _high , and the low level comparison result COMP when the differential signal Vout is lower than the lower limit voltage V _low. -Is output. The comparison result COMP is a signal including these comparison results COMP + and COMP−.

Although the comparator 440 compares both the upper limit voltage and the lower limit voltage with the differential signal Vout, only one of them may be compared with the differential signal Vout. In this case, unnecessary transistors can be eliminated. For example, when comparing only with the upper limit voltage, only the P-type transistor 441 and the N-type transistor 442 are arranged.

FIG. 6 is a graph showing an example of the input / output characteristics of the comparator 440 according to the first embodiment of the present technology. In the figure, the vertical axis represents the level of the output signal (comparison result COMP + or COMP-) of the comparator 440, and the horizontal axis represents the level of the input signal (differential signal) of the comparator 440. The solid line shows the locus of the comparison result COMP +, and the alternate long and short dash line shows the locus of the comparison result COMP-.

If the positive light amount difference (variation amount) relative to the reference when the differential signal is at the “0” level exceeds the value corresponding to the upper limit voltage V _high , the comparison result COMP + changes from the low level to the high level. To do. The amount of change corresponding to this upper limit voltage V _high will be referred to as “unit change amount (+)” below. On the other hand, when the negative light amount difference from the reference falls below the value corresponding to the lower limit voltage V _low , the comparison result COMP− changes from the high level to the low level. Hereinafter, the amount of change corresponding to the lower limit voltage V _low will be referred to as “unit change amount (−)”.

[Configuration Example of Counting Unit]
FIG. 7 is a block diagram showing a configuration example of the counting unit 310 according to the first embodiment of the present technology. The counting unit 310 includes an upper limit counter 320 and a lower limit counter 330. For example, a binary counter is used as the upper limit counter 320 and the lower limit counter 330. The control signal SW from the control circuit 211 includes an upper limit N (N is an integer) bit control signal SW + and a lower limit N (N is an integer) bit control signal SW−. Of these, the control signal SW + is input to the upper limit counter 320, and the control signal SW− is input to the lower limit counter 330.

Incidentally, as the upper limit counter 320 and the lower limit counter 330, counters other than the binary counter (Johnson counter, Gray code counter, etc.) can be used. Further, the upper limit counter 320 and the lower limit counter 330 can be realized by an LFSR (Linear Feedback Shift Register), a latch, an adder, and the like.

The upper limit counter 320 counts (for example, increments by 1) each time the comparison result COMP + of the value (for example, high level) when the differential signal Vout is higher than the upper limit voltage V _high is output. .. In addition, the upper limit counter 320 selects the bit of the n-th (n is an integer of 0 to N−1) digit among the N bits indicating the count value according to the control signal SW +, and outputs it to the transfer unit 380 as the detection signal DET +. Output.

Here, as described above, every time the amount of change in the light amount exceeds the unit change amount (+), the high-level comparison result COMP + is output and the count value is counted. In the case of a binary counter, the n-th digit of the N bits indicating the count value becomes high level when the count value becomes 2 ⁿ . Therefore, the bit of the n-th digit indicates whether or not the change amount of the light amount exceeds the unit change amount (+) × 2 ⁿ . When this unit change amount (+) × 2 ⁿ is set as the upper limit threshold, the bit of the nth digit (detection signal DET +) indicates whether or not the change amount of the light amount exceeds the upper limit threshold (in other words, whether or not there is an on event). ) Is shown.

The lower limit counter 330 counts (for example, increments by 1) each time a comparison result COMP-of a value (for example, low level) when the differential signal Vout is lower than the lower limit voltage V _low is output. is there. Further, the lower limit counter 330 selects the bit of the n-th digit among the N bits indicating the count value according to the control signal SW-, and outputs it to the transfer unit 380 as the detection signal DET-.

In the lower limit side counter 330, the bit of the nth digit (detection signal DET−) indicates whether or not the amount of change in the light amount is below the lower limit threshold (in other words, whether or not there is an off event).

Also, the count values of the upper limit counter 320 and the lower limit counter 330 are initialized to initial values (for example, “0”) by the reset signal RST from the transfer unit 380.

Although both the upper limit counter 320 and the lower limit counter 330 are arranged, only one of them may be arranged. For example, the lower limit counter 330 is not necessary when only the on event is detected.

The upper limit counter 320 and the lower limit counter 330 both output the n-th digit as a detection signal, but they can also output different digits. For example, the upper limit counter 320 may output the third digit as the detection signal DET +, while the lower limit counter 330 may output the second digit as the detection signal DET +.

Also, although the upper limit counter 320 and the lower limit counter 330 increment (ie, increment) the count value by one, the increment value can be two or more. Further, these counters can also decrement the count value.

[Counter configuration example]
FIG. 8 is a block diagram showing a configuration example of the upper limit counter 320 and the lower limit counter 330 according to the first embodiment of the present technology. In the figure, a is a block diagram showing one configuration example of the upper limit counter 320, and b in the figure is a block diagram showing one configuration example of the lower limit counter 330.

The upper limit counter 320 includes N n-th digit output units such as the 0-th digit output unit 321, the first digit output unit 322, and the second digit output unit 323, and N switches such as the

switches

324, 325, and 326. With. Further, the control signal SW + from the control circuit 211 includes N control signals SW2 ⁿ + such as the control signals SW1 +, SW2 + and SW4 +. These control signals are signals for instructing the output of any one of N digits. For example, only the control signal corresponding to the digit to be output out of N is set to the high level and the remaining control signals are set to the low level. Is set to.

The 0th digit output unit 321 outputs the LSB (Least Significant Bit) of the bit string indicating the count value of the upper limit counter 320, in other words, the 0th digit. The 0th digit output unit 321 is realized by, for example, a toggle flip-flop, inverts the held value every time the comparison result COMP + falls, and outputs the held value to the 1st digit output unit 322 and the switch 324 as the 0th digit. To do.

The first digit output unit 322 outputs the first digit of the bit string indicating the count value. The first digit output unit 322 is realized by, for example, a toggle flip-flop, inverts the held value every time the 0th digit falls, and outputs the held value as the first digit to the second digit output unit 323 and the switch 325. To do.

The second digit output unit 323 outputs the second digit of the bit string indicating the count value. The second digit output unit 323 is realized by, for example, a toggle flip-flop, inverts the held value every time the first digit falls, and outputs the held value as the second digit.

The switch 324 outputs the 0th digit as a detection signal DET + to the transfer unit 380 when the control signal SW1 + is at a high level.

The switch 325 outputs the first digit to the transfer unit 380 as the detection signal DET + when the control signal SW2 + is at a high level.

The switch 326 outputs the second digit to the transfer unit 380 as the detection signal DET + when the control signal SW4 + is at the high level.

The configurations of the n-th digit output section and the switches after the third digit are the same as those up to the second digit. With the above configuration, the upper limit counter 320 outputs the n-th digit of N bits as the detection signal DET + according to the control signal SW2 ⁿ +.

This detection signal DET + indicates whether or not the change amount of the light amount exceeds the upper limit threshold value of the unit change amount (+) × 2 ⁿ . Further, the upper limit threshold can be changed by the digital control signal SW +.

Here, in a general DVS, the counting unit 310 is not arranged, and the comparison result COMP of the comparator is output as it is as the detection signal DET. In this configuration, the upper limit threshold corresponds to the analog upper limit voltage V _high . Then, in order to change the threshold value, it is necessary to increase or decrease the upper limit voltage V _high . However, when the analog voltage is increased / decreased, it takes a certain period of time for the increased / decreased voltage to stabilize, and the adjustment of the threshold value takes longer.

On the other hand, in the configuration in which the counting unit 310 is provided, the upper limit threshold can be changed by the digital control signal SW +. Therefore, the time required to adjust the threshold value can be shortened as compared with the case where the analog voltage is increased or decreased. The same applies to the lower threshold.

Moreover, in order to increase or decrease the analog voltage, it is necessary to operate an analog circuit such as a DAC (Digital to Analog Converter), which consumes more power than when operating a digital circuit. On the other hand, in the configuration in which the counting unit 310 is provided, it is sufficient to operate the digital control circuit 211 and the counting unit 310, so that the power consumption is smaller than that in the case where the analog voltage is increased or decreased.

The lower limit counter 330 includes N-th n-th digit output units such as the 0-th digit output unit 331, the first-digit output unit 332, and the second-digit output unit 333, and N switches such as the

switches

334, 335, and 336. With. These configurations are similar to those of the upper limit counter 320.

FIG. 9 is a graph showing an example of the relationship between the amount of change in light amount and the count value according to the first embodiment of the present technology. In the figure, the vertical axis represents the count value on the upper limit side, and the horizontal axis represents the change amount of the light amount.

The upper limit counter 320 counts up the count value each time the change amount of the light amount exceeds the unit change amount (+). Further, the upper limit counter 320 outputs the bit of the nth digit as the detection signal DET +. When the upper limit counter 320 is a binary counter and the integrated change amount of the unit change amount (+) × 2 ⁿ is the upper limit threshold value, the change amount of the light amount of the bit of the nth digit (detection signal DET +) exceeds the upper limit threshold value. It indicates whether or not (in other words, the presence or absence of an on event). As described above, this upper limit threshold value is variable and can be easily changed by the control signal SW +. Similarly, regarding the detection of the off event, the lower limit threshold value can be easily changed.

FIG. 10 is a circuit diagram showing a configuration example of the initialization control unit 390 according to the first embodiment of the present technology. The initialization control unit 390 includes

delay units

391 and 392, and XOR (exclusive OR)

gates

393 and 394.

The delay unit 391 delays the comparison result COMP + from the comparator 440. The delay unit 391 supplies the delayed signal to the XOR gate 393. The delay unit 392 delays the comparison result COMP- from the comparator 440. The delay unit 391 supplies the delayed signal to the XOR gate 394.

The XOR gate 393 generates the exclusive OR of the comparison result COMP + before and after the delay. The XOR gate 394 generates an exclusive OR of the comparison result COMP- before and after the delay. A pulse signal is generated by these

XOR gates

393 and 394. This pulse signal is output to the differentiating circuit 430 as the auto-zero signal XAZ.

The initialization control unit 390 generates the auto-zero signal XAZ from the comparison results COMP + and COMP-, but the configuration is not limited to this. For example, as illustrated in FIG. 11, the initialization control unit 390 can also generate the auto-zero signal XAZ from the LSBs of the upper limit counter 320 and the lower limit counter 330. In this way, by detecting the change in the LSB, it is possible to perform the initialization when the count is reliably performed.

Alternatively, as illustrated in FIG. 12, the initialization control unit 390 may generate the auto-zero signal XAZ from a plurality of digits of the upper limit counter 320 and the lower limit counter 330. For example, when a 2-bit Johnson counter is used as the upper limit counter 320 and the lower limit counter 330, the count value is counted in binary order of “00”, “01”, “11” and “10”. Therefore, the LSB alone cannot detect the start of counting. In this case, the initialization control unit 390 may refer to the 0th digit and the 1st digit and perform initialization when the combination of them becomes "01".

[Operation example of imaging device]
FIG. 13 is a flowchart showing an example of the operation of the solid-state image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for detecting an address event is executed.

The solid-state imaging device 200 initializes the count value of the counting unit 310 (step S901) and initializes the differentiating circuit 430 (step S902). Then, the comparator 440 determines whether or not the differential signal Vout is outside the voltage range from the lower limit voltage V _low to the upper limit voltage V _high (step S903). When the differential signal Vout is within the voltage range (step S903: No), the comparator 440 repeats step S903.

On the other hand, when the differential signal Vout is out of the voltage range (step S903: Yes), the counting unit 310 counts up the count value (step S904), and whether the count value is 2 ⁿ or more on the upper limit side or the lower limit side. It is determined whether or not (step S905). When the count value is less than 2 ⁿ (step S905: No), the solid-state imaging device 200 repeatedly executes step S902 and subsequent steps.

When the count value is 2 ⁿ or more (step S905: Yes), the counting unit 310 detects the address event (step S906), and the transfer unit 380 transfers the detection signal (step S907). After step S907, the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps.

As described above, according to the first embodiment of the present technology, the counting unit 310 counts the count value based on the comparison result COMP and outputs the n-th digit of the count value as the detection signal, which corresponds to the threshold value. 2 ⁿ can be adjusted by the digital control signal SW. As a result, the time required for the adjustment can be shortened as compared with the case where the threshold value is adjusted by the analog voltage.

[First Modification]
In the first embodiment described above, the comparator 440 compares both the upper limit voltage and the lower limit voltage with the differential signal Vout, but it is also possible to compare the variable voltage with the differential signal Vout. The comparator 440 of the first modified example of the first embodiment is different from that of the first embodiment in that a variable voltage is compared with a differential signal Vout.

FIG. 14 is a diagram showing a control example of the voltage comparison unit 400 and the control circuit 211 in the first modified example of the first embodiment of the present technology. In the figure, a is a circuit diagram showing a configuration example of the voltage comparison unit 400 in the first modification of the first embodiment. B in the same figure is a diagram showing an example of control by the control circuit 211 in the first modification of the first embodiment.

As illustrated in a in the figure, in the voltage comparison unit 400 of the first modification, the comparator 440 does not include the P-type transistor 443 and the N-type transistor 444. Further, the variable voltage Vb is input to the comparator 440 as a threshold voltage instead of the upper limit voltage and the lower limit voltage. The variable voltage Vb is generated by the control circuit 211, for example. The comparator 440 outputs the comparison result COMP with the variable voltage Vb to the counting unit 310.

Further, as illustrated in b in the same figure, the value of the variable voltage Vb is controlled by the control circuit 211 to be a different value in a time division manner between the upper limit voltage V _high and the lower limit voltage V _low . The control circuit 211 also generates a polarity signal V _polarity indicating whether the variable voltage Vb is the upper limit voltage V _high or the lower limit voltage V _low, and supplies the polarity signal V _polarity to the counting unit 310. For example, when the variable voltage Vb is the upper limit voltage V _high , the polarity signal V _polarity is set to a high level (power supply voltage VDD or the like). On the other hand, when the variable voltage Vb is the lower limit voltage V _low , the polarity signal V _polarity is set to a low level (ground voltage GND or the like).

FIG. 15 is a block diagram showing a configuration example of the counting unit 310 in the first modified example of the first embodiment of the present technology. The counting unit 310 of the first modification of the first embodiment differs from that of the first embodiment in that it further includes

switches

311 and 312.

The switch 311 opens and closes the path between the voltage comparison unit 400 and the upper limit counter 320 according to the polarity signal V _polarity from the control circuit 211. The switch 312 opens and closes the path between the voltage comparison unit 400 and the lower limit counter 330 according to the polarity signal V _polarity . When the polarity signal V _polarity is at a high level (that is, the variable voltage Vb is the upper limit voltage V _high ), the switch 311 is closed and the switch 312 is opened. On the other hand, when the polarity signal V _polarity is at a low level (that is, the variable voltage Vb is the lower limit voltage V _low ), the switch 311 is opened and the switch 312 is closed. The switch 311 is an example of the upper limit switch described in the claims, and the switch 312 is an example of the lower limit switch described in the claims.

As described above, according to the first modification of the first embodiment of the present technology, the comparator 440 compares the variable voltage with the differential signal Vout, so that the number of transistors in the comparator 440 can be reduced. ..

[Second Modification]
In the above-described first embodiment, the counting unit 310 is arranged for each pixel 300, but as the number of pixels increases, the number of counting units 310 increases and the circuit scale of the solid-state imaging device 200 may increase. There is. The solid-state imaging device 200 of the second modification of the first embodiment is different from the first embodiment in that the plurality of pixels 300 share the counting unit 310.

FIG. 16 is a plan view showing a configuration example of the pixel array section 214 in the second modified example of the first embodiment of the present technology. The pixel array section 214 in the modification of the first embodiment is different from that of the first embodiment in that it is divided by a plurality of pixel blocks 301.

In each pixel block 301, M (M is an integer of 2 or more) pixels 300 are arranged. These M pixels 300 share one counting unit 310.

FIG. 17 is a block diagram showing a configuration example of a pixel block 301 in the second modification example of the first embodiment of the present technology. The pixel block 301 of the second modification of the first embodiment includes M voltage comparison units 400, M initialization control units 390, a counting unit 310, and a transfer unit 380.

The m-th (m is an integer from 0 to M−1) -th voltage comparison unit 400 outputs the comparison result COMPm to the counting unit 310 and the m-th initialization control unit 390. The m-th initialization control unit 390 supplies the auto-zero signal XAZ to the m-th voltage comparison unit 400.

The m-th initialization control unit 390, the m-th initialization control unit 390, the counting unit 310, and the transfer unit 380 form the m-th pixel 300. That is, the M pixels 300 share the counting unit 310 and the transfer unit 380.

FIG. 18 is a block diagram showing a configuration example of the counting unit 310 in the second modified example of the first embodiment of the present technology. The counting unit 310 of the second modified example of the first embodiment differs from that of the first embodiment in that an upper limit side comparison result processing unit 340 and a lower limit side comparison result processing unit 350 are further provided.

The upper limit side comparison result processing unit 340 processes the comparison result COMPm + with the upper limit voltage of each of the M pixels to generate a 1-bit signal. The upper limit comparison result processing unit 340 supplies the bit of the processing result to the upper limit counter 320.

The lower limit side comparison result processing unit 350 processes the comparison result COMPm− with the lower limit voltage of each of the M pixels to generate a 1-bit signal. The lower limit comparison result processing unit 350 supplies the bit of the processing result to the lower limit counter 330.

FIG. 19 is a circuit diagram showing a configuration example of the upper limit side comparison result processing unit 340 in the second modification example of the first embodiment of the present technology. In the figure, “a” is an example of a circuit diagram of the upper limit side comparison result processing unit 340 when the XOR gate is used. In the figure, b is an example of a circuit diagram of the upper limit side comparison result processing unit 340 when an OR (logical sum) gate is used. C in the figure is an example of a circuit diagram of the upper limit side comparison result processing unit 340 when a switch is used.

An XOR gate 341 is arranged in the upper limit side comparison result processing unit 340 as illustrated in a in the figure. The XOR gate 341 outputs the exclusive OR of the M comparison results COMPm + to the upper limit counter 320 as the comparison result COMP + (processing result).

Note that an OR gate 342 may be arranged in the upper limit side comparison result processing unit 340 instead of the XOR gate 341 as illustrated in b in the figure. The OR gate 342 outputs the logical sum of the M comparison results COMPm + to the upper limit counter 320 as the comparison result COMP +.

Also, as illustrated in c in the figure, M switches 343 can be arranged in the upper limit side comparison result processing unit 340 instead of the XOR gate 341. The m-th switch 343 outputs the m-th comparison result COMPm + to the upper limit counter 320 as the comparison result COMP + according to the selection signal SELC from the control circuit 211. The control circuit 211 outputs any one of the M comparison results COMPm + according to the selection signal SELC. The comparison result to be output is switched, for example, at regular intervals.

For example, it is assumed that the comparison result COMP1 + becomes high level for a certain period of time, and the comparison result COMP2 + becomes high level for a certain period of time after a short delay. Further, it is assumed that the high-level periods of the comparison results COMP1 + and COMP2 + partially overlap. In this case, in the configuration in which the XOR gate 341 is provided, the upper limit counter 320 counts up twice. On the other hand, in the configuration in which the OR gate 342 is provided, the upper limit counter 320 counts up only once. As described above, in the configuration in which the OR gate 342 is provided, the number of times of counting can be reduced.

Also, in the configuration in which the switch 343 is arranged, it is possible to select only a part of the comparison results of the M pixels and to thin out the rest without outputting them.

The configuration of the lower limit side comparison result processing unit 350 is similar to that of the upper limit side comparison result processing unit 340.

As described above, according to the second modified example of the first embodiment of the present technology, since a plurality of pixels 300 share one counting unit 310, comparison with the case where the counting unit 310 is arranged for each pixel As a result, the circuit scale of the solid-state image sensor 200 can be reduced.

[Third Modification]
In the second modification of the first embodiment described above, the comparator 440 compares both the upper limit voltage and the lower limit voltage with the differential signal Vout. However, the comparator 440 compares the variable voltage with the differential signal Vout. You can also The third modification of the first embodiment is an application of the first modification to the second modification.

FIG. 20 is a block diagram showing a configuration example of the counting unit 310 in the third modification example of the first embodiment of the present technology. The configurations of the comparator 440 and the control circuit 211 in the third modified example of the first embodiment are similar to those of the first modified example of the first embodiment.

Also, the counting unit 310 of the third modified example is provided with a plurality of switches such as switches 311 to 314. The number of switches is twice the input comparison result COMPm. For example, when the comparison results COMP1 and COMP2 are input, four switches 311 to 314 are arranged.

The switch 311 opens and closes a path between the voltage comparison unit 400 corresponding to the comparison result COMP1 and the upper limit comparison result processing unit 340 according to the polarity signal V _polarity from the control circuit 211. The switch 312 opens and closes a path between the voltage comparison unit 400 corresponding to the comparison result COMP2 and the upper limit side comparison result processing unit 340 according to the polarity signal V _polarity . The switch 313 opens and closes a path between the voltage comparison unit 400 corresponding to the comparison result COMP1 and the lower limit side comparison result processing unit 350 according to the polarity signal V _polarity . The switch 314 opens and closes a path between the voltage comparison unit 400 corresponding to the comparison result COMP2 and the lower limit side comparison result processing unit 350 according to the polarity signal V _polarity .

When the polarity signal V _polarity is at a high level (that is, the variable voltage Vb is the upper limit voltage V _high ), the

switches

311 and 312 are closed and the

switches

313 and 314 are opened. On the other hand, when the polarity signal V _polarity is at the low level (that is, the variable voltage Vb is the lower limit voltage V _low ), the

switches

311 and 312 are open and the

switches

313 and 314 are closed. The

switches

311 and 312 are an example of an upper limit switch described in the claims, and the

switches

313 and 314 are an example of a lower limit switch described in the claims.

If there are three or more comparison results, one switch is added to the upper limit side and one switch to the lower limit side each time the comparison result increases by one.

As described above, according to the third modification of the first embodiment of the present technology, the comparator 440 compares the variable voltage with the differential signal Vout, so that the number of transistors in the comparator 440 can be reduced. ..

<2. Second Embodiment>
In the above-described first embodiment, the upper limit counter 320 and the lower limit counter 330 individually count the number of times the differential signal Vout is higher than the upper limit voltage and the number of times the differential signal is lower than the upper limit voltage. It was However, in this configuration, when flicker occurs in a fluorescent lamp or the like, a periodic change in brightness due to the flicker is detected as an address event, which may increase the number of address event detections. The counting unit 310 of the second embodiment differs from that of the first embodiment in that an up / down counter is arranged to suppress the influence of flicker.

FIG. 21 is a block diagram showing a configuration example of the counting unit 310 according to the second embodiment of the present technology. The counting section 310 of the second embodiment includes an up / down counter 361, an upper limit side comparison circuit 362 and a lower limit side comparison circuit 363.

The up / down counter 361 performs increment processing of the count value CNT when the high level comparison result COMP + is input, and performs decrement processing of the count value CNT when the low level comparison result COMP- is input. Is. That is, the count value CNT is counted up when the differential signal Vout becomes higher than the upper limit voltage, and the count value CNT is counted down when the differential signal Vout becomes lower than the lower limit voltage. The up / down counter 361 supplies the count value CNT to the upper limit side comparison circuit 362 and the lower limit side comparison circuit 363.

The up / down counter 361 performs the increment processing by the comparison result COMP + and the decrement processing by the comparison result COMP-, but the configuration is not limited to this. The up / down counter 361 can also perform decrement processing by the comparison result COMP + and increment processing by the comparison result COMP-.

The upper limit side comparison circuit 362 compares the digital value Dth + from the control circuit 211 with the count value CNT. Here, the digital value Dth + indicates an upper limit threshold. The upper limit side comparison circuit 362 outputs the comparison result as a detection signal DET +.

The lower limit side comparison circuit 363 compares the digital value Dth− from the control circuit 211 with the count value CNT. Here, the digital value Dth- indicates a lower limit threshold. The lower limit side comparison circuit 363 outputs the comparison result as a detection signal DET-.

For example, it is assumed that the flicker causes the light amount to increase for a certain period of time and then decreases for a certain period of time. The number of times that the differential signal Vout becomes higher than the upper limit voltage due to the increase of the light amount is 10 times, and the number of times that the differential signal Vout becomes lower than the lower limit voltage due to the decrease of the light amount is 10 times. Further, 2 ⁿ indicating the upper limit threshold and the lower limit threshold is set to “8”. In the first embodiment in which the upper limit counter 320 and the lower limit counter 330 individually count, the count value of each of the upper limit counter 320 and the lower limit counter 330 exceeds “8”, and the on event and the off event are 1 It is detected one by one.

On the other hand, when arranging the up-down counter 361, for example, the initial value of the count value is set to “−5”, the digital value Dth + indicating the upper limit threshold is set to “+8”, and the lower limit threshold is set. The digital value Dth− shown is “−8”. As a result, the count value is incremented to “+5” when the light amount is increased, and then the count value is decremented to “−5”. Since the count value is within the range of “−8” to “+8”, neither an on event nor an off event is detected. In this way, the count-up by the comparison result COMP + and the count-down by the comparison result COMP- cancel each other out, so that the influence of flicker can be suppressed.

Further, when the counter outputs only one of the digits as in the first embodiment, for example, in the binary counter, the threshold value is set to a value between 2 ⁿ (8 etc.) and 2 ^{n + 1} (16 etc.). Can not be adjusted. On the other hand, the up / down counter 361 outputs not only the nth digit but the entire count value CNT, and compares it with the digital value (threshold value) in the subsequent stage. As a result, the threshold between 2 ⁿ and 2 ^{n + 1} can be set, and the threshold can be adjusted more finely.

Incidentally, the up-down counter 361, as in the first embodiment, and the n ₊ digit corresponding to the upper limit threshold value, the n corresponding to the lower threshold _- outputting the digit as the detection signal DET + and DET- You can also Here, n ₊ and n ₋ are different integers from 0 to N−1. In this case, the upper limit comparison circuit 362 and the lower limit comparison circuit 363 are unnecessary. Further, although both the upper limit side comparison circuit 362 and the lower limit side comparison circuit 363 are arranged in the counting unit 310, only one of them may be arranged.

As described above, according to the second embodiment of the present technology, the up / down counter 361 performs the increment process according to the comparison result COMP + and the decrement process according to the comparison result COMP−. The decrease due to the decrease in the amount of light can be offset. As a result, it is possible to suppress the influence of flicker in which the light amount periodically increases and decreases.

[Modification]
In the above-described second embodiment, the comparator 440 compares both the upper limit voltage and the lower limit voltage with the differential signal Vout, but it is also possible to compare the variable voltage with the differential signal Vout. The modification of the second embodiment is a modification of the first embodiment further applied to the first modification of the first embodiment.

FIG. 22 is a block diagram showing a configuration example of the counting unit 310 in the modified example of the second embodiment of the present technology. The configurations of the comparator 440 and the control circuit 211 in the modification of the second embodiment are similar to those of the first modification of the first embodiment.

Further, the comparison result COMP from the voltage comparison unit 400 and the polarity signal V _polarity from the control circuit 221 are input to the up / down counter 361 of the modification of the second embodiment. The up / down counter 361 increments the count value CNT according to the comparison result COMP when the high-level polarity signal V _polarity is input. On the other hand, the up / down counter 361 decrements the count value CNT according to the comparison result COMP when the low-level polarity signal V _polarity is input.

As described above, according to the modified example of the second embodiment of the present technology, the comparator 440 compares the variable voltage with the differential signal Vout, so that the number of transistors in the comparator 440 can be reduced.

<3. Third Embodiment>
In the above-described first embodiment, the solid-state image sensor 200 only detects an address event, but image data may be required to be captured for purposes such as recording the status of a traffic accident. The solid-state image sensor 200 of the third embodiment is different from that of the first embodiment in that image data is further imaged.

FIG. 23 is a block diagram showing a configuration example of the solid-state imaging device 200 according to the third embodiment of the present technology. The solid-state image sensor 200 of the third embodiment differs from that of the first embodiment in that it further includes a DAC 215.

The DAC 215 generates a predetermined reference signal by DA (Digital to Analog) conversion. For example, a ramp signal whose level changes in a slope is generated as a reference signal. The DAC 215 supplies the reference signal to each of the pixels 300.

A mode signal MODE is also input to the pixel array unit 214. The mode signal MODE is a signal indicating either the imaging mode or the detection mode. Here, the imaging mode is a mode in which image data is imaged using the reference signal. On the other hand, the detection mode is a mode for detecting an address event. The imaging mode is used, for example, to record the situation of a traffic accident with image data. On the other hand, the detection mode is used when performing image recognition or the like.

FIG. 24 is a block diagram showing a configuration example of the pixel 300 according to the third embodiment of the present technology. The pixel 300 according to the third embodiment is different from that according to the first embodiment in that the pixel 300 according to the third embodiment further includes a reference signal comparison unit 500.

The reference signal comparison unit 500 compares the pixel signal corresponding to the light amount with the reference signal Vref from the DAC 215. The reference signal comparison unit 500 supplies the comparison result CM to the counting unit 310. Details of the reference signal comparison unit 500 will be described later.

The counting unit 310 according to the third embodiment counts the count value in the imaging mode until the comparison result CM is inverted, and supplies the count value CNT to the signal processing unit 212. On the other hand, in the detection mode, the address event is detected as in the first embodiment.

FIG. 25 is a circuit diagram showing a configuration example of the voltage comparison unit 400 according to the third embodiment of the present technology. The P-type transistor 443 and the N-type transistor 444 are not arranged in the comparator 440 in the voltage comparison unit 400 according to the third embodiment. Therefore, the comparator 440 outputs only the comparison result COMP + regarding the ON event.

In addition, in the logarithmic response unit 410 of the third embodiment, the N-type transistor 412 supplies the voltage signal obtained by converting the photocurrent to the reference signal comparison unit 500 as a pixel signal.

FIG. 26 is a block diagram showing a configuration example of the counting unit 310 according to the third embodiment of the present technology. The counting unit 310 of the third embodiment includes a selector 371 and an upper limit counter 320.

The selector 371 selects either the comparison result COMP + from the voltage comparison unit 400 or the comparison result CM from the reference signal comparison unit 500 according to the mode signal MODE. The selector 371 selects the comparison result CM in the imaging mode and outputs it to the upper limit counter 320, and selects the comparison result COMP + in the detection mode and outputs it to the upper limit counter 320.

The mode signal MODE is further input to the upper limit counter 320 of the third embodiment. In the imaging mode, the upper limit counter 320 counts the count value CNT over the period until the output signal (comparison result CM) from the selector 371 is inverted from the initial value, and supplies the count value CNT to the signal processing unit 212. The signal processing unit 212 arranges the data indicating the count value CNT for each pixel in a two-dimensional lattice as pixel data of the pixel to generate image data.

On the other hand, in the detection mode, the upper limit counter 320 counts the count value each time the selector 371 outputs the high-level output signal (comparison result COMP +), and detects the nth digit according to the control signal SW + to detect the on event. The signal is output to the transfer unit 380 as the signal DET +.

FIG. 27 is a circuit diagram showing a configuration example of the reference signal comparison unit 500 according to the third embodiment of the present technology. The reference signal comparison unit 500 includes a selector 511, a transfer transistor 512, a reset transistor 513, an amplification transistor 514, and a comparator 515. As a transistor in the reference signal comparison unit 500, for example, an N-type MOS transistor is used.

The selector 511 selects either the power supply terminal or the transfer transistor 512 according to the mode signal MODE and connects it to the current-voltage conversion unit 416. The switch 511 connects the transfer transistor 512 to the current-voltage conversion unit 416 in the imaging mode, and connects the power supply terminal to the current-voltage conversion unit 416 in the detection mode.

The transfer transistor 512 transfers the electric charge from the current-voltage conversion unit 416 to the floating diffusion layer according to the transfer signal SH from the control circuit 211. The reset transistor 513 initializes the floating diffusion layer according to the reset signal RST from the control circuit 211. The amplification transistor 514 amplifies the potential of the floating diffusion layer and supplies it to the comparator 515 as a pixel signal. The comparator 515 compares the pixel signal with the reference signal Vref from the DAC 215.

In the imaging mode, the control circuit 211 generates a reset level by the reset signal RST immediately before the end of exposure, and transfers a charge by the transfer signal SH at the end of exposure to generate a signal level.

With the above configuration, the counting unit 310 is used for both the on-event detection process and the AD conversion process for generating pixel data. Therefore, the circuit scale of the solid-state imaging device 200 can be reduced as compared with a configuration in which a counter for AD conversion is added to the outside of the counting unit 310.

As described above, according to the third embodiment of the present technology, the counting unit 310 counts the count value based on either the comparison result CM with the reference signal or the comparison result COMP + with the threshold voltage. Therefore, it is not necessary to add a counter that counts based on the comparison result CM. As a result, the circuit scale of the solid-state imaging device 200 can be reduced as compared with the case where the counter is added.

[First Modification]
Although the counting unit 310 outputs the N-bit count value CNT (that is, pixel data) in the above-described third embodiment, the data size of the pixel data may be insufficient with N bits. Therefore, the counting unit 310 of the first modified example of the third embodiment differs from that of the third embodiment in that the size of pixel data is enlarged to eliminate the lack of the data size.

FIG. 28 is a block diagram showing a configuration example of the counting unit 310 in the first modified example of the third embodiment of the present technology. The counting unit 310 of the first modified example of the third embodiment differs from that of the third embodiment in that it further includes a selector 372 and a lower limit counter 330.

Further, a P-type transistor 443 and an N-type transistor 444 are further arranged in the comparator 440 (not shown) of the first modification of the third embodiment, and the comparator 440 further outputs the comparison result COMP-. I shall.

Also, the upper limit counter 320 of the first modification of the third embodiment supplies the Nth digit bit to the selector 372 in the imaging mode. The upper limit counter 320 also supplies the N bits to the signal processing unit 212 as a bit string of the lower digit of the count value CNT of 2N bits.

The selector 372 outputs either the Nth digit from the upper limit counter 320 or the comparison result COMP− to the lower limit counter 330 according to the mode signal MODE. The selector 371 is an example of the pre-stage selector described in the claims, and the selector 372 is an example of the post-stage selector described in the claims. The circuit including the

selectors

371 and 372 is an example of the selection unit described in the claims.

The lower limit counter 330 of the first modification of the third embodiment counts an N-bit count value each time a high-level output signal (Nth digit) is output from the selector 372 in the imaging mode. Then, the lower limit counter 330 supplies the N bits to the signal processing unit 212 as a high-order bit string of the 2N-bit count value CNT.

A 2N-bit count value CNT is generated for each pixel by N bits from the upper limit counter 320 in the preceding stage and N bits from the lower limit counter 330 in the subsequent stage. The signal processing unit 212 arranges the data indicating the count value CNT for each pixel in a two-dimensional lattice as pixel data of the pixel to generate image data. The upper limit side counter 320 is an example of the preceding stage counter described in the claims, and the lower limit side counter 330 is an example of the latter stage counter described in the claims.

On the other hand, in the detection mode, the lower limit counter 330 counts the count value every time a low-level output signal (comparison result COMP-) is output from the selector 371, and the nth digit is turned off event according to the control signal SW-. Output to the transfer unit 380 as the detection signal DET-.

Although the upper limit counter 320 is arranged in the front stage and the lower limit counter 330 is arranged in the rear stage, the configuration is not limited to this. Conversely, the upper limit counter 320 may be arranged in the latter stage and the lower limit counter 330 may be arranged in the former stage.

As described above, according to the first modified example of the third embodiment of the present technology, since the lower limit counter 330 is further arranged at the subsequent stage of the upper limit counter 320, the size larger than that of only the upper limit counter 320 is provided. It is possible to count a count value (such as 2N bits).
[Second Modification]
In the first modification of the above-described third embodiment, the counting unit 310 outputs the count value CNT (that is, pixel data) of 2N bits, but with 2N bits, the data size of pixel data is There may be a shortage. Therefore, the counting unit 310 of the second modification of the third embodiment differs from that of the third embodiment in that the size of the pixel data is further expanded to eliminate the lack of the data size.

FIG. 29 is a block diagram showing a configuration example of the counting unit 310 in the second modified example of the third embodiment of the present technology. The counting unit 310 of the second modified example of the third embodiment differs from that of the third embodiment in that it further includes a switch 373 and a spare counter 374.

The switch 373 opens and closes the path between the terminal for outputting the Nth digit of the lower limit counter 330 and the input terminal of the spare counter 374 according to the mode signal MODE. The switch 373 shifts to the closed state in the imaging mode and shifts to the open state in the detection mode.

The spare counter 374 counts a count value of M (M is an integer) bits each time a high-level output signal (Nth digit) is output from the switch 373 in the imaging mode. The spare counter 374 supplies the M bits to the signal processing unit 212 as a bit string of the upper digit of the count value CNT. A count value CNT of 2N + M bits is generated for each pixel by the N bits from the upper limit counter 320, the N bits from the lower limit counter 330, and the M bits of the spare counter 374.

Note that the backup counter 374 can be arranged in the preceding stage of the upper limit counter 320, as illustrated in FIG. By arranging the spare counter 374 between the selector 371 and the reference signal comparison unit 500, it is possible to reduce the parasitic capacitance of the N digit LSB of the upper limit counter 320 as compared with FIG. Thereby, power consumption can be reduced.

As described above, according to the first modification of the third embodiment of the present technology, since the spare counter 374 is further arranged, a size larger than the case of only the upper limit counter 320 and the lower limit counter 330 (2N + M bits, etc.). The counted value of) can be counted.

<4. Imaging Device According to Fourth Embodiment (Scan Method)>
The imaging device 20 according to the first configuration example described above is an asynchronous imaging device that reads events by an asynchronous reading method. However, the event reading method is not limited to the asynchronous reading method, and may be the synchronous reading method. The image pickup apparatus to which the synchronous reading method is applied is the same scan type image pickup apparatus as a normal image pickup apparatus that performs image pickup at a predetermined frame rate.

FIG. 31 is a block diagram showing an example of the configuration of an image capturing apparatus according to the second configuration example, that is, a scan type image capturing apparatus, which is used as the image capturing apparatus 20 in the image capturing system 10 to which the technology according to the present disclosure is applied. .

As shown in FIG. 31, the imaging device 20 according to the second configuration example as the imaging device of the present disclosure includes a pixel array unit 21, a drive unit 22, a signal processing unit 25, a read area selection unit 27, and a signal generation unit. 28 is provided.

The pixel array unit 21 includes a plurality of pixels 30. The plurality of pixels 30 output an output signal in response to a selection signal from the read area selection unit 27. The configuration of each of the plurality of pixels 30 is similar to that of the pixel 300 illustrated in FIG. 4. The plurality of pixels 30 output an output signal corresponding to the amount of change in light intensity. The plurality of pixels 30 may be two-dimensionally arranged in a matrix as shown in FIG.

The drive unit 22 drives each of the plurality of pixels 30 and outputs the pixel signal generated by each pixel 30 to the signal processing unit 25. The drive unit 22 and the signal processing unit 25 are circuit units for acquiring gradation information. Therefore, when only the event information is acquired, the drive unit 22 and the signal processing unit 25 may be omitted.

The read area selection unit 27 selects a part of the plurality of pixels 30 included in the pixel array unit 21. Specifically, the read area selection unit 27 determines the selected area in response to a request from each pixel 30 of the pixel array unit 21. For example, the read area selection unit 27 selects any one or a plurality of rows included in the structure of the two-dimensional matrix corresponding to the pixel array unit 21. The read area selection unit 27 sequentially selects one or a plurality of rows according to a preset cycle. The read area selection unit 27 may determine the selected area in response to a request from each pixel 30 of the pixel array unit 21.

The signal generation unit 28 generates an event signal corresponding to an active pixel of the selected pixels that has detected an event, based on the output signal of the pixel selected by the read area selection unit 27. The event is an event in which the intensity of light changes. The active pixel is a pixel in which the amount of change in the intensity of light corresponding to the output signal exceeds or falls below a preset threshold value. For example, the signal generator 28 compares an output signal of a pixel with a reference signal, detects an active pixel that outputs an output signal when the output signal is larger or smaller than the reference signal, and generates an event signal corresponding to the active pixel. ..

The signal generation unit 28 may be configured to include, for example, a column selection circuit that arbitrates a signal that enters the signal generation unit 28. Further, the signal generation unit 28 may be configured to output not only the information of the active pixel in which the event is detected, but also the information of the inactive pixel in which the event is not detected.

The signal generation unit 28 outputs address information and time stamp information (for example, (X, Y, T)) of the active pixel in which the event is detected, through the output line 15. However, the data output from the signal generation unit 28 may be not only the address information and the time stamp information, but also frame format information (for example, (0,0,1,0, ...)). ..

<5. Application to mobiles>
The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. May be.

FIG. 32 is a block diagram showing a schematic configuration example of a vehicle control system which is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in FIG. 32, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, a vehicle exterior information detection unit 12030, a vehicle interior information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 includes a drive force generation device for generating a drive force of a vehicle such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to wheels, and a steering angle of the vehicle. It functions as a steering mechanism for adjusting and a control device such as a braking device for generating a braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a head lamp, a back lamp, a brake lamp, a winker, or a fog lamp. In this case, the body system control unit 12020 can be input with radio waves or signals of various switches transmitted from a portable device that substitutes for a key. The body system control unit 12020 receives input of these radio waves or signals and controls the vehicle door lock device, power window device, lamp, and the like.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the image capturing unit 12031 to capture an image of the vehicle exterior and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.

The image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of received light. The image pickup unit 12031 can output the electric signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects in-vehicle information. To the in-vehicle information detection unit 12040, for example, a driver state detection unit 12041 that detects the state of the driver is connected. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether or not the driver is asleep.

The microcomputer 12051 calculates the control target value of the driving force generation device, the steering mechanism or the braking device based on the information on the inside and outside of the vehicle acquired by the outside information detection unit 12030 or the inside information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation of a vehicle, follow-up traveling based on an inter-vehicle distance, vehicle speed maintenance traveling, a vehicle collision warning, or a vehicle lane departure warning. It is possible to perform cooperative control for the purpose.

Further, the microcomputer 12051 controls the driving force generation device, the steering mechanism, the braking device, or the like on the basis of the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's It is possible to perform cooperative control for the purpose of autonomous driving or the like that autonomously travels without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control for the purpose of antiglare such as switching the high beam to the low beam. It can be carried out.

The voice image output unit 12052 transmits an output signal of at least one of a voice and an image to an output device capable of visually or audibly notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of FIG. 32, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

FIG. 33 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 33, the image pickup unit 12031 includes

image pickup units

12101, 12102, 12103, 12104, and 12105.

The

imaging units

12101, 12102, 12103, 12104, 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield inside the vehicle. The image capturing unit 12101 provided on the front nose and the image capturing unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire images in front of the vehicle 12100. The

imaging units

12102 and 12103 included in the side mirrors mainly acquire images of the side of the vehicle 12100. The image capturing unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that FIG. 33 shows an example of the shooting range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the

imaging units

12102 and 12103 provided on the side mirrors, and the imaging range 12114 indicates The imaging range of the imaging part 12104 provided in a rear bumper or a back door is shown. For example, by overlaying the image data captured by the image capturing units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera including a plurality of image capturing elements or may be an image capturing element having pixels for phase difference detection.

For example, the microcomputer 12051, based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed with respect to the vehicle 12100). In particular, the closest three-dimensional object on the traveling path of the vehicle 12100, which travels in the substantially same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or more), can be extracted as a preceding vehicle. it can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform cooperative control for the purpose of autonomous driving, which autonomously travels without depending on the operation of the driver.

For example, the microcomputer 12051 uses the distance information obtained from the image capturing units 12101 to 12104 to convert three-dimensional object data regarding a three-dimensional object to other three-dimensional objects such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, telephone poles, and the like. It can be classified, extracted, and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles visible to the driver of the vehicle 12100 and obstacles difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or more than the set value and there is a possibility of collision, the microcomputer 12051 outputs the audio through the audio speaker 12061 and the display unit 12062. A driver can be assisted for avoiding a collision by outputting an alarm to the driver and performing forced deceleration or avoidance steering through the drive system control unit 12010.

At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian is present in the images captured by the imaging units 12101 to 12104. To recognize such a pedestrian, for example, a procedure for extracting a feature point in an image captured by the image capturing units 12101 to 12104 as an infrared camera and pattern matching processing on a series of feature points indicating the contour of an object are performed to determine whether or not the pedestrian is a pedestrian. The procedure for determining When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 causes the recognized pedestrian to have a rectangular contour line for emphasis. The display unit 12062 is controlled so as to superimpose. Further, the audio image output unit 12052 may control the display unit 12062 to display an icon indicating a pedestrian or the like at a desired position.

Above, an example of the vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to the image capturing unit 12031 and the like among the configurations described above. Specifically, for example, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to shorten the time required for adjusting the threshold and improve the convenience and safety of the system.

Note that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a correspondence relationship. Similarly, the matters specifying the invention in the claims and the matters having the same names in the embodiments of the present technology have a correspondence relationship. However, the present technology is not limited to the embodiments and can be embodied by making various modifications to the embodiments without departing from the scope of the invention.

Further, the processing procedure described in the above-described embodiment may be regarded as a method having these series of procedures, or as a program for causing a computer to execute the series of procedures or a recording medium storing the program. You can catch it. As this recording medium, for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be present.

In addition, the present technology may have the following configurations.
(1) A voltage comparison unit that compares an analog signal according to the amount of change in incident light with a predetermined voltage indicating a boundary of a predetermined voltage range and outputs a comparison result as a voltage comparison result,
A solid-state image sensor, comprising: a counter that counts a count value each time the voltage comparison result indicating that the analog signal is out of the voltage range is output.
(2) Further comprising a control circuit for supplying a predetermined control signal,
The solid-state imaging device according to (1), wherein the counting unit selects and outputs any one of a plurality of bits indicating the count value according to the control signal.
(3) The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The counting unit,
An upper limit counter that counts a count value each time the voltage comparison result indicating that the analog signal is higher than the upper limit voltage is output,
The lower limit counter that counts a count value each time the voltage comparison result indicating that the analog signal is lower than the lower limit voltage is output, and the solid-state imaging device according to (2).
(4) The predetermined voltage is a variable voltage that changes to either an upper limit voltage or a lower limit voltage different from each other,
The counting unit,
An upper limit switch that opens and closes a path between the voltage comparison unit and the upper limit counter according to a polarity signal indicating the value of the variable voltage,
The solid-state imaging device according to (3), further including: a lower limit switch that opens and closes a path between the voltage comparison unit and the lower limit counter according to the polarity signal.
(5) A reference signal comparison unit that further compares a pixel signal according to the light amount of the incident light with a predetermined reference signal and outputs a comparison result as a reference signal comparison result,
The counting unit,
A selection unit for selecting one of the voltage comparison result and the reference signal comparison result,
The solid-state imaging device according to (1), further comprising: a counter that counts the count value based on the selected comparison result.
(6) The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The voltage comparison result includes an upper limit side comparison result showing a comparison result with the upper limit voltage and a lower limit side comparison result showing a comparison result with the lower limit voltage,
The counter includes a front stage counter and a rear stage counter,
The selection unit,
A pre-stage selector that selects one of the upper limit side comparison result and the lower limit side comparison result and the reference signal comparison result and supplies the reference signal comparison result to the pre-stage counter,
The solid-state imaging device according to (5), further comprising: a rear stage selector that selects one of the other one of the upper limit side comparison result and the lower limit side comparison result and an output bit of the front stage counter and supplies the selected output bit to the rear stage counter.
(7) The solid-state imaging device according to (6), wherein the counter further includes a preliminary counter.
(8) The preliminary counter counts a count value based on the output bit of the latter-stage counter,
The solid-state imaging device according to (7), further including a switch that opens and closes a path between the latter-stage selector and the preliminary counter.
(9) The solid-state imaging device according to (7), wherein the spare counter is inserted between the pre-stage selector and the reference signal comparison unit.
(10) a control circuit that supplies a predetermined threshold,
The counting unit,
A counter that counts the count value each time the voltage comparison result indicating that the analog signal is outside the voltage range is output,
The solid-state imaging device according to (1), further including a threshold comparison unit that compares the count value with the threshold.
(11) The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The counter is
When the voltage comparison result indicating that the analog signal is higher than the upper limit voltage is output, one of increment processing and decrement processing is performed on the count value, and the analog signal is lower than the lower limit voltage. The solid-state imaging device according to (10), wherein when the voltage comparison result indicating is output, the other one of the increment process and the decrement process is performed on the count value.
(12) The predetermined voltage is a variable voltage that changes to either an upper limit voltage or a lower limit voltage different from each other,
The solid-state imaging device according to (11), wherein the counter performs one of the increment processing and the decrement processing based on a polarity signal indicating the value of the variable voltage and the voltage comparison result.
(13) The voltage comparison unit is arranged in each of a plurality of pixels,
The counting unit is arranged in a pixel block in which the plurality of pixels are arranged,
The counting unit,
A comparison result processing unit that processes the voltage comparison result corresponding to each of the plurality of pixels;
The solid-state imaging device according to any one of (1) to (12), further comprising: a counter that counts the count value based on a processing result of the comparison result processing unit.
(14) The predetermined voltage is a variable voltage that changes to either an upper limit voltage or a lower limit voltage different from each other,
The comparison result processing unit,
An upper limit side comparison result processing unit that processes the voltage comparison result corresponding to the upper limit voltage,
A lower limit side comparison result processing unit that processes the voltage comparison result corresponding to the lower limit voltage,
The counting unit,
An upper limit switch that opens and closes a path between the voltage comparison unit and the upper limit comparison result processing unit according to a polarity signal indicating the value of the variable voltage,
The solid-state imaging device according to (13), further including: a lower limit switch that opens and closes a path between the voltage comparison unit and the lower limit comparison result processing unit according to the polarity signal.
(15) The solid-state imaging device according to (13), wherein the comparison result processing unit outputs an exclusive OR of the voltage comparison results corresponding to each of the plurality of pixels as the processing result.
(16) The solid-state imaging device according to (13), wherein the comparison result processing unit outputs a logical sum of the voltage comparison results corresponding to each of the plurality of pixels as the processing result.
(17) The solid-state imaging device according to (13), wherein the comparison result processing section selects any one of the voltage comparison results corresponding to each of the plurality of pixels and outputs the selected result as the processing result.
(18) The voltage comparison unit is
A current-voltage converter that converts photocurrent into a voltage signal,
A differentiating circuit for differentiating the voltage signal and outputting it as the analog signal;
The solid-state imaging device according to any one of (1) to (17), including a comparator that compares the analog signal with the predetermined voltage.
(19) The solid-state imaging device according to (18), further including an initialization control unit that controls the differentiating circuit every time the count value is counted to set the analog signal to a predetermined initial value.
(20) The method according to any one of (1) to (19), further comprising: a transfer unit that transfers a signal indicating a result of comparing the count value with a predetermined threshold value, and initializes the count value after transferring the signal. The solid-state imaging device according to any one of claims.

100 image pickup apparatus 110 image pickup lens 120 recording section 130 control section 200 solid-state image pickup element 201 light receiving chip 202 circuit chip 211 control circuit 212 signal processing section 213 arbiter 214 pixel array section 215 DAC
300 pixels 301 pixel blocks 310 counting units 311 to 314, 324, 325, 326, 334, 335, 336, 343, 373 switches 320 upper limit counters 321, 331 0th

digit output unit

322, 332 1st

digit output unit

323, 333 Second digit output unit 330 Lower limit counter 340 Upper limit comparison

result processing unit

341, 393, 394 XOR (exclusive OR) gate 342 OR (logical OR) gate 350 Lower limit comparison result processing unit 361 Up-down counter 362 Upper limit Side comparison circuit 363 Lower limit

side comparison circuit

371, 372, 511 Selector 374 Spare counter 380 Transfer unit 390

Initialization control unit

391, 392 Delay unit 400 Voltage comparison unit 410 Logarithmic response unit 411

Photoelectric conversion element

412, 415, 435, 442, 444 N

type tran Dista

413, 431, 434

Capacitor

414, 421, 422, 432, 433, 441, 443 P-type transistor 416 Current-voltage converter 420 Buffer 430 Differentiator 440 Comparator 500 Reference signal comparator 512 Transfer transistor 513 Reset transistor 514 Amplification transistor 515 Comparator 12031 Imaging unit

Claims

A voltage comparison unit that compares an analog signal according to the amount of change in incident light with a predetermined voltage indicating the boundary of a predetermined voltage range and outputs the comparison result as a voltage comparison result,
A solid-state image sensor, comprising: a counter that counts a count value each time the voltage comparison result indicating that the analog signal is out of the voltage range is output.
Further comprising a control circuit for supplying a predetermined control signal,
The solid-state imaging device according to claim 1, wherein the counting unit selects and outputs any one of a plurality of bits indicating the count value according to the control signal.
The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The counting unit,
An upper limit counter that counts a count value each time the voltage comparison result indicating that the analog signal is higher than the upper limit voltage is output,
The solid-state imaging device according to claim 2, further comprising: a lower limit counter that counts a count value each time the voltage comparison result indicating that the analog signal is lower than the lower limit voltage is output.
The predetermined voltage is a variable voltage that fluctuates to either an upper limit voltage or a lower limit voltage different from each other,
The counting unit,
An upper limit switch that opens and closes a path between the voltage comparison unit and the upper limit counter according to a polarity signal indicating the value of the variable voltage,
The solid-state imaging device according to claim 3, further comprising: a lower limit switch that opens and closes a path between the voltage comparison unit and the lower limit counter according to the polarity signal.
Further comprising a reference signal comparison unit that compares a pixel signal according to the light amount of the incident light with a predetermined reference signal and outputs a comparison result as a reference signal comparison result,
The counting unit,
A selection unit for selecting one of the voltage comparison result and the reference signal comparison result,
The solid-state imaging device according to claim 1, further comprising a counter that counts the count value based on the selected comparison result.
The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The voltage comparison result includes an upper limit side comparison result showing a comparison result with the upper limit voltage and a lower limit side comparison result showing a comparison result with the lower limit voltage,
The counter includes a front stage counter and a rear stage counter,
The selection unit,
A pre-stage selector that selects one of the upper limit side comparison result and the lower limit side comparison result and the reference signal comparison result and supplies the reference signal comparison result to the pre-stage counter,
The solid-state imaging device according to claim 5, further comprising a rear stage selector that selects one of the other one of the upper limit side comparison result and the lower limit side comparison result and an output bit of the front stage counter and supplies the selected output bit to the rear stage counter.
The solid-state image sensor according to claim 6, wherein the counter further includes a preliminary counter.
The preliminary counter counts a count value based on the output bits of the latter-stage counter,
The solid-state imaging device according to claim 7, further comprising a switch that opens and closes a path between the latter stage selector and the preliminary counter.
The solid-state imaging device according to claim 7, wherein the spare counter is inserted between the preceding stage selector and the reference signal comparison unit.
A control circuit for supplying a predetermined threshold,
The counting unit,
A counter that counts the count value each time the voltage comparison result indicating that the analog signal is outside the voltage range is output,
The solid-state image sensor according to claim 1, further comprising a threshold value comparison unit that compares the count value with the threshold value.
The predetermined voltage includes an upper limit voltage indicating an upper limit of the voltage range and a lower limit voltage indicating a lower limit of the voltage range,
The counter is
When the voltage comparison result indicating that the analog signal is higher than the upper limit voltage is output, one of increment processing and decrement processing is performed on the count value, and the analog signal is lower than the lower limit voltage. 11. The solid-state image sensor according to claim 10, wherein when the voltage comparison result indicating is output, the other one of the increment process and the decrement process is performed on the count value.
The predetermined voltage is a variable voltage that fluctuates to either an upper limit voltage or a lower limit voltage different from each other,
The solid-state image sensor according to claim 11, wherein the counter performs one of the increment processing and the decrement processing based on a polarity signal indicating the value of the variable voltage and the voltage comparison result.
The voltage comparison unit is arranged in each of a plurality of pixels,
The counting unit is arranged in a pixel block in which the plurality of pixels are arranged,
The counting unit,
A comparison result processing unit that processes the voltage comparison result corresponding to each of the plurality of pixels;
The solid-state imaging device according to claim 1, further comprising a counter that counts the count value based on a processing result of the comparison result processing unit.
The predetermined voltage is a variable voltage that fluctuates to either an upper limit voltage or a lower limit voltage different from each other,
The comparison result processing unit,
An upper limit side comparison result processing unit that processes the voltage comparison result corresponding to the upper limit voltage,
A lower limit side comparison result processing unit that processes the voltage comparison result corresponding to the lower limit voltage,
The counting unit,
An upper limit switch that opens and closes a path between the voltage comparison unit and the upper limit comparison result processing unit according to a polarity signal indicating the value of the variable voltage,
14. The solid-state imaging device according to claim 13, further comprising: a lower limit switch that opens and closes a path between the voltage comparison unit and the lower limit comparison result processing unit according to the polarity signal.
14. The solid-state imaging device according to claim 13, wherein the comparison result processing unit outputs an exclusive OR of the voltage comparison results corresponding to each of the plurality of pixels as the processing result.
The solid-state image sensor according to claim 13, wherein the comparison result processing unit outputs a logical sum of the voltage comparison results corresponding to each of the plurality of pixels as the processing result.
14. The solid-state image sensor according to claim 13, wherein the comparison result processing section selects one of the voltage comparison results corresponding to each of the plurality of pixels and outputs the selected result as the processing result.
The voltage comparison unit,
A current-voltage converter that converts photocurrent into a voltage signal,
A differentiating circuit for differentiating the voltage signal and outputting it as the analog signal;
The solid-state image sensor according to claim 1, further comprising a comparator that compares the analog signal with the predetermined voltage.
The solid-state imaging device according to claim 18, further comprising an initialization control unit that controls the differentiating circuit each time the count value is counted to set the analog signal to a predetermined initial value.
The solid-state imaging device according to claim 1, further comprising a transfer unit that transfers a signal indicating a result of comparison between the count value and a predetermined threshold value and initializes the count value after transferring the signal.