JP2020126396A - Constant voltage power source circuit and semiconductor device comprising the same - Google Patents

Abstract

To provide a constant voltage power source circuit which can prevent an output voltage from varying due to a pseudo load current.SOLUTION: A constant voltage power source circuit 1 comprises a pseudo load circuit 12 which generates a monitor current I5 with a value corresponding to a current I1 flowing in an output transistor P1 and causes a pseudo load current I3 with a value corresponding to difference between a bias current IB with a fixed value and the monitor current I5 to flow out from an output terminal T3. Consequently, an output voltage VO can be prevented from varying due to the pseudo load current I3 because the pseudo load current I3 continuously linearly varies.SELECTED DRAWING: Figure 1

Description

The present invention relates to a constant voltage power supply circuit and a semiconductor device including the same.

For example, Japanese Patent Laid-Open No. 2015-230585 discloses an output transistor that outputs a current having a value corresponding to a control voltage to an output terminal, and a voltage divider that divides the voltage of the output terminal to generate a monitor voltage. , An operational amplifier that outputs the control voltage so that the monitor voltage becomes the reference voltage, and if the control voltage is higher than the threshold voltage, the pseudo load current of a constant value flows out from the output terminal, and the control voltage becomes the threshold voltage. There is disclosed a constant voltage power supply circuit including a pseudo load circuit that cuts off a pseudo load current when the voltage is lower than the voltage.

JP, 2015-230585, A

However, in Patent Document 1, since the pseudo load current having a constant value is caused to flow out or cut off, there is a problem that the output voltage varies due to the pseudo load current.

Therefore, a main object of the present disclosure is to provide a constant voltage power supply circuit capable of preventing the output voltage from varying due to a pseudo load current, and a semiconductor device including the constant voltage power supply circuit.

The constant voltage power supply circuit according to the present invention includes an output transistor, a voltage divider, an operational amplifier, and a pseudo load circuit. The output transistor outputs a current having a value corresponding to the control voltage to the output terminal. The voltage divider divides the voltage at the output terminal to generate a monitor voltage. The operational amplification outputs the control voltage so that the monitor voltage becomes the reference voltage. The pseudo load circuit generates a monitor current having a value corresponding to the current flowing through the output transistor, and causes a pseudo load current having a value corresponding to the difference between the bias current having a predetermined value and the monitor current to flow out from the output terminal.

In the constant voltage power supply circuit according to the present invention, a monitor current having a value corresponding to the current flowing through the output transistor is generated, and a pseudo load current having a value corresponding to the difference between the bias current having a predetermined value and the monitor current is output. Let it flow out from the terminal. Therefore, since the pseudo load current continuously and linearly changes, it is possible to prevent the output voltage from changing due to the pseudo load current.

FIG. 3 is a circuit diagram showing the configuration of the semiconductor device according to the first embodiment. FIG. 3 is a diagram showing an operation of the semiconductor device shown in FIG. 1. 3 is a time chart showing the operation of the semiconductor device shown in FIG. 1. 6 is another time chart showing the operation of the semiconductor device shown in FIG. 1. 7 is a circuit diagram showing a comparative example of the first embodiment. FIG. 6 is a time chart showing the operation of the semiconductor device shown in FIG. 6 is another time chart showing the operation of the semiconductor device shown in FIG. 7 is a circuit diagram showing a modification of the first embodiment. FIG. 7 is a circuit diagram showing another modification of the first embodiment. FIG. FIG. 9 is a circuit diagram showing a configuration of a semiconductor device according to a second embodiment. FIG. 9 is a circuit diagram showing a modified example of the second embodiment.

Embodiment 1.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor device 1 according to the first embodiment. In FIG. 1, a semiconductor device 1 is formed on the surface of a semiconductor substrate (not shown) such as a silicon chip, and has a power supply terminal T1, a ground terminal T2, an output terminal T3, a reference voltage source 2, a constant voltage power supply circuit 3, A load capacity 4 and a load 5 are provided. The reference voltage source 2, the load capacitance 4, and the load 5 may be separately provided outside the semiconductor device 1.

The power supply terminal T1 receives a power supply voltage VDD (first power supply voltage) from the outside. The ground terminal T2 receives a ground voltage GND (second power supply voltage) from the outside. The semiconductor device 1 is driven by the power supply voltage VDD and the ground voltage GND.

The reference voltage source 2 generates a reference voltage VR1. The constant voltage power supply circuit 3 outputs a constant DC voltage VO having a value corresponding to the reference voltage VR1 to the output terminal T3. The load capacitance 4 is connected between the output terminal T3 and the ground voltage GND line, and is charged to the output voltage VO of the constant voltage power supply circuit 3. The load 5 is connected between the output terminal T3 and the line of the ground voltage GND and is driven by the output voltage VO of the constant voltage power supply circuit 3. The consumption current IL of the load 5 changes.

The constant voltage power supply circuit 3 includes an output transistor P1, a voltage divider 10, an operational amplifier 11, and a pseudo load circuit 12. The output transistor P1 is a P-channel field effect transistor. The source (one main electrode) of the output transistor P1 receives the power supply voltage VDD, its gate (control electrode) receives the output voltage VC of the operational amplifier 11, and its drain (other main electrode) is connected to the output terminal T3. The output transistor P1 causes the current I1 having a value corresponding to the control voltage VC to flow from the line of the power supply voltage VDD to the output terminal T3.

The voltage divider 10 includes resistance elements 10a and 10b connected in series between the output terminal T3 and the line of the ground voltage GND, and divides the output voltage VO to generate the monitor voltage VM. When the resistance values of the resistance elements 10a and 10b are R1 and R2, respectively, VM=VO×R2/(R1+R2). The current I2 flowing through the voltage divider 10 is I2=VO/(R1+R2).

The inverting input terminal (-terminal) of the operational amplifier 11 receives the reference voltage VR1 from the reference voltage source 2, its non-inverting input terminal (+ terminal) receives the monitor voltage VM from the voltage divider 10, and its output terminal outputs. It is connected to the gate of the transistor P1.

The operational amplifier 11 controls the value of the control voltage VC, that is, the current I1 flowing through the output transistor P1 so that the monitor voltage VM becomes the reference voltage VR1. Therefore, the output voltage VO of the constant voltage power supply circuit 3 is VO=VR1×(R1+R2)/R2.

The pseudo load circuit 12 causes the pseudo load current I3 having a value corresponding to the control voltage VC to flow from the output terminal T3 to the ground voltage GND line. That is, the pseudo load circuit 12 includes a P-channel field effect transistor P2 (first current source, first transistor of first conductivity type), N-channel field effect transistors Q1 to Q4 (second conductivity type). Second to fifth transistors), and a current source 13 (second current source).

The source of the transistor P2 is connected to the line of the power supply voltage VDD, the gate thereof receives the control voltage VC from the operational amplifier 11, and the drain thereof is connected to the node N1. The transistors P1 and P2 have the same characteristics, but the transistors P1 and P2 have different sizes. The ratio of the gate width W to the gate length L of the output transistor P1 (hereinafter referred to as W/L) is A1 times the W/L of the transistor P2. However, A1 is a positive real number.

Therefore, a current (control current) I4=I1/A1 of 1/A1 of the current I1 flowing through the output transistor P1 flows through the transistor P2. The current source 13 is connected between the line of the power supply voltage VDD and the node N2, and flows a bias current IB having a predetermined constant value.

The drain and gate of the transistor Q1 are connected to the node N1, and the source thereof is connected to the line of the ground voltage GND. The transistor Q2 has a drain connected to the node N2, a gate connected to the node N1, and a source connected to the ground voltage GND line.

The transistors Q1 and Q2 have the same characteristics, but the transistors Q1 and Q2 have different sizes. The W/L of the transistor Q2 is A2 times the W/L of the transistor Q1. However, A2 is a positive real number.

Since the transistors P2 and Q1 are connected in series, the same current I4=I1/A1 flows through the transistors P2 and Q1. Since the gates of the transistors Q1 and Q2 are connected to each other and the W/L of the transistor Q2 is A2 times the W/L of the transistor Q1, the transistor Q2 has a current A4 times the current I4 flowing through the transistor Q1 (monitor current). ) I5=I1×A2/A1 flows.

Transistors Q1 and Q2 have a current mirror circuit CM1 (first current I1=A1/A1 times A2 times current I5=I1×A2/A1 received from node N1) flowing from node N2 to the ground voltage GND line (first current Mirror circuit).

The drain and gate of the transistor Q3 are connected to the node N2, and the source thereof is connected to the line of the ground voltage GND. The drain of the transistor Q4 is connected to the output terminal T3, its gate is connected to the node N2, and its source is connected to the line of the ground voltage GND.

The transistors Q3 and Q4 have the same characteristics, but the transistors Q3 and Q4 have different sizes. The W/L of the transistor Q3 is A3 times the W/L of the transistor Q2. However, A3 is a positive real number.

When IB>I5=I1×A2/A1, a current I6=IB−I1×A2/A1 which is a difference between the bias current IB and a current I5=I1×A2/A1 flowing in the transistor Q2 flows in the transistor Q3. .. Since the gates of the transistors Q3 and Q4 are connected to each other and the W/L of the transistor Q4 is A2 times the W/L of the transistor Q3, the transistor Q4 has a pseudo load current I3=A3 times the current I6 flowing through the transistor Q3. I6*A3=(IB-I1*A2/A1)*A3 flows.

Transistors Q3 and Q4 receive a pseudo load current I3=(IB-I1*A2/A1)*A3, which is A3 times the current I6=IB-I1*A2/A1 received from node N2, from output terminal T3 to ground voltage GND. The current mirror circuit CM2 (second current mirror circuit) that flows in the line is formed.

When IB≦I5=I1×A2/A1, all the bias current IB flows through the transistor Q2 and no current flows through the transistor Q3. Therefore, the pseudo load current I3 becomes 0A.

In the above description, in each transistor, the current flowing between the gate electrode and the other electrode (source electrode, etc.) and the current flowing between the body electrode and the other electrode (source electrode, etc.) are ignored. The current flowing through the transistor is a current flowing between the source and the drain of the transistor.

However, even if a current flows between the gate electrode and another electrode (source electrode, etc.), or a current flows between the body electrode and another electrode (source electrode, etc.), that is the constant voltage power supply circuit. The effect on the operation of 3 is small.

As described above, when IB≦I1×A2/A1, I3=0A. When IB≦I1×A2/A1 is modified, IL≧IB×A1/A2-VO/(R1+R2). Letting IB×A1/A2-VO/(R1+R2) be the threshold current Ith, I3=0A when IL≧Ith, and the pseudo load when the load current IL is equal to or greater than the threshold current Ith. The current I3 becomes 0A.

When IL<Ith, I3=IB*A3-I1*A2*A3/A1. As can be seen from this formula, when the load current IL is smaller than the threshold current Ith, the pseudo load current I3 decreases from IB×A3 to 0A in proportion to the current I1 flowing through the output transistor P1. In other words, the pseudo load current I3 increases as the current I1 flowing through the output transistor P1 decreases, and I3 and I2 have a linear relationship. In this case, each of the transistors P1, P2, Q1 to Q4 operates in the saturation region.

Further, by substituting I1=IL+I3+VO/(R1+R2) into this equation, the following equation (1) is obtained.
I3=(IB*A1/A2-VO/(R1+R2)-IL)*K...(1)
However, K=A2×A3/(A1+A2×A3).

Therefore, the pseudo load current I3 increases as the load current IL decreases, so that the current I1 flowing through the output transistor P1 does not decrease and the operation of the constant voltage power supply circuit 3 does not become unstable even when the load current IL is small. .. Therefore, the constant voltage power supply circuit 3 operates stably regardless of the magnitude of the load current IL.

2A to 2C are diagrams showing the operation of the semiconductor device 1 shown in FIG. 2A shows the relationship between the load current IL and the control voltage VC, FIG. 2B shows the relationship between the load current IL and the current I1 flowing through the output transistor P1, and FIG. 2C shows the load. The relationship between the current IL and the pseudo load current I3 is shown.

In FIGS. 2A to 2C, ILmin is the minimum value of the load current IL that is designed, and ILmax is the maximum value of the load current IL that is designed. That is, the range of values that the load current IL can take is from ILmin to ILmax.

As shown in FIG. 2C, the pseudo load current I3 has a maximum value when IL=ILmin, decreases linearly as the load current IL increases, and has a minimum value (0A) when IL=Ith. Become. The slope in the range where the pseudo load current I3 linearly decreases is −K=−A2×A3/(A1+A2×A3), as can be seen from the equation (1).

The current I1 flowing through the output transistor P1 increases as the load current IL increases, as shown in FIG. Assuming that there is no pseudo load circuit 12, I1 in the range of IL<Ith is shown by a dotted line.

When there is no pseudo load circuit 12 and I1 is small, the poles and zeros are located at the lower frequency side, and the operation of the constant voltage power supply circuit 3 becomes unstable. The current that becomes the boundary is defined as IS. That is, when the current I1 is smaller than IS, the operation of the constant voltage power supply circuit 3 becomes unstable. I1 indicated by the dotted line has a portion smaller than IS, and the constant voltage power supply circuit 3 becomes unstable at that portion.

On the other hand, when the pseudo load circuit 12 is provided, the pseudo load current I3 flows in the range where the load current IL is small, so the current I1 does not become smaller than IS as shown by the solid line. Therefore, the constant voltage power supply circuit 3 always operates stably.

Here, a method of determining A1, A2, and A3 will be described. Since it is necessary to supply the load current IL as the output transistor P1, a large-sized transistor is usually used. On the other hand, since the transistor P2 is not directly connected to the load 5 and does not need to flow a large current, the current I4 flowing through the transistors P2 and Q1 can be increased by increasing A1 and decreasing the size of the transistor P2. To reduce power consumption.

Since the magnitude of the pseudo load current I3 is determined by the magnitude of the load current IL as described above, the stability of the constant voltage power supply circuit 3 can be improved even if the pseudo load current I3 is 0 A by decreasing A1 or increasing A2. In a range in which the load current IL is sufficiently large, the pseudo load current I3 can be set to 0 A to suppress the power consumption. A1, A2, and A3 may be determined so that the current I1 having a magnitude such that the constant voltage power supply circuit 3 operates stably in the assumed range ILmin to ILmax of the load current IL flows through the output transistor 1.

So far, the steady operation of the constant voltage power supply circuit 3 has been described, but next, the transient operation when the load current IL changes with time and transits between the above two states (IL<Ith, IL>Ith) will be described. To do. 3A to 3E are time charts showing the operation of the semiconductor device 1 shown in FIG.

3A shows the waveform of the load current IL, FIG. 3B shows the waveform of the control voltage VC, FIG. 3C shows the waveform of the current I1 flowing through the output transistor P1, and FIG. 3D shows the waveform of the pseudo load current I3, and FIG. 3E shows the waveform of the output voltage VO. 3A to 3E show the operation of the semiconductor device 1 when the load current IL decreases.

At times t0 to t1, the load current IL is maintained at the maximum value ILmax, and the other voltages VC and VO and the currents I1 and I3 are also maintained at constant values. Since the load current IL is larger than the threshold current Ith, the pseudo load current I3 is 0A.

At time t1, the load current IL begins to decrease, at time t2 the load current IL reaches the threshold current Ith, at time t3 the load current IL reaches the minimum value ILmin, and after time t3, IL=ILmin.

At times t1 to t2, since IL>Ith, the pseudo load current I3 is maintained at 0A. As the load current IL decreases, the current I1 flowing through the output transistor P1 decreases and the control voltage VC increases.

From time t2 to t3, IL<Ith, and the pseudo load current I3 increases with a constant gradient as the load current IL decreases. Since I1=I2+I3+IL, the slope of I1 becomes smaller and the slope of VC becomes smaller. After time t3, the load current IL is maintained at the minimum value ILmin, the pseudo load current I3 is maintained at the maximum value, and the other voltages VC, VO and the current I1 are also maintained at constant values. The maximum value of the pseudo load current I3 is a value where IL=ILmin in the above formula (1).

As can be seen from FIGS. 3A to 3E, even if the load current IL decreases from the maximum value ILmax to the minimum value ILmin, the pseudo load current I3 changes gently, so the output voltage VO does not change, It is maintained at a constant value.

4A to 4E are other time charts showing the operation of the semiconductor device 1 shown in FIG. In particular, FIG. 4A shows the waveform of the load current IL, FIG. 4B shows the waveform of the control voltage VC, FIG. 4C shows the waveform of the current I1 flowing through the output transistor P1, and FIG. 4D shows the waveform of the pseudo load current I3, and FIG. 4E shows the waveform of the output voltage VO. 4A to 4E show the operation of the semiconductor device 1 when the load current IL increases.

From time t0 to t1, the load current IL is maintained at the minimum value ILmin, and the other voltages VC and VO and the currents I1 and I3 are also maintained at constant values. Since the load current IL is smaller than the threshold current Ith, the pseudo load current I3 has a constant value.

The load current IL starts to increase at time t1, reaches the threshold current Ith at time t2, the load current IL reaches the maximum value ILmax at time t3, and IL=ILmax after time t3.

From time t1 to t2, since IL<Ith, the pseudo load current I3 linearly decreases with a constant slope as the load current IL increases. As the load current IL increases, the current I1 flowing through the output transistor P1 increases and the control voltage VC decreases.

From time t2 to t3, IL>Ith, and the pseudo load current I3 is maintained at 0A. Since I1=I2+I3+IL, the slope of I1 becomes large and the slope of VC becomes large. After time t3, the load current IL is maintained at the maximum value ILmax, the pseudo load current I3 is maintained at 0A, and the other voltages VC, VO and the current I1 are also maintained at constant values.

As can be seen from FIGS. 4A to 4E, even if the load current IL increases from the minimum value ILmin to the maximum value ILmax, the pseudo load current I3 changes gently, so the output voltage VO does not change, It is maintained at a constant value.

As described above, in the first embodiment, the monitor current I5 having a value corresponding to the current I1 flowing through the output transistor P1 is generated, and the pseudo current having a value corresponding to the difference between the constant bias current IB and the monitor current I5 is generated. A load current I3 is passed. Therefore, even if the load current IL changes, the pseudo load current I3 continuously changes in proportion to the load current IL, so that the pseudo load current I3 can prevent the output voltage VO from changing.

Further, as described above, the power consumption of the constant voltage power supply circuit 3 can be suppressed by adjusting the W/L ratios A1, A2, A3 of the transistors P1, P2, Q1 to Q4.

Comparative example.
Next, a comparative example of the first embodiment will be described in order to clarify the effect of the first embodiment. FIG. 5 is a circuit diagram showing a modification of the first embodiment and is a diagram to be compared with FIG. 1. Referring to FIG. 5, semiconductor device 30 is different from semiconductor device 1 of FIG. 1 in that constant voltage power supply circuit 3 is replaced with constant voltage power supply circuit 31. The constant voltage power supply circuit 31 is obtained by replacing the pseudo load circuit 12 of the constant voltage power supply circuit 3 with the pseudo load circuit 32.

The pseudo load circuit 32 includes a voltage source 33, an operational amplifier 34, a resistance element 35, and an N-channel field effect transistor Q5. The voltage source 33 generates the reference voltage VR2. The operational amplifier 34 has a hysteresis characteristic, generates two threshold voltages VTL and VTH based on the reference voltage VR2, compares the threshold voltages VTL and VTH with the control voltage VC, and compares the results. Is output. However, VTL<VTH.

When control voltage VC rises and control voltage VC exceeds threshold voltage VTH, signal φ34 attains the "L" level. When control voltage VC drops and control voltage VC drops below threshold voltage VTL, signal φ34 attains the "H" level.

The drain of the transistor Q5 is connected to the output terminal T3 via the resistance element 35, the gate thereof receives the output signal φ34 of the operational amplifier 34, and the source thereof is connected to the line of the ground voltage GND. Since the other structure is the same as that of semiconductor device 1, the description thereof will not be repeated.

Next, the operation of the semiconductor device 30 will be described. When the load current IL decreases, the current I1 flowing through the output transistor P1 decreases and the control voltage VC increases. When the control voltage VC exceeds the threshold voltage VTH, the output signal φ34 of the operational amplifier 34 becomes "H" level, the transistor Q5 is turned on, and the pseudo load current I3 having a constant value IC flows. When the resistance value of the resistance element 35 is R3, the constant value IC is IC=VO/R3.

Conversely, when the load current IL increases, the current I1 flowing through the output transistor P1 increases and the control voltage VC decreases. When the control voltage VC becomes lower than the threshold voltage VTL, the output signal φ34 of the operational amplifier becomes "L" level, the transistor Q5 is turned off, and the pseudo load current I1 becomes 0A.

In the semiconductor device 30, since the pseudo load current I3 flows when the load current IL is small, it is possible to prevent the current I1 flowing through the output transistor P1 from becoming small. Therefore, the constant voltage power supply circuit 31 can be stably operated even when the load current IL is small. However, this semiconductor device 30 has a problem that the output voltage VO fluctuates when the transistor Q5 turns on and off.

FIGS. 6A to 6E are time charts showing the operation of the semiconductor device 30 shown in FIG. 5, and are diagrams to be compared with FIGS. 3A to 3E. 6A shows the waveform of the load current IL, FIG. 6B shows the waveform of the control voltage VC, FIG. 6C shows the waveform of the current I1 flowing through the output transistor P1, and FIG. 6D shows the waveform of the pseudo load current I3, and FIG. 6E shows the waveform of the output voltage VO. 6A to 6E show the operation of the semiconductor device 30 when the load current IL decreases.

From time t0 to t1, the load current IL is maintained at a relatively large value IL1, and the other voltages VC and VO and the currents I1 and I3 are also maintained at constant values. The control voltage VC has a value between the two threshold voltages VTL and VTH. A relatively large current I1 flows through the output transistor P1, the transistor Q5 is turned off, and the pseudo load current I3 is 0A.

At time t1, the load current IL begins to decrease. As the load current IL decreases, the control voltage VC increases and the current I1 flowing through the output transistor P1 decreases. At time t2, when control voltage VC reaches threshold voltage VTH, transistor Q5 turns on, and pseudo load current I3 instantaneously increases from 0A to constant value IC.

When the pseudo load current I3 instantaneously increases, the output voltage VO instantaneously decreases. The operational amplifier 11 lowers the control voltage VC in order to return the output voltage VO to the target value. When the control voltage VC decreases, the current I1 flowing through the output transistor P1 increases and the output voltage VO increases.

At time t3, the output voltage VO returns to the target value. After time t3, the load current IL is maintained at a relatively low value IL2, the pseudo load current I3 is maintained at a constant value IC, and the other voltages VC, VO and the current I1 are also maintained at constant values.

As can be seen from FIGS. 6A to 6E, in the semiconductor device 30 of the comparative example, when the load current IL decreases from IL1 to IL2 and the control voltage VC reaches the threshold voltage VTH, the transistor Q5 turns on. Then, the pseudo load current I3 suddenly flows and the output voltage VO fluctuates.

On the other hand, in the semiconductor device 1 of the first embodiment, as shown in FIGS. 3A to 3E, even if the load current IL decreases from the maximum value ILmax to the minimum value ILmin, the pseudo load current I3 Changes slowly, the output voltage VO does not fluctuate and is maintained at a constant value.

7A to 7E are other time charts showing the operation of the semiconductor device 30 shown in FIG. 5, which are compared with FIGS. 4A to 4E. In particular, FIG. 7A shows the waveform of the load current IL, FIG. 7B shows the waveform of the control voltage VC, FIG. 7C shows the waveform of the current I1 flowing through the output transistor P1, and FIG. 7D shows the waveform of the pseudo load current I3, and FIG. 7E shows the waveform of the output voltage VO. 7A to 7E show the operation of the semiconductor device 30 when the load current IL increases.

From time t0 to t1, the load current IL is maintained at a relatively small value IL3, and the other voltages VC and VO and the currents I1 and I3 are also maintained at constant values. The control voltage VC has a value between the two threshold voltages VTL and VTH. A relatively small current I1 flows through the output transistor P1, the transistor Q5 is turned on, and the pseudo load current I3 has a constant value IC.

At time t1, the load current IL starts to increase. As the load current IL increases, the control voltage VC decreases and the current I1 flowing through the output transistor P1 increases. At time t2, when the control voltage VC reaches the threshold voltage VTL, the transistor Q5 is turned off and the pseudo load current I3 instantaneously decreases from the constant value IC to 0A.

When the pseudo load current I3 instantaneously decreases, the output voltage VO instantaneously increases. The operational amplifier 11 raises the control voltage VC in order to return the output voltage VO to the target value. When the control voltage VC increases, the current I1 flowing through the output transistor P1 decreases and the output voltage VO decreases.

At time t3, the output voltage VO returns to the target value. After time t3, the load current IL is maintained at a relatively large value IL4, the pseudo load current I3 is maintained at 0 A, and the other voltages VC, VO and the current I1 are also maintained at constant values.

As seen from FIGS. 7A to 7E, in the semiconductor device 30 of the comparative example, when the load current IL increases from IL3 to IL4 and the control voltage VC reaches the threshold voltage VTL, the transistor Q5 is turned off. Then, the pseudo load current I3 suddenly decreases and the output voltage VO fluctuates.

On the other hand, in the semiconductor device 1 of the first embodiment, as shown in FIGS. 4A to 4E, even if the load current IL increases from the minimum value ILmin to the maximum value ILmax, the pseudo load current I3 Changes slowly, the output voltage VO does not fluctuate and is maintained at a constant value.

Modification example 1.
FIG. 8 is a circuit diagram showing a first modification of the first embodiment and is a diagram to be compared with FIG. 1. Referring to FIG. 8, semiconductor device 1A differs from semiconductor device 1 of FIG. 1 in that constant voltage power supply circuit 3 is replaced with constant voltage power supply circuit 3A, and current source 13 is provided outside constant voltage power supply circuit 3A. It is a point provided. The constant voltage power supply circuit 3A is obtained by replacing the pseudo load circuit 12 of the constant voltage power supply circuit 3 with the pseudo load circuit 12A.

The pseudo load circuit 12A is obtained by removing the current source 13 from the pseudo load circuit 12, and includes transistors P2, Q1 to Q4. The current source 13 supplies the bias current IB from the outside of the constant voltage power supply circuit 3A to the node N2 (the drains of the transistors Q2 and Q3) in the pseudo load circuit 12A. The same effect as in the first embodiment can be obtained in the first modification.

Modification example 2.
FIG. 9 is a circuit diagram showing another modification 2 of the first embodiment and is a diagram to be compared with FIG. 1. Referring to FIG. 9, semiconductor device 1B differs from semiconductor device 1 of FIG. 1 in that constant voltage power supply circuit 3 is replaced with constant voltage power supply circuit 3B. The constant voltage power supply circuit 3B differs from the constant voltage power supply circuit 3 in that the output transistor P1 is replaced by the output transistor Q6 and the pseudo load circuit 12 is replaced by the pseudo load circuit 12B.

The output transistor P1 is a P-channel field effect transistor (first conductivity type transistor), while the output transistor Q6 is an N-channel field effect transistor (second conductivity type transistor). The drain of the output transistor Q6 is connected to the line of the power supply voltage VDD, the source thereof is connected to the output terminal T3, and the gate thereof receives the control voltage VC.

The non-inverting input terminal of the operational amplifier 11 receives the reference voltage VR1, its inverting input terminal receives the monitor voltage, and its output terminal is connected to the gate of the output transistor Q6. The operational amplifier 11 generates the control voltage VC and controls the current I1 flowing through the output transistor Q6 so that the monitor voltage VM becomes the reference voltage VR1.

The pseudo load circuit 12B is obtained by replacing the transistor P2 of the pseudo load circuit 12 with a transistor Q7. Transistor Q7 is an N-channel field effect transistor, the drain thereof is connected to the line of power supply voltage VDD, the gate thereof receives control voltage VC, and the source thereof is connected to node N1.

The transistors Q6 and Q7 have the same characteristics, but the transistors Q6 and Q7 have different sizes. The W/L of the output transistor Q6 is A1 times the W/L of the transistor Q7. However, A1 is a positive real number. Therefore, a current I4=I1/A1 which is 1/A1 of the current I1 flowing through the transistor Q6 flows through the transistor Q7.

Other configurations and operations are the same as those in the first embodiment, and therefore description thereof will not be repeated. Also in the second modification, the same effect as that of the first embodiment can be obtained.

Embodiment 2.
FIG. 10 is a circuit diagram showing a configuration of semiconductor device 1C according to the second embodiment and is a diagram to be compared with FIG. Referring to FIG. 10, semiconductor device 1C differs from semiconductor device 1 of FIG. 1 in that constant voltage power supply circuit 3 is replaced with constant voltage power supply circuit 3C. The constant voltage power supply circuit 3C is obtained by replacing the pseudo load circuit 12 of the constant voltage power supply circuit 3 with the pseudo load circuit 12C.

The pseudo load circuit 12C is obtained by replacing the current mirror circuits CM1 and CM2 of the pseudo load circuit 12 with cascode current mirror circuits CM3 and CM4, respectively. The cascode current mirror circuit CM3 includes N-channel field effect transistors Q1, Q2, Q11, Q12. The transistors Q1 and Q2 are as described in FIG. The transistors Q1 and Q11 have the same size and characteristics, and the transistors Q2 and Q12 have the same size and characteristics.

The drain and gate of the transistor Q11 are connected to the node N1, and the source thereof is connected to the drain and gate of the transistor Q1. The drain of the transistor Q12 is connected to the node N2, its gate is connected to the node N1, and its source is connected to the drain of the transistor Q2.

Similar to the current mirror circuit CM1 (FIG. 1), the cascode current mirror circuit CM3 supplies the current I4=I1/A1 times A2 times the current I4=I1/A1/A1 received from the node N1, and the ground voltage GND from the node N2. On the line.

The drain and gate of the transistor Q13 are connected to the node N2, and the source thereof is connected to the drain and gate of the transistor Q3. The drain of the transistor Q14 is connected to the output terminal T3, its gate is connected to the node N2, and its source is connected to the drain of the transistor Q4.

The cascode current mirror circuit CM4, like the current mirror circuit CM2 (FIG. 1), has a pseudo load current I3=(IB-I1×A2/A1 times the current I6=IB−I1×A2/A1 received from the node N2. A1)×A3 flows from the output terminal T3 to the line of the ground voltage GND.

Other configurations and operations are the same as those in the first embodiment, and therefore description thereof will not be repeated. Also in this second embodiment, the same effect as in the first embodiment can be obtained. Since the cascode current mirror circuits CM3 and CM4 are provided, the influence of the channel length modulation of the transistors Q1 to Q4 can be reduced, and the pseudo load current I3 can be controlled with high accuracy. Therefore, the pseudo load current I3 can be prevented from unnecessarily increasing, and the power consumption can be reduced.

In the second embodiment, both the current mirror circuits CM1 and CM2 are replaced with the cascode current mirror circuit. However, the present invention is not limited to this, and only one of the current mirror circuits CM1 and CM2 is cascode current. It may be replaced with a mirror circuit.

FIG. 11 is a circuit diagram showing a modified example of the second embodiment, which is compared with FIG. 10. Referring to FIG. 11, the semiconductor device 1D of this modification is different from semiconductor device 1C of FIG. 10 in that constant voltage power supply circuit 3C is replaced with constant voltage power supply circuit 3D. The constant voltage power supply circuit 3D is obtained by replacing the pseudo load circuit 12C of the constant voltage power supply circuit 3C with the pseudo load circuit 12D.

The pseudo load circuit 12D is obtained by replacing the current mirror circuits CM3 and CM4 of the pseudo load circuit 12C with low voltage cascode current mirror circuits CM5 and CM6, respectively. The low-voltage cascode current mirror circuit CM5 applies a bias voltage VB1 to the gates of the transistors Q11 and Q12 of the cascode current mirror circuit CM3 and connects the gates of the transistors Q1 and Q2 to the node N1.

The low voltage cascode current mirror circuit CM6 is a circuit in which the bias voltage VB2 is applied to the gates of the transistors Q13 and Q14 of the cascode current mirror circuit CM4 and the gates of the transistors Q3 and Q4 are connected to the node N2. The voltage source that generates the bias voltages VB1 and VB2 may be provided inside the pseudo load circuit 12D or may be provided outside the pseudo load circuit 12D.

The low-voltage cascode current mirror circuit CM5, like the cascode current mirror circuit CM3 (FIG. 10), supplies a current I5=I1×A2/A1 that is A2 times the current I4=I1/A1 received from the node N1, from the node N2. It flows to the line of the ground voltage GND.

The low-voltage cascode current mirror circuit CM6, like the cascode current mirror circuit CM4 (FIG. 10), has a pseudo load current I3=(IB-I1) which is a current I6 received from the node N2=IB-I1×A2/A1. XA2/A1)xA3 is caused to flow from the output terminal T3 to the line of the ground voltage GND.

Other configurations and operations are the same as those in the second embodiment, and therefore description thereof will not be repeated. Also in this modification, the same effect as that of the second embodiment can be obtained. Further, since the low voltage cascode current mirror circuits CM5 and CM6 are provided, the operating voltage VDD can be reduced.

In this modification, both the current mirror circuits CM1 and CM2 are replaced with the low-voltage cascode current mirror circuit, but the present invention is not limited to this, and only one of the current mirror circuits CM1 and CM2 has the low voltage. It may be replaced with a cascode current mirror circuit. Further, the current mirror circuits CM1 and CM2 may be replaced with a current mirror circuit having any configuration.

Further, the first embodiment and its modification examples 1 and 2 may be combined with the second embodiment and its modification examples as appropriate.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The present invention is shown not by the above description but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

1, 1A to 1D, 30 semiconductor device, T1 power supply terminal, T2 ground terminal, T3 output terminal, 2, 33 reference voltage source, 3, 3A to 3D, 31 constant voltage power supply circuit, 4 load capacity, 5 load, P1, Q6 output transistor, 10 voltage divider, 10a, 10b resistance element, 11, 34 operational amplifier, 12, 12A to 12D, 32 pseudo load circuit, 13 current source, P2 P channel type field effect transistor, Q1 to Q5, Q7, Q11 -Q14 N-channel field effect transistor, CM1, CM2 current mirror circuit, CM3, CM4 cascode current mirror circuit, CM5, CM6 low voltage cascode current mirror circuit.

Claims (11)

An output transistor that outputs a current of a value according to the control voltage to the output terminal,
A voltage divider that divides the voltage at the output terminal to generate a monitor voltage,
An operational amplifier that outputs the control voltage so that the monitor voltage becomes a reference voltage;
A pseudo load circuit which generates a monitor current having a value corresponding to the current flowing through the output transistor and causes a pseudo load current having a value corresponding to a difference between a bias current having a predetermined value and the monitor current to flow out from the output terminal. And a constant voltage power supply circuit. When the monitor current is smaller than the bias current, the pseudo load current decreases in proportion to the monitor current,
The constant voltage power supply circuit according to claim 1, wherein the pseudo load current is 0 A when the monitor current is larger than the bias current. The output transistor is connected between a line of a first power supply voltage and the output terminal,
The voltage divider is connected between the output terminal and a line of a second power supply voltage lower than the first power supply voltage,
The constant voltage power supply circuit according to claim 1, wherein the pseudo load circuit causes the pseudo load current to flow from the output terminal to the line of the second power supply voltage. The pseudo load circuit is
A first current source that generates a control current having a value according to the control voltage;
A line connected to a first node receiving the control current and a second node receiving the bias current, and supplying the monitor current having a value corresponding to the control current from the second node to the second power supply voltage line. A first current mirror circuit that flows to
A second node connected to the second node and the output terminal, which allows the pseudo load current having a value corresponding to a difference between the bias current and the monitor current to flow from the output terminal to the line of the second power supply voltage. The constant voltage power supply circuit according to claim 3, further comprising a current mirror circuit. The constant voltage power supply circuit according to claim 4, wherein the pseudo load circuit further includes a second current source that supplies the bias current to the second node. One main electrode of the output transistor is connected to the line of the first power supply voltage, the other main electrode is connected to the output terminal, and its control electrode receives the control voltage,
The first current source includes a first transistor,
The first current mirror circuit includes second and third transistors,
The second current mirror circuit includes fourth and fifth transistors,
One main electrode of the first transistor is connected to the line of the first power supply voltage, the other main electrode is connected to the first node, and its control electrode receives the control voltage,
One main electrodes of the second to fifth transistors are both connected to the line of the second power supply voltage,
The other main electrode and control electrode of the second transistor are connected to the first node,
The other main electrode of the third transistor is connected to the second node, and its control electrode is connected to the first node,
The other main electrode and control electrode of the fourth transistor are connected to the second node,
6. The constant voltage power supply circuit according to claim 4, wherein the other main electrode of the fifth transistor is connected to the output terminal, and the control electrode thereof is connected to the second node. The output transistor and the first transistor are of a first conductivity type,
The constant voltage power supply circuit according to claim 6, wherein the second to fifth transistors have a second conductivity type different from the first conductivity type. The constant voltage power supply circuit according to claim 6, wherein the output transistor and the first to fifth transistors have the same conductivity type. The constant voltage power supply circuit according to claim 4, wherein at least one of the first and second current mirror circuits is a cascode current mirror circuit. 6. The constant voltage power supply circuit according to claim 4, wherein at least one of the first and second current mirror circuits is a low voltage cascode current mirror circuit. A semiconductor device comprising the constant voltage power supply circuit according to claim 1.

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