JP2020119028A - Control board - Google Patents

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JP2020119028A
JP2020119028A JP2019007109A JP2019007109A JP2020119028A JP 2020119028 A JP2020119028 A JP 2020119028A JP 2019007109 A JP2019007109 A JP 2019007109A JP 2019007109 A JP2019007109 A JP 2019007109A JP 2020119028 A JP2020119028 A JP 2020119028A
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storage medium
cpu
terminal
connector
control board
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JP7151498B2 (en
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智博 金子
Tomohiro Kaneko
智博 金子
大輔 芳賀
Daisuke Haga
大輔 芳賀
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Brother Industries Ltd
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Brother Industries Ltd
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Abstract

To provide a control board capable of detecting a connected storage medium and automatically connecting the storage medium and a CPU.SOLUTION: The control board 1 includes a plurality of connectors 10 and 14 to which a plurality of storage mediums 5 and 6 are connected, one switching circuit 4 to which the plurality of connectors 10 and 14 are connected, a CPU 2 which is connected to the switching circuit 4, and a detection circuit which detects whether the storage medium 5 is connected to the connector 10. When the detection circuit detects that the storage medium 5 is connected to the connector 10, the switching circuit 4 connects the connector 10 and the CPU 2, and when it detects that the storage medium 5 is not connected to the connector 10, it connects the CPU 2 with the connector 14 which is connected to the storage medium 6.SELECTED DRAWING: Figure 2

Description

本発明は、工作機械等の産業機械に備えられる制御基板に関する。 The present invention relates to a control board provided in an industrial machine such as a machine tool.

工作機械等の産業機械の制御基板は、ＣＰＵの中にメモリを備えないものがある。この場合、制御基板に記憶媒体を接続し、記憶媒体に格納されたオペレーティングシステムによりＣＰＵを駆動する。
製品寿命が長い産業機械は、将来の製造中止に備え、複数の記憶媒体を制御基板に接続できるようにする必要がある。この場合、ＳＡＴＡ（Serial Advanced Technology Attachment）スイッチＩＣ（例えば特許文献１）により、ＣＰＵと記憶媒体との接続を切り替える。記憶媒体として、ＳＡＴＡのインタフェース規格に対応したＳＳＤ（Solid State Drive）、Ｈａｌｆ−ｓｌｉｍ ＳＳＤ、ｍＳＡＴＡ ＳＳＤ、Ｃｆａｓｔ等が挙げられる。 Some control boards of industrial machines such as machine tools do not have a memory in the CPU. In this case, a storage medium is connected to the control board, and the CPU is driven by the operating system stored in the storage medium.
Industrial machines with long product life must be able to connect multiple storage media to a control board in case of future discontinuation. In this case, the connection between the CPU and the storage medium is switched by a SATA (Serial Advanced Technology Attachment) switch IC (for example, Patent Document 1). Examples of the storage medium include SSDs (Solid State Drives), Half-slim SSDs, mSATA SSDs, Cfast, and the like that comply with the SATA interface standard.

特開２００５−３２７２３０号公報JP, 2005-327230, A

上述の場合、起動中のＯＳ（オペレーティングシステム）を格納した記憶媒体が制御基板のコネクタから外れたとき、ＣＰＵが動かなくなるという問題がある。 In the case described above, there is a problem that the CPU does not work when the storage medium storing the operating OS (operating system) is detached from the connector of the control board.

本発明は斯かる事情に鑑みてなされたものであり、接続されている記憶媒体を検知し、自動で、記憶媒体とＣＰＵとを接続することができる制御基板を提供することを目的とする。 The present invention has been made in view of such circumstances, and an object thereof is to provide a control board that can detect a connected storage medium and can automatically connect the storage medium and the CPU.

本発明の一態様に係る制御基板は、複数の記憶媒体が接続される複数のコネクタと、該複数のコネクタが接続された一つの切替回路と、該切替回路に接続された第１ＣＰＵと、一のコネクタに一の記憶媒体が接続されたか否かを検知する検知回路とを備え、前記切替回路は、前記検知回路が前記一のコネクタに前記一の記憶媒体が接続されたことを検知した場合に、前記一のコネクタと前記第１ＣＰＵとを接続し、前記一のコネクタに前記一の記憶媒体が接続されていないことを検知した場合に、他の記憶媒体が接続されている他のコネクタと前記第１ＣＰＵとを接続する。 A control board according to one aspect of the present invention includes a plurality of connectors to which a plurality of storage media are connected, a switching circuit to which the plurality of connectors are connected, and a first CPU connected to the switching circuit. A detection circuit for detecting whether or not one storage medium is connected to the connector, and the switching circuit detects that the one storage medium is connected to the one connector. When the one connector is connected to the first CPU and it is detected that the one storage medium is not connected to the one connector, another connector is connected to another connector. The first CPU is connected.

上記構成によれば、複数の記憶媒体を制御基板に接続する場合に、制御基板に接続した記憶媒体を検知し、自動で、該記憶媒体と第１ＣＰＵとを接続できる。 According to the above configuration, when a plurality of storage media are connected to the control board, the storage media connected to the control board can be detected and the storage media and the first CPU can be automatically connected.

上述の制御基板において、前記一の記憶媒体は導線を有し、前記一のコネクタは、所定の電圧でプルアップされた第１端子、及び接地された第２端子を有し、前記検知回路は、前記一のコネクタに前記一の記憶媒体が接続されて前記導線と前記第１端子及び前記第２端子とが接続されたときに、前記第１端子におけるハイレベルからローレベルへの変化に基づいて、前記一の記憶媒体の接続を検知してもよい。 In the control board described above, the one storage medium has a conductive wire, the one connector has a first terminal pulled up by a predetermined voltage, and a second terminal grounded, and the detection circuit is , Based on a change from a high level to a low level at the first terminal when the one storage medium is connected to the one connector and the conducting wire is connected to the first terminal and the second terminal Then, the connection of the one storage medium may be detected.

上記構成によれば、記憶媒体を制御基板に接続していることを良好に、容易に検知できる。 According to the above configuration, it is possible to favorably and easily detect that the storage medium is connected to the control board.

上述の制御基板において、第３の記憶媒体が接続された第２ＣＰＵを備え、前記検知回路は検知結果を前記第２ＣＰＵへ出力し、前記第２ＣＰＵは、前記検知結果を第３の記憶媒体に保存し、外部へ出力してもよい。 The above control board includes a second CPU to which a third storage medium is connected, the detection circuit outputs the detection result to the second CPU, and the second CPU stores the detection result in the third storage medium. However, it may be output to the outside.

上記構成によれば、第２ＣＰＵにより記憶媒体の接続の切断を記憶媒体に保存し、作業者に報知し、作業者により接続し直すことができる。 According to the above configuration, the disconnection of the connection of the storage medium can be stored in the storage medium by the second CPU, the worker can be notified, and the worker can reconnect.

上述の制御基板において、前記一の記憶媒体は、前記第１ＣＰＵを動作するためのオペレーティングシステムを記憶してもよい。 In the above-mentioned control board, the one storage medium may store an operating system for operating the first CPU.

上記構成によれば、第１ＣＰＵがメモリを有さない場合でも、第１ＣＰＵを駆動できる。 According to the above configuration, even if the first CPU does not have a memory, the first CPU can be driven.

上述の制御基板において、前記複数の記憶媒体の規格は異なり、前記一の記憶媒体が前記一のコネクタに接続されている場合は、該一の記憶媒体に記憶されたオペレーティングシステムにより前記第１ＣＰＵは動作し、前記一の記憶媒体が前記一のコネクタに接続されていない場合、他のコネクタに接続されている他の記憶媒体に記憶されたオペレーティングシステムにより前記第１ＣＰＵは動作してもよい。 In the above control board, when the standards of the plurality of storage media are different and the one storage medium is connected to the one connector, the first CPU is controlled by the operating system stored in the one storage medium. When operating and the one storage medium is not connected to the one connector, the first CPU may be operated by an operating system stored in another storage medium connected to another connector.

上記構成によれば、異なる規格の記憶媒体を制御基板に接続でき、優先度が高い記憶媒体が接続されている時は該記憶媒体により第１ＣＰＵを起動し、接続していない時は優先度が低い記憶媒体により第１ＣＰＵを起動できる。 According to the above configuration, storage media of different standards can be connected to the control board, the first CPU is activated by the storage medium when a storage medium having a high priority is connected, and the priority is set when the storage medium is not connected. The low storage medium can boot the first CPU.

本発明にあっては、接続されている記憶媒体を検知し、自動で、記憶媒体とＣＰＵとを接続できる。 According to the present invention, the connected storage medium can be detected and the storage medium and the CPU can be automatically connected.

実施の形態に係る工作機械の平面図である。It is a top view of the machine tool which concerns on embodiment. 制御基板の構成を示す回路図である。It is a circuit diagram which shows the structure of a control board. 記憶媒体がコネクタから外れた状態を示す回路図である。It is a circuit diagram which shows the state which the storage medium detached from the connector. 第２ＣＰＵによる、切断の報知処理を示すフローチャートである。It is a flowchart which shows the notification process of a disconnection by a 2nd CPU. ＣｆａｓｔのＣＤＩ、ＣＤＯ信号を使わずに、記憶媒体の接続を切り替える場合の回路図である。It is a circuit diagram in the case of switching the connection of the storage medium without using the CDi and CDO signals of Cfast. 記憶媒体がコネクタから外れた状態を示す回路図である。It is a circuit diagram which shows the state which the storage medium detached from the connector.

以下、実施の形態を図面に基づいて説明する。図１は実施の形態に係る工作機械２１の平面図である。以下の説明では図に示す前後左右を使用する。
工作機械２１は、基台（図示略）と、該基台に設けた立柱２３とを備える。立柱２３は主軸ヘッド２７を上下動可能に支持する。主軸ヘッド２７は、上下方向を回転軸方向とした主軸（図示略）を回転可能に支持する。主軸ヘッド２７の上端に主軸モータ２５が設けてある。主軸は主軸モータ２５の駆動により回転する。 Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a plan view of a machine tool 21 according to the embodiment. In the following description, front, rear, left and right shown in the figure will be used.
The machine tool 21 includes a base (not shown) and a vertical column 23 provided on the base. The upright pillar 23 supports the spindle head 27 so as to be vertically movable. The main spindle head 27 rotatably supports a main spindle (not shown) whose vertical direction is the rotation axis direction. A spindle motor 25 is provided on the upper end of the spindle head 27. The main shaft is rotated by driving the main shaft motor 25.

立柱２３はタレット型の工具マガジン２６を支持する。工具マガジン２６は主軸ヘッド２７の前側に配置してある。工具マガジン２６の周囲に複数の工具が保持してある。工具マガジン２６が回転し、主軸ヘッド２７の上下動によって、主軸に対する工具の取付及び取り外しを行う。主軸の下方に左右方向及び前後方向に移動可能なテーブル２８が配置してある。テーブル２８に治具２４を設ける。治具２４はワークの保持及び保持の解除を行う。 The uprights 23 support a turret type tool magazine 26. The tool magazine 26 is arranged in front of the spindle head 27. A plurality of tools are held around the tool magazine 26. The tool magazine 26 rotates and the spindle head 27 moves up and down to attach and detach the tool to and from the spindle. A table 28 that is movable in the left-right direction and the front-back direction is arranged below the main shaft. The jig 24 is provided on the table 28. The jig 24 holds and releases the work.

工作機械２１の上側、前側、後側、右側及び左側をカバー２２が覆う。カバー２２の前面に扉３１が設けてある。扉３１の右側に、作業者の操作を受け付ける操作部３２及び画像を表示する表示部３０が設けてある。カバー２２の後側に制御装置２９が設けてある。制御装置２９は、後述する制御基板１を有する。表示部３０は後述する記憶媒体５がコネクタ１０から外れたことを検知した時に報知する。上記検知を報知する手段は表示部３０に限定されない。 A cover 22 covers the upper side, front side, rear side, right side, and left side of the machine tool 21. A door 31 is provided on the front surface of the cover 22. On the right side of the door 31, an operation unit 32 that receives an operation of an operator and a display unit 30 that displays an image are provided. A control device 29 is provided on the rear side of the cover 22. The control device 29 has a control board 1 described later. The display unit 30 gives a notification when it is detected that the storage medium 5, which will be described later, is detached from the connector 10. The means for informing the detection is not limited to the display unit 30.

図２は、制御基板１の構成を示す回路図である。
制御基板１は、第１ＣＰＵ２、第２ＣＰＵ３、スイッチＩＣ４、コネクタ１０、及び接続端子１４を備える。
第１ＣＰＵ２は、メモリを有さず、表示部３０の表示等を制御する。
第２ＣＰＵ３は工作機械２１の主軸の回転量等の数値の制御を行う。第２ＣＰＵ３には記憶媒体（第３の記憶媒体）７を接続してある。記憶媒体７としては、ＮＶＳＲＡＭ（Non-Volatile Static Random Access Memory）、フラッシュメモリ等が挙げられる。第１ＣＰＵ２と第２ＣＰＵ３は通信バス１８により接続されており、第２ＣＰＵ３の指示に基づいて第１ＣＰＵ２は表示を行う。 FIG. 2 is a circuit diagram showing the configuration of the control board 1.
The control board 1 includes a first CPU 2, a second CPU 3, a switch IC 4, a connector 10, and a connection terminal 14.
The first CPU 2 does not have a memory and controls the display of the display unit 30 and the like.
The second CPU 3 controls numerical values such as the amount of rotation of the spindle of the machine tool 21. A storage medium (third storage medium) 7 is connected to the second CPU 3. Examples of the storage medium 7 include NVSRAM (Non-Volatile Static Random Access Memory) and flash memory. The first CPU 2 and the second CPU 3 are connected by a communication bus 18, and the first CPU 2 displays based on an instruction from the second CPU 3.

スイッチＩＣ４はＳＡＴＡスイッチＩＣであり、第１端子４１、第２端子４２、第３端子４３、第４端子４４、及びスイッチ回路４５を備える。第１端子４１には、第１ＣＰＵ２が接続されている。第２端子４２には外部の記憶媒体５が、第３端子４３には記憶媒体６が接続される。第４端子４４にはスイッチ回路４５に対する切替信号が入力される。 The switch IC 4 is a SATA switch IC and includes a first terminal 41, a second terminal 42, a third terminal 43, a fourth terminal 44, and a switch circuit 45. The first CPU 2 is connected to the first terminal 41. The external storage medium 5 is connected to the second terminal 42, and the storage medium 6 is connected to the third terminal 43. A switching signal for the switch circuit 45 is input to the fourth terminal 44.

スイッチ回路４５は単極双投スイッチであり、例えばトランジスタ等から構成される。スイッチ回路４５には、第４端子４４への切替信号の入力に応じて制御信号が入力され、第２端子４２に接続した記憶媒体５と、第３端子４３に接続した記憶媒体６のいずれかを選択的に第１端子４１に接続する。 The switch circuit 45 is a single-pole double-throw switch, and is composed of, for example, a transistor. A control signal is input to the switch circuit 45 in response to the input of the switching signal to the fourth terminal 44, and either the storage medium 5 connected to the second terminal 42 or the storage medium 6 connected to the third terminal 43 is input. Are selectively connected to the first terminal 41.

記憶媒体５はＣｆａｓｔであり、記憶媒体６はＳＳＤである。
記憶媒体５は、第１端子５１、第２端子５２、第３端子５３、第１端子５１と第３端子５３とを接続する導線５４を備える。
記憶媒体６は接続端子６１を有し、接続端子６１は接続端子１４に接続する。
記憶媒体５、記憶媒体６は夫々オペレーティングシステム（ＯＳ）５５、６２を記憶しており、第１ＣＰＵ２は、接続したいずれかの記憶媒体に記憶したＯＳにより駆動する。 The storage medium 5 is Cfast and the storage medium 6 is SSD.
The storage medium 5 includes a first terminal 51, a second terminal 52, a third terminal 53, and a conducting wire 54 connecting the first terminal 51 and the third terminal 53.
The storage medium 6 has a connection terminal 61, and the connection terminal 61 is connected to the connection terminal 14.
The storage media 5 and 6 store operating systems (OS) 55 and 62, respectively, and the first CPU 2 is driven by the OS stored in any of the connected storage media.

コネクタ１０は、ＣＤＯ（Card Detect Out）端子（第１端子）１１、接続端子１２、及びＣＤＩ（Card Detect In）端子（第２端子）１３を備える。接続端子１２は第２端子４２に接続し、ＣＤＩ端子１３はグランド接続する。
一端がＣＤＯ端子１１に接続した信号線１７（検知回路）は、他端側に設けられた分岐点１７ａを介して第２ＣＰＵ３及び第４端子４４に接続する。ＣＤＯ端子１１と分岐点１７ａとの間には分岐点１７ｂが設けてあり、分岐点１７ｂにはプルアップ抵抗１６を介し、３．３Ｖの電源１５に接続する。
上述の切替信号は０Ｖ又は３．３Ｖの電圧に対応し、０Ｖに対応する切替信号が第４端子４４に入力された場合、第１端子４１と第２端子４２とを接続する制御信号がスイッチ回路４５に入力される。３．３Ｖに対応する切替信号が第４端子４４に入力された場合、第１端子４１と第３端子４３とを接続する制御信号がスイッチ回路４５に入力される。 The connector 10 includes a CDO (Card Detect Out) terminal (first terminal) 11, a connection terminal 12, and a CDI (Card Detect In) terminal (second terminal) 13. The connection terminal 12 is connected to the second terminal 42, and the CDI terminal 13 is grounded.
The signal line 17 (detection circuit) whose one end is connected to the CDO terminal 11 is connected to the second CPU 3 and the fourth terminal 44 via the branch point 17a provided on the other end side. A branch point 17b is provided between the CDO terminal 11 and the branch point 17a, and the branch point 17b is connected to a 3.3V power supply 15 via a pull-up resistor 16.
The switching signal described above corresponds to a voltage of 0V or 3.3V, and when the switching signal corresponding to 0V is input to the fourth terminal 44, the control signal that connects the first terminal 41 and the second terminal 42 is a switch. It is input to the circuit 45. When the switching signal corresponding to 3.3V is input to the fourth terminal 44, the control signal that connects the first terminal 41 and the third terminal 43 is input to the switch circuit 45.

記憶媒体５をコネクタ１０に挿入した場合、第１端子５１、第２端子５２、及び第３端子５３は夫々ＣＤＯ端子１１、接続端子１２、ＣＤＩ端子１３に接続する。信号線１７はＣＤＯ端子１１及び第１端子５１を介し導線５４の一端に接続し、導線５４の他端は第３端子５３を及びＣＤＩ端子１３を介し接地する。
スイッチＩＣ４の第４端子４４には、接地に基づく０Ｖの切替信号が入力し、スイッチ回路４５には第１端子４１と第２端子４２とを接続する制御信号が入力し、第１ＣＰＵ２と記憶媒体５とを接続する。第１ＣＰＵ２は、記憶媒体５に記憶したＯＳ５５により駆動する。 When the storage medium 5 is inserted into the connector 10, the first terminal 51, the second terminal 52, and the third terminal 53 are connected to the CDO terminal 11, the connection terminal 12, and the CDI terminal 13, respectively. The signal line 17 is connected to one end of the conducting wire 54 via the CDO terminal 11 and the first terminal 51, and the other end of the conducting wire 54 is grounded via the third terminal 53 and the CDI terminal 13.
A switch signal of 0V based on ground is input to the fourth terminal 44 of the switch IC 4, and a control signal for connecting the first terminal 41 and the second terminal 42 is input to the switch circuit 45, and the first CPU 2 and the storage medium are input. 5 is connected. The first CPU 2 is driven by the OS 55 stored in the storage medium 5.

図３は、記憶媒体５がコネクタ１０から外れた状態を示す回路図である。図中、図と同一部分は同一符号を付して詳細な説明を省略する。
記憶媒体５をコネクタ１０に挿入していない場合、第１端子５１、第２端子５２、及び第３端子５３はＣＤＯ端子１１、接続端子１２、ＣＤＩ端子１３に接続していない。信号線１７は接地せず、第４端子４４には電源１５から３．３Ｖの電圧が印加する。
スイッチＩＣ４の第４端子４４には、３．３Ｖの切替信号が入力し、スイッチ回路４５には第１端子４１と第３端子４３とを接続する制御信号が入力し、第１ＣＰＵ２と記憶媒体６を接続する。第１ＣＰＵ２は、記憶媒体６に記憶したＯＳ６２により駆動する。 FIG. 3 is a circuit diagram showing a state in which the storage medium 5 is detached from the connector 10. In the figure, the same parts as those in the figure are designated by the same reference numerals, and detailed description thereof will be omitted.
When the storage medium 5 is not inserted into the connector 10, the first terminal 51, the second terminal 52, and the third terminal 53 are not connected to the CDO terminal 11, the connection terminal 12, and the CDI terminal 13. The signal line 17 is not grounded, and a voltage of 3.3 V is applied from the power supply 15 to the fourth terminal 44.
A switching signal of 3.3V is input to the fourth terminal 44 of the switch IC 4, a control signal for connecting the first terminal 41 and the third terminal 43 is input to the switch circuit 45, and the first CPU 2 and the storage medium 6 are input. Connect. The first CPU 2 is driven by the OS 62 stored in the storage medium 6.

第２ＣＰＵ３は信号線１７を介し、記憶媒体５をコネクタ１０に挿入していないことを検知でき、接続の切断を検知した場合、作業者に報知する。
図４は、第２ＣＰＵ３による、切断の報知処理を示すフローチャートである。
第２ＣＰＵ３は、記憶媒体５と制御基板１の接続を切断したか否かを判定する（Ｓ１）。第２ＣＰＵ３は接続を切断していないと判定した場合（Ｓ１：ＮＯ）、この判定処理を繰り返す。 The second CPU 3 can detect, via the signal line 17, that the storage medium 5 is not inserted in the connector 10, and when it detects disconnection, it notifies the operator.
FIG. 4 is a flowchart showing disconnection notification processing by the second CPU 3.
The second CPU 3 determines whether or not the connection between the storage medium 5 and the control board 1 has been disconnected (S1). When the second CPU 3 determines that the connection has not been disconnected (S1: NO), this determination process is repeated.

第２ＣＰＵ３は、接続を切断したと判定した場合（Ｓ１：ＹＥＳ）、記憶媒体７に、記憶媒体５がコネクタ１０から外れたことをログとして記録し（Ｓ２）、表示部３０に切断を表示して、作業者に報知し（Ｓ３）、処理を終了する。Ｓ２は省略してもよい。尚、表示部３０に切断を表示することは、検知結果を外部へ出力する一例であり、その他制御基板１上に発光ＬＥＤを備え、該発光ＬＥＤを点灯させることでもよい。 When determining that the connection has been disconnected (S1: YES), the second CPU 3 records that the storage medium 5 is disconnected from the connector 10 as a log in the storage medium 7 (S2), and displays the disconnection on the display unit 30. Then, the operator is notified (S3), and the process is terminated. S2 may be omitted. Displaying the disconnection on the display unit 30 is an example of outputting the detection result to the outside, and other light emitting LEDs may be provided on the control board 1 and the light emitting LEDs may be turned on.

図５は、比較例であり、ＣｆａｓｔのＣＤＩ、ＣＤＯ信号を使わずに、記憶媒体の接続を切り替える場合の回路図である。図中、図２と同一部分は同一符号を付して詳細な説明を省略する。
図５の制御基板１は、スイッチ２０を有する。スイッチ２０の一方の接点はプルアップ抵抗１６を介し電源１５に接続する。スイッチ２０の他方の接点は抵抗１９を介し接地する。
手動によりスイッチ２０の他方の接点を抵抗１９を介し接地した場合、０Ｖの電圧が第４端子４４に印加し、０Ｖの切替信号に基づいてスイッチ回路４５に第１端子４１と第２端子４２とを接続する制御信号が入力し、第１ＣＰＵ２と記憶媒体５とを接続する。 FIG. 5 is a comparative example, and is a circuit diagram in the case of switching the connection of the storage medium without using the CDI and CDO signals of Cfast. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a detailed description thereof will be omitted.
The control board 1 of FIG. 5 has a switch 20. One contact of the switch 20 is connected to the power supply 15 via the pull-up resistor 16. The other contact of the switch 20 is grounded via the resistor 19.
When the other contact of the switch 20 is manually grounded via the resistor 19, a voltage of 0V is applied to the fourth terminal 44, and the switch circuit 45 is connected to the first terminal 41 and the second terminal 42 based on the 0V switching signal. A control signal for connecting is input to connect the first CPU 2 and the storage medium 5.

図６は、記憶媒体５がコネクタ１０から外れた状態を示す回路図である。図中、図２と同一部分は同一符号を付して詳細な説明を省略する。
記憶媒体５がコネクタ１０から外れた場合、第１ＣＰＵ２は、記憶媒体５に接続していないので、動かなくなる。ここで、第２ＣＰＵ３は第１ＣＰＵ２が動かない理由を判断できず、作業者に報知してスイッチ２０の接点を切り替えて記憶媒体６に接続するか、又は記憶媒体５を接続し直すように報知することができない。
実施例の場合、比較例の上述の問題は生じない。 FIG. 6 is a circuit diagram showing a state in which the storage medium 5 is detached from the connector 10. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a detailed description thereof will be omitted.
When the storage medium 5 is detached from the connector 10, the first CPU 2 does not move because it is not connected to the storage medium 5. Here, the second CPU 3 cannot determine the reason why the first CPU 2 does not move, and notifies the operator to switch the contact of the switch 20 to connect to the storage medium 6 or to reconnect the storage medium 5. I can't.
In the case of the example, the above-mentioned problems of the comparative example do not occur.

以上より、本発明の制御基板１によれば、制御基板１に複数の規格の記憶媒体を接続している場合に、記憶媒体を制御基板１に接続しているか否かを検知し、手動で記憶媒体５を第１ＣＰＵ２に接続するように切り替えることなく、自動で、記憶媒体５と第１ＣＰＵ２を接続できることが分かる。
また、第２ＣＰＵ３は、記憶媒体５と第１ＣＰＵ２の接続を切断した場合に、作業者に報知することができる。 As described above, according to the control board 1 of the present invention, when the control board 1 is connected with storage media of a plurality of standards, it is detected whether or not the storage media are connected to the control board 1, and the control board 1 is manually operated. It can be seen that the storage medium 5 and the first CPU 2 can be automatically connected without switching the storage medium 5 to be connected to the first CPU 2.
In addition, the second CPU 3 can notify the operator when the connection between the storage medium 5 and the first CPU 2 is disconnected.

以上の構成により、製品寿命が長い工作機械２１において、記憶媒体の将来の製造中止に備え、複数の記憶媒体を制御基板１に接続することができる。
そして、優先度が高い記憶媒体５を接続している時は記憶媒体５により第１ＣＰＵ２を起動し、接続していない時は優先度が低い記憶媒体６により第１ＣＰＵ２を起動できる。
なお、スイッチＩＣはＳＡＴＡスイッチＩＣに限定されず、他のインタフェース規格のスイッチＩＣを用いてもよい。記憶媒体も上述の規格に対応する場合には限定されない。 With the above configuration, in the machine tool 21 having a long product life, a plurality of storage media can be connected to the control board 1 in preparation for future discontinuation of storage media production.
Then, when the storage medium 5 having a high priority is connected, the first CPU 2 can be activated by the storage medium 5, and when not connected, the first CPU 2 can be activated by the storage medium 6 having a low priority.
The switch IC is not limited to the SATA switch IC, and a switch IC of another interface standard may be used. The storage medium is not limited to the case that it corresponds to the above-mentioned standard.

１ 制御基板
１０ コネクタ
１１ ＣＤＯ端子
１２ 接続端子
１３ ＣＤＩ端子
１４ 接続端子
１５ 電源
１６ プルアップ抵抗
１７ 信号線
１８ 通信バス
２ 第２ＣＰＵ
３ 第３ＣＰＵ
４ スイッチＩＣ
５、６、７ 記憶媒体
５１ 第１端子
５２ 第２端子
５３ 第３端子
５４ 導線
５５、６２ ＯＳ 1 Control Board 10 Connector 11 CDO Terminal 12 Connection Terminal 13 CDI Terminal 14 Connection Terminal 15 Power Supply 16 Pull-up Resistor 17 Signal Line 18 Communication Bus 2 Second CPU
3rd CPU
4 switch IC
5, 6, 7 Storage medium 51 1st terminal 52 2nd terminal 53 3rd terminal 54 Conductive wire 55, 62 OS

Claims (5)

複数の記憶媒体が接続される複数のコネクタと、
該複数のコネクタが接続された一つの切替回路と、
該切替回路に接続された第１ＣＰＵと、
一のコネクタに一の記憶媒体が接続されたか否かを検知する検知回路と
を備え、
前記切替回路は、前記検知回路が前記一のコネクタに前記一の記憶媒体が接続されたことを検知した場合に、前記一のコネクタと前記第１ＣＰＵとを接続し、前記一のコネクタに前記一の記憶媒体が接続されていないことを検知した場合に、他の記憶媒体が接続されている他のコネクタと前記第１ＣＰＵとを接続する、制御基板。 A plurality of connectors to which a plurality of storage media are connected,
One switching circuit to which the plurality of connectors are connected,
A first CPU connected to the switching circuit,
A detection circuit for detecting whether or not one storage medium is connected to one connector,
The switching circuit connects the one connector and the first CPU when the detection circuit detects that the one storage medium is connected to the one connector, and the one connector is connected to the one connector. The control board, which connects the other connector to which the other storage medium is connected and the first CPU when it is detected that the storage medium is not connected. 前記一の記憶媒体は導線を有し、
前記一のコネクタは、所定の電圧でプルアップされた第１端子、及び接地された第２端子を有し、
前記検知回路は、前記一のコネクタに前記一の記憶媒体が接続されて前記導線と前記第１端子及び前記第２端子とが接続されたときに、前記第１端子におけるハイレベルからローレベルへの変化に基づいて、前記一の記憶媒体の接続を検知する、請求項１に記載の制御基板。 The one storage medium has a conductor,
The one connector has a first terminal pulled up by a predetermined voltage and a second terminal grounded,
The detection circuit changes from a high level to a low level at the first terminal when the one storage medium is connected to the one connector and the conducting wire is connected to the first terminal and the second terminal. The control board according to claim 1, wherein the connection of the one storage medium is detected on the basis of the change of. 第３の記憶媒体が接続された第２ＣＰＵを備え、
前記検知回路は検知結果を前記第２ＣＰＵへ出力し、
前記第２ＣＰＵは、前記検知結果を第３の記憶媒体に保存し、外部へ出力する、請求項１又は２に記載の制御基板。 A second CPU to which a third storage medium is connected,
The detection circuit outputs a detection result to the second CPU,
The control board according to claim 1, wherein the second CPU stores the detection result in a third storage medium and outputs the detection result to the outside. 前記一の記憶媒体は、前記第１ＣＰＵを動作するためのオペレーティングシステムを記憶している、請求項１から３までのいずれか１項に記載の制御基板。 The control board according to any one of claims 1 to 3, wherein the one storage medium stores an operating system for operating the first CPU. 前記複数の記憶媒体の規格は異なり、
前記一の記憶媒体が前記一のコネクタに接続されている場合は、該一の記憶媒体に記憶されたオペレーティングシステムにより前記第１ＣＰＵは動作し、前記一の記憶媒体が前記一のコネクタに接続されていない場合、他のコネクタに接続されている他の記憶媒体に記憶されたオペレーティングシステムにより前記第１ＣＰＵは動作する、請求項４に記載の制御基板。 The standards of the plurality of storage media are different,
When the one storage medium is connected to the one connector, the first CPU operates by the operating system stored in the one storage medium, and the one storage medium is connected to the one connector. If not, the control board according to claim 4, wherein the first CPU is operated by an operating system stored in another storage medium connected to another connector.
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