JP2013050839A - Information processor, information processing method, and information processing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance security and inhibit an abnormal BIOS (Basic Input/Output System) from starting.SOLUTION: An information processor 9 comprises: a BIOS (Basic Input/Output System) storage unit 91 prestoring a BIOS 910; a code storage unit 92 prestoring an error detection code 920 of composite data including data of the normal BIOS 910 and additional data predefined to an optional value; and a control unit 93 which generates an error detection code of the composite data including the data of the BIOS 910 and additional data when the BIOS 910 stored in the BIOS storage unit 91 starts, compares the generated error detection code with the error detection code 920 stored in the code storage unit 92, and inhibits the BIOS 910 from starting when the error detection codes do not match with each other.

Description

  The present invention relates to an information processing apparatus, an information processing method, and an information processing program, and more particularly, to a technique for controlling activation of a basic input / output system (BIOS).

  In recent years, crimes caused by computer viruses have frequently occurred in information processing apparatuses. For this reason, it is desired to prevent important information from being erased or destroyed by computer viruses.

  The information processing apparatus starts up an operating system by a program such as a basic input / output system (BIOS) written in a nonvolatile memory at the time of activation. The BIOS is written in a rewritable nonvolatile memory. Some information processing apparatuses inhibit activation in POST (Power On Self Test) when the BIOS is destroyed by a computer virus or when the BIOS is infected by a computer virus.

  Patent Document 1 discloses a technique for preventing an information processing apparatus from being activated by a BIOS or IPL that is destroyed or infected by a computer virus or the like. The information processing apparatus disclosed in Patent Document 1 includes a flash ROM section, a jumper section, a flash ROM reading section, an addition circuit section, and a comparison circuit section. Programs such as IPL (Initial Program Load) and BIOS are written in the flash ROM section. In the jumper part, the total of data when the contents of the flash ROM part are normal is set. When power is supplied to the information processing apparatus, the flash ROM reading unit reads the contents of the flash ROM unit one after another and sends it to the adding circuit unit. The adding circuit unit calculates the sum. The comparison circuit unit compares the total result of the addition circuit unit with the total set in the jumper unit. If they match, the information processing apparatus starts an operation such as IPL or BIOS. On the other hand, if they do not match, the information processing apparatus does not start operations such as IPL and BIOS.

Japanese Patent Laid-Open No. 10-027035

  However, in Patent Document 1, it is simply determined whether the BIOS or the like is destroyed or infected by the total value of the flash ROM section. However, since the third party can easily know only the total value of the flash ROM portion, there is a problem that it is not sufficient as a security measure.

  For example, a computer virus that has infected an information processing device can calculate the total value by simply reading the data in the flash ROM section. Therefore, programs such as BIOS stored in the flash ROM unit can be easily altered by rewriting the data in the flash ROM unit so that the total value of the data in the flash ROM unit matches the calculated total value. it can.

  An object of the present invention is to provide an information processing apparatus, an information processing method, and an information processing program that can suppress startup by an abnormal BIOS while improving security in order to solve the above-described problems. That is.

  An information processing apparatus according to a first aspect of the present invention includes a BIOS storage unit in which a BIOS (Basic Input / Output System) is stored in advance, normal BIOS data, and additional data set in advance to an arbitrary value. An error detection code of the composite data including the BIOS data and the additional data when the BIOS stored in the BIOS storage unit is activated. A management unit that suppresses activation of the BIOS when the generated error detection code is compared with the error detection code stored in the code storage unit and the error detection code does not match; It is provided.

  In the information processing method according to the second aspect of the present invention, when starting up a basic input / output system (BIOS), composite data including data of the BIOS and additional data set in advance to an arbitrary value is stored. A step of generating an error detection code; an error detection code of composite data including the normal BIOS data and the additional data generated in advance; and an error detection code generated when starting the BIOS In comparison, if the error detection codes do not match, the step of inhibiting the activation of the BIOS is provided.

  When an information processing program according to the third aspect of the present invention starts up a BIOS (Basic Input / Output System), the information processing program includes a combination data including the BIOS data and additional data set in advance to an arbitrary value. A process for generating an error detection code, an error detection code for composite data including the normal BIOS data and the additional data, and an error detection code generated when the BIOS is started. In comparison, if the error detection codes do not match, the BMC (Baseboard Management Controller) is caused to execute a process of inhibiting the activation of the BIOS.

  According to each aspect of the present invention described above, it is possible to provide an information processing apparatus, an information processing method, and an information processing program that can suppress activation by an abnormal BIOS while improving security.

It is a block diagram which shows the outline | summary of a structure of the information processing apparatus concerning embodiment of this invention. It is a block diagram which shows the structure of the information processing apparatus concerning embodiment of this invention. It is a flowchart which shows the starting process of the information processing apparatus concerning embodiment of this invention. It is a flowchart which shows the setting information update process of the information processing apparatus concerning embodiment of this invention.

  First, with reference to FIG. 1, the structure of the information processing apparatus 9 used as the outline | summary of the information processing apparatus 1 concerning embodiment of this invention is demonstrated. FIG. 1 is a block diagram showing a configuration of an information processing apparatus 9 according to an embodiment of the present invention.

  The information processing apparatus 9 includes a BIOS storage unit 91, a code storage unit 92, and a management unit 93.

  The BIOS storage unit 91 stores a BIOS 910 in advance. The code storage unit 92 stores in advance an error detection code of composite data including normal BIOS 910 data and additional data set to an arbitrary value in advance. When the management unit 93 activates the BIOS 910 stored in the BIOS 91, the management unit 93 generates an error detection code of composite data including the data of the BIOS 910 and the code data. The management unit 93 compares the generated error detection code with the error detection code stored in the code storage unit 92, and suppresses activation of the BIOS 910 if the error detection codes do not match.

  Next, processing of the information processing apparatus 9 according to the embodiment of the present invention will be described.

  When the management unit 93 activates the BIOS 910, the management unit 93 generates an error detection code of composite data including the data of the BIOS 910 and additional data set in advance to an arbitrary value. The management unit 93 compares the error detection code 920 of the combined data including normal BIOS 910 data and additional data with the error detection code generated when the BIOS 910 is activated. If the error detection codes do not match, the management unit 93 suppresses the activation of the BIOS 910.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. First, the configuration of the information processing apparatus 1 according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the information processing apparatus 1 according to the embodiment of the present invention. The information processing apparatus 1 is, for example, a server.

  More specifically, FIG. 2 shows the architecture of the mother board 10 included in the information processing apparatus 1. This architecture exemplifies one example, and the configuration thereof may be changed as appropriate as long as the functions of the present invention described later can be realized.

  The motherboard 10 includes a CPU (Central Processing Unit) 11, a processor bus 12, a north bridge 13, a memory 14, a south bridge 15, a low pin count (LPC) bus 16, nonvolatile memories 17 and 19, and a BMC 18. Have. The CPU 11 and the north bridge 13 are connected to each other via the processor bus 12. The south bridge 15, the nonvolatile memories 17 and 19, and the BMC 18 are connected to each other via the LPC bus 16.

  The CPU 11 loads the BIOS 170 from the nonvolatile memory 17 and executes it. The CPU 11 executes POST such as initialization of a unit included in the information processing apparatus 1 by executing the BIOS 170. The CPU 11 executes an OS (Operating System) after the end of POST. Note that “CPU” is also referred to as “processor”.

  The processor bus 12 is a transfer path through which data is transferred between the CPU 11 and the north bridge 13. The north bridge 13 manages data transferred between the memory 14 and the CPU 11 and data transferred between the south bridge 15 and the CPU 11. The north bridge 13 is a chip that controls a unit that is faster than a unit controlled by the south bridge 15. Here, the memory 14 corresponds to such a unit.

  The memory 14 includes a memory unit (not shown) and a memory controller (not shown). The memory unit is a random accessible volatile memory such as an SRAM (Static Random Access Memory) and a DRAM (Dynamic Random Access Memory). The memory controller controls reading and writing of data with respect to the memory unit in response to a request from the CPU 11. The function of the memory controller may be included in the north bridge 13.

  The south bridge 15 manages data transferred between the north bridge 13 and the nonvolatile memories 17 and 19 and the BMC 18. The south bridge 15 is a chip that controls a unit that is slower than a unit controlled by the north bridge 13. The south bridge 15 has functions such as an LPC bus controller, a PCI (Peripheral Component Interconnect) bus controller, an IDE (Integrated Drive Electronics) controller, and a USB (Universal Serial Bus) controller. In the present embodiment, among these functions, an LPC bus in which data transfer control is performed by the function of the LPC bus controller is illustrated. The other buses and the units connected to the buses are not shown. These units include, for example, input / output devices such as a mouse and a keyboard, and a storage device such as a hard disk. For example, the OS executed by the CPU 11 is stored in this hard disk. The north bridge 13 and the south bridge 15 are also referred to as a chip set in the motherboard 10.

  Note that data transfer control between the constituent elements 11, 14, 17, 18, and 19 by the memory controller, the north bridge 13, and the south bridge 15 is a well-known technique, and thus detailed description thereof is omitted.

  The LPC bus 16 is a transfer path through which data is transferred between the south bridge 15, the nonvolatile memories 17 and 19, and the BMC 18. The nonvolatile memory 17 stores the BIOS 170 in advance. The nonvolatile memory 17 also stores setting information 171 of the BIOS 170. The BIOS 170 is a program that causes the CPU 11 to execute POST. Further, when the BIOS 170 updates the data 170 and 171 stored in the nonvolatile memory 17, the checksum value 190 is also updated accordingly. The checksum value 190 will be described later. The setting information 171 includes, for example, information such as the priority order of the boot device, clock, and device configuration.

  The BMC 18 performs power control of the information processing apparatus 1 and management of temperatures and voltages of various units included in the information processing apparatus 1. The BMC 18 functions as an interface between system management software executed on the OS by the CPU 11 and various units. The acquisition of information from the BMC 18 by the system management software here is performed by a command interface based on the IPMI (Intelligent Platform Management Interface) specification. That is, acquisition of unit information by the system management software is realized by the system management software outputting an IPMI command requesting unit information to the BMC 18, and the BMC 18 outputting unit information to the CPU 11 accordingly. Strictly speaking, the processing by these system management software is executed by the CPU 11.

  Further, the BMC 18 monitors whether or not the OS operating in the CPU 11 is stalled by a WDT (watch dock timer). Specifically, the BMC 18 determines that the OS has stalled when there is no response from the OS for a predetermined time. If the BMC 18 determines that the OS has stalled, the BMC 18 restarts the CPU 11. For example, the BMC 18 restarts the CPU 11 by outputting a signal for restarting the CPU 11 to the CPU 11.

  Further, the BMC 18 generates additional data. An arbitrary value can be determined in advance as the value of the additional data. The data length of the additional data can also be set to an arbitrary length in advance. The additional data generated by the BMC 18 is used for calculation of a checksum value to be described later. The BMC 18 reads data from the nonvolatile memory 17 before the BIOS 170 is started by the CPU 11. This data includes BIOS 170 data and setting information 171. The BMC 18 calculates a checksum value for data obtained by adding the generated additional data to the read data in the nonvolatile memory 17. Then, the BMC 18 compares the calculated checksum value with the checksum value 190 stored in the nonvolatile memory 19. Here, the checksum value 190 is an expected value of the calculated checksum value, which will be described in detail later. For this reason, the BMC 18 allows the CPU 11 to execute the BIOS 170 when the compared checksum values match, and suppresses the execution of the BIOS 170 by the CPU 11 when the compared checksum values do not match.

  Here, the processing of the BMC 18 according to the present embodiment is realized by firmware operating on the BMC 18. The BMC 18 includes, for example, a CPU that executes the firmware and a memory.

  The non-volatile memory 19 stores a checksum value 190 in advance. This checksum value is a checksum value calculated in advance for data obtained by adding additional data to normal data in the nonvolatile memory 17. That is, the checksum value 190 stored in the nonvolatile memory 19 becomes an expected value of the checksum value of data obtained by adding the additional data generated by the BMC 18 to the data stored in the nonvolatile memory 17. Therefore, when the checksum value calculated by the BMC 18 when the BIOS 170 is started up matches the checksum value stored in advance in the nonvolatile memory 19, the data stored in the nonvolatile memory 17 is destroyed or altered. Will not be. Here, the non-volatile memories 17 and 19 are, for example, flash memories.

  Subsequently, a startup process of the information processing apparatus 1 according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a flowchart showing a startup process of the information processing apparatus 1 according to the embodiment of the present invention. Strictly speaking, the following processing executed by the BIOS 170 is executed by the CPU 11.

  When the BMC 18 receives a power-on instruction (S1), the BMC 18 starts to start the information processing apparatus 1. The power-on instruction is, for example, a signal output from the information processing device 1 to the BMC 18 when the user presses the power-on switch of the information processing device 1. In response to the power-on instruction, the BMC 18 generates additional data before starting the activation of the BIOS 170 (S2). Further, the BMC 18 reads the data of the nonvolatile memory 17 and calculates a checksum value for the data obtained by adding the generated additional data to the read data of the nonvolatile memory 17 (S3).

  The BMC 18 compares the calculated checksum value with the checksum value 190 stored in the nonvolatile memory 19 (S4).

  If the compared checksum values match, the BMC 18 activates the information processing apparatus 1 (S5). That is, the BMC 18 outputs a boot instruction for the BIOS 170 to the CPU 11. The CPU 11 reads out the BIOS 170 from the non-volatile memory 17 and executes it in response to the activation instruction of the BIOS 170 from the BMC 18. Here, the BMC 18 may output an interrupt signal to the CPU 11 as an activation instruction of the BIOS 170, and the CPU 11 may activate the BIOS 170 in response to the interrupt signal. Further, the BMC 18 may output information indicating that to the BIOS 170 as an activation instruction of the BIOS 170 to the CPU 11 via the south bridge 15 and the north bridge 13, and the CPU 11 may activate the BIOS 170 according to the information. The BIOS 170 that has started execution executes POST. Then, the CPU 11 starts up the OS after the completion of the POST. Thereby, the activation of the information processing apparatus 1 is completed.

  On the other hand, when the compared checksum values do not match, the BMC 18 suppresses the activation of the information processing apparatus 1 (S6). That is, in this case, it is determined that the BIOS 170 or the setting information 171 is destroyed by a computer virus or the like. Therefore, in this case, the BMC 18 does not output an instruction to start the BIOS 170 to the CPU 11. As a result, activation of the BIOS 170 and the information processing apparatus 1 is suppressed.

  Next, with reference to FIG. 4, the setting information update process of the information processing apparatus 1 according to the embodiment of the present invention will be described. FIG. 4 is a flowchart showing setting information update processing of the information processing apparatus 1 according to the embodiment of the present invention. Strictly speaking, the following processing executed by the BIOS 170 is executed by the CPU 11.

  After the BIOS 170 is activated, the BIOS 170 acquires additional data from the BMC 18 (S12) when the setting information 171 is rewritten by normal operation (S11). Here, the rewriting of the setting information 171 in the normal operation is, for example, when the user sets various BIOS setting information on the BIOS setting screen after starting the BIOS 170, or when the BIOS 170 is POST in the configuration of the information processing apparatus 1. This includes a case where device configuration information is set by automatically detecting a change.

  Further, an IPMI command is used to acquire additional data from the BMC 18. Specifically, an OEM (Original Equipment Manufacturer) extension command of IPMI is used. That is, a command for requesting additional data from the BIOS 170 to the BMC 18 may be implemented using an IPMI OEM extension command. When the BIOS 170 outputs a command requesting the additional data to the BMC 18, the BMC 18 generates additional data according to the command, and outputs the generated additional data to the CPU 11.

  The CPU 11 calculates a checksum value for the data obtained by adding the additional data acquired from the BMC 18 to the data in the new nonvolatile memory 17 after rewriting (S13). For example, after the setting information 171 is rewritten, the data in the nonvolatile memory 17 is read and the checksum value is calculated. The additional data acquisition in step S12 may be executed at any timing before or after the setting information 171 is rewritten as long as the checksum value is calculated. The CPU 11 updates the checksum value 190 of the nonvolatile memory 19 with the calculated checksum value (S14).

  As described above, in the present embodiment, the checksum value is calculated by adding the additional data to the data instead of only the checksum value of only the data of the nonvolatile memory 7 in which the BIOS 170 is stored, The destruction of the BIOS 170 is detected by the checksum value. According to this, in order to obtain the checksum value, the third party needs to know the existence of the additional data and further acquire the additional data. Therefore, the third party cannot easily know the checksum value. Therefore, for example, programs such as BIOS can be prevented from being easily tampered with by a computer virus. In other words, it is possible to suppress the activation by the abnormal BIOS while improving the security.

  In this embodiment, the BMC 18 generates additional data and calculates a checksum value for the data to which the additional data is added. According to this, it is not possible for a third party to easily acquire additional data such that the additional data can be acquired simply by referring to one of the storage devices. Therefore, security can be further improved.

  Further, in Patent Document 1, it is determined whether the BIOS or the like has been destroyed or infected by the total value of all data in the flash ROM section in which the BIOS is stored. Further, the total value of data when the contents of the flash ROM portion are normal is fixedly set in the jumper portion. However, generally, the BIOS setting information is stored in a storage device (flash ROM unit) in which the BIOS is stored. Therefore, when the BIOS updates the setting information, the calculated total value is different from the total value set in the jumper unit, and the information processing apparatus cannot be activated even though the BIOS or the like is normal. There was a problem. On the other hand, in this embodiment, when the setting information 171 stored in the nonvolatile memory 17 is rewritten, the checksum value 190 that is an expected value is also updated accordingly. Therefore, even when the BIOS setting information is rewritten, it is possible to accurately prevent the information processing apparatus from starting only when there is an abnormality in the BIOS.

  In the present embodiment, the checksum value 190 is updated when the setting information 171 of the BIOS 170 is rewritten. However, the checksum value 190 is also updated when the BIOS 170 is rewritten. The rewriting of the BIOS 170 includes, for example, a case where the user rewrites the BIOS 170 on the setting screen of the BIOS 170 after starting the BIOS 170 or a case where the user rewrites the BIOS 170 by executing an application program for rewriting the BIOS 170 from the OS after starting the OS. . The update of the checksum value 190 in this case may be performed in the same way as when the setting information 171 is rewritten. For example, after the BIOS 170 is rewritten, the data in the nonvolatile memory 17 is read and the checksum value is calculated. The additional data may be acquired in the same manner.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  In the present embodiment, the case where the checksum value 190 is stored in the nonvolatile memory 19 connected to the LPC bus 16 has been exemplified. However, the CPU 11 and the BMC 18 update and refer to the storage location of the checksum value 190. Any place can be used as long as it is possible. For example, the checksum value 190 may be stored in the memory 14, or a volatile memory or a non-volatile memory may be provided in the BMC 18 and stored therein. The storage device that stores the checksum value 190 is not limited to a volatile memory and a nonvolatile memory, and may be a register.

  In this embodiment, the destruction of the entire nonvolatile memory 17 including the data of the BIOS 170 and the setting information 171 is calculated by checking the destruction, but the data for checking the destruction is nonvolatile. It may be a part of data stored in the memory 17. For example, among the data stored in the nonvolatile memory 17, only the data of the BIOS 17 may be calculated to check for destruction by calculating a checksum value. That is, a checksum value may be calculated for data obtained by adding additional data to the BIOS 17 data to check for destruction of the BIOS 17. In this case, a checksum value for data obtained by adding additional data to normal BIOS 17 data is stored in the nonvolatile memory 19. Even in such a case, it is possible to detect the destruction of the BIOS 170 while improving the security.

  In this embodiment, the checksum value is calculated to check for destruction, but other error detection codes may be used. For example, CRC (Cyclic Redundancy Check), parity, checksum, hash value, etc. may be used.

  In the embodiment of the present invention, the firmware of the BIOS 170 and the BMC 18 is included as a program. These programs can be stored using various types of non-transitory computer readable media and supplied to a computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  In addition to the case where the function of the above-described embodiment is realized by the computer executing the program that realizes the function of the above-described embodiment, this program is not limited to the OS ( A case where the functions of the above-described embodiment are realized in cooperation with an operating system or application software is also included in the embodiment of the present invention. Furthermore, the present invention is also applicable to the case where the functions of the above-described embodiment are realized by performing all or part of the processing of the program by a function expansion board inserted into the computer or a function expansion unit connected to the computer. It is included in the embodiment.

1, 9 Information processing device 10 Motherboard 11 CPU
12 processor bus 13 north bridge 14 memory 15 south bridge 16 LPC bus 17, 19 non-volatile memory 18 BMC
91 BIOS storage unit 92 Code storage unit 93 Management unit 170 BIOS
171 Setting information 190 Checksum value 910 BIOS
920 error detection code

Claims (8)

A BIOS storage unit in which BIOS (Basic Input / Output System) is stored in advance;
A code storage unit for storing in advance an error detection code of composite data including normal BIOS data and additional data set to an arbitrary value in advance;
When starting up the BIOS stored in the BIOS storage unit, an error detection code of composite data including the BIOS data and the additional data is generated, and the generated error detection code and the code storage unit are stored. When the error detection code is compared and the error detection code does not match, the management unit that suppresses activation of the BIOS;
An information processing apparatus comprising: The information processing apparatus further includes an additional data generation unit that generates the additional data,
The management unit generates an error detection code of composite data including the BIOS data and the additional data generated by the additional data generation unit;
The information processing apparatus according to claim 1. The BIOS storage unit further stores setting information of the BIOS,
The composite data further includes setting information of the BIOS,
The information processing apparatus acquires additional data generated by the additional data generation unit when rewriting the setting information stored in the BIOS storage unit, and acquires the acquired additional data, the BIOS data, and the post-rewriting The information according to claim 2, further comprising: a control unit that generates an error detection code of the composite data including the BIOS setting information and updates the error detection code stored in the code storage unit with the generated error detection code. Processing equipment. The control unit is a processor;
The information processing apparatus further includes a BMC (Baseboard Management Controller) including the management unit and the additional data generation unit.
The information processing apparatus according to claim 3. The processor transmits / receives information regarding hardware included in the information processing apparatus to / from the BMC by an IPMI (Intelligent Platform Management Interface) command,
The information processing apparatus according to claim 4, wherein the processor acquires the additional data from the BMC by an OEM (Original Equipment Manufacturer) extension command of the IPMI.   The information processing apparatus according to claim 1, wherein the error detection code is a checksum value of the combined data. Generating an error detection code of composite data including the BIOS data and additional data set in advance to an arbitrary value when starting up a BIOS (Basic Input / Output System);
The error detection code of the composite data including the normal BIOS data and the additional data generated in advance is compared with the error detection code generated when the BIOS is started, and those error detection codes are compared. If they do not match, the step of inhibiting the activation of the BIOS;
An information processing method comprising: A process of generating an error detection code of composite data including the BIOS data and additional data set in advance at an arbitrary value when starting up a BIOS (Basic Input / Output System);
The error detection code of the composite data including the normal BIOS data and the additional data generated in advance is compared with the error detection code generated when the BIOS is started, and those error detection codes are compared. If they do not match, a process of inhibiting the activation of the BIOS;
Is an information processing program that causes a BMC (Baseboard Management Controller) to execute.

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