JP2020113782A - Method of assembling semiconductor power device - Google Patents

Abstract

To provide a switching power semiconductor device comprising two substrates better aligned with each other.SOLUTION: A semiconductor power device 100 comprises: a first substrate 140; a second substrate 110; and interconnection structure. The first substrate comprises: a switching semiconductor element 144; a first conductive layer 142; and a first receiving element 150. The second substrate includes: a second receiving element 120; and a second conductive layer 112. The interconnect structure provides an electric connection between the first conductive layer and the second conductive layer. The interconnect structure further comprises a plurality of interconnect elements 130 that are electrically conductive materials. At least one of the interconnection elements is an alignment interconnection element. The alignment interconnection element is partially received by the first receiving element and partially by the second receiving element to align a relative position of the first substrate with respect to the second substrate.SELECTED DRAWING: Figure 2a

Description

The present invention relates to semiconductor power devices. Power devices are capable of switching relatively large currents and/or relatively high voltages. Such currents can be on the order of 1 to several hundred amps, and such voltages can be on the order of hundreds to thousands of volts. The invention further relates to assembling semiconductor power devices.

Published patent application US78509079B2, which is incorporated herein by reference, discloses a switching power semiconductor device with at least two substrates. The substrates are arranged substantially parallel to each other. The surface of the substrate and the surface of the semiconductor device arranged on the substrate may include electrodes. The subsets of electrodes face each other and provide electrical connections between them. In one embodiment, this electrical connection is provided by a copper sphere located between the two electrodes and soldered to the electrodes. In another embodiment, solder or lead drop shaped elements are provided between the two electrodes. In yet another embodiment, drop-shaped elements of solder or lead are provided on the electrodes of one substrate with copper spheres disposed between those drop-shaped elements and the electrodes of the other substrate. The copper spheres and/or drop-shaped elements are sized to fit the required distance between the electrodes between which the two substrates are arranged substantially parallel to each other. Copper spheres and/or drop shaped elements provide electrical connections between the different electrical elements of the two substrates. Further, heat may be transported via copper spheres and/or drop shaped elements away from the semiconductor devices provided on the substrate.

The copper spheres and/or drop-shaped elements of the patent applications discussed above provide spacing between the two substrates, thereby defining the distance between the two substrates. In the rest of this document, it is assumed that the straight line forming the shortest distance between two substrates is z-dimensional. Thus, in other words, the copper spheres and/or the drop-shaped elements define the relative position of the two substrates with respect to one another in the z dimension. It is further envisioned later in this document that the x and y dimensions are oriented perpendicular to the z dimension discussed above. Thus, a three-dimensional Cartesian coordinate system is envisioned. In the patent publication cited above, the size is such that the first substrate and the second substrate are exactly flat and the copper spheres are arranged so that the two substrates are exactly parallel to each other. , The x and y dimensions define a virtual plane that is parallel to both substrates.

During assembly of switching power semiconductor devices, such as the switching power semiconductor devices of the patents cited above, the two substrates must also be well aligned with each other in the x and y dimensions. One solution for aligning the two substrates in the x and y dimensions during assembly is to utilize a visible alignment marker, which is recorded by a camera and actuator and used for video processing. Based on the output of the system, the two substrates are controlled to move to the correct (x,y) position with respect to each other. Unfortunately, such solutions for aligning the first substrate with the second substrate in the x and y dimensions have not been accurate enough. Typically, immediately before the copper sphere or drop-shaped element is secured (eg, by soldering) to the first or second substrate, the first and/or second substrate is x-dimensional. Or it may move in the y dimension, in which case the substrates would not be sufficiently accurately aligned with each other.

U.S. Pat. No. 7,859,079

Manfred Goetz et al., "Comparison of Silicon Nitride DBC and AMB Substrate for for differential applications, page 65-Verve, 14th November, 14th, 14th of October, PCIM.

It is an object of the present invention to provide a switching power semiconductor device with two substrates that are better aligned with each other.

A first aspect of the invention provides a semiconductor power device. A second aspect of the invention provides a method of assembling a semiconductor power device. Advantageous embodiments are defined in the dependent claims.

A semiconductor power device according to the first aspect of the present invention comprises a first substrate, a second substrate, and an interconnection structure. The first substrate includes a switching semiconductor element. The first substrate has a first surface and locally comprises a first conductive layer and a first receiving element. A switching semiconductor element is provided on the first surface. The second substrate comprises a second surface facing the first surface. The second substrate comprises a second receiving element and locally comprises a second conductive layer. The interconnect structure is for providing at least one electrical connection between at least one of the first conductive layers on one side and at least one of the second conductive layers on the other side. The interconnect structure comprises a plurality of interconnect elements that are electrically conductive materials. At least one of the plurality of interconnection elements is an alignment interconnection element. The alignment interconnection element is partially received by the first receiving element and partially by the second receiving element to align the relative position of the first substrate with respect to the second substrate. .. The receiving element has a recess having a shape for at least partially receiving an alignment interconnection element, the receiving element and the alignment interconnection element being abutted against each other, and the alignment interconnection element or the The shape of the alignment interconnection element is selected to affect the positioning of the alignment interconnection element in a unique and fixed relative position with respect to the receiving element when one of the receiving elements is subjected to a force. As described above, the first substrate is aligned with the second substrate.

In a power semiconductor device according to the embodiments discussed above, alignment of the first substrate with respect to the second substrate is provided as follows. Receiving elements configured to receive alignment interconnection elements at appropriate locations on the first substrate and at appropriate corresponding locations on the second substrate are provided. The first receiving element receives a portion of the alignment interconnect element, the second receiving element also receives a portion of the alignment interconnect element, and a relative position of the first substrate with respect to the second substrate (required). 3.) When it comes to the aligned position, the appropriate position is selected and the specific size and shape of the alignment interconnect element is selected. Since the receiving element receives a portion of the alignment interconnect element, the position of the alignment interconnect element is fixed with respect to the position of the receiving element, and consequently the relative position of the first substrate with respect to the second substrate. It Furthermore, the shape of the recess of the receiving element and the shape of the alignment interconnection element are such that they are unique and fixed of the alignment interconnection element to the receiving element when they are brought into contact with each other under the influence of a force. There are only one possible specific relative arrangements of alignment interconnection elements with respect to the receiving element, as they are chosen together to cooperate towards position. By the above, the receiving elements are forced towards a properly defined and fixed relative position with respect to each other, whereby the substrates are forced towards a properly defined and fixed relative position with respect to each other. It In most embodiments, the force exerted on the receiving element or the alignment interconnection element can be gravity, but it can also be the force exerted positively on one of those elements. As a result of aligning these substrates towards a unique and fixed relative position with respect to each other, the pattern of the first conductive layer is aligned with the pattern of the second conductive layer. It should be noted that Thus, it will be seen in the present application that the receiving element and the alignment interconnection element have the function of aligning the patterns of said conductive layer with respect to each other.

According to the background discussion, a Cartesian coordinate system can be defined in a semiconductor power device. In the semiconductor power device according to the present invention, the shape and size of the receiving element and the alignment interconnection element define the distance between the two substrates and, consequently, in the z dimension of the first substrate relative to the second substrate. Define relative position. The position of the first receiving element on the first substrate and the position of the second receiving element on the second substrate define the relative alignment of the two substrates in the x and y dimensions. ..

According to one embodiment, both elements of the alignment interconnection element and the receiving element are arranged on top of each other, the force being received by one of these elements and the other element being in a fixed position. The part of the alignment interconnection element is automatically received by the receiving element. For example, when the alignment interconnection element is placed over a receiving element having a fixed position, gravity is received by the alignment interconnection element and as a result of this force, the alignment interconnection element is caused by each receiving element. Partially received, gravity forces the alignment interconnection elements towards a unique, fixed position. In one example, the alignment interconnection element has a spherical shape and the receiving element is a hole: when the spherical shape is placed on top of the hole, the spherical shape automatically, at least partially, Received by the hole, this sphere rotates towards one unique position so that it is optimally partially received by the receiving element. This has the effect that the alignment is done automatically during assembly of the power semiconductor device and no separate steps are required to force the receiving element to receive part of the alignment interconnection element. Have.

The switching semiconductor device may be a transistor, a field effect transistor (FET), a MOS field effect transistor (MOSFET), a thyristor, an insulated gate bipolar transistor (IGBT), a diode or any other suitable type of semiconductor switching device. The first substrate and/or the second substrate may also be another element made of a semiconductor material such as silicon, silicon carbide, gallium arsenide, gallium nitride, diamond based semiconductor material or any other suitable semiconductor material. Other electronic devices including can also be included. Examples of other electronic devices are resistors, capacitors, inductors, integrated circuits, or other suitable electronic devices.

The substrate can be made of multiple layers of thermally and electrically insulating material (eg, ceramic) and highly conductive material (eg, metal) for routing. Examples of ceramics are aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ) and silicon nitride (Si ₃ N ₄ ). Other examples of the substrate are Si ₃ N ₄ sandwiched between, for example copper or two thin metal layer is a thin layer of aluminum. Typically, in the related art, such substrates are referred to as direct bond copper (DBC) substrates or active metal bonding/brazing (AMB) substrates. The conductive layers and/or interconnect elements can be made of metal such as copper or aluminum, but can also be made of other metals or other conductive materials. Optionally, the material from which the conductive layer and/or the interconnection element is made is a good thermal conductor, the layer and the interconnection element being able to conduct heat away from the semiconductor power device. Contributes to the distribution and conduction of heat to some location (eg, the interface to the heat sink). In the following description of this document, it may be possible to read “electrode” instead of conductive layer, but conductive layer is not by definition coupled to a specific voltage or signal, and conductive layer is also It should be noted that it can be an isolated island of such material.

Optionally, the first substrate comprises a plurality of first receiving elements, the second substrate comprises a plurality of second receiving elements and the interconnection element comprises a plurality of alignment interconnection elements. Wherein each one of the plurality of alignment interconnection elements is partially received by each one of the first receiving elements to align the relative position of the first substrate with respect to the second substrate, and Partially received by each one of the receiving elements. In other words, there are a plurality of 3-tuples, each of the plurality of 3-tuples comprising a first receiving element, a second receiving element and an alignment interconnection element. The position of the first receiving element of the 3-tuple on the first substrate is such that the alignment element and the alignment receiving element of the particular 3-tuple are at least partially received by the receiving element of the 3-tuple. The combination with the connecting element corresponds to a position on the second substrate in order to obtain the effect of providing the required alignment in the x and y dimensions. The semiconductor power device discussed above comprises at least one such 3-tuple, while this optional embodiment comprises a plurality of such 3-tuples. By providing multiple such 3-tuples, the alignment mechanism becomes more accurate and more reliable.

Optionally, the first substrate comprises at least three first receiving elements, at least three second receiving elements and at least three alignment interconnection elements. In other words, in the optional embodiment discussed above, there were at least two 3-tuples of receiving elements and alignment interconnection elements, while this optional embodiment has at least three. Provide such a 3-tuple. This results in stable positioning of the first substrate with respect to the second substrate, at least in the z dimension. It is possible to make a comparison with a table, i.e. if a table has at least three legs, this table may be positioned in a stable position on the ground, while on the other hand two legs are used. A table with a will fall over.

Optionally, at least one of the first receiving element and the second receiving element is a hole or depression in each of one of the first conductive layers and one of the second conductive layers. is there. The holes or depressions can be manufactured relatively easily. Furthermore, if the receiving element is a hole or a depression, no additional element is required for the receiving element, thus saving costs. Furthermore, if holes or depressions are made in the conductive layer only, such holes or depressions do not extend into the first and second substrates, and some electrical connection is provided inside the substrate. As such, this is advantageous in most modern electronic circuits, in other words, the other electrical connections provided to the board are not damaged or designed to avoid holes or depressions. You don't have to be. In addition, the holes or depressions may relatively easily partially receive a portion of a particular alignment interconnection element. For example, if the alignment interconnection element has a spherical shape, or is oval, it is automatically formed by a hole in the conductive layer having a size suitable to partially receive such alignment interconnection element. Partially received.

Optionally, the first receiving element is electrically coupled to one of the first conductive layers. Optionally, the second receiving element is electrically coupled to one of the second conductive layers. Optionally, the alignment interconnection element is electrically coupled to the receiving element. In addition to providing good alignment, the alignment interconnect element may serve as a conductor that provides electrical connection between the first substrate and the second substrate. To fulfill this role, the interconnect alignment element may be electrically coupled to a receiving element, which may be electrically coupled to the conductive layer of the substrate. If the receiving element is a separate element provided on the substrate, the receiving element also electrically connects to the conductive layer to provide an electrical connection between the alignment interconnection element and the conductive layer. Can be combined with. The receiving element and the interconnection element may be attached (eg, soldered) to the conductive layer and the receiving element, respectively, and the receiving element and the interconnection element may also be directly attached to the conductive layer and the receiving element, respectively. Physical contact is possible.

Note that the receiving element can be a hole in the conductive layer, and the alignment interconnection element is a spherically shaped object. When a spherically shaped object is partially provided within the hole, the spherically shaped object may contact the edge of the hole, thereby obtaining a conductive bond. In addition, a spherically shaped object partially received by the hole may be attached (eg, soldered) to the conductive layer.

Optionally, the first receiving element is thermally coupled to one of the first conductive layers. Optionally, the second receiving element is thermally coupled to one of the second conductive layers. Optionally, the interconnect alignment element is thermally coupled to the receiving element. In addition to providing good alignment, the alignment interconnection elements may be from a first substrate to a second substrate or from a second substrate to a first substrate (and optionally further, such as a heat sink, for example). Interface) and may act as a heat conductor for transferring heat.

Optionally, the plurality of interconnection elements comprises at least two interconnection elements having different depths and adapted depths to the distance between the conductive layers, between which the interconnection elements are Is located and the depth is measured in the direction of the shortest straight line from the first substrate to the second substrate at the location of the interconnection element. In this optional embodiment, at least two interconnect elements have different depths. These two interconnection elements can be alignment interconnection elements, but also two interconnection elements that have no role in the alignment of the first substrate with respect to the second substrate. In an ideal semiconductor power device, the interconnection elements have a very good contact with the conductive layer of the substrate, which is the size/depth of the interconnection elements and the respective interconnection elements arranged. Can be achieved by adapting the distance between the first substrate and the second substrate in the position where it is located. Additionally, the interconnection elements can be attached (eg, soldered) to the conductive layer, thereby increasing the cross-sectional area of the electrical connection.

In many real world applications, the first substrate would be placed parallel to the second substrate, but the distance between the first and second substrates is substantially a few micrometers. It can fluctuate in the order of. For example, the first substrate and/or the second substrate may be warped, which results in an immediate optimum if the depth of the interconnection elements does not accommodate such distance variations. Not electrical connection occurs. As a result, an open circuit may occur, rather than a connection. Additionally, the first substrate and/or the second substrate are subject to manufacturing tolerances, resulting in, for example, variations in substrate thickness and/or uneven surfaces. The conductive layer may also have a non-uniform thickness, eg, as a result of different amounts of etching or other manufacturing tolerances. Further, the conductive layer may be attached to the substrate by, for example, a particular material that adheres the conductive layer to the substrate, but the amount of this particular material may also vary along the surface of the substrate. Additionally, some of the electrical elements (not only switching semiconductor elements, but also passive elements such as resistors) may have surface electrodes to which the interconnection elements provide electrical connection, such electrical The elements have a certain thickness that must be taken into account when choosing a particular depth for the interconnection elements in contact with their electrical elements.

In a practical method of assembling a semiconductor power device, how to align a first substrate with a second substrate, assuming that one or more alignment interconnection elements are provided at that one or more locations. The exact alignment to the first is measured or determined. Then, at any required position of the interconnection element, the distance between the conductive layers at which the respective interconnection element has to be located is measured and determined. Then, according to the measured or determined distance, different interconnection elements are selected and these different interconnection elements are arranged in their required positions.

Optionally, the shape of the alignment interconnection element is one of a sphere, a square box, a cube, a cuboid, a cylinder, a tube, an oval, a rugby ball, a diamond ball, and a diamond. These shapes provide good alignment properties when used with a receiving element having a corresponding shape that can partially receive the alignment interconnection element. Optionally, the interconnection element, which is not an alignment interconnection element, has a shape that is one of a sphere, a square box, a cube, a cube, a cylinder, a tube, an oval, a rugby ball, a diamond ball, or a diamond. There may be cases. Optionally, different interconnection elements and/or different alignment interconnection elements are selected from one of sphere, square box, cube, cuboid, cylinder, tube, oval, rugby ball, rhombus ball, or rhombus It is also possible to have different shapes described. Optionally, the receiving element is a hole in each one of the conductive layers and the alignment interconnection element is a sphere. The radius of the sphere is larger than the radius of the hole. If a hole is made in the conductive layer and the hole has a radius smaller than the radius of the spherical alignment interconnect element, the hole is placed in/on the spherical alignment interconnect element, or Or, conversely, when under the influence of gravity, it will automatically partially receive the spherical alignment interconnection element in some fixed position. Thus, the alignment interconnection element can only move in the x or y direction by applying a considerable force in the x or y direction, thus the position of the alignment interconnection element relative to the position of the receiving element. Relatively well fixed. As a result, based on purely mechanical/physical effects, the alignment is performed almost automatically and well on its own.

Furthermore, the edge of the hole may contact the spherically shaped alignment interconnection element, thereby providing a good gap between the alignment interconnection element and the conductive layer (assuming the alignment interconnection element is also electrically conductive). Provides electrical contact.

It should be noted that interconnection elements that are not alignment interconnection elements may also have a spherical shape.

If the radius of the hole is relatively small with respect to the expected radius of the spherically shaped alignment interconnect element, a wide range of spherically shaped alignment interconnect elements with different radii will be present along with the relatively small hole. Can be used. For example, the expected radius of the hole is about half the expected radius of the alignment interconnect element. This provides the freedom to use different spherically shaped alignment interconnect elements during the fabrication of semiconductor power devices. For example, a particular radius for the alignment interconnect element can be selected to obtain a particular distance between the first substrate and the second substrate. The radius of the alignment interconnect element may also be affected by possible warpage of the first or second substrate, or by variations in the thickness of the conductive layer or other manufacturing tolerances. ..

The same effect if the alignment interconnection element is oval, rugby ball or diamond shaped and has a "radius" (measured midway between the first and second substrate) that is larger than the radius of the hole. Is obtained.

Optionally, the radius of the sphere is relatively large compared to the radius of the hole, especially if the hole is not very deep. The radius of the hole is small enough to ensure that when the sphere is positioned in the hole it does not touch the entire bottom but the edge of the hole. For example, the radius of a sphere is 1.3 to 2.5 times larger than the radius of a hole.

Optionally, the second substrate comprises semiconductor elements. The semiconductor element can also be a passive semiconductor element such as a diode, or a resistor made of semiconductor material, the examples of which are switching semiconductor elements discussed above. The first substrate and/or the second substrate may also comprise other electrical elements such as resistors, inductors or capacitors. The semiconductor device can also be an integrated circuit.

Optionally, one or more first conductive layers are disposed on or at the first surface. Optionally, one or more first conductive layers are arranged on or at the surface of the switching semiconductor element facing away from the first surface. Optionally, one or more second conductive layers are disposed on or at the second surface. Optionally, one or more second conductive layers are arranged on or at the surface of the semiconductor device. It should be noted that there may be some other material present between the conductive layer and the substrate, switching semiconductor element or semiconductor element, examples of such other materials are: It is some kind of adhesive, gel, epoxy resin or brazing. The conductive layer provided on the surface of the switching semiconductor element or on the surface of another electrical element may also be referred to as a "surface electrode".

According to another aspect of the invention, a method of assembling a power semiconductor device is provided. The method comprises: i) obtaining a first substrate with switching semiconductor elements, the first substrate having a first surface, the first conductive layer and the first receiving element. Locally comprising the switching semiconductor element being provided on a first surface, and ii) obtaining a second substrate having a second surface facing the first surface. A second substrate comprising a second receiving element and locally comprising a second conductive layer, vi) obtaining an alignment interconnection element, and v. ) Providing an alignment interconnection element to one of the first and second receiving elements to affect the partial reception of the alignment interconnection element by said receiving element; vi) said Providing the alignment interconnection element to one of the first and second receiving elements to affect the partial reception of the alignment interconnection element by the receiving element.

The method according to the above aspects of the invention provides the same advantages as the power semiconductor device according to the first aspect of the invention and has similar embodiments with similar effects as the corresponding embodiments of the system. Therefore, this method is an efficient and effective method for manufacturing a power semiconductor device in which the first substrate is properly aligned with the second substrate. In particular, as discussed above, the receiving element and the alignment interconnection element are provided between the first substrate and the second substrate (assuming the receiving element is provided in the correct position). It provides an effective mechanical means to ensure that the alignment is accurate. To ensure the accurate positioning of the second substrate with respect to the first substrate during the step of fixing the conductive alignment interconnection element to another one of the first receiving element and the second receiving element. , No additional sensors and/or actuators are required, ie correct alignment is automatically ensured by the partial reception of the alignment interconnection element by the receiving element. Even if the pre-alignment step is relatively weak, this mechanism ensures that it will correct itself towards the final correct alignment.

In this method, a first substrate and a second substrate are obtained. In an optional embodiment, obtaining the first substrate and/or obtaining the second substrate comprises manufacturing the first substrate and/or the second substrate.

Optionally, the method of assembling a power semiconductor device comprises: a) obtaining data describing required positioning of the first substrate relative to the second substrate; and b) first receiving element and second receiving element. And c) determining a property of the alignment interconnect element based on the acquired data and the measured property, the step of acquiring the alignment interconnect element. At, alignment interconnection elements are obtained based on the determined characteristics.

The data obtained to describe the required positioning of the first substrate with respect to the second substrate may include the required distance between the first substrate and the second substrate, but at a particular location. , May include more information, such as the distance between substrates must be a particular value, at another particular location the distance between substrates must be another particular value, and so on.

At the stage of measuring the characteristics of the first receiving element and the second receiving element, for example, the shape of each receiving element is determined. Another characteristic may be the distance that the receiving element projects from the surface of the substrate if the receiving element is some kind of projection. Measuring the property may also include determining the exact position of the receiving element.

In the step of determining the characteristic of the alignment interconnection element, the obtained alignment interconnection element has the determined characteristic and is at least partially received by the first receiving element and partially by the second receiving element. If so, the first substrate is positioned as described in the data required for the second substrate, in other words, the first substrate is relative to the second substrate. Ensures proper alignment. For example, at this stage the shape of the alignment interconnect element is selected and/or the length/depth of the alignment interconnect element is selected. For example, if the available alignment interconnection elements are spheres and the receiving elements are holes, then a particular radius is selected for the spherically shaped alignment interconnection elements. In a particular embodiment, the receiving elements are strictly opposite each other, for example when the first substrate is positioned as described in the data obtained for the second substrate. If not, during the determination of the properties of the alignment interconnection element, a particular shape may be chosen in which the receiving elements are not exactly opposite one another, but still result in good alignment. ..

Providing the alignment interconnection element to one of the receiving elements means bringing the alignment interconnection element into contact with the receiving element such that it is partially received by the receiving element. This can be done by simply placing the alignment interconnection element over the receiving element, or by placing the receiving element over the alignment interconnection element and using gravity to align the alignment interconnection element or the receiving element. This can be done by moving the interconnection element to a position partially received by the receiving element. In certain embodiments, it may include providing a force to ensure that the alignment interconnection element is partially received by the receiving element.

The alignment interconnect elements used in this method can be manufactured from a conductive material.

Optionally, at least one of said steps of providing a conductive alignment interconnection element to said receiving element comprises i) soldering said conductive alignment interconnection element to said receiving element; and ii) said conductive element. And sintering the alignment interconnection element of said to said receiving element. Using one of these fastening techniques ensures that a good electrical connection and/or a good thermal path is obtained from the receiving element to the alignment interconnection element.

Optionally, if the receiving element is a hole or an indent, the step of measuring the characteristics of the first receiving element and the second receiving element determines the radius of the receiving element and Determining the depth, the radius of the first receiving element is measured in a plane substantially parallel to the first surface, and the radius of the second receiving element is The depth of the first receiving element is measured in a plane substantially parallel to the surface of the first receiving element and the depth of the second receiving element is measured in a plane substantially perpendicular to the first surface. Measured in a plane substantially perpendicular to the surface of the. It should be noted that the holes or depressions may extend only into the conductive layer, or into the substrate, or into the combination of the conductive layer and the substrate. ..

These and other aspects of the invention will be apparent from, and will be apparent with reference to, the embodiments described hereinafter.

It will be understood by those skilled in the art that two or more of the options, implementations, and/or aspects of the invention referred to above may be combined in any way deemed useful. You will understand.

Modifications and alterations of the device and/or method correspond to those described for the device and may be performed by one of ordinary skill in the art based on this specification.

1 is a schematic exploded view of an embodiment of a semiconductor power device. FIG. 2 is a schematic cross-sectional view of the embodiment of the semiconductor power device of FIG. 1 taken along a plane passing through a straight line II-II′ and perpendicular to the first substrate. FIG. 6 is a schematic cross-sectional view of another embodiment of a semiconductor power device. FIG. 6 is a schematic diagram of an embodiment of a second substrate. 3 is a schematic view of an embodiment of a first substrate. FIG. 1 is a schematic diagram of an embodiment of a semiconductor device. 3 is a schematic view of a method of assembling a power semiconductor device.

It should be noted that items designated by the same reference numeral in different drawings have the same structural feature and the same function, or the same signal. Where the function and/or structure of such an item is described, there is no need to repeat the description regarding it in this detailed description.

The drawings are purely schematic and not drawn to scale. In particular, some dimensions have been transiently highlighted for purposes of clarity.

FIG. 1 schematically illustrates an embodiment of a semiconductor power device 100 as an exploded view. The semiconductor power device comprises a first substrate 140, a second substrate 110 and an interconnect structure. The first substrate 140 has a first surface 141 on which a switching semiconductor element 144 is provided. The first substrate further comprises first conductive layers 142, 146. The first substrate 140 further comprises a first receiving element 150, which in this particular embodiment is a hole in one of the first conductive layers 146. The second substrate 110 has a second surface 111 facing towards the first surface 141 and comprises second conductive layers 112, 116 provided on the second surface. The second substrate 110 further comprises a second receiving element 120, which in this particular embodiment is a hole 150 in one of the second conductive layers 116. The interconnect structure provides at least one electrical connection between one of the first conductive layers 142, 146 and one of the second conductive layers 112, 116. In the example of FIG. 1, two electrical connections are provided: one between the first conductive layer 142 and the second conductive layer 112, and the first conductive layer 146 and the second conductive layer 116. And one in between. The interconnect structure comprises interconnecting elements 130, 132, one of which is the alignment interconnecting element 130. In the example of FIG. 1, interconnect element 132 and alignment interconnect element 130 are spheres made of a conductive material (eg, copper). The interconnection element 132 is disposed between the first conductive layer 142 and the second conductive layer 112. The alignment interconnect element 130 is at least partially received by the first receiving element 150 and at least partially by the second receiving element 120. It is observed in FIG. 1 that the radius of the first receiving element 150 and the second receiving element 120 is smaller than the radius of the alignment interconnection element 130. This means that when the spherical alignment interconnection element 130 contacts the respective receiving element 120, 150, a portion of the spherical alignment interconnection element 130 is received by the hole forming the respective receiving element 120, 150. Means A small portion of the alignment interconnect element 130 that is spherical projects into the holes 120, 150 in the respective conductive layers 116, 146, which causes the alignment interconnect element 130 that is spherical to have the first surface 141 and/or the first surface 141. It is impossible to roll to another position on the second surface 111, which means that the relative position of the first substrate 140 is fixed with respect to the relative position of the second substrate 110.

The switching semiconductor device 144 may be a transistor, a field effect transistor (FET), a MOS field effect transistor (MOSFET), a thyristor, an insulated gate bipolar transistor (IGBT) or any other suitable type of semiconductor switching device. The first substrate 140 and/or the second substrate 110 may also be made of other semiconductor materials such as silicon, silicon carbide, gallium arsenide, gallium nitride, diamond based semiconductor materials or other suitable semiconductor materials. It should be noted that other electronic devices may be included, including those in. Examples of other electronic devices are diodes, resistors, capacitors, inductors, integrated circuits, or any other suitable electronic device.

Substrates 110, 140 may be manufactured with multiple layers of thermally and electrically insulating materials (eg, ceramics) and highly conductive materials (eg, metals) for routing. Examples of ceramics are aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ) or silicon nitride (Si ₃ N ₄ ). Other examples of the substrate are Si ₃ N ₄ sandwiched between, for example copper or two thin metal layer is a thin layer of aluminum. Typically, in the related art, such substrates are referred to as direct bond copper (DBC) substrates or active metal bonding/brazing (AMB) substrates. A suitable substrate is the paper by Manfred Goetz et al. at the PCIM Europe conference in Nuremberg May 14-16, 2013, "Comparison of Silicone Nitridef berth der Bunds der DBCande der DBCandres de DBCande. in power electronics", pages 57-65.

Conductive layers 112, 116, 142, 146 and/or interconnect elements 130, 132 may be made of metals such as copper and aluminum, other metals, or other conductive materials. Optionally, the material from which the conductive layers 112, 116, 142, 146 and/or the interconnection elements 130, 132 are made is such that the layers 112, 116, 142, 146 and the interconnection elements 130, 132 have good thermal properties. A conductor that contributes to the distribution and conduction of heat to a location (not shown) (eg, interface to a heat sink) where heat can be conducted away from the semiconductor power device 100.

Instead of the conductive layers 112, 116, 142, 146, it may be read as “electrode”. However, it should be noted that the conductive layers 112, 116, 142, 146 are not by definition coupled to a particular voltage or signal. Thus, the conductive layers 112, 116, 142, 146 can be isolated islands provided on the first surface 111 or the second surface 141. They may also be electrically connected to other elements of the semiconductor power device 100, such as switching semiconductor elements. This may be due to an additional conductive layer (not shown) provided on the first or second surface and/or an additional electrical connection (not shown) provided inside the substrate. ) And/or an additional conductive layer provided on the surface of the first substrate 140 and the second surface 110 facing away from the gap between the two substrates 110, 140 (FIG. (Not shown) and/or by conductive vias through these substrates.

In the example of FIG. 1, semiconductor power device 100 is provided with a single alignment interconnect element 130. However, two, three or more alignment interconnection elements may be provided, each with a receiving element coupled to the first substrate and a receiving element coupled to the second substrate. obtain. In all the examples below, only one or two alignment interconnection elements (and corresponding receiving elements) have been drawn and discussed, but those skilled in the art will appreciate that more than one or two such alignment elements may be used. Alignment interconnection elements (with corresponding receiving elements) may be provided. In particular, it should be noted that the use of three (or more) alignment interconnection elements results in stable positioning of the second substrate 110 with respect to the first substrate 140. Is.

The material of the alignment interconnect element 130, and also the material of the interconnect element 132, can be a conductive material such as copper or aluminum. In the example of FIG. 1, alignment interconnect element 130 is partially received by holes 120, 150 in respective conductive layers 116, 146. This means that the alignment interconnect element 130 contacts the edges of the holes 120, 150 formed by the material of the respective conductive layers 116, 146. As a result, there will be an electrical connection between the alignment interconnect element 130 and the respective conductive layer 116, 146. In order to improve the electrical connection (and/or better fix the position of the alignment interconnect element 130), the alignment interconnect element 130 may be soldered (not shown) or any other suitable anchor. It may be fixed to the respective conductive layer 116, 146 by a material (not shown) or by a fixing method. The use of such additional fastening material may also be applied to the contacts between the interconnection elements 132 and their respective conductive layers 112, 142. Further, it should be noted that the interconnection element 132 is at least in contact with its respective conductive layer 112, 142 such that there is an electrical connection therebetween. Also, the material of the alignment interconnect element 130 and the interconnect element 132 is thermally conductive so that heat can be transferred, for example, from the first substrate 140 to the second substrate 110. obtain. Heat may be generated at the switching semiconductor device 144. Copper is also a good heat conductor. The amount of heat that can be carried through the alignment interconnect element 130 can be increased by soldering the alignment interconnect element 130 to the respective conductive layers 116, 146. These optional choices for materials for the elements of the interconnect structure also apply to the alignment interconnect elements and interconnect elements in the examples discussed below. As discussed below, first substrate 140 and/or second substrate 110 may be provided with a heat sink (not shown) that forms a heat transfer interface to the environment.

The shape of interconnect element 132 and alignment interconnect element 130 is a sphere. Embodiments of interconnect element 132 and alignment interconnect element 130 are not limited to these shapes. Other possible shapes are: square box, cube, cuboid, cylinder, tube, oval, rugby ball, rhombus ball, and rhombus.

Although the receiving elements 120, 150 are holes in the example of FIG. 1, embodiments of the receiving elements 120, 150 are not limited to such shapes. Any shape, such as capable of receiving a portion of the alignment interconnection element, thereby fixing the relative position of the alignment interconnection element with respect to the receiving element, is a suitable shape. For example, if the alignment interconnect element has a cylindrical shape, a portion of the cylindrical shape may be received by the hole or depression, but also by a hollow cylinder extending from the surface of the substrate.

Although not explicitly shown in FIG. 1, the first substrate 140 and/or the second substrate 110 may include additional active semiconductor devices (eg, transistors, or any other type of switching semiconductor). Elements), additional passive semiconductor elements (eg, resistors based on diodes or semiconductor materials), and/or other passive electrical elements (eg, resistors, capacitors and/or inductors). It may include elements.

2a schematically shows a cross-sectional view of the embodiment of the semiconductor power device 100 of FIG. 1 along a plane perpendicular to the first substrate 140 and passing through the line II-II'. The semiconductor power device 100 includes a first substrate 140, a second substrate 110, and an interconnection structure. The first substrate 140 has a first surface 141, comprises first conductive layers 142, 146 provided on the first surface 141, and provides switching on the first surface 141. The semiconductor device 144 is provided. The second substrate 110 comprises a second surface 111 facing the first surface 141. The second substrate 100 comprises second conductive layers 112, 116 provided on the second surface 111. The first conductive layer 146 and the second conductive layer 116 both comprise receiving elements 120, 150 having the shape of holes in the respective conductive layers 116, 146. The interconnect structure comprises an alignment interconnect element 130, which is a metal sphere partially received by holes in the respective conductive layers 116, 146 forming the receiving elements 120, 150. The interconnect structure also includes an interconnect element 132 disposed between the first conductive layer 142 and the second conductive layer 112. The alignment interconnect element 130, like the interconnect element 132, provides an electrical connection between each particular first conductive layer 142, 146 and each particular second conductive layer 112, 116.

The receiving elements 120, 150 are, for example, circular holes. The radius r1 of the circular receiving element 150 is shown in FIG. 2a. The radius of the receiving element 120 is substantially equal to the radius r1 of the receiving element 150. The alignment interconnection element 130 is a sphere, the radius r2 of which is shown in Figure 2a. The radius r1 of each of the circular receiving elements 120, 150 is smaller than the radius r2 of the spherical alignment interconnection element 130. It should be noted that the radius of the receiving element 120 is related to the radius r2 of the spherical alignment interconnection element 130 in a similar manner. A typical example is: the thickness of the conductive layer is about 300 μm, the radius r1 of the hole forming the receiving element 150 is 1 mm and the radius r2 of the spherical alignment interconnection element is 1.6 mm. In one embodiment, depending on the depth of the hole forming the receiving element 150, the radius r1 of the receiving element 150 is such that the spherical alignment interconnection element 130 does not contact the bottom of the hole forming the receiving element 150 and is conductive. It is relatively small compared to the radius r2 of the spherical alignment interconnection element 130 so that it touches the entire edge at the top of the layer.

FIG. 2b shows a cross-sectional view of another embodiment of semiconductor power device 200. The semiconductor power device 200 comprises a first substrate 240, a second substrate 210 and an interconnect structure.

The first substrate 240 includes a first surface 241, a switching semiconductor element 244, and first conductive layers 246 and 242. The switching semiconductor element 244 is provided on the first surface 241 and one specific first conductive layer 246 is provided on the first surface 241. Another first conductive layer 242 is provided on the surface of the switching semiconductor element 244 facing away from the first substrate 240. The first substrate 240 also includes a first receiving element 250 that has a recess that projects away from the first conductive layer 246 and that conforms to the shape of a diamond-shaped element. The second substrate 210 has a second surface 211 facing in the direction of the first surface 241. The first substrate 240 is also coupled to a heat sink 298 (optional) that is thermally coupled to the first substrate 240 at the first substrate 210 facing away from the first surface 241.

The second substrate 210 has a second conductive layer 212 and optionally another second conductive layer 216. The second substrate 210 also comprises a second receiving element 220. The second receiving element 220 projects away from the second surface 211 and has a depression that matches the shape of the diamond-shaped element.

The interconnect structure of the semiconductor power device of FIG. 2b comprises a spherically shaped interconnect element 232 electrically and thermally coupled to the first conductive layer 242 and the second conductive layer 212 by a mounting joint 299. ing. The mounting joint 299 may be formed of solder, adhesive, epoxy resin, or it may be a ceramic material formed by a sintering process. The interconnect structure also comprises a diamond-shaped alignment interconnect element 230. One end of the diamond-shaped alignment interconnection element 230 has a shape corresponding to the shape of the recess of the first receiving element 250, and the opposite end of the diamond-shaped alignment interconnection element 230 has a second shape. Has a shape corresponding to the shape of the recess of the receiving element 220 of. Each end of the diamond-shaped alignment interconnection element 230 is received by a recess in the first receiving element 250 and a recess in the second receiving element 220. Thus, the receiving elements 220, 250 at least partially receive the diamond-shaped alignment interconnection elements 230. As a result of partially receiving the diamond-shaped alignment interconnection element 230, alignment of the position of the first substrate 140 with respect to the second substrate 110 is obtained.

It has already been shown in FIG. 2b that the shape and size of the alignment interconnection element 230 must be adapted to the shape and size of the receiving elements 220,250. In particular, the length of the alignment interconnect element 230 (measured along a straight line parallel to the shortest straight line from the first substrate 140 to the second substrate 110) and the receiving elements 250, 220 on the first surface. 141 and the amount of protrusion in the direction away from the second surface 211 are each the first substrate 240 relative to the second substrate 210 in the z dimension (and thus the distance between the substrate 210 and the substrate 240). Determine the positioning of. The size of the interconnection element 232 is adapted to the required distance (in the z dimension) between the two substrates 210, 240 and to the depth of the conductive layers 212, 242 and the switching semiconductor element 244. As shown in exaggerated form in FIG. 2b, the second substrate 210 may be subject to warpage. The size of the interconnection element 232 also depends on the particular distance between the first substrate 240 and the second substrate 210 where the interconnection element 232 is provided so that a good electrical connection is obtained. Has been adapted. During assembly of the semiconductor power device, how large should the interconnect element 232 be in order to obtain good contact between the interconnect element 232 and the respective conductive layers 212, 242? The amount of warp is determined (eg, measured) to determine It also shows that different sized interconnect elements are used, and that different sized interconnect elements must be used if the distance between the substrates and/or the conductive layers varies. Immediately apparent from 2b. The size of the interconnection elements is determined based on the decisions discussed above. In an optional embodiment, there are at least two interconnect elements having different sizes (both are not alignment interconnect elements).

FIG. 3a shows a schematic diagram of an embodiment of a second substrate 310 for use in a semiconductor power device. In this figure, the second surface 311 of the second substrate 310 faces towards the viewer. On this second surface 311, a plurality of conductive layers are provided, some of which are indicated by reference numerals 312,..., 318. A number of circular shaped holes (depicted by the black filled circles) are provided in the conductive layer, some of which are indicated by reference numeral 320. The circular shaped hole is a receiving element that at least partially receives the alignment interconnection element.

FIG. 3b shows a schematic diagram of one embodiment of a first substrate 340 for use in the same semiconductor power device as that of the second substrate 310 of FIG. 3a. In this figure, the first surface 341 of the first substrate 340 is facing the viewer. When the semiconductor power device is assembled, the first surface 341 should face the second surface 311 of the second substrate 310. A plurality of conductive layers are provided on the first surface 341, one of which is indicated with reference numeral 342. When the first substrate 340 is assembled facing the second substrate 310, the conductive layer 342 faces the conductive layer 316 of the second substrate 310. Some of the conductive layers are electrically coupled to external electrodes 381 or external pins 382. When the semiconductor power device is assembled, the external electrodes 381 and the external pins 382 are for receiving and/or providing control signals for receiving power signals that must be controlled by the semiconductor power device.

Optionally, on the first surface, a switching semiconductor element 344 is provided directly on one of the conductive layers. These switching semiconductor elements 344 include surface electrodes made of a conductive material. One of the surface electrodes is indicated with reference numeral 345. The surface electrode is provided on the surface of the switching semiconductor element 344 facing away from the first surface 341.

In FIG. 3 b, six circles are drawn with a solid black fill, some of which are indicated with reference numeral 350. The six circles represent circular holes in the conductive layer, which are receiving elements for at least partially receiving the alignment interconnection elements. Upon careful consideration of FIGS. 3b and 3a, the portion of the receiving element of the first substrate 340 is the second substrate when the first substrate 340 and the second substrate 310 are assembled into a semiconductor power device. It may be noted that it is adapted to face the receiving element of 310. Although not shown, the alignment interconnect element may be (at least partially) received by a receiving element of the first substrate 340 or a receiving element of the second substrate 310. In one embodiment, a suitable alignment interconnect element is a copper sphere having a radius larger than the radius of the receiving element. For example, a copper sphere is placed over the receiving elements of the first substrate 340 and optionally attached to the conductive layer on which each receiving element is provided (eg, soldered or sintered). ). Then, if the second substrate 310 is placed on top of these copper spheres around the location where a portion of the copper spheres are received by the receiving elements of the second substrate 310, the second substrate 310 is The receiving element of the substrate 340 will receive a portion of the copper sphere, so that the position of the second substrate 310 is fixed at the position of the first substrate 340 (in other words, aligned). ). The copper spheres are also attached (eg, soldered or sintered) to the conductive layers of the second substrate 310 where the respective receiving elements are provided.

In the view of FIG. 3b, the interconnection elements are depicted by small circles. Several interconnect elements are indicated with reference numeral 332. Also, interconnection elements are provided on top of the switching semiconductor elements 344. In the embodiment of Figure 3b, the interconnection elements are copper spheres that can be attached (eg, soldered or sintered) to their respective conductive layers or their respective surface electrodes. When the second substrate 310 is placed on top of the first substrate (and the alignment interconnection elements are partially received by the receiving elements of both substrates), the interconnection elements are moved to the second substrate. It contacts a particular conductive layer provided on the second surface 311 of 310 and provides an electrical and thermally conductive connection between the first substrate 340 and the second substrate 310. Optionally, the interconnection elements are attached (eg, soldered or sintered) to the conductive layer of the second substrate 310 with which they are in contact.

FIG. 4 schematically illustrates a side view of one embodiment of the semiconductor power device 400. The arrow shown using IV in FIG. 3b indicates the direction of the person looking at the figure, from which this side view is obtained. The semiconductor power device 400 shows an assembled semiconductor power device 400 comprising each of the first substrate 340 and the second substrate 310 of FIGS. 3b and 3a.

The semiconductor power device 400 of FIG. 4 comprises a substrate 340 and a second substrate 310, wherein the interconnection structure comprises an alignment interconnection element 430, interconnection elements 332, 332' and two cooling fins 498. It has and. As discussed in the context of Figure 3b, the second substrate comprises external pins/contacts 381,382. In the semiconductor power device 400, the first surface 341 of the first substrate 340 faces the second surface 311 of the second substrate 310.

Above the first surface 341 is provided a first conductive layer 342, which in the side view of FIG. 4 is depicted as a black line on the first surface 341. Provided on the second surface 311 is a second conductive layer 312, which in the side view of FIG. 4 is depicted as a black line on the second surface 311.

The cooling fins 498 are provided on the surface of the second substrate 310 facing away from the first surface 341 and the second surface 311, and on the surface of the first substrate 340, respectively. .. The cooling fins 498 receive heat from the respective substrates 310, 340 and provide this heat to the environment of the semiconductor power device 400. In a particular assembly, multiple semiconductor power devices 400 may be integrated, for example, in a larger assembly with means for providing active cooling to cooling fins 498.

The interconnect structure provides a plurality of electrical connections between the first conductive layer 342 and the second conductive layer 312. It is observed that a plurality of interconnection elements 332, 332' are attached (eg, soldered) to the respective conductive layers 342, 312. It can also be observed that the radius of the interconnection element 332' is smaller than the radius of the interconnection element 332. This may be due to the interconnection element 332′ being between the electrodes provided on the semiconductor element, or at the location of the interconnection element 332′ the distance between the respective conductive layers. It may be due to being smaller than in other locations.

The interconnect structure also comprises an alignment interconnect element of which one particular alignment interconnect element 430 can be observed in FIG. Alignment interconnect element 430 is partially received by a hole in one of first conductive layers 342 and partially by a hole in one of second conductive layers 312. The radius of the alignment interconnect element 430 is larger than the radius of the hole that receives the alignment interconnect element 430. In addition, the alignment interconnect elements 430 have a larger radius than the other interconnect elements 332, 332' because the alignment interconnect elements 430 partially project into their respective conductive layers.

FIG. 5 schematically illustrates a method 500 of assembling a power semiconductor device. A method 500 of assembling a power semiconductor device includes
A step 502 of obtaining a first substrate with switching semiconductor elements, the first substrate having a first surface and locally comprising a first conductive layer and a first receiving element. A switching semiconductor element is provided on the first surface, the obtaining step 502;
A step 504 of obtaining a second substrate with a second surface facing the first surface, the second substrate comprising a second receiving element and locally providing a second conductive layer. Preparing for step 504 to obtain,
Obtaining 512 an alignment interconnection element,
Providing 514 an alignment interconnection element to one of the first receiving element and the second receiving element to affect the partial reception of the alignment interconnection element by said receiving element;
Providing 516 an alignment interconnection element to the other of the first and second receiving elements to affect the partial reception of the alignment interconnection element by said receiving element;
Equipped with.

Optionally, method 500 also:
Obtaining 506 data describing the required positioning of the first substrate with respect to the second substrate;
-Determining 508 a characteristic of the first receiving element and the second receiving element;
Determining 510 the properties of the alignment interconnection elements based on the acquired data and the measured properties, wherein the step 512 of obtaining the alignment interconnection elements comprises the properties of the alignment interconnection elements. Based on the result of the step 510 of determining (in other words, the obtained alignment interconnection element has substantially the determined characteristic).

Data describing the required positioning of the first substrate relative to the second substrate is obtained at 506, which data may include a required distance between the first substrate and the second substrate, , The distance between these substrates must be a specific value, at another specific position the distance between these substrates must be another specific value, etc. It may contain information.

At the stage of measuring the characteristics of the first receiving element and the second receiving element at 508, for example, the shape of each receiving element is determined. Another characteristic may be the distance that the receiving element projects from the surface of the substrate if the receiving element is any kind of projection. Measuring the property can also include determining the exact location of the receiving element.

In the step of determining 510 a characteristic of the alignment interconnection element, the obtained alignment interconnection element has the determined characteristic and is at least partially received by the first receiving element and by the second receiving element. If at least partially received, the first substrate is positioned relative to the second substrate as described in the requested data, in other words the first substrate is relative to the second substrate. And is properly aligned. For example, at this stage, the shape of the alignment interconnect element and/or the length of the alignment interconnect element is selected. For example, if the available alignment interconnect elements are spheres and the receiving elements are holes, then at this stage a particular radius is selected for the spherically shaped alignment interconnect elements. In a particular embodiment, for example, the receiving elements are not strictly opposite one another and the first substrate is positioned as described in the data acquired for the second substrate. In some cases, the step of determining the properties of the alignment interconnection element may select a particular shape that results in good alignment even though the receiving elements are not exactly opposite one another.

Providing the alignment interconnection element to one of the receiving elements at 514, 516 means contacting the alignment interconnection element with the receiving element such that it is partially received by the receiving element. This is done by placing the alignment interconnection element over the receiving element, or by placing the receiving element over the alignment interconnection element and using gravity to force the alignment interconnection element or the receiving element into contact with the alignment interconnection element. This can be done by moving it to a position such that it is partially received by the receiving element. In certain embodiments, it may comprise providing a force that ensures that the alignment interconnection element is partially received by the receiving element.

In one embodiment, providing an alignment interconnection element to one of the first receiving element and the second receiving element at 514 includes soldering the alignment receiving element to the receiving element at 534, or Sintering the alignment interconnection element to the receiving element at 536. Generally, at this stage, the alignment interconnection element is attached to the receiving element.

In one embodiment, providing an alignment interconnection element to one of the first receiving element and the second receiving element at 516 includes soldering the alignment receiving element to the receiving element at 538, or Sintering the alignment interconnection element to the receiving element at 540. Generally, at this stage, the alignment interconnection element is attached to the receiving element.

In one embodiment, if the receiving element is a hole or depression, measuring the characteristic of the first receiving element and the second receiving element at 508 determines a radius of the receiving element at 538. And determining the depth of said receiving element at 540, wherein the radius of the first receiving element is measured in a plane substantially parallel to the first surface, and The radius of the receiving element is measured in a plane substantially parallel to the second surface and the depth of the first receiving element is measured in a plane substantially perpendicular to the first surface, The depth of the receiving element is measured in a plane substantially perpendicular to the second surface.

In one embodiment, obtaining the first substrate at 502 comprises manufacturing or assembling the first substrate at 542. Manufacturing or assembling at 542 includes providing a first conductive layer and a switching semiconductor element on a first surface and providing a first receiving element on a first substrate. May be included.

In one embodiment, obtaining the second substrate at 504 comprises manufacturing or assembling the second substrate at 544. Manufacturing or assembling at 544 may include providing a second conductive layer on the second surface and providing a second receiving element on the second substrate.

In FIG. 5, the steps of the method are presented in a particular order. The method is not limited to the shown order of steps of the method. Unless the particular steps are directly dependent on each other, they may be executed in another order and/or in parallel.

The embodiments described above are illustrative of the invention rather than limiting, and a person skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. Would be possible.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb "comprise" and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article “a” or “an” preceding an element does not exclude the presence of a plurality of that element. The present invention may be implemented by hardware with several separate elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to produce an effect.

A first aspect of the invention provides a method of assembling a semiconductor power device. Advantageous embodiments are defined in the dependent claims.

The first semiconductor power device assembled Ri by the aspect of the present invention includes a first substrate, a second substrate, an interconnect structure. The first substrate includes a switching semiconductor element. The first substrate has a first surface and locally comprises a first conductive layer and a first receiving element. A switching semiconductor device is provided on the first surface. The second substrate comprises a second surface facing the first surface. The second substrate comprises a second receiving element and locally comprises a second conductive layer. The interconnect structure is for providing at least one electrical connection between at least one of the first conductive layers on one side and at least one of the second conductive layers on the other side. The interconnect structure comprises a plurality of interconnect elements that are electrically conductive materials. At least one of the plurality of interconnection elements is an alignment interconnection element. The alignment interconnection element is partially received by the first receiving element and partially by the second receiving element to align the relative position of the first substrate with respect to the second substrate. .. The receiving element has a recess having a shape for at least partially receiving an alignment interconnection element, when the receiving element and the alignment interconnection element are abutted against each other, and the alignment interconnection element or said The shape of the alignment interconnection element is selected to affect the positioning of the alignment interconnection element in a unique and fixed relative position with respect to the reception element when one of the reception elements is subjected to a force. As described above, the first substrate is aligned with the second substrate.

The power semiconductor device according to the embodiment discussed above, the alignment of the first substrate to the second substrate is provided as follows. Receiving elements configured to receive alignment interconnection elements at appropriate locations on the first substrate and at appropriate corresponding locations on the second substrate are provided. The first receiving element receives a portion of the alignment interconnect element, the second receiving element also receives a portion of the alignment interconnect element, and a relative position of the first substrate with respect to the second substrate (required). 3.) When it comes to the aligned position, the appropriate position is selected and the specific size and shape of the alignment interconnect element is selected. Since the receiving element receives a portion of the alignment interconnect element, the position of the alignment interconnect element is fixed with respect to the position of the receiving element, and consequently the relative position of the first substrate with respect to the second substrate. It Furthermore, the shape of the recess of the receiving element and the shape of the alignment interconnection element are such that they are unique and fixed of the alignment interconnection element to the receiving element when they are brought into contact with each other under the influence of a force. There are only one possible specific relative arrangements of alignment interconnection elements with respect to the receiving element, as they are chosen together to cooperate towards position. By the above, the receiving elements are forced towards a properly defined and fixed relative position with respect to each other, whereby the substrates are forced towards a properly defined and fixed relative position with respect to each other. It In most embodiments, it is added to the receiving element or alignment interconnection element forces but may be gravity, can also be a force applied actively to one of those elements. As a result of aligning these substrates towards a unique and fixed relative position with respect to each other, the pattern of the first conductive layer is aligned with the pattern of the second conductive layer. It should be noted that Thus, it will be seen in the present application that the receiving element and the alignment interconnection element have the function of aligning the patterns of said conductive layer with respect to each other.

According to the background discussion, a Cartesian coordinate system can be defined in a semiconductor power device. The I Ri assembled semiconductor power device of the present invention, the shape and size of the receiving element and the alignment interconnecting elements defining a distance between the two substrates, as a result, the first to the second substrate It defines the relative position of the substrate in the z dimension. The position of the first receiving element on the first substrate and the position of the second receiving element on the second substrate define the relative alignment of the two substrates in the x and y dimensions. ..

According to one embodiment, is disposed on the elements of both receiving and alignment interconnection elements elements of the top of each other, a force is received by one of these elements, when in the position in which the other element is fixed The part of the alignment interconnection element is automatically received by the receiving element. For example, when the alignment interconnection element is placed over a receiving element having a fixed position, gravity is received by the alignment interconnection element and as a result of this force, the alignment interconnection element is caused by the respective receiving element. Partially received, gravity forces the alignment interconnection elements towards a unique, fixed position. In one example, the alignment interconnection element has a spherical shape and the receiving element is a hole: when the spherical shape is placed on top of the hole, the spherical shape automatically, at least partially, Received by the hole, this sphere rotates towards one unique position so that it is optimally partially received by the receiving element. This has the effect that the alignment is done automatically during assembly of the power semiconductor device and no separate steps are required to force the receiving element to receive part of the alignment interconnection element. Have.

Optionally, the first substrate comprises a plurality of first receiving elements, the second substrate comprises a plurality of second receiving elements and the interconnection element comprises a plurality of alignment interconnection elements. Wherein each one of the plurality of alignment interconnection elements is partially received by each one of the first receiving elements to align the relative position of the first substrate with respect to the second substrate, and Partially received by each one of the receiving elements. In other words, there are a plurality of 3-tuples, each of the plurality of 3-tuples comprising a first receiving element, a second receiving element and an alignment interconnection element. The position of the first receiving element of the 3-tuple on the first substrate is such that the alignment element and the alignment receiving element of the particular 3-tuple are at least partially received by the receiving element of the 3-tuple. The combination with the connecting element corresponds to a position on the second substrate in order to obtain the effect of providing the required alignment in the x and y dimensions. The semiconductor power device discussed above is provided with the at least one such 3-tuple, on the other hand, this embodiment includes a plurality of such 3-tuple. By providing multiple such 3-tuples, the alignment mechanism becomes more accurate and more reliable.

Optionally, the first substrate comprises at least three first receiving elements, at least three second receiving elements and at least three alignment interconnection elements. In other words, in the example previously discussed, the 3-tuple of the receiving element and the alignment interconnection element is present at least two, on the other hand, this embodiment, at least three such 3-tuple provide. This results in stable positioning of the first substrate with respect to the second substrate, at least in the z dimension. It is possible to make a comparison with a table, i.e. if a table has at least three legs, this table may be positioned in a stable position on the ground, while on the other hand two legs are used. A table with a will fall over.

Optionally, the plurality of interconnection elements comprises at least two interconnection elements having different depths and adapted depths to the distance between the conductive layers, between which the interconnection elements are Is located and the depth is measured in the direction of the shortest straight line from the first substrate to the second substrate at the location of the interconnection element. In this example , at least two interconnect elements have different depths. These two interconnection elements can be alignment interconnection elements, but also two interconnection elements that have no role in the alignment of the first substrate with respect to the second substrate. In an ideal semiconductor power device, the interconnection elements have a very good contact with the conductive layer of the substrate, which is the size/depth of the interconnection elements and the respective interconnection elements arranged. Can be achieved by adapting the distance between the first substrate and the second substrate in the position where it is located. Additionally, the interconnection elements can be attached (eg, soldered) to the conductive layer, thereby increasing the cross-sectional area of the electrical connection.

According to a first aspect of the invention, a method of assembling a power semiconductor device is provided. The method comprises: i) obtaining a first substrate with switching semiconductor elements, the first substrate having a first surface, the first conductive layer and the first receiving element. Locally comprising the switching semiconductor element being provided on a first surface, and ii) obtaining a second substrate having a second surface facing the first surface. A second substrate comprising a second receiving element and locally comprising a second conductive layer, vi) obtaining an alignment interconnection element, and v. ) Providing an alignment interconnection element to one of the first and second receiving elements to affect the partial reception of the alignment interconnection element by said receiving element; vi) said Providing the alignment interconnection element to one of the first and second receiving elements to affect the partial reception of the alignment interconnection element by the receiving element.

The method according to the above aspects of the present invention provides a first same advantage as by Ri assembled power semiconductor device to an aspect of the present invention, similar with corresponding examples similar effect of the power semiconductor devices Has an embodiment. Therefore, this method is an efficient and effective method for manufacturing a power semiconductor device in which the first substrate is properly aligned with the second substrate. In particular, as discussed above, the receiving element and the alignment interconnection element are provided between the first substrate and the second substrate (assuming the receiving element is provided in the correct position). It provides an effective mechanical means to ensure that the alignment is accurate. To ensure the accurate positioning of the second substrate with respect to the first substrate during the step of fixing the conductive alignment interconnection element to another one of the first receiving element and the second receiving element. , No additional sensors and/or actuators are required, ie correct alignment is automatically ensured by the partial reception of the alignment interconnection element by the receiving element. Even if the pre-alignment step is relatively weak, this mechanism ensures that it will correct itself towards the final correct alignment.

Method of assembling a power semiconductor device, a) acquiring data describing the positioning required of the first substrate to the second substrate, b) the first receiving element and the second receiving element Further comprising the step of measuring a characteristic, and c) determining a characteristic of the alignment interconnection element based on the acquired data and the measured characteristic, wherein in the step of obtaining the alignment interconnection element, Alignment interconnect elements are obtained based on the determined characteristics.

The method of assembling a power semiconductor device, wherein the receiving element is a hole or recess der is, the and the step of measuring the characteristics of the first receiving element and the second receiving element determines the radius of the receiving element And/or determining the depth of the receiving element . The radius of the first receiving element is measured in a plane substantially parallel to the first surface and the radius of the second receiving element is measured in a plane substantially parallel to the second surface; The depth of the second receiving element can be measured in a plane substantially perpendicular to the first surface and the depth of the second receiving element can be measured in a plane substantially perpendicular to the second surface. To be understood . It should be noted that the holes or depressions may extend only into the conductive layer, or into the substrate, or into the combination of the conductive layer and the substrate. ..

Is a schematic exploded view of one embodiment of a semiconductor power device. Passes through the straight line II-II 'along the first substrate and the plane perpendicular, it is a schematic cross-sectional view of a semiconductor power device in the embodiment of FIG. It is a schematic sectional drawing of another Example of a semiconductor power device. FIG. 6 is a schematic view of an example of a second substrate. FIG. 6 is a schematic view of an example of a first substrate. 1 is a schematic diagram of an example of a semiconductor device. 3 is a schematic view of a method of assembling a power semiconductor device.

Figure 1 is an example of a semiconductor power device 100, as an exploded view, are schematically shown. The semiconductor power device comprises a first substrate 140, a second substrate 110 and an interconnect structure. The first substrate 140 has a first surface 141 on which a switching semiconductor element 144 is provided. The first substrate further comprises first conductive layers 142, 146. The first substrate 140 further includes a first receiving element 150 is a hole in one 146 of the this particular embodiment the first conductive layer. The second substrate 110 has a second surface 111 facing towards the first surface 141 and comprises second conductive layers 112, 116 provided on the second surface. The second substrate 110 further includes a second receiving element 120 is a hole 150 on one 116 of the this particular embodiment the second conductive layer. The interconnect structure provides at least one electrical connection between one of the first conductive layers 142, 146 and one of the second conductive layers 112, 116. In the example of FIG. 1, two electrical connections are provided: one between the first conductive layer 142 and the second conductive layer 112, and the first conductive layer 146 and the second conductive layer 116. And one in between. The interconnect structure comprises interconnecting elements 130, 132, one of which is the alignment interconnecting element 130. In the example of FIG. 1, interconnect element 132 and alignment interconnect element 130 are spheres made of a conductive material (eg, copper). The interconnection element 132 is disposed between the first conductive layer 142 and the second conductive layer 112. The alignment interconnection element 130 is at least partially received by the first receiving element 150 and at least partially by the second receiving element 120. It is observed in FIG. 1 that the radius of the first receiving element 150 and the second receiving element 120 is smaller than the radius of the alignment interconnection element 130. This is because when the spherical alignment interconnection element 130 contacts the respective receiving element 120, 150, a portion of the spherical alignment interconnection element 130 is received by the hole forming the respective receiving element 120, 150. Means A small portion of the alignment interconnect element 130 that is spherical projects into the holes 120, 150 in the respective conductive layers 116, 146, which causes the alignment interconnect element 130 that is spherical to have the first surface 141 and/or the first surface 141. It is impossible to roll to another position on the second surface 111, which means that the relative position of the first substrate 140 is fixed with respect to the relative position of the second substrate 110.

Claims (14)

A semiconductor power device (100, 200, 400),
A first substrate (140, 240, 340) with switching semiconductor elements (144, 244, 344) having a first surface (141, 241, 341) and a first receiving element (150). , 250, 350) and locally with first conductive layers (142, 146, 246, 242, 342, 345), and the switching semiconductor elements (144, 244, 344) have a first surface. A first substrate (140, 240, 340) provided on (141, 241, 341);
A second substrate (110, 210, 310) having a second surface (111, 211, 311) facing the first surface (141, 241, 341), the second receiving element (120). , 220, 320) and locally comprising second conductive layers (112, 116, 212, 216, 312,..., 318), and a second substrate (110, 210, 310),
At least one of the first conductive layers (142, 146, 246, 242, 342, 345) on one side and the second conductive layers (112, 116, 212, 216, 312,...) On the other side. 318) with at least one electrical connection and comprising a plurality of interconnecting elements (130, 132, 230, 232, 332, 332', 430) of electrically conductive material. And,
At least one of the plurality of interconnecting elements is an alignment interconnecting element (130, 230, 430), the alignment interconnecting element (130, 230, 430) being the first to the second substrate (110, 210, 310). The second receiving element (120, 220, 320) is partially received by the first receiving element (150, 250, 350) to align the relative positions of the first substrate (140, 240, 340). ), said receiving element (120, 150, 220, 250, 320, 350) having a recess having a shape for at least partially receiving an alignment interconnection element (130, 230, 430). And each of said receiving element (120, 150, 220, 250, 320, 350) and alignment interconnection element (130, 230, 430) are applied to each other, and alignment interconnection element (130). , 230, 430) or each of said receiving elements (120, 150, 220, 250, 320, 350) are subjected to a force, the shape of the alignment interconnection elements (130, 230, 430) is such that the receiving elements (120 , 150, 220, 250, 320, 350), each of which is selected to affect the positioning of the alignment interconnect element (130, 230, 430) in a unique and fixed position. Device (100, 200, 400). The first substrate (140, 240, 340) comprises a plurality of first receiving elements (150, 250, 350) and the second substrate (110, 210, 310) comprises a plurality of second receiving elements. (120, 220, 320), said interconnection element (130, 132, 230, 232, 332, 332', 430) comprising a plurality of alignment interconnection elements (130, 230, 430), Each one of the plurality of alignment interconnect elements (130, 230, 430) aligns the relative position of the first substrate (140, 240, 340) with respect to the second substrate (110, 210, 310). , Partially received by a corresponding one of the first receiving elements (150, 250, 350) and partially by a corresponding one of the second receiving elements (120, 220, 320). Item 2. The semiconductor power device (100, 200, 400) according to Item 1. The first substrate (140, 240, 340) has at least three first receiving elements (150, 250, 350), at least three second receiving elements (120, 220, 320) and at least three. A semiconductor power device (100, 200, 400) according to claim 2, comprising alignment interconnection elements (130, 230, 430). At least one of the first receiving element (150, 250, 350) and the second receiving element (120, 220, 320) has at least one of the first conductive layers (142, 146, 246, 242, 342, 345). Any of claims 1-3, which is a hole or depression in each of one of said second conductive layers (112, 116, 212, 216, 312,..., 318). The semiconductor power device (100, 200, 400) as described in 1 above. A first receiving element (150, 250, 350) is electrically coupled to one of the first conductive layers (142, 146, 246, 242, 342, 345),
A second receiving element (120, 220, 320) is electrically coupled to one of the second conductive layers (112, 116, 212, 216, 312,..., 318), and Alignment interconnection elements (130, 230, 430) are electrically coupled to said receiving elements (120, 150, 220, 250, 320, 350),
The semiconductor power device (100, 200, 400) according to any one of claims 1 to 4, which is at least one of: A plurality of interconnecting elements (130, 132, 230, 232, 332, 332', 430) have different depths from each other and have the conductive layers (112, 116, 142, 146, 212, 216, 242, 246). , 312,..., 318, 342, 345) with at least two interconnection elements (130, 132, 230, 232, 332, 332', 430) having a depth adapted to the distance between In between, the interconnection elements (130, 132, 230, 232, 332, 332', 430) are arranged, the depth from the first substrate (140, 240, 340) to the interconnection elements ( 130, 132, 230, 232, 332, 332', 430) at the position of the shortest straight line to the second substrate (110, 210, 310). A semiconductor power device (100, 200, 400) according to the item. The alignment interconnection element (130, 230, 430) is one of the shape of a sphere, square box, cube, cuboid, cylinder, tube, oval, rugby ball, diamond ball, or diamond. Item 7. The semiconductor power device (100, 200, 400) according to any one of items 1 to 6. If the receiving element (120, 150, 220, 250, 320, 350) is a hole and the alignment interconnection element (130, 230, 430) is a sphere, the radius of the sphere is greater than the radius of the hole. A semiconductor power device (100, 200, 400) according to the combination of claim 4 and claim 7. The semiconductor power device (100, 200, 400) according to any one of claims 1 to 8, wherein the second substrate (110, 210, 310) comprises a semiconductor element. One or more first conductive layers (142, 146, 246, 242, 342, 345) arranged on or at the first surface;
One or more first conductive layers (142, 146, 246, 242, 342, 345) facing the first substrate (140, 240, 340) toward the switching semiconductor element (144, 244, 344) on or at the surface of
One or more second conductive layers (112, 116, 212, 216, 312,..., 318) are arranged on or at the second surface (111, 211, 311). , And with reference to claim 9, one or more second conductive layers (112, 116, 212, 216, 312,..., 318) arranged on or at the surface of the semiconductor device. Has been
The semiconductor power device (100, 200, 400) according to any one of claims 1 to 9, which is at least one of the following. A method (500) for assembling a power semiconductor device, the method comprising:
A step (502) of obtaining a first substrate comprising a switching semiconductor element, the first substrate having a first surface and locally providing a first conductive layer and a first receiving element. A switching semiconductor element is provided on the first surface, the step of obtaining (502),
Obtaining (504) a second substrate having a second surface facing the first surface, the second substrate comprising a second receiving element and localizing a second conductive layer. The step of obtaining (504),
Obtaining an alignment interconnection element (512),
Providing (514) an alignment interconnection element to one of the first and second receiving elements to affect the partial reception of the alignment interconnection element by said receiving element;
Providing an alignment interconnection element to the other of the first and second receiving elements to affect the partial receipt of the alignment interconnection element by the receiving element (516).
A method (500) comprising: Obtaining data describing the required positioning of the first substrate with respect to the second substrate (506);
Measuring (508) a characteristic of the first receiving element and the second receiving element;
Determining (510) a property of the alignment interconnection element based on the acquired data and the measured property, the method further comprising:
12. The method (500) of assembling a power semiconductor device of claim 11, wherein in obtaining alignment interconnection elements (502), alignment interconnection elements are obtained based on the determined characteristics. At least one of the steps of providing an alignment interconnection element to the receiving element comprises soldering the alignment interconnection element to the receiving element and sintering the alignment interconnection element to the receiving element. A method (500) for assembling a power semiconductor device according to claim 11 or 12, comprising one. If the receiving element is a hole or a depression, the step of measuring the characteristics of the first receiving element and the second receiving element determines the radius of the receiving element and determines the depth of the receiving element. Determining the radius of the first receiving element in a plane substantially parallel to the first surface, and the radius of the second receiving element substantially equal to the second surface. Measured in a plane parallel to the first receiving element, the depth of the first receiving element is measured in a plane substantially perpendicular to the first surface, and the depth of the second receiving element is substantially equal to the second surface. A method (500) for assembling a power semiconductor device according to any one of claims 11, 12, 13 measured in a plane perpendicular to.

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