JP2020113582A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2020113582A
JP2020113582A JP2019001430A JP2019001430A JP2020113582A JP 2020113582 A JP2020113582 A JP 2020113582A JP 2019001430 A JP2019001430 A JP 2019001430A JP 2019001430 A JP2019001430 A JP 2019001430A JP 2020113582 A JP2020113582 A JP 2020113582A
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signal terminal
signal
semiconductor device
solder
semiconductor element
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JP7180385B2 (en
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崇功 川島
Takayoshi Kawashima
崇功 川島
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Toyota Motor Corp
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

To provide a semiconductor device that can prevent a solder that joins a signal terminal and a signal pad from spreading excessively over an unintended range.SOLUTION: A semiconductor device disclosed in the present specification includes a semiconductor device having a signal pad, and a signal terminal whose one end is bonded to the signal pad via a solder layer. The signal terminal is provided with a recess adjacent to the solder layer from the other end side of the signal terminal. Further, a groove is formed on the bottom surface of the recess of the signal terminal along the longitudinal direction of the signal terminal.SELECTED DRAWING: Figure 2

Description

本明細書が開示する技術は、半導体装置に関する。 The technology disclosed in this specification relates to a semiconductor device.

特許文献１に、半導体装置が開示されている。この半導体装置は、信号端子と、半導体素子に接合された導体層が一方側に設けられた放熱部材とを備える。信号端子は、当該導体層にはんだ層を介して接合されることによって、半導体素子の信号パッドに電気的に接続されている。 Patent Document 1 discloses a semiconductor device. This semiconductor device includes a signal terminal and a heat dissipation member having a conductor layer joined to a semiconductor element provided on one side. The signal terminal is electrically connected to the signal pad of the semiconductor element by being joined to the conductor layer via the solder layer.

特開２００４−２９６５８８号公報JP 2004-296588 A

上記した半導体装置では、信号端子の一端が、導体層を介して、半導体素子の信号パッドへ接続されている。これに対して、信号端子の一端を、半導体素子の信号パッドへ直接的に接合して、半導体装置の小型化を図ることが考えられる。しかしながら、信号端子は細長い部材であることから、信号端子の一端を半導体素子の信号パッドへ接合するときに、当該一端の位置が安定せず、信号パッドに対して意図せず近接することがある。信号端子の一端と信号パッドとの間が過度に近接すると、それら二つの部材の間からはんだが溢れるおそれがある。この場合、溢れ出たはんだが他の配線部分（例えば、隣接する他の信号パッド等）にまで濡れ広がることにより、半導体装置に短絡が生じるおそれがある。本明細書では、信号端子と信号パッドとを接合するはんだの過大な濡れ広がりを防止し得る技術を提供する。 In the above semiconductor device, one end of the signal terminal is connected to the signal pad of the semiconductor element via the conductor layer. On the other hand, it is conceivable to directly bond one end of the signal terminal to the signal pad of the semiconductor element to reduce the size of the semiconductor device. However, since the signal terminal is an elongated member, when one end of the signal terminal is joined to the signal pad of the semiconductor element, the position of the one end may not be stable and may unintentionally approach the signal pad. .. If the one end of the signal terminal and the signal pad are too close to each other, the solder may overflow between the two members. In this case, the overflowed solder may spread to other wiring portions (for example, other adjacent signal pads, etc.) so that a short circuit may occur in the semiconductor device. The present specification provides a technique capable of preventing excessive wetting and spreading of solder that joins a signal terminal and a signal pad.

本明細書が開示する半導体装置は、信号パッドを有する半導体素子と、一端が信号パッドにはんだ層を介して接合された信号端子とを備え、信号端子には、信号端子の他端側からはんだ層に隣接する凹部が設けられており、凹部の底面には、信号端子の長手方向に沿って溝が形成されている。 A semiconductor device disclosed in the present specification includes a semiconductor element having a signal pad and a signal terminal having one end joined to the signal pad via a solder layer, and the signal terminal is soldered from the other end side of the signal terminal. A recess is provided adjacent to the layer, and a groove is formed on the bottom surface of the recess along the longitudinal direction of the signal terminal.

上記した半導体装置の信号端子には、はんだ層に隣接する位置に、凹部が設けられている。このような構成によると、信号端子の一端と半導体素子との間から溢れたはんだを凹部によって収容し、はんだの過剰な濡れ広がりを抑制することができる。さらに、凹部の底面には、信号端子の長手方向に沿って溝が形成されている。このような構成によると、凹部へ流れ込んだ余剰のはんだが、信号端子の長手方向に沿って案内されることで、より多くのはんだを凹部によってスムーズに収容することができる。従って、はんだが意図しない範囲まで過大に濡れ広がり、例えば半導体装置を短絡させるといった問題を防止することができる。 The signal terminal of the semiconductor device described above is provided with a recess at a position adjacent to the solder layer. With such a configuration, the solder overflowing from between the one end of the signal terminal and the semiconductor element can be accommodated in the recess, and excessive wetting and spreading of the solder can be suppressed. Further, a groove is formed on the bottom surface of the recess along the longitudinal direction of the signal terminal. With such a configuration, the excess solder that has flowed into the recess is guided along the longitudinal direction of the signal terminal, so that more solder can be smoothly accommodated in the recess. Therefore, it is possible to prevent the problem that the solder excessively spreads to an unintended range and short-circuits the semiconductor device, for example.

実施例の半導体装置１０の内部構造を示す断面図。Sectional drawing which shows the internal structure of the semiconductor device 10 of an Example. 信号端子１８の構造を説明する下面図。The bottom view explaining the structure of the signal terminal 18. 信号端子１８の溝１８ｄのいくつかの実施形態を示す図であって、図２のＩＩＩ−ＩＩＩ線における断面図。FIG. 3 is a view showing some embodiments of the groove 18d of the signal terminal 18 and is a cross-sectional view taken along line III-III of FIG. 2. 信号端子１８の一端１８ａに設けられた凸部のいくつかの実施形態を示す図であって、図２のＩＶ−ＩＶ線における断面図。FIG. 4 is a view showing some embodiments of a convex portion provided at one end 18 a of the signal terminal 18, and is a cross-sectional view taken along line IV-IV in FIG. 2. 信号端子１８の一端の１８ａの形状のいくつかの実施形態を示す下面図。The bottom view which shows some embodiment of the shape of 18a of the end of the signal terminal 18.

図面を参照して、実施例の半導体装置１０について説明する。半導体装置１０は、電力制御装置に採用され、例えばインバータやコンバータといった電力変換回路の一部を構成することができる。ここでいう電力制御装置は、例えば電気自動車、ハイブリッド自動車、燃料電池車等に搭載される。 A semiconductor device 10 according to an embodiment will be described with reference to the drawings. The semiconductor device 10 is used in a power control device and can form a part of a power conversion circuit such as an inverter or a converter. The power control device mentioned here is mounted in, for example, an electric vehicle, a hybrid vehicle, a fuel cell vehicle, or the like.

図１に示すように、半導体装置１０は、半導体素子１２、信号端子１８及び封止体２０を備える。半導体素子１２は、封止体２０の内部に封止されている。封止体２０は、例えばエポキシ樹脂といった絶縁性を有する材料を用いて構成されている。信号端子１８は、封止体２０から外部に向かって突出して延びている。信号端子１８は、封止体２０の内部において、半導体素子１２と電気的に接続されている。 As shown in FIG. 1, the semiconductor device 10 includes a semiconductor element 12, a signal terminal 18, and a sealing body 20. The semiconductor element 12 is sealed inside the sealing body 20. The sealing body 20 is made of, for example, an insulating material such as an epoxy resin. The signal terminal 18 projects and extends from the sealing body 20 to the outside. The signal terminal 18 is electrically connected to the semiconductor element 12 inside the sealing body 20.

半導体素子１２は、パワー半導体素子であって、例えば、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）又はＩＧＢＴ（Insulated Gate Bipolar Transistor）である。但し、半導体素子の数や種類については、特に限定されない。半導体素子１２を構成する材料には、例えばケイ素（Ｓｉ）、炭化ケイ素（ＳｉＣ）又は窒化ガリウム（ＧａＮ）又は他の種類の半導体材料を採用することができる。半導体素子１２は、一対の主電極１２ａ、１２ｂと、信号端子１８に接続される信号パッド１２ｃを有する。一対の主電極１２ａ、１２ｂには、第１主電極１２ａと第２主電極１２ｂとが含まれている。第１主電極１２ａ及び信号パッド１２ｃは、半導体素子１２の一方の表面に位置しており、第２主電極１２ｂは、半導体素子１２の他方の表面に位置している。一対の主電極１２ａ、１２ｂ及び信号パッド１２ｃは、アルミニウム系又は他の金属といった導体材料を用いて構成されている。 The semiconductor element 12 is a power semiconductor element and is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). However, the number and types of semiconductor elements are not particularly limited. As a material forming the semiconductor element 12, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or another type of semiconductor material can be adopted. The semiconductor element 12 has a pair of main electrodes 12 a and 12 b and a signal pad 12 c connected to the signal terminal 18. The pair of main electrodes 12a and 12b includes a first main electrode 12a and a second main electrode 12b. The first main electrode 12a and the signal pad 12c are located on one surface of the semiconductor element 12, and the second main electrode 12b is located on the other surface of the semiconductor element 12. The pair of main electrodes 12a and 12b and the signal pad 12c are made of a conductive material such as aluminum or another metal.

半導体装置１０は、下側放熱板１４と上側放熱板１６を備える。放熱板１４、１６は、概して直方体形状の部材であり、例えば、銅又は他の金属といった導体材料を用いて構成されている。下側放熱板１４は、第１主表面１４ａと、第１主表面１４ａの反対側に位置する第２主表面１４ｂを有する。下側放熱板１４の第１主表面１４ａは、半導体素子１２の第２主電極１２ｂにはんだ層２２を介して接合される。従って、下側放熱板１４は、半導体素子１２と電気的に接続される。下側放熱板１４の第２主表面１４ｂは、封止体２０の一方の面において露出される。 The semiconductor device 10 includes a lower heat dissipation plate 14 and an upper heat dissipation plate 16. The heat dissipation plates 14 and 16 are generally rectangular parallelepiped members, and are made of a conductive material such as copper or other metal. The lower heat dissipation plate 14 has a first main surface 14a and a second main surface 14b located on the opposite side of the first main surface 14a. The first main surface 14a of the lower heat dissipation plate 14 is bonded to the second main electrode 12b of the semiconductor element 12 via the solder layer 22. Therefore, the lower heat dissipation plate 14 is electrically connected to the semiconductor element 12. The second main surface 14b of the lower heat dissipation plate 14 is exposed on one surface of the sealing body 20.

上側放熱板１６も、下側放熱板１４と同様に、第１主表面１６ａと、第１主表面１６ａの反対側に位置する第２主表面１６ｂを有する。上側放熱板１６は、第２主表面１６ｂから突出するスペーサ部１６ｃを一体に有し、この点に関して、下側放熱板１４とは異なる。但し、上側放熱板１６の実施形態はこれに特に限定されず、別体の部材である導体スペーサを用いて構成されていてもよい。スペーサ部１６ｃは、必ずしも必要としないが、これにより、信号端子１８を信号パッド１２ｃに接合するスペースを確保することができる。上側放熱板１６の第２主表面１６ｂは、半導体素子１２の第１主電極１２ａにはんだ層２４を介して接合される。従って、上側放熱板１６は、半導体素子１２と電気的に接続される。上側放熱板１６の第１主表面１６ａは、封止体２０の他方の面において露出される。以上より、下側放熱板１４及び上側放熱板１６は、半導体素子１２で発生する熱を放出する放熱板として機能する。従って、半導体装置１０は、放熱板１４、１６が封止体２０の両面に露出する両面冷却構造を有している。 Like the lower heat dissipation plate 14, the upper heat dissipation plate 16 also has a first main surface 16a and a second main surface 16b located on the opposite side of the first main surface 16a. The upper heat dissipation plate 16 integrally has a spacer portion 16c protruding from the second main surface 16b, and in this respect, it is different from the lower heat dissipation plate 14. However, the embodiment of the upper heat dissipation plate 16 is not particularly limited to this, and may be configured using a conductor spacer which is a separate member. Although the spacer portion 16c is not always necessary, it is possible to secure a space for joining the signal terminal 18 to the signal pad 12c. The second main surface 16b of the upper heat dissipation plate 16 is bonded to the first main electrode 12a of the semiconductor element 12 via the solder layer 24. Therefore, the upper heat dissipation plate 16 is electrically connected to the semiconductor element 12. The first main surface 16a of the upper heat dissipation plate 16 is exposed on the other surface of the sealing body 20. As described above, the lower heat radiating plate 14 and the upper heat radiating plate 16 function as heat radiating plates that radiate the heat generated in the semiconductor element 12. Therefore, the semiconductor device 10 has a double-sided cooling structure in which the heat dissipation plates 14 and 16 are exposed on both sides of the sealing body 20.

信号端子１８は、概して細長い板形状の部材である。信号端子１８は、一端１８ａと、信号端子１８の長手方向において一端１８ａの反対側に位置する他端（図示省略）を有する。信号端子１８は、信号パッド１２ｃと部分的に対向している。信号端子１８は、例えば銅又は他の金属といった導体材料を用いて構成されており、上述したように、信号端子１８は、封止体２０の内部において、半導体素子１２と電気的に接続されている。詳しくは、信号端子１８の一端１８ａが、半導体素子１２の信号パッド１２ｃとはんだ層２６を介して接合されている。 The signal terminal 18 is a generally elongated plate-shaped member. The signal terminal 18 has one end 18a and the other end (not shown) located on the opposite side of the one end 18a in the longitudinal direction of the signal terminal 18. The signal terminal 18 partially faces the signal pad 12c. The signal terminal 18 is configured by using a conductor material such as copper or another metal, and as described above, the signal terminal 18 is electrically connected to the semiconductor element 12 inside the sealing body 20. There is. Specifically, one end 18a of the signal terminal 18 is joined to the signal pad 12c of the semiconductor element 12 via the solder layer 26.

上記したように信号端子１８は細長い部材であることから、信号端子１８の一端１８ａを半導体素子１２の信号パッド１２ｃへ接合するときに、一端１８ａの位置が安定せず、信号パッド１２ｃに対して意図せず近接することがある。信号端子１８の一端１８ａと信号パッド１２ｃとの間が過度に近接すると、それら二つの部材の間からはんだが溢れるおそれがある。この場合、溢れ出たはんだが他の配線部分（例えば、隣接する他の信号パッド等）にまで濡れ広がることにより、半導体装置１０に短絡が生じるおそれがある。 As described above, since the signal terminal 18 is an elongated member, when the one end 18a of the signal terminal 18 is joined to the signal pad 12c of the semiconductor element 12, the position of the one end 18a is not stable and the signal terminal 12c is not stable. They may come close to each other unintentionally. If the one end 18a of the signal terminal 18 and the signal pad 12c are excessively close to each other, the solder may overflow between the two members. In this case, the overflowed solder may spread to another wiring portion (for example, another adjacent signal pad or the like) to cause a short circuit in the semiconductor device 10.

上記の点に関して、図２に示すように、本実施例の半導体装置１０の信号端子１８には、信号端子１８の他端側からはんだ層２６に隣接する凹部１８ｂが設けられている。このような構成によると、信号端子１８の一端１８ａと半導体素子１２との間から溢れたはんだを凹部１８ｂによって収容し、はんだの過剰な濡れ広がりを抑制することができる。加えて、凹部１８ｂの底面１８ｃには、信号端子１８の長手方向に沿って溝１８ｄが形成されている。このような構成によると、凹部１８ｂへ流れ込んだ余剰のはんだが、信号端子１８の長手方向に沿って案内されることで、より多くのはんだを凹部１８ｂによってスムーズに収容することができる。従って、はんだが意図しない範囲まで過大に濡れ広がり、例えば半導体装置１０を短絡させるといった問題を防止することができる。 With respect to the above point, as shown in FIG. 2, the signal terminal 18 of the semiconductor device 10 of the present embodiment is provided with the recess 18b adjacent to the solder layer 26 from the other end side of the signal terminal 18. With such a configuration, the solder overflowing between the one end 18a of the signal terminal 18 and the semiconductor element 12 can be accommodated in the recess 18b, and excessive wetting and spreading of the solder can be suppressed. In addition, a groove 18d is formed in the bottom surface 18c of the recess 18b along the longitudinal direction of the signal terminal 18. With such a configuration, the excess solder that has flowed into the recess 18b is guided along the longitudinal direction of the signal terminal 18, so that a larger amount of solder can be smoothly accommodated in the recess 18b. Therefore, it is possible to prevent the problem that the solder excessively spreads to an unintended range and short-circuits the semiconductor device 10, for example.

図２に示すように、溝１８ｄは信号端子１８の長手方向に沿って、例えば直線状に設けられている。但し、これに限定されず、溝１８ｄが例えば波線状に設けられていてもよい。溝１８ｄの本数についても特に限定されない。また、本技術における信号端子１８の実施形態は、様々に変更可能であり、以下に信号端子１８のいくつかの実施形態について説明する。 As shown in FIG. 2, the groove 18d is provided, for example, in a straight line along the longitudinal direction of the signal terminal 18. However, the present invention is not limited to this, and the groove 18d may be provided in, for example, a wavy line shape. The number of the grooves 18d is also not particularly limited. Further, the embodiment of the signal terminal 18 in the present technology can be variously modified, and some embodiments of the signal terminal 18 will be described below.

図３（Ａ）に示す例では、信号端子１８に設けられた溝１８ｄが、矩形状の断面形状を有している。なお、本明細書において、溝１８ｄの断面形状とは、溝１８ｄの長手方向に垂直な断面の形状、即ち、信号端子１８の長手方向に垂直な断面の形状を意味する。図３（Ｂ）に示す例では、溝１８ｄの断面形状が台形形状を有しており、図３（Ｃ）に示す例では、溝１８ｄの断面形状が三角形状を有している。これらの実施形態において、溝１８ｄの深さ寸法や幅寸法は、特に限定されない。一例ではあるが、図３（Ｄ）に示すように、溝１８ｄは、底面１８ｃから底面１８ｃとは反対側の面に向かって、貫通していてもよい。即ち、溝１８ｄは、有底のものに限定されない。また、溝１８ｄは、信号端子１８の長手方向に沿って複数設けられていてもよい。 In the example shown in FIG. 3A, the groove 18d provided in the signal terminal 18 has a rectangular cross-sectional shape. In the present specification, the cross-sectional shape of the groove 18d means a shape of a cross section perpendicular to the longitudinal direction of the groove 18d, that is, a shape of a cross section perpendicular to the longitudinal direction of the signal terminal 18. In the example shown in FIG. 3B, the groove 18d has a trapezoidal sectional shape, and in the example shown in FIG. 3C, the groove 18d has a triangular sectional shape. In these embodiments, the depth dimension and the width dimension of the groove 18d are not particularly limited. As an example, as shown in FIG. 3D, the groove 18d may penetrate from the bottom surface 18c to the surface opposite to the bottom surface 18c. That is, the groove 18d is not limited to the bottomed one. Further, a plurality of grooves 18d may be provided along the longitudinal direction of the signal terminal 18.

上述したが、信号端子１８の一端１８ａは、はんだ層２６を介して信号パッド１２ｃに接合されており、信号端子１８には、はんだ層２６に隣接する凹部１８ｂが設けられている。言い換えると、信号端子１８の一端１８ａは、凹部１８ｂから見ると、信号パッド１２ｃに対向して延びる凸部となっている。図４（Ａ）に示すように、本実施例の信号端子１８の凸部は、円錐台や多角錐台といった錐台状に設けられている。但し、この凸部の形態についても、特に限定されず、様々に変更することができる。凸部は、図４（Ｂ）に示すように、円錐や多角推といった錐体状であってもよいし、図４（Ｃ）に示すように、柱状であってもよい。ここで、この信号端子１８の凸部が柱状である場合については、凸部の周囲に存在する平坦部のうち、凸部の一方側（即ち、信号端子１８の他端側）に位置する部分が、凹部１８ｂに相当する。 As described above, the one end 18a of the signal terminal 18 is joined to the signal pad 12c via the solder layer 26, and the signal terminal 18 is provided with the recess 18b adjacent to the solder layer 26. In other words, the one end 18a of the signal terminal 18 is a convex portion that extends toward the signal pad 12c when viewed from the concave portion 18b. As shown in FIG. 4A, the convex portion of the signal terminal 18 of the present embodiment is provided in a truncated cone shape such as a truncated cone or a polygonal truncated cone. However, the form of the convex portion is not particularly limited and can be variously modified. The convex portion may have a cone shape such as a cone or a polygonal thrust as shown in FIG. 4B, or may have a columnar shape as shown in FIG. 4C. Here, when the convex portion of the signal terminal 18 is columnar, a portion of the flat portion existing around the convex portion, which is located on one side of the convex portion (that is, the other end side of the signal terminal 18). Corresponds to the recess 18b.

また、図５（Ａ）に示すように、信号端子１８の一端１８ａに設けられた凸部は、矩形状の断面形状を有してもよいし、図５（Ｂ）に示すように、円形状の断面形状を有してもよい。なお、ここでいう凸部の断面形状とは、凸部の高さ方向に垂直な断面の形状を意味する。 Further, as shown in FIG. 5A, the convex portion provided at one end 18a of the signal terminal 18 may have a rectangular cross-sectional shape, or as shown in FIG. It may have a cross-sectional shape. In addition, the cross-sectional shape of the convex portion here means a shape of a cross section perpendicular to the height direction of the convex portion.

本実施例では、信号端子１８の一端１８ａに設けられた凸部の側面（言い換えると、凹部１８ｂの側面）は、テーパ形状を有している。このような構成によると、余剰のはんだが信号端子１８の凹部１８ｂに流れ込みやすく、溝１８ｄとの相乗効果によって、信号端子１８の凹部１８ｂにより多くのはんだをスムーズに吸収することができる。なお、凸部の側面は、その全体がテーパ形状を有さなくてよく、少なくとも凹部１８ｂの底面１８ｃに接続する範囲（例えば、凹部１８ｂ側に位置する部分）において、テーパ形状を有するとよい。加えて、又は代えて、凸部の側面（即ち、凹部１８ｂの側面）にも、凹部１８ｂの底面１８ｃに向けて延びる溝が設けられてもよく、これが底面１８ｃの溝１８ｄと接続されていてもよい。 In this embodiment, the side surface of the convex portion provided on the one end 18a of the signal terminal 18 (in other words, the side surface of the concave portion 18b) has a tapered shape. With such a configuration, excess solder easily flows into the concave portion 18b of the signal terminal 18, and a large amount of solder can be smoothly absorbed by the concave portion 18b of the signal terminal 18 due to the synergistic effect with the groove 18d. The side surface of the convex portion does not have to have a tapered shape as a whole, and may have a tapered shape at least in a range connected to the bottom surface 18c of the concave portion 18b (for example, a portion located on the concave portion 18b side). Additionally or alternatively, the side surface of the convex portion (that is, the side surface of the concave portion 18b) may be provided with a groove extending toward the bottom surface 18c of the concave portion 18b, which is connected to the groove 18d of the bottom surface 18c. Good.

以上、いくつかの具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書又は図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものである。 Although some specific examples have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical utility alone or in various combinations.

１０：半導体装置
１２：半導体素子
１２ａ、１２ｂ：主電極
１２ｃ：信号パッド
１４、１６：放熱板
１８：信号端子
１８ａ：一端
１８ｂ：凹部
１８ｃ：底面
１８ｄ：溝
２０：封止体
２２、２４、２６：はんだ層 10: semiconductor device 12: semiconductor elements 12a, 12b: main electrode 12c: signal pads 14, 16: heat sink 18: signal terminal 18a: one end 18b: concave portion 18c: bottom surface 18d: groove 20: sealing bodies 22, 24, 26 : Solder layer

Claims (1)

信号パッドを有する半導体素子と、
一端が前記信号パッドにはんだ層を介して接合された信号端子と、
を備え、
前記信号端子には、前記信号端子の他端側から前記はんだ層に隣接する凹部が設けられており、
前記凹部の底面には、前記信号端子の長手方向に沿って溝が形成されている、
半導体装置。
A semiconductor device having a signal pad;
A signal terminal, one end of which is joined to the signal pad via a solder layer,
Equipped with
The signal terminal is provided with a recess adjacent to the solder layer from the other end side of the signal terminal,
A groove is formed on the bottom surface of the recess along the longitudinal direction of the signal terminal,
Semiconductor device.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0499848U (en) * 1991-02-06 1992-08-28
JP2007165476A (en) * 2005-12-12 2007-06-28 Mitsubishi Electric Corp Surface mounting part
US20070267727A1 (en) * 2006-05-04 2007-11-22 International Rectifier Corporation Copper straps
US20090294934A1 (en) * 2008-05-30 2009-12-03 Alpha & Omega Semiconductor, Ltd. Conductive clip for semiconductor device package
US20100193921A1 (en) * 2009-02-05 2010-08-05 Jereza Armand Vincent C Semiconductor die package and method for making the same
JP2011243929A (en) * 2010-05-21 2011-12-01 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2013149760A (en) * 2012-01-18 2013-08-01 Fuji Electric Co Ltd Semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0499848U (en) * 1991-02-06 1992-08-28
JP2007165476A (en) * 2005-12-12 2007-06-28 Mitsubishi Electric Corp Surface mounting part
US20070267727A1 (en) * 2006-05-04 2007-11-22 International Rectifier Corporation Copper straps
US20090294934A1 (en) * 2008-05-30 2009-12-03 Alpha & Omega Semiconductor, Ltd. Conductive clip for semiconductor device package
US20100193921A1 (en) * 2009-02-05 2010-08-05 Jereza Armand Vincent C Semiconductor die package and method for making the same
JP2011243929A (en) * 2010-05-21 2011-12-01 Hitachi Ltd Semiconductor device and manufacturing method thereof
JP2013149760A (en) * 2012-01-18 2013-08-01 Fuji Electric Co Ltd Semiconductor device

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