JP2020102535A - Nitride semiconductor device manufacturing method and nitride semiconductor device - Google Patents

Abstract

To provide a nitride semiconductor device manufacturing method and a nitride semiconductor device that can increase the mechanical strength of a metal electrode.SOLUTION: A nitride semiconductor device manufacturing method includes the steps of: depositing an insulative first inorganic compound film containing Si on a nitride semiconductor layer; depositing a second inorganic compound film containing Al on the first inorganic compound film; forming an opening penetrating the first inorganic compound film and the second inorganic compound film by dry etching; and depositing a metal electrode in the opening. In the step of forming the opening, the second inorganic compound film and the first inorganic compound film are continuously etched using an etching gas mainly containing a fluorine-based gas species.SELECTED DRAWING: Figure 3

Description

The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Patent Document 1 discloses a technique relating to a dry etching method for a high dielectric constant metal oxide film. This method is a method of dry etching a high dielectric constant metal oxide film using plasma, and a small amount of fluorocarbon gas having a high carbon element ratio is added to BCl ₃ gas mixed with a rare gas. Patent Document 2 discloses a technique relating to a compound semiconductor device and a method for manufacturing the same. This device includes a carrier traveling layer of a nitride semiconductor, a carrier supply layer of a nitride semiconductor provided on the carrier traveling layer, a SiN film provided on the carrier supply layer, and an Al provided on the SiN film. _{And a 2} O ₃ film. When forming the gate opening, the Al ₂ O ₃ film is etched using BCl ₃ gas and then the SiN film is etched using CF ₄ gas.

JP, 2009-064991, A JP, 2016-134541, A

In order to improve electrical characteristics such as high frequency characteristics of nitride semiconductor devices, miniaturization of the devices themselves is progressing. For example, in a field effect transistor such as a high electron mobility transistor (HEMT), the shorter the length of the contact surface between the gate electrode and the semiconductor layer (gate length), the higher the electrical characteristics such as high frequency characteristics. Is required to do. Currently, gate lengths on the order of, for example, tens of nm are realized. However, in a metal electrode such as a gate electrode, the shorter the contact surface with the semiconductor layer, the lower the mechanical strength of the metal electrode.

An object of one aspect of the present invention is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of increasing the mechanical strength of a metal electrode.

A method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes a step of depositing an insulating first inorganic compound film containing Si on a nitride semiconductor layer, and including Al on the first inorganic compound film. The method includes depositing a second inorganic compound film, forming an opening penetrating the first inorganic compound film and the second inorganic compound film by dry etching, and depositing a metal electrode in the opening. In the step of forming the opening, the second inorganic compound film and the first inorganic compound film are continuously etched using an etching gas containing a fluorine-based gas species and not containing a chlorine-based gas species.

According to one aspect of the present invention, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of increasing the mechanical strength of a metal electrode.

FIG. 1 is a cross-sectional view showing a field effect transistor as an example of a semiconductor device manufactured by a manufacturing method according to an embodiment. 2A to 2C are cross-sectional views illustrating each step after forming the nitride semiconductor layer 7 on the substrate 2. FIGS. 3A and 3B are cross-sectional views illustrating each step after the nitride semiconductor layer 7 is formed on the substrate 2. FIGS. 4A and 4B are cross-sectional views for explaining each step after the nitride semiconductor layer 7 is formed on the substrate 2. FIG. 5 is an SEM photograph showing the vicinity of the gate electrode 23 of the transistor 1 prototyped by the present inventor.

Specific examples of the method for manufacturing a nitride semiconductor device and the nitride semiconductor device according to the embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to these exemplifications, and is shown by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and overlapping description will be omitted.

FIG. 1 is a cross-sectional view showing a field effect transistor (hereinafter, simply referred to as a transistor) as an example of a semiconductor device manufactured by the manufacturing method according to the present embodiment. As shown in FIG. 1, the transistor 1 includes a substrate 2, a nitride semiconductor layer 7, a SiN film 11, Al ₂ O ₃ films 12 and 13, an Al _x F _y film 14, a source electrode 21, a drain electrode 22, and a gate. The electrode 23 is provided. The nitride semiconductor layer 7 includes a buffer layer 3, a channel layer 4, a barrier layer 5, and a cap layer 6 in order from the substrate 2 side. The transistor 1 of this embodiment is a high electron mobility transistor (HEMT). Two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is generated in the channel layer 4 and in the vicinity of the interface between the channel layer 4 and the barrier layer 5. As a result, a channel region is formed in the channel layer 4.

The substrate 2 is a substrate for crystal growth. Examples of the substrate 2 include a SiC substrate, a GaN substrate, and a sapphire (Al ₂ O ₃ ) substrate. In one example, the substrate 2 is a SiC substrate. The buffer layer 3 is a buffer layer for epitaxially growing the channel layer 4 and the barrier layer 5 on the substrate 2. The buffer layer 3 is made of a nitride semiconductor and is, for example, an AlN layer. The thickness of the buffer layer 3 is, for example, 10 nm or more and 100 nm or less. The channel layer 4 is a semiconductor layer epitaxially grown on the buffer layer 3. The channel layer 4 is made of a nitride semiconductor and is, for example, a GaN layer. The thickness of the channel layer 4 is, for example, 400 nm or more and 2000 nm or less.

The barrier layer 5 is a semiconductor layer epitaxially grown on the channel layer 4. The barrier layer 5 is made of a nitride semiconductor having a higher electron affinity than the channel layer 4, and includes, for example, an AlGaN layer, an InAlN layer, or an InAlGaN layer. The barrier layer 5 may exhibit n-type conductivity. The thickness of the barrier layer 5 is, for example, 5 nm or more and 30 nm or less. The cap layer 6 is a semiconductor layer epitaxially grown on the barrier layer 5. The cap layer 6 is made of a nitride semiconductor and is, for example, a GaN layer. The cap layer 6 may also contain impurities. The lower limit of the thickness of the cap layer 6 is, for example, 1 nm. The upper limit of the thickness of the cap layer 6 is, for example, 5 nm. In one embodiment, the barrier layer 5 is an n-type AlGaN layer and the cap layer 6 is an n-type GaN layer.

The SiN film 11 is a protective film provided on the nitride semiconductor layer 7 (on the cap layer 6 in the present embodiment), and is an example of an insulating first inorganic compound film containing Si in the present embodiment. is there. The SiN film 11 is provided to protect the surface of the nitride semiconductor layer 7 (in particular, the surface 6a of the cap layer 6). As will be described later, the SiN film 11 is formed by using, for example, a low pressure chemical vapor deposition (LPCVD) method or a plasma CVD method. The LPCVD method is a method of forming a dense film by lowering the film formation pressure and raising the film formation temperature.

The Al ₂ O ₃ film 13 is a protective film provided on the SiN film 11 and is an example of the second inorganic compound film containing Al in the present embodiment. Like the SiN film 11, the Al ₂ O ₃ film 13 is provided to protect the surface of the nitride semiconductor layer 7 (in particular, the surface 6a of the cap layer 6). As described later, the Al ₂ O ₃ film 13 is formed by using, for example, an atomic layer deposition method (Atomic Layer Deposition; ALD).

The SiN film 11 and the Al ₂ O ₃ film 13 are formed with a gate opening 15a, a source opening 15b, and a drain opening 15c which penetrate the films 11 and 13. The distance between the source opening 15b and the drain opening 15c is 2.5 μm, for example. The gate opening 15a is located between the source opening 15b and the drain opening 15c. The cap layer 6 is exposed in the gate opening 15a. In the source opening 15b and the drain opening 15c, the cap layer 6 is removed and the barrier layer 5 is exposed.

The source electrode 21 closes the source opening 15b and is provided on the nitride semiconductor layer 7. The source electrode 21 is in contact with the barrier layer 5 via the source opening 15b. The drain electrode 22 closes the drain opening 15c and is provided on the nitride semiconductor layer 7. The drain electrode 22 is in contact with the barrier layer 5 via the drain opening 15c. The source electrode 21 and the drain electrode 22 are ohmic electrodes and are, for example, alloys with a tantalum (Ta) layer, an aluminum (Al) layer, and a molybdenum (Mo) layer that overlap with each other. For example, the Ta layer before alloying has a thickness of 10 nm, the Al layer has a thickness of 120 nm, and the Mo layer has a thickness of 60 nm. A titanium (Ti) layer may be used instead of the Ta layer.

The gate electrode 23 is an example of the metal electrode in the present embodiment, and is provided at least in the gate opening 15a on the region of the nitride semiconductor layer 7 located between the source electrode 21 and the drain electrode 22. The gate electrode 23 is in contact with the cap layer 6 via the gate opening 15a. Specifically, the gate electrode 23 fills at least the gate opening 15a. The gate electrode 23 includes a material that is in Schottky contact with the cap layer 6, and has, for example, a laminated structure of a nickel (Ni) layer and a gold (Au) layer. In this case, the Ni layer comes into Schottky contact with the cap layer 6. As a material that can be in Schottky contact with the cap layer 6, Pt (platinum) or the like can be used in addition to Ni. The Ni layer has a thickness of, for example, 80 nm, and the Au layer has a thickness of, for example, 120 nm.

The gate electrode 23 has a first portion 23a in contact with the cap layer 6 and the SiN film 11, and a second portion 23b located on the first portion 23a. The width of the second portion 23b is larger than the width of the first portion 23a. Therefore, the gate electrode 23 has a substantially T-shaped cross section. The first portion 23a is in contact with at least the cap layer 6 exposed from the gate opening 15a and the opening edge of the gate opening 15a.

The Al ₂ O ₃ film 12 is provided on the Al ₂ O ₃ film 13 and covers the gate electrode 23. As described later, the Al ₂ O ₃ film 12 is formed by using, for example, the ALD method. Openings 12b and 12c are formed in the Al ₂ O ₃ film 12. The opening 12b is formed in a portion of the Al ₂ O ₃ film 12 that covers the source electrode 21, and exposes the upper surface of the source electrode 21. The source electrode 21 contacts a source electrode pad (not shown) through the opening 12b. The opening 12c is formed in a portion of the Al ₂ O ₃ film 12 that covers the drain electrode 22, and exposes the upper surface of the drain electrode 22. The drain electrode 22 is in contact with a drain electrode pad (not shown) via the opening 12c.

The Al _x F _y film 14 is an example of an inorganic compound film containing Al and F in the present embodiment. The Al _x F _y film 14 is adhered in a film shape on the side wall of the first portion 23a of the gate electrode 23 and the lower surface of the second portion 23b connected to the side wall. In other words, the Al _x F _y film 14 is formed between the Al ₂ O ₃ film 12 and the side wall of the first portion 23 a of the gate electrode 23 and the lower surface of the second portion 23 b connected to the side wall. .. As described later, Al _x F _y film 14 Al _x F _y constituting the, when forming a gate opening 15a by dry etching on the Al ₂ O ₃ film 13, a gas species containing fluorine, Al Al of the ₂ O ₃ film 13 reacts with Al and is generated. The Al _x F _y film 14 has the Al _x F _y attached to the gate electrode 23. The lower limit of the thickness of the Al _x F _y film 14 is, for example, 10 nm, and the upper limit thereof is, for example, 50 nm. The composition x of Al and the composition y of F can take various values depending on the forming conditions. Further, another atom different from Al and F may be mixed in the Al _x F _y film 14.

Next, a method of manufacturing the transistor 1 according to this embodiment will be described. When manufacturing the transistor 1, first, the nitride semiconductor layer 7 including the buffer layer 3, the channel layer 4, the barrier layer 5, and the cap layer 6 is formed on the substrate 2. For example, using the MOCVD method, an AlN layer functioning as the buffer layer 3, a GaN layer functioning as the channel layer 4, an AlGaN layer functioning as the barrier layer 5, and a GaN layer functioning as the cap layer 6 are formed on the SiC substrate. Epitaxial growth is performed in order.

2A to 2C, FIGS. 3A and 3B, and FIGS. 4A and 4B are views after the nitride semiconductor layer 7 is formed on the substrate 2. It is sectional drawing explaining a process. The substrate 2 is not shown in these figures. As shown in FIG. 2A, a SiN film 11 that is in contact with and covers the surface of the nitride semiconductor layer 7 is deposited on the nitride semiconductor layer 7. In this step, the SiN film 11 is deposited on the nitride semiconductor layer 7 by a low pressure CVD method or a plasma CVD method using dichlorosilane gas and ammonia gas as raw materials. In this step, the thickness of the SiN film 11 is set to, for example, 5 nm or more and 150 nm or less by controlling the deposition time. In one embodiment, the SiN film 11 has a thickness of 60 nm. When the SiN film 11 is formed by the low pressure CVD method, the lower limit value of the film forming temperature is, for example, 800° C. and the upper limit value is, for example, 900° C. This is a temperature extremely higher than the film forming temperature in the plasma CVD method. However, this temperature is lower than the growth temperature of the nitride semiconductor layer 7. When depositing the SiN film 11 by the low pressure CVD method, the lower limit value of the film forming pressure is, for example, 10 Pa, and the upper limit value is, for example, 100 Pa. The ratio (F1/F2) between the flow rate F1 of dichlorosilane and the flow rate F2 of ammonia gas is, for example, 0.3 or more. Since the flow rate ratio of this dichlorosilane is larger than the flow rate ratio of dichlorosilane that becomes stoichiometry, a Si-rich film is formed. The flow rate of dichlorosilane is, for example, in the range of 10 sccm to 100 sccm, and the flow rate of ammonia gas is, for example, in the range of 200 sccm to 2000 sccm. The unit sccm means cubic centimeter per minute in a standard state. 1 sccm corresponds to 1.69×10 ⁻⁴ Pa·m ³ ·sec ⁻¹ .

Next, an Al ₂ O ₃ film 13 that is in contact with the surface of the SiN film 11 and covers the surface is deposited on the SiN film 11. In this step, the Al ₂ O ₃ film 13 is deposited on the SiN film 11 by the ALD method using trimethylaluminum (TMA) and ozone (O ₃ ) as an oxidizing agent as raw materials. In this step, the thickness of the Al ₂ O ₃ film 13 is set to, for example, 10 nm or more and 50 nm or less by controlling the number of ALD cycles. In one example, the thickness of the Al ₂ O ₃ film 13 is 20 nm. The usage rate of TMA is, for example, 8×10 ⁻⁵ g/sec. The lower limit of the film forming temperature of the Al ₂ O ₃ film 13 is, for example, 200° C., and the upper limit thereof is, for example, 400° C. In one embodiment, the film forming temperature of the Al ₂ O ₃ film 13 is 300°C.

Subsequently, each part of the SiN film 11 and the Al ₂ O ₃ film 13 is selectively etched to form the source opening 15b and the drain opening 15c shown in FIG. 2B. Specifically, a resist is applied on the Al ₂ O ₃ film 13, and an opening pattern having the same planar shape as the source opening 15b and the drain opening 15c is formed in the resist. Then, first, dry etching of the Al ₂ O ₃ film 13 is performed through the opening pattern. At that time, the Al ₂ O ₃ film 13 is etched using a reaction gas containing a chlorine-based gas species (for example, a mixed gas of BCl ₃ and Cl ₂ ). The flow rate of BCl ₃ is, for example, 30 sccm, and the flow rate of Cl ₂ is, for example, 5 sccm. The RF power is, for example, 200 W, and the bias power is, for example, 10 W. The pressure is 0.4 Pa, for example. Next, dry etching of the SiN film 11 is performed through the opening pattern of the resist. At that time, the SiN film 11 is etched by using a reaction gas containing a fluorine-based gas species (for example, CF ₄ ). The flow rate of CF ₄ is, for example, 50 sccm. The RF power is, for example, 100 W, and the bias power is, for example, 30 W. The pressure is 0.4 Pa, for example. By this step, the source opening 15b and the drain opening 15c penetrating the SiN film 11 and the Al ₂ O ₃ film 13 are formed, and the nitride semiconductor layer 7 is exposed.

Then, the cap layer 6 in the source opening 15b and the drain opening 15c is removed by dry etching using chlorine gas as a reaction gas. As a result, the barrier layer 5 is exposed in the source opening 15b and the drain opening 15c. Then, the source electrode 21 is formed in the source opening 15b, and the drain electrode 22 is formed in the drain opening 15c. In this step, a metal for the source electrode 21 and the drain electrode 22 (for example, Ta layer, Al layer, and Mo layer) is formed by physical vapor deposition (PVD) such as vacuum deposition and lift-off. Form. Then, in order to use these as ohmic electrodes, the above metals are alloyed by heat treatment at, for example, 500° C. to 600° C. (570° C. for 5 minutes in one embodiment).

Subsequently, as shown in FIG. 2C, a laminated resist 30 is formed on the entire surface of the nitride semiconductor layer 7 (on the Al ₂ O ₃ film 13 and the electrodes 21 and 22). The laminated resist 30 is formed by sequentially laminating resists 31 to 33 on the Al ₂ O ₃ film 13 and the electrodes 21 and 22. Therefore, the resist 31 (lowermost layer resist) is in contact with the Al ₂ O ₃ film 13, and the resist 32 (intermediate layer resist) is located between the resist 31 and the resist 33 (uppermost layer resist). The thickness of each of the resists 31 to 33 is, for example, 150 nm or more and 800 nm or less. In the present embodiment, the resists 31 and 33 are formed to have substantially the same thickness, but the present invention is not limited to this. Further, although the resist 32 is formed thickest, the invention is not limited to this. In one example, the thickness of each of the resists 31-33 is 290/400/320 nm.

Each of the resists 31 to 33 is an electron beam resist. The electron beam resist is a resist exposed by an electron beam. The resists 31 and 33 are, for example, a copolymer of α-chloroacrylate and α-methylstyrene. In one embodiment, ZEP520A-7 manufactured by Nippon Zeon Co., Ltd. is used as the resists 31 and 33. The resist 32 is made of a substance different from the resists 31 and 33. Unlike the resists 31 and 33, the resist 32 is soluble in an alkaline solution. In one example, polymethylglutarimide (PMGI) is used as the resist 32.

Then, the opening 30a is formed in the laminated resist 30. In this step, first, the opening 33a (third opening) is formed in the resist 33. Specifically, the resist 33 is exposed with a first width corresponding to the opening width of the opening 33a. The electron beam applied to the resist 33 during this exposure does not reach the resist 31. Thereby, the width of the second portion 23b of the gate electrode 23 can be controlled accurately. In one embodiment, the dose of the electron beam during this exposure is 60 μC/cm ² . Then, the exposed portion of the resist 33 is developed to form an opening 33a in the resist 33. In the development, the above-mentioned portion of the resist 33 is etched with a solution containing at least one of methyl isobutyl ketone (MIBK) and methyl ethyl ketone (MEK). In one embodiment, a solution in which the ratio of MIBK and MEK (MIBK/MEK) is set to 6/4 or more is used.

After forming the opening 33a in the resist 33, an opening 32a (second opening) overlapping the opening 33a is formed in the resist 32. Specifically, the resist 32 is wet-etched through the opening 33a. In the wet etching, an opening 32a is formed in the resist 32 using, for example, an alkaline solution. The alkaline solution is, for example, a tetramethylammonium hydroxide (TMAH) aqueous solution. The opening width of the opening 32a is larger than the opening width of the opening 33a. Therefore, a part of the resist 33 functions as an eaves to the resist 32.

After forming the opening 32a in the resist 32, an opening 31a (first opening) that overlaps the openings 32a and 33a is formed in the resist 31. Specifically, the resist 31 is exposed through the openings 32a and 33a with a width corresponding to the opening width of the opening 31a. The dose amount of the electron beam applied to the resist 31 at the time of this exposure is larger than the dose amount of the electron beam at the time of exposing the resist 33. As a result, the opening 31a can be reliably formed, and the width of the opening 31a can be controlled with good reproducibility. In one embodiment, the dose of electron beam during this exposure is 800 μC/cm ² . The width of the opening 31a is narrower than the width of the opening 33a. That is, when the gate opening 15a is formed in a later step, the width of the gate opening 15a is set to, for example, 60 nm or more and 150 nm or less (90 nm in one embodiment). Further, from the viewpoint of preventing the shapes of the openings 32a and 33a from being changed when the openings 31a are formed, the electron beam applied to the resist 31 is not directly applied to the resists 32 and 33. Then, the exposed portion of the resist 31 is developed to form an opening 31a in the resist 31. In the development, a developing solution weaker than the solution used for developing the resist 33 is used. This can prevent or suppress the etching of the resist 33 during the development of the resist 31. In one embodiment, the developing solution for the resist 31 is a mixed solution of MIBK and isopropyl alcohol (IPA).

By performing exposure, development, and etching as described above, the laminated resist 30 including the resist 31 having the opening 31a, the resist 32 having the opening 32a, and the resist 33 having the opening 33a is formed. The openings 31a to 33a overlap each other and form the opening 30a. Among the openings 31a to 33a, the opening width of the opening 31a is the smallest and the opening width of the opening 32a is the largest.

Subsequently, as shown in FIG. 3A, a gate opening 15a penetrating the Al ₂ O ₃ film 13 and the SiN film 11 is formed in these films 13 and 11 by dry etching using the laminated resist 30 as a mask. Form. In this step, the Al ₂ O ₃ film 13 and the SiN film 11 are continuously etched without changing the type of etching gas. The plasma etching is, for example, reactive ion etching (RIE). As the etching gas (reactive gas), a gas mainly containing a fluorine-based gas species is used. As the fluorine-based gas species, for example, one or more is selected from the group consisting of SF ₆ , CF ₄ , CHF ₃ , C ₃ F ₆ , and C ₂ F ₆ . The phrase “mainly contains a fluorine-based gas species” means that the fluorine-based gas species occupy more than half of the etching gas (excluding an inert gas such as N ₂ that does not contribute to etching). In one example, the etching gas used in this step is composed of a fluorine-based gas species and an inert gas, and does not include a chlorine-based gas species (for example, BCl ₃ , Cl ₂ etc.).

When the fluorine-based gas species contained in the etching gas is CF ₄ , the etching gas flow rate is, for example, 50 sccm, the RF power is, for example, 100 W, and the reaction pressure is, for example, 0. 0 through the etching of the Al ₂ O ₃ film 13 and the SiN film 11. It is set to 4 Pa. The bias power when etching the SiN film 11 is set to be smaller than the bias power when etching the Al ₂ O ₃ film 13. In one example, the bias power when etching the SiN film 11 is 30 W, and the bias power when etching the Al ₂ O ₃ film 13 is 10 W. That is, the bias power is changed before and after the timing when the etching of the Al ₂ O ₃ film 13 ends and the etching of the SiN film 11 starts.

When a fluorine-based gas species is used, the etching rate of SiN is significantly higher than the etching rate of Al ₂ O ₃ . For example, when the bias power is 30 W, the etching rate of Al ₂ O ₃ is 0.12 nm/sec, and the etching rate of SiN is 1.2 nm/sec. When the bias power is 10 W, the etching rate of Al ₂ O ₃ is 0.04 nm/sec, and the etching rate of SiN is 0.4 nm/sec. Therefore, by changing the bias power as described above, while suppressing the etching time of the Al ₂ O ₃ film 13 from becoming excessively long, the etching time of the SiN film 11 is secured and the etching stop timing is accurately adjusted. Can be controlled.

For example, when the thickness of the Al ₂ O ₃ film 13 is 20 nm and the bias power is 30 W, the etching time of the Al ₂ O ₃ film 13 is calculated as 168 seconds. Actually, about 30 seconds is added as overetching to it. The overetching time is set to 18% or less of the calculated etching time, and is set within the range of 10 to 15%, for example. As a result, the portion of the Al ₂ O ₃ film 13 in the gate opening 15a is completely etched. In that case, the first SiN layer 11 is etched up to about 36 nm, but if the thickness of the first SiN layer 11 is more than that (for example, 60 nm), the nitride semiconductor layer 7 is exposed. There is no. Then, the remaining portion (thickness: 24 nm) of the first SiN layer 11 is etched with a bias power of 10 W. The etching time is calculated as 60 seconds, and about 30 seconds is added as overetching to it.

In the above description, the bias power change timing is controlled by time, but a so-called endpoint monitor may be used. That is, even in a part of a region unrelated to the device (for example, a region in which a process monitor element or the like is formed) out of the entire region on the wafer surface, the Al ₂ O ₃ film 13 and the SiN film 11 are formed at the same time when the gate opening 15a is formed. Etching. Then, by observing the change in the reflectance at the boundary between the Al ₂ O ₃ film 13 and the first SiN layer 11, the timing when the etching of the Al ₂ O ₃ film 13 is completed (that is, the bias power change timing) is determined. It can be detected accurately.

In this step, as shown in FIG. 3A, the Al _x F _y film 14 is formed on the inner surface of the opening 31a of the resist 31 and around the opening 31a. The Al _x F _y film 14 is attached in a film shape on the inner surface of the opening 31 a of the resist 31 and around the opening 31 a. Al _x F _y constituting the Al _x F _y layer 14, when performing dry etching on the Al ₂ O ₃ film 13, cross the gas species containing fluorine, and Al of the Al ₂ O ₃ film 13 is Generated in response to. As described above, the Al composition x and the F composition y can take various values depending on the formation conditions (gas species and etching conditions). Further, another atom different from Al and F may be mixed in the Al _x F _y film 14.

Subsequently, as shown in FIG. 3B, a metal electrode is deposited in the gate opening 15a and around the gate opening 15a through the openings 31a to 33a and the gate opening 15a. The deposition of the metal electrode is performed by a vapor deposition method such as PVD. In this step, first, using the laminated resist 30 as a mask, a first portion 23a having a width corresponding to the opening width of the opening 31a and contacting the nitride semiconductor layer 7 with the opening width of the gate opening 15a is deposited. Next, using the laminated resist 30 as a mask, a second portion 23b having a width larger than that of the first portion 23a is deposited on the first portion 23a and the resist 31. In this step, the Al _x F _y film 14 described above is attached to the side surface of the first portion 23a, the portion facing the resist 31, and the lower surface of the second portion 23b.

Subsequently, as shown in FIG. 4A, the laminated resist 30 is removed to lift off the metal material deposited on the laminated resist 30. As the peeling liquid, for example, clean-through KS-7008B (registered trademark) is used. Note that Al _x F _y has high resistance to a stripping solution and inhibits stripping of the laminated resist 30. Further, in the previous step, Al _x F _y adheres not only to the resist 31 but also to the inner surface of the opening 32 a of the resist 32 and the inner surface of the opening 33 a of the resist 33. However, when the present inventor prototyped the transistor 1, Al _x F _y was mostly adhered to the resist 31, and the openings 32a and 33a of the resists 32 and 33 were slightly exposed (the resists 32 and 33 were completely removed). It was not covered by. Therefore, there is no difficulty in peeling the laminated resist 30.

Subsequently, as shown in FIG. 4B, an Al ₂ O ₃ film 12 is deposited on the SiN film 11 and the electrodes 21 and 22, and the gate electrode 23 is covered with the Al ₂ O ₃ film 12. In this step, the Al ₂ O ₃ film 12 is deposited by the ALD method using TMA and O ₃ as an oxidizing agent as raw materials. In this step, the thickness of the Al ₂ O ₃ film 12 is set to, for example, 10 nm or more and 60 nm or less by controlling the number of ALD cycles. After that, the Al ₂ O ₃ film 12 on the electrodes 21 and 22 is etched to form openings 12b and 12c (see FIG. 1). Through the above steps, the transistor 1 shown in FIG. 1 is manufactured. Instead of the Al ₂ O ₃ film 12, a SiN film may be deposited by the plasma CVD method.

The operation and effect obtained by the transistor 1 and the manufacturing method thereof according to the present embodiment described above will be described. As described above, in a field effect transistor such as HEMT, the shorter the length of the contact surface between the gate electrode and the nitride semiconductor layer (gate length), the higher the electric characteristics such as high frequency characteristics. Therefore, the gate length should be shortened. Is required. However, the smaller the width of the contact surface between the gate electrode and the nitride semiconductor layer, the weaker the degree of adhesion between the gate electrode and the nitride semiconductor layer, and the lower the mechanical strength of the gate electrode. Furthermore, when forming the gate electrode on the nitride semiconductor layer, it is necessary to suppress damage to the nitride semiconductor layer. Therefore, when forming the gate electrode, the vapor deposition lift-off method as in this embodiment is used. Often used. The gate electrode formed by evaporation has a lower density and a lower degree of adhesion to the nitride semiconductor layer than the gate electrode formed by a sputtering method. Therefore, defects such as collapse of the gate electrode are likely to occur, the yield rate of the transistor is suppressed, and the yield is reduced.

As in the present embodiment, the mechanical strength of the gate electrode can be increased by covering the gate electrode with a protective film such as an Al ₂ O ₃ film. And, the thicker the protective film is, the more the loss of the gate electrode can be reduced. However, the thicker the protective film is, the more the gate capacitance is increased, so that the high frequency characteristics of the transistor 1 are deteriorated. Therefore, in order to provide the transistor 1 with sufficient high frequency characteristics, the mechanical strength of the gate electrode cannot be sufficiently increased.

In order to solve such a problem, in the present embodiment, in the step of forming the gate opening 15a, the Al ₂ O ₃ film 13 and the SiN film 11 are continuously formed by using an etching gas mainly containing a fluorine-based gas species. Is being etched. As a result, the Al _x F _y film 14 attached to the gate electrode 23 contributes to increase the resistance (mechanical strength) of the gate electrode 23 to the subsequent steps. Therefore, according to the present embodiment, since the mechanical strength of the gate electrode 23 can be increased, defects such as the collapse of the gate electrode 23 can be reduced, and the yield rate of the transistor 1 can be improved by increasing the yield rate of the transistor 1. .. In particular, this embodiment is suitable when the gate length is short and when the gate electrode 23 is formed by using the vapor deposition lift-off method.

FIG. 5 is an SEM photograph showing the vicinity of the gate electrode 23 of the transistor 1 prototyped by the present inventor. Referring to FIG. 5, the Al _x F _y film 14 is attached to the side surface of the first portion 23a of the gate electrode 23 and the lower surface of the second portion 23b, and the gate electrode 23 is formed without any defect. Recognize. In the figure, the Ni layer 23c of the gate electrode 23 and the Au layer 23d are shown.

As in the present embodiment, the gate electrode 23 may be the gate electrode of a field effect transistor. As described above, the shorter the gate length of the gate electrode, the higher the high frequency characteristics of the field effect transistor. According to the transistor 1 and the method of manufacturing the same of the present embodiment, the mechanical strength of the gate electrode 23 can be increased, so that the gate length can be further shortened while suppressing an increase in defects of the gate electrode 23. ..

As in the present embodiment, the step of forming the gate opening 15a includes a resist 31 having an opening 31a, a resist 32 having an opening 32a, and a resist 33 having an opening 33a, and the openings 31a to 33a overlap each other and the opening 32a is formed. opening width formed forming the largest laminated resist 30 on the Al ₂ O ₃ film 13, a gate opening 15a in the Al ₂ O ₃ film 13 and the SiN film 11 by dry etching using laminated resist 30 as a mask for The process may be included. For example, the T-type gate electrode 23 can be formed by such a method. Further, the Al _x F _y film 14 is attached to the side surface of the first portion 23a of the gate electrode 23 and the lower surface of the second portion 23b to effectively increase the mechanical strength of the first portion 23a of the gate electrode 23. Can be increased to

As in the present embodiment, the fluorine-based gas species may be one or more gas species selected from the group consisting of SF ₆ , CF ₄ , CHF ₃ , C ₃ F ₆ , and C ₂ F _6. Good. As a result, the Al _x F _y film 14 can be preferably formed.

The method for manufacturing a semiconductor device according to the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the above embodiment, the Al ₂ O ₃ film 13 is formed before forming the ohmic electrodes (source electrode and drain electrode), but the ohmic electrode is formed first, and then the Al ₂ O ₃ film 13 is formed. It may be formed. Further, in the above embodiment, the SiN film 11 is exemplified as the insulating first inorganic compound film containing Si, but another Si compound film may be used. Further, in the above embodiment, the Al ₂ O ₃ film 13 is exemplified as the second inorganic compound film containing Al, but another Al compound film may be used.

1... Transistor, 2... Substrate, 3... Buffer layer, 4... Channel layer, 5... Barrier layer, 6... Cap layer, 6a... Surface, 7... Nitride semiconductor layer, 11... SiN film, 12... Al ₂ O ₃ Films, 12b, 12c... Openings, 13... Al ₂ O ₃ films, 14... Al _x F _y films, 15a... Gate openings, 15b... Source openings, 15c... Drain openings, 21... Source electrodes, 22... Drain electrodes, 23 ...Gate electrode, 23a...first part, 23b...second part, 30... laminated resist, 31...resist (lowermost layer resist), 31a...opening (first opening), 32...resist (intermediate layer resist) , 32a... Opening (second opening), 33... Resist (uppermost layer resist), 33a... Opening (third opening).

Claims (12)

A method for manufacturing a nitride semiconductor device, comprising:
Depositing an insulative first inorganic compound film containing Si on the nitride semiconductor layer;
Depositing a second inorganic compound film containing Al on the first inorganic compound film;
Forming an opening penetrating the first inorganic compound film and the second inorganic compound film by dry etching;
Depositing a metal electrode in the opening,
Including,
The method for manufacturing a nitride semiconductor device, wherein in the step of forming the opening, the second inorganic compound film and the first inorganic compound film are continuously etched by using an etching gas mainly containing a fluorine-based gas species. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the metal electrode is a gate electrode of a field effect transistor. The step of forming the opening includes
A bottom layer resist having a first opening, an intermediate layer resist having a second opening, and a top layer resist having a third opening, wherein the first to third openings overlap each other, and the second opening Forming a laminated resist having the largest width on the second inorganic compound film,
Forming the opening in the second inorganic compound film and the first inorganic compound film by dry etching using the laminated resist as a mask;
The method for manufacturing a nitride semiconductor device according to claim 1, further comprising: The method for manufacturing a nitride semiconductor device according to claim 1, wherein the first inorganic compound film is a SiN film. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the second inorganic compound film is an Al ₂ O ₃ film. The fluorine gas species is _{SF 6, CF 4, CHF 3} , C 3 F 6, and one or more gas species selected from the group consisting of C ₂ F _6, one of the claims 1 to 5 2. A method for manufacturing a nitride semiconductor device according to item 1. The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the step of depositing the second inorganic compound film, the second inorganic compound film is deposited using an ALD method. The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the step of depositing the second inorganic compound film, the thickness of the second inorganic compound film is 10 nm or more and 50 nm or less. 9. The nitride semiconductor device according to claim 1, wherein in the step of depositing the first inorganic compound film, the first inorganic compound film is deposited using a plasma CVD method or a low pressure CVD method. Production method. The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the step of depositing the first inorganic compound film, the thickness of the first inorganic compound film is set to 5 nm or more and 150 nm or less. The method for manufacturing a nitride semiconductor device according to claim 1, wherein in the step of forming the opening, the width of the opening is 60 nm or more and 150 nm or less. A nitride semiconductor layer,
An insulating first inorganic compound film containing Si, which is provided on the nitride semiconductor layer;
A second inorganic compound film containing Al, which is provided on the first inorganic compound film;
A metal electrode provided in an opening penetrating the first inorganic compound film and the second inorganic compound film;
Equipped with
A nitride semiconductor device in which an inorganic compound containing Al and F is adhered in a film shape on the side wall of the metal electrode.