JP2020072156A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To improve estimation accuracy of a yield.SOLUTION: A method for manufacturing a silicon carbide semiconductor device comprises the steps of: forming an epitaxial wafer 50 by growing an epitaxial layer 40 on an SiC wafer 10; forming a semiconductor wafer 60 by forming a semiconductor element on the epitaxial wafer 50; deriving a contrast value based on an uneven variance on a surface of each epitaxial layer 40 formed on each chip formation region 30 using a confocal scanning device including a differential interference optical system after forming the epitaxial wafer 50; determining whether or not the contrast value is within a contrast threshold value range; and determining epitaxial wafer acceptability by comparing a ratio of a total number of the chip formation regions 30 in which a portion in which the contrast value is out of the contrast threshold value is arranged to a total number of a plurality of chip formation regions 30 with a prescribed wafer threshold value. The method forms the semiconductor wafer 60 only when determining that the ratio is less than the wafer threshold value by determining epitaxial wafer acceptability.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a SiC semiconductor device using a silicon carbide (hereinafter referred to as SiC) wafer.

  Conventionally, it has been proposed to form an epitaxial layer on a SiC wafer, perform a predetermined semiconductor manufacturing process to form a semiconductor element, and then divide the chip into chips to manufacture an SiC semiconductor device. However, it is known that various defects can be introduced into the epitaxial layer when the epitaxial layer is formed on the SiC wafer.

  Therefore, for example, Patent Document 1 proposes a method of using a confocal scanning device having a differential interference optical system to identify the type of defects introduced into the epitaxial layer based on the confocal differential interference image. .. Then, for example, the yield or the like is estimated based on the identified defect type, and when it is estimated that the yield will be equal to or higher than a predetermined value, a step of forming a semiconductor element or the like is performed.

JP, 2011-211035, A

  However, as a result of examination by the present inventors, the characteristic variation (for example, drain leak) in the SiC semiconductor device depends strongly on the surface irregularity state in the epitaxial layer, although it also depends on the type of defects introduced into the epitaxial layer. It was confirmed to do. That is, according to the study by the present inventors, it is confirmed that the accurate yield is difficult to be estimated even if the type of the defect is specified, and the desired yield may not be obtained when the SiC semiconductor device is manufactured. Was done.

  In view of the above points, an object of the present invention is to provide a method for manufacturing a SiC semiconductor device, which can obtain a desired yield when manufacturing a SiC semiconductor device while improving the accuracy of yield estimation.

  A method for manufacturing a SiC semiconductor device having an epitaxial layer (40) according to claim 1 for achieving the above object, comprising a main surface (10a), a single crystal of SiC, and a plurality of chip forming regions. Preparing a SiC wafer (10) having (30), growing an epitaxial layer composed of SiC on the main surface to form an epi-wafer (50), and forming a semiconductor device on the epi-wafer to form a semiconductor. Forming a wafer (60). Then, after forming the epi-wafer, a confocal scanning device having a differential interference optical system is used to derive a contrast value based on the amount of unevenness change on the surface of each epitaxial layer formed on the plurality of chip formation regions. And comparing each of the derived contrast values with the contrast value to determine whether it is within the range of the contrast threshold value set in a predetermined range, and the contrast value with respect to the total number of the plurality of chip formation regions is Forming a semiconductor wafer by performing a pass / fail judgment of an epi-wafer comparing a ratio of the total number of chip formation regions in which a portion outside the range of the contrast threshold is arranged, with a predetermined wafer threshold, Only when it is determined that the ratio is less than the wafer threshold value when the quality of the epitaxial wafer is determined.

  According to this, as the characteristic variation in the SiC semiconductor device depends on the contrast value as shown in FIG. 5, the yield estimation accuracy can be improved. Then, the semiconductor wafer is formed only when the ratio is determined to be less than the wafer threshold value when the quality of the epitaxial wafer is determined. Therefore, the SiC semiconductor device can be manufactured in a state where a desired yield is expected.

  The reference numerals in parentheses that are given to the respective components and the like indicate an example of a correspondence relationship between the components and the like and specific components and the like described in the embodiments described later.

6 is a flowchart showing a manufacturing process of the SiC semiconductor device in the first embodiment. It is sectional drawing of the SiC wafer prepared by a SiC wafer preparation process. It is sectional drawing of the epi-wafer formed in an epi-wafer formation process. It is sectional drawing of the semiconductor wafer formed in a semiconductor wafer formation process. It is a top view of a SiC wafer. It is a figure which shows the experimental result regarding the relationship between a contrast value and surface unevenness. It is a figure which shows the experimental result regarding the relationship between a contrast value and the area | region where the characteristic variation generate | occur | produced. It is a schematic diagram which shows the position estimated to become a defective product in a contrast value comparison process. It is a schematic diagram which shows the position determined to be defective in a semiconductor element characteristic inspection process. It is a figure which shows the relationship between the defect rate estimated to become a defective product in a some semiconductor wafer, and the defect rate judged to be a defective product actually.

  Embodiments of the present invention will be described below with reference to the drawings. In each of the following embodiments, the same or equivalent portions will be denoted by the same reference numerals for description.

(First embodiment)
The first embodiment will be described. In the method for manufacturing the SiC semiconductor device of the present embodiment, as shown in FIG. 1, a SiC wafer preparation step S100, an epi wafer formation step S110, a contrast value derivation step S120, and a contrast value comparison step S130 are sequentially performed. Further, in the method of manufacturing the SiC semiconductor device, the epitaxial wafer quality determination step S140, the semiconductor wafer forming step S150, and the semiconductor element characteristic inspection step S160 are sequentially performed. Hereinafter, each of the steps S100 to S160 will be described in order.

First, in SiC wafer preparation step S100, as shown in FIGS. 2A and 3, SiC wafer 10 having main surface 10a is prepared. For example, as the SiC wafer 10, a 4H-type SiC single crystal having an angle (that is, an off angle) formed by the main surface 10a with respect to a (0001) Si plane of 4 ° and an off direction of <11-20> is used. What is configured and prepared as n ⁺ type is prepared. Further, the SiC wafer 10 has a plurality of chip forming regions 30 partitioned by the dicing line 20, and each of the plurality of chip forming regions 30 has a square shape with one side of about 2 to 10 mm. In this embodiment, each side has a square shape of 5 mm.

  Note that the off direction here is a “direction parallel to the vector obtained by projecting the normal vector of the growth surface onto the (0001) plane”. Further, FIG. 2A is a cross-sectional view showing a part of one chip formation region 30. In addition, the chip formation region 30 of the SiC wafer 10 is actually provided in a larger number than that shown in FIG.

  In the epi-wafer forming step S110, as shown in FIG. 2B, an epitaxial layer 40 composed of SiC is grown on the main surface 10a of the SiC wafer 10 by a CVD (abbreviation of Chemical Vapor Deposition) method or the like. Form 50. At this time, various defects such as convex defects, concave defects, particle defects, carrots, and triangular defects may be introduced into the epitaxial layer 40.

It is known that the defects introduced into the epitaxial layer 40 are introduced with a plane size of about 20 to 400 μm, which is sufficiently smaller than the chip formation region 30. Further, in the present embodiment, the epitaxial layer 40 is, for example, an n ⁻ type with an impurity concentration lower than that of the SiC wafer 10.

  In the contrast value deriving step S120, a confocal scanning device having a differential interference optical system (hereinafter, simply referred to as a confocal scanning device) is used to derive a contrast value based on the unevenness change amount on the surface of the epitaxial layer 40. The surface of the epitaxial layer 40 is the surface of the epitaxial layer 40 opposite to the main surface 10a. Further, the unevenness change amount on the surface of the epitaxial layer 40 also means, in other words, the gradient change amount.

  In this embodiment, a confocal scanning device having the same configuration as the confocal scanning device described in Japanese Patent Application Laid-Open No. 2011-211035 is used. Therefore, a detailed description of the configuration of the confocal scanning device will be omitted, but in brief description, the confocal scanning device determines a minute unevenness variation amount of about several nm formed on the surface of the epitaxial layer 40. It is configured so that it can be detected as a phase difference. Further, the confocal scanning device is configured to be able to detect the variation amount of the unevenness as a brightness image when the unevenness of several nm is formed on the surface of the epitaxial layer 40. That is, in the confocal differential interference contrast image obtained by the confocal scanning device, the unevenness variation amount is detected as a low-luminance image or a high-luminance image.

  Then, in the contrast value deriving step S120, the confocal scanning device is appropriately scanned to image the entire surface of the epi-wafer 50, and based on the obtained confocal differential interference image, the coordinate (that is, address) and the contrast value at the coordinate are calculated. Derive. That is, the contrast value is derived according to the variation amount of the unevenness of the surface of the epitaxial layer 40 formed on each chip formation region 30.

  The contrast value in this specification is a value derived from "maximum luminance-minimum luminance in a predetermined area in a confocal differential interference image represented by luminance gradation". That is, in the confocal differential interference contrast image, the brightness changes depending on the amount of unevenness on the surface of the epitaxial layer 40, and therefore the contrast value is derived as “maximum brightness-minimum brightness of the extracted defect region and its peripheral portion”. It can be said to be a value.

  Then, since the contrast value is defined as described above, the magnitude of the contrast value depends on the unevenness change amount. Specifically, as shown in FIG. 4, the contrast value increases as the unevenness change amount increases.

  The confocal scanning device can also acquire information on the three-dimensional shape and the cross-sectional shape, and can specify the detailed type of the defect. However, in this embodiment, only the contrast value is derived using the confocal scanning device, and the type of defect is not specified. Further, as described above, the defect has a plane size of about 20 to 400 μm, and it is not assumed that the entire epitaxial layer 40 formed on one chip formation region 30 is filled with the defect. Therefore, when the epitaxial layer 40 formed on each chip formation region 30 has unevenness, a contrast value corresponding to the unevenness is derived.

  In the contrast value comparison step S130, it is determined whether or not the contrast value in the epitaxial layer 40 on each chip forming region 30 is within a contrast threshold range set in a predetermined range.

  Here, the range of the contrast value and the characteristic variation of the SiC semiconductor device obtained by the present inventors in an actual experiment will be described with reference to FIG. Note that, here, a MOSFET (abbreviation of metal oxide semiconductor field effect transistor) is configured as the SiC semiconductor device, and the characteristic variation is defined when a drain leak occurs. As shown in FIG. 5, it is confirmed that the characteristic variation in the SiC semiconductor device depends not on the type of defect but on the magnitude of the contrast value (that is, the magnitude of the unevenness change on the surface of the epitaxial layer 40). It Specifically, the experiments conducted by the present inventors have confirmed that when the contrast value is 0 to 90, the characteristic of the SiC semiconductor device does not vary regardless of the type of defect.

  The range of the contrast threshold depends on various members constituting the confocal scanning device and is set for each confocal scanning device used. For example, when the result shown in FIG. 5 is obtained, the contrast threshold is set to 0-90.

  Then, in the contrast value comparing step S130, when the contrast value is within the range of the contrast threshold value, it is estimated that the SiC semiconductor device including this region is a good product. Further, in the contrast value comparing step S130, when the contrast value is outside the range of the contrast threshold value, it is estimated that the SiC semiconductor device including this region is defective.

  In the contrast value deriving step S120, when a plurality of defects are introduced in the epitaxial layer 40 formed on one chip formation region, a plurality of contrasts are obtained from the confocal differential interference contrast image corresponding to the epitaxial layer 40. The value is derived. That is, when the epitaxial layer 40 formed on one chip formation region has a plurality of irregularities, a plurality of contrast values are derived from the confocal differential interference contrast image corresponding to the epitaxial layer 40. In this case, in the contrast value comparing step S130, if at least one contrast value is outside the range of the contrast threshold value, it is estimated that the SiC semiconductor device including this region is defective.

  Then, in the contrast value comparison step S130, for example, as shown in FIG. 6, the chip formation region 30 and the portion estimated to be a defective product are mapped in correspondence with each other. Note that, in FIG. 6, the chip formation region 30 in which a portion estimated to be a defective product is arranged is hatched. Further, FIG. 6 shows the result of actually performing the contrast value comparison step S130.

  In the epi-wafer quality determination step S140, first, the total number of chip formation regions 30 in which the portions estimated to be defective in the contrast value comparison step S130 are arranged (hereinafter simply referred to as the total number of estimated defects) is specified. .. Then, in the epitaxial wafer quality determination step S140, the ratio of the total number of estimated defects to the total number of chip formation regions 30 (hereinafter referred to as the estimated defect rate) is compared with a predetermined wafer threshold. For example, in FIG. 6, since the total number of chip formation regions is 198 and the total number of estimated defects is 20, the estimated defective rate is about 10%. The predetermined wafer threshold value is appropriately changed according to the required yield, and is set to 20%, for example.

  In the semiconductor wafer forming step S150, as shown in FIG. 2C, for example, various semiconductor manufacturing processes are appropriately performed to form the p-type layer 61 and the n-type layer 62, thereby forming a MOSFET (Metal Oxide Semiconductor Field Effect). A desired semiconductor element such as an element (abbreviated as Transistor) is formed. As a result, the semiconductor wafer 60 having the semiconductor element is formed.

  However, the semiconductor wafer forming step S150 is performed only when the estimated defective rate is less than the wafer threshold. In other words, the semiconductor wafer forming step S150 is not performed when the estimated defective rate is equal to or higher than the wafer threshold. That is, the semiconductor wafer forming step S150 is performed only when a yield higher than a predetermined value is expected.

  In the semiconductor element characteristic inspection step S160, characteristic inspection including electrical characteristics of the semiconductor element is performed. In the present embodiment, in the contrast value comparison step S130, the semiconductor element characteristic inspection step S160 is performed on the semiconductor element including only the portion estimated to be non-defective. That is, in the contrast value comparison step S130, the semiconductor element characteristic inspection step S160 of electrical characteristics and the like is not performed on the semiconductor element including the portion estimated to be defective.

  FIG. 7 shows the result of the semiconductor device characteristic inspection step S160 actually performed on all the portions by the present inventors. In FIG. 7, the chip formation of the portion determined to be defective in the actual characteristic inspection is shown. The area 30 is hatched. Further, FIG. 7 shows the results corresponding to FIG. 6, and the wafer used in the experiment of FIG. 6 is used as it is. As shown in FIGS. 6 and 7, it is confirmed that the estimation result and the actual result substantially match. Further, as shown in FIG. 8, the estimated defective rate and the actually measured defective rate are almost the same, and it is confirmed that a correct answer rate of 70% or more is obtained. The measured defective rate is a value based on the total number of the chip forming areas 30 in which the portion actually determined to be defective is arranged, with respect to the total number of the chip forming areas 30.

  Thereafter, although not particularly shown, the semiconductor wafer 60 is divided into chips to manufacture the SiC semiconductor device.

  As described above, the characteristic variation (for example, drain leak) in the SiC semiconductor device depends on the contrast value as shown in FIG. Then, in the present embodiment, based on the contrast value on the surface of the epitaxial layer 40, the portion that becomes a defective product when the SiC semiconductor device is configured is estimated. Therefore, the yield estimation accuracy can be improved. Further, it is not necessary to specify the type of defect, and the manufacturing process can be simplified.

  Further, in the present embodiment, the semiconductor wafer forming step S150 is performed only when it is determined in the epitaxial wafer quality determination step S140 that the estimated defective rate is less than the wafer threshold. Therefore, the SiC semiconductor device can be manufactured in a state in which a yield higher than a predetermined value is expected.

  Further, in the present embodiment, the semiconductor element characteristic inspection step S160 is performed only on the portion which is estimated to be a good product in the contrast value comparison step S130. Therefore, the inspection process can be simplified.

(Other embodiments)
The present invention is not limited to the above-described embodiments, but can be appropriately modified within the scope of the claims.

  For example, in each of the above-described embodiments, the 4H-type SiC wafer 10 is described as an example, but other polymorphic SiC wafers 10 such as 6H-type, 3C-type, and 15R-type may be used. Further, although the off angle with respect to the (0001) plane is 4 ° as an example, another angle may be used.

  Further, in the first embodiment, in the semiconductor wafer forming step S150, the semiconductor element may not be formed in the portion estimated to be defective in the contrast value comparing step S130. That is, in the first embodiment, in the semiconductor wafer forming step S150, the semiconductor element including the portion estimated to be defective in the contrast value comparing step S130 may not be formed. According to this, the semiconductor wafer forming process can be simplified.

  Then, in the first embodiment, in the semiconductor element characteristic inspection step S160, the characteristic inspection of all the semiconductor elements may be performed. Even in the method of manufacturing such a SiC semiconductor device, the semiconductor wafer forming step S150 is performed only when the estimated defect rate is less than the wafer threshold, and thus a desired yield can be obtained.

  Furthermore, in the first embodiment described above, the SiC wafer 10 prepared may be p-type.

  In the first embodiment, the semiconductor element formed on the epi-wafer 50 may be a diode element instead of a MOSFET element, an IGBT (abbreviation of Insulated Gate Bipolar Transistor) element, or the like.

  In addition, when indicating the crystal orientation, a bar (-) should be added above the desired number, but there is a restriction in terms of expression based on the electronic application. A bar shall be added before the number.

10 SiC Wafer 10a Main Surface 30 Chip Forming Area 40 Epitaxial Layer 50 Epiwafer 60 Semiconductor Wafer

Claims (3)

A method of manufacturing a silicon carbide semiconductor device having an epitaxial layer (40), comprising:
Providing a silicon carbide wafer (10) having a main surface (10a) and made of silicon carbide single crystal and having a plurality of chip forming regions (30);
Growing the epitaxial layer of silicon carbide on the major surface to form an epi-wafer (50);
Forming a semiconductor element on the epi-wafer to form a semiconductor wafer (60),
After forming the epi-wafer,
Using a confocal scanning device having a differential interference optical system, deriving a contrast value based on the unevenness change amount on the surface of each of the epitaxial layers formed on the plurality of chip formation regions,
Comparing the contrast values to determine whether each of the derived contrast values is within the range of the contrast threshold value set in a predetermined range,
Determining the quality of the epi-wafer comparing the ratio of the total number of the chip forming regions in which the part where the contrast value is outside the range of the contrast threshold value to the total number of the plurality of chip forming regions and a predetermined wafer threshold value And
The method of manufacturing a silicon carbide semiconductor device, wherein forming the semiconductor wafer is performed only when it is determined that the ratio is less than the wafer threshold value when the quality of the epi wafer is determined. After forming the semiconductor wafer, inspect the characteristics of the semiconductor device,
Inspecting the characteristic, in comparing the contrast values, inspects the characteristic of the semiconductor element formed so as to include only a portion where the contrast value is determined to be within the range of the contrast threshold. The method for manufacturing the silicon carbide semiconductor device according to claim 1. In forming the semiconductor wafer, the semiconductor element is formed so as to include only a portion where the contrast value is determined to be within the range of the contrast threshold when comparing the contrast values. 1. A method for manufacturing a silicon carbide semiconductor device according to 1.

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