JP2016025241A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a silicon carbide semiconductor device capable of making a process more efficient.SOLUTION: A method for manufacturing a silicon carbide semiconductor device comprises the steps of: preparing an epitaxial wafer containing a silicon carbide substrate and a silicon carbide layer (S10, S20); forming an impurity region in the silicon carbide layer (S30); determining a position coordinate of a defective part existing inside the silicon carbide layer in which the impurity region is formed by detecting the light emitted due to the defective part after the silicon carbide layer is irradiated with excitation light of a wavelength not more than 400 nm (photoluminescence measuring step S60); forming a plurality of elements (S70 to S100); determining a defective element in which a defective part was introduced into the inside of the silicon carbide layer on the basis of the position coordinate of the defective part (S110); and measuring withstand voltage of other elements except the defective elements among the plurality of elements (withstand voltage measuring step S120).SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device. In particular, the present invention relates to a method for manufacturing a silicon carbide semiconductor device including a withstand voltage measurement step.

  Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material constituting a semiconductor device. Therefore, for example, a semiconductor device using silicon carbide as a material (hereinafter, also referred to as “silicon carbide semiconductor device”), such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), can increase the breakdown voltage of the semiconductor device and reduce the on-resistance. Can be achieved.

  Since there are more defects in the silicon carbide crystal than in the silicon crystal, there may be a breakdown voltage defect due to the defect in the silicon carbide semiconductor device. Therefore, in the manufacturing process of the silicon carbide semiconductor device, after a plurality of elements are formed on the silicon carbide substrate, withstand voltage measurement is performed on each element. Based on the result of the pressure resistance measurement, the non-defective product and the defective product are selected.

  Since the withstand voltage measurement is performed on each element, there is a problem that the measurement time becomes long when the number of elements is large (when the substrate size is large and the element size is small). On the other hand, in JP2013-118242A (Patent Document 1), after a silicon carbide layer is epitaxially grown on a silicon carbide substrate, micropipes existing inside the silicon carbide layer are detected, and then In addition, a method of excluding an element including the micropipe from an evaluation object in the characteristic evaluation of the element is described.

JP2013-118242A

  In the method described in Patent Document 1, after a silicon carbide layer is epitaxially grown on a silicon carbide substrate, a carbon layer is formed on the silicon carbide layer by performing a high-temperature annealing treatment. Then, the micropipe can be exposed on the surface of the silicon carbide layer by removing the carbon layer by an etching process. Thereby, a micropipe can be detected. However, the above method has a problem that the efficiency of the entire process is lowered because a multi-step process is required to expose the micropipe to the surface.

  In view of the above, an object of one embodiment of the present invention is to make a process more efficient in a method for manufacturing a silicon carbide semiconductor device including a withstand voltage measurement step.

  A method for manufacturing a silicon carbide semiconductor device according to an aspect of the present invention includes a step of preparing an epitaxial wafer including a silicon carbide substrate having a main surface and a silicon carbide layer formed by epitaxial growth on the main surface; A step of forming an impurity region by ion implantation in the silicon layer, and after the excitation light having a wavelength of 400 nm or less is irradiated from the main surface side to the silicon carbide layer in which the impurity region is formed, the wavelength is longer than 400 nm, and After detecting the light emitted due to the defect existing in the silicon carbide layer, the photoluminescence measurement step for determining the position coordinates of the defect in the main surface, after the photoluminescence measurement step, A step of forming a plurality of elements by forming an insulating film and an electrode on the epitaxial wafer; Based on the position coordinates of the defective portion determined in the sense measurement step, a step of determining a defective element having a defective portion introduced into the silicon carbide layer among the plurality of elements, and a defective element among the plurality of elements And a withstand voltage measuring step for measuring the withstand voltage of the other elements excluded.

  According to the above, the process can be made more efficient in the method for manufacturing the silicon carbide semiconductor device provided with the withstand voltage measurement step.

3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. It is the schematic for demonstrating the process (S10) and (S20) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S30) and (S40) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S50) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S60) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S60) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S70)-(S90) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S90) and (S100) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S110) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S120) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is the schematic for demonstrating the process (S130) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 2 of this invention. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 3 of this invention. It is a photograph which shows the mode of the photoluminescence measurement in a silicon carbide layer.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described.

  (1) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention includes an epitaxial wafer 10 including a silicon carbide substrate 11 having a main surface 11a and a silicon carbide layer 5 formed by epitaxial growth on main surface 11a. A step of forming impurity regions (body region 13, source region 14, contact region 18) by ion implantation in silicon carbide layer 5, and silicon carbide layer 5 in which the impurity regions are formed. After the surface 10a side is irradiated with the excitation light P1 having a wavelength of 400 nm or less, the light P2 emitted from the defect portion 40 having a wavelength longer than 400 nm and existing inside the silicon carbide layer 5 is detected. By the photoluminescence measurement step for determining the position coordinates of the defect portion 40 in the main surface 10a, and the photoluminescence measurement step By forming an insulating film (interlayer insulating film 21) and electrodes (source electrode 16, source pad electrode 19, drain electrode 20, back surface pad electrode 23, gate electrode 27) on epitaxial wafer 10, a plurality of elements (MOSFET 80) are formed. , 81) and a defect in which the defective portion 40 is introduced into the silicon carbide layer 5 among the plurality of MOSFETs 80, 81 based on the position coordinates of the defective portion 40 determined in the photoluminescence measurement step. A step of determining an element (MOSFET 81) and a withstand voltage measuring step of measuring the withstand voltage of another MOSFET 80 excluding the MOSFET 81 among the plurality of MOSFETs 80 and 81 are provided.

  The present inventors diligently studied to shorten the time for measuring the withstand voltage and improve the efficiency of the entire process in the method for manufacturing the silicon carbide semiconductor device provided with the withstand voltage measuring step. As a result, the present inventors have obtained the following knowledge.

  In the manufacturing process of a silicon carbide semiconductor device, first, a silicon carbide layer is formed by epitaxial growth on a silicon carbide substrate, and then an impurity region is formed in the silicon carbide layer by ion implantation. According to the study by the inventors, impurity ions are implanted into the silicon carbide layer and many crystal defects are introduced during the ion implantation. The crystal defect becomes one of the causes of the breakdown voltage failure of the element. Therefore, there is a high possibility that an element including the crystal defect is determined as a defective product in the breakdown voltage measurement. Therefore, the present inventor has conceived that the position coordinates of the crystal defects introduced by ion implantation are determined in advance before the breakdown voltage measurement, and that defective elements including the crystal defects are excluded from the breakdown voltage measurement targets. As a result, the number of elements to be subjected to withstand voltage measurement can be reduced, so that the time required for withstand voltage measurement can be shortened.

  Further, the present inventor has come up with the use of photoluminescence measurement as a method for detecting crystal defects caused by ion implantation as described above. According to the inventor's study, when the silicon carbide layer after ion implantation is irradiated with excitation light having a wavelength of 400 nm or less, light having a wavelength longer than 400 nm is emitted from the silicon carbide layer due to the crystal defects. Is done. Therefore, the position coordinates of the crystal defect can be determined by detecting the light, and the element formed in the region including the crystal defect can be handled as a defective element.

  In the method for manufacturing the silicon carbide semiconductor device, the position coordinates of the defect portion 40 existing in the silicon carbide layer 5 are determined in advance by performing the photoluminescence measurement on the silicon carbide layer 5 after the ion implantation. be able to. Then, after the MOSFETs 80 and 81 are formed, the MOSFET 81 including the defective portion 40 is determined as a defective element based on the position coordinates, and is excluded from the object of the withstand voltage measurement. As described above, in the method for manufacturing the silicon carbide semiconductor device, the measurement time can be shortened by reducing the parameter of the withstand voltage measurement, and the defect portion 40 can be nondestructively performed without performing multi-steps as in the prior art. Can be detected. Therefore, according to the method for manufacturing the silicon carbide semiconductor device, the entire process can be made more efficient.

  (2) The method for manufacturing a silicon carbide semiconductor device according to (1) further includes a step of forming a gate oxide film 15 on the silicon carbide layer 5 in which the impurity regions are formed. The photoluminescence measurement step is performed after gate oxide film 15 is formed on silicon carbide layer 5.

  According to the study of the present inventors, the defect 40 may be introduced into the silicon carbide layer 5 not only at the time of ion implantation but also at the time of forming the gate oxide film 15. Therefore, by performing photoluminescence measurement after formation of the gate oxide film 15, in addition to the defect portion 40 introduced into the silicon carbide layer 5 during ion implantation, the defect portion 40 introduced during formation of the gate oxide film 15 is also combined. Can be detected.

  (3) The method for manufacturing a silicon carbide semiconductor device according to (1) further includes a step of forming a gate oxide film 15 on the silicon carbide layer 5 in which the impurity regions are formed. The photoluminescence measurement step is performed after the impurity region is formed in the silicon carbide layer 5 and before the gate oxide film 15 is formed on the silicon carbide layer 5.

  Thereby, light P2 emitted from silicon carbide layer 5 due to defect 40 can be detected more reliably than in the case where photoluminescence measurement is performed after formation of gate oxide film 15. As a result, the position coordinates of defect portion 40 existing inside silicon carbide layer 5 can be determined more reliably.

  (4) In the method for manufacturing the silicon carbide semiconductor device, in the photoluminescence measurement step, light P2 having a wavelength of 500 nm or more and 1000 nm or less is detected.

  According to the study of the present inventor, when the silicon carbide layer 5 after ion implantation is irradiated with excitation light P1 having a wavelength of 400 nm or less, the wavelength is caused by the defect 40 existing inside the silicon carbide layer 5. Light P2 in the range of 500 nm to 1000 nm is emitted from silicon carbide layer 5. Thus, the presence of the defect portion 40 in the silicon carbide layer 5 can be easily confirmed by detecting the light P2 in the wavelength region from the visible region to the near infrared region.

  (5) In the method for manufacturing the silicon carbide semiconductor device, the defect portion 40 has a maximum width W of 1 μm or more when the shape is observed by detecting the light P2 from the main surface 10a side in the photoluminescence measurement step. Have.

  When large defect portion 40 is introduced into silicon carbide layer 5 as described above, there is a high possibility that a breakdown voltage failure of the element will occur. In the method for manufacturing the silicon carbide semiconductor device, a defective element (MOSFET 81) including a large defect portion 40 is determined in advance, and is excluded from the object of withstand voltage measurement, whereby the measurement time can be shortened.

  (6) In the method for manufacturing the silicon carbide semiconductor device, after the breakdown voltage measurement step, a dividing step of dividing the plurality of MOSFETs 80 and 81 into the respective MOSFETs 80 and 81, and a plurality of divided MOSFETs 80 after the dividing step. , 81 is further provided with a step of selecting non-defective products and defective products including defective elements (MOSFET 81).

  Thereby, the non-defective product and the defective product can be reliably selected in the plurality of MOSFETs 80 and 81. In the subsequent mounting process, only non-defective elements can be reliably incorporated into the module.

  (7) In the method for manufacturing a silicon carbide semiconductor device, silicon carbide substrate 11 has a diameter of 150 mm or more.

  Thereby, more MOSFETs 80 and 81 can be formed on one silicon carbide substrate 11. Even when a large number of MOSFETs 80 and 81 are formed in this way, it is possible to suppress an increase in measurement time by excluding the defective element (MOSFET 81) including the defective portion 40 from the object of withstand voltage measurement as described above. Can do.

  (8) In the method for manufacturing the silicon carbide semiconductor device, MOSFETs 80 and 81 have a rectangular shape with side lengths L1 and L2 of 10 mm or less.

  Thereby, more MOSFETs 80 and 81 can be formed on one silicon carbide substrate 11. Even when a large number of MOSFETs 80 and 81 are formed in this way, it is possible to suppress an increase in measurement time by excluding the defective element (MOSFET 81) including the defective portion 40 from the object of withstand voltage measurement as described above. Can do.

  (9) In the method for manufacturing the silicon carbide semiconductor device, silicon carbide layer 5 is made of 4H-type or 6H-type silicon carbide.

  As described above, the light P2 emitted from the silicon carbide layer 5 due to the defective portion 40 is detected regardless of whether the 4H-type or 6H-type polytype silicon carbide layer 5 is irradiated with the excitation light P1. can do.

[Details of the embodiment of the present invention]
Next, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
First, the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 which is one Embodiment of this invention is demonstrated. Referring to FIG. 1, first, a silicon carbide substrate preparation step is performed as a step (S10). In this step (S10), for example, a silicon carbide ingot (not shown) whose polytype is 4H type or 6H type is sliced to a predetermined thickness. Thereby, silicon carbide substrate 11 having main surface 11a as shown in FIG. 2 is obtained. Silicon carbide substrate 11 has a diameter of, for example, 150 mm or more (6 inches or more).

Next, an epitaxial growth film forming step is performed as a step (S20). In this step (S20), referring to FIG. 2, silicon carbide layer 5 is formed on main surface 11a of silicon carbide substrate 11 by epitaxial growth using, for example, a CVD (Chemical Vapor Deposition) method. At this time, silane gas (SiH ₄ ) and propane gas (C ₃ H ₈ ) are used as source gases, hydrogen gas (H ₂ ) is used as a carrier gas, and nitrogen gas (N ₂ ) or ammonia gas (NH _3). ) Is used as a doping gas. Then, the silicon carbide layer 5 doped with nitrogen (N) atoms is formed by thermally decomposing the source gas and the doping gas and precipitating them on the main surface 11a. The polytype of silicon carbide constituting silicon carbide layer 5 is, for example, 4H type or 6H type. Thus, epitaxial wafer 10 having silicon carbide substrate 11 and silicon carbide layer 5 and including main surface 10a and main surface 10b opposite to main surface 10a is obtained. In addition, defect portion 40 inherited from silicon carbide substrate 11 exists in silicon carbide layer 5 as shown in FIG.

  Next, an ion implantation step is performed as a step (S30). In this step (S30), referring to FIG. 3, first, for example, aluminum (Al) ions are implanted into silicon carbide layer 5 from the main surface 10a side, whereby body region 13 is formed in silicon carbide layer 5. Is formed. Next, for example, phosphorus (P) ions are implanted into the body region 13 to form the source region 14 in the body region 13. Next, for example, aluminum (Al) ions are implanted into the body region 13 to form the contact region 18 adjacent to the source region 14 in the body region 13. A region where none of body region 13, source region 14, and contact region 18 is formed in silicon carbide layer 5 is drift region 12. Further, by the ion implantation, a defect portion 40 which is a crystal defect is further introduced in the region where the impurity region (body region 13, source region 14 and contact region 18) of silicon carbide layer 5 is formed.

  Next, an activation annealing step is performed as a step (S40). In this step (S40), referring to FIG. 3, epitaxial wafer 10 is annealed at a predetermined temperature. As a result, the impurity implanted into silicon carbide layer 5 is activated, and desired carriers are generated in the impurity region. Moreover, the defect part 40 introduced into the silicon carbide layer 5 during the ion implantation is partially repaired by the annealing treatment.

Next, a gate oxide film forming step is performed as a step (S50). In this step (S50), referring to FIG. 4, epitaxial wafer 10 is heated at a predetermined temperature in an atmosphere containing, for example, oxygen (O ₂ ). Thereby, the region including main surface 10a of epitaxial wafer 10 is thermally oxidized. As a result, as shown in FIG. 4, a gate oxide film 15 made of silicon dioxide (SiO ₂ ) is formed so as to cover the entire main surface 10a. Further, defect portion 40 is further introduced in silicon carbide layer 5 by the thermal oxidation treatment.

  Next, as a step (S60), a photo luminescence (PL) measurement step is performed. In this step (S60), as described below, PL measurement is performed on silicon carbide layer 5 in which the impurity region is formed. Thereby, the position coordinate in the main surface 10a of the defect part 40 introduced into the inside of the silicon carbide layer 5 in the said process (S20)-(S50) can be determined.

  Referring to FIG. 5, in the PL measurement, first, excitation light P1 is irradiated onto epitaxial wafer 10 from the main surface 10a side. The excitation light P1 is light having a wavelength (λ) of 400 nm or less. For example, helium-cadmium (He—Cd) laser (λ = 325 nm) or mercury-xenon (Hg—Xe) UV (Ultra Violet) lamp (λ = 314 nm). ). When defect 40 (FIGS. 2 to 4) is present inside silicon carbide layer 5 in the region irradiated with excitation light P1, light P2 in a specific wavelength region as shown in FIG. 5 is released. The light P2 is emitted due to the defective portion 40, and has a wavelength exceeding 400 nm (for example, not less than 500 nm and not more than 1000 nm). The light P2 is detected by a detector (not shown) such as a photomultiplier tube. Then, the excitation light P1 is scanned over the entire surface of the epitaxial wafer 10, and the light P2 emitted at that time is detected. Thereby, the position coordinate of the defect part 40 in the main surface 10a can be determined. The position coordinates can be determined as coordinates on the XY plane with reference to the orientation flat OF of the epitaxial wafer 10, for example.

  Referring to FIG. 6, defect 40 is, for example, a basal plane dislocation (BPD), a threading screw dislocation (Threading Screw Dislocation), a threading edge dislocation (TED), or a triangular defect. obtain. Moreover, as shown in FIG. 6, when the shape of the defect part 40 is observed in the PL image obtained by detecting the light P2 (FIG. 5) from the main surface 10a side, the maximum width W of the defect part 40 is 1 μm or more. . In an element formed in a region including such a large defect portion 40, there is a high possibility that a breakdown voltage failure will occur. In particular, when the maximum width W of the defect portion 40 is 5 μm or more or 10 μm or more, the possibility that a breakdown voltage failure occurs in the element formed in the region including the defect portion 40 is further increased.

  Next, a gate electrode forming step is performed as a step (S70). In this step (S70), referring to FIG. 7, gate electrode 27 is formed to be in contact with gate oxide film 15 by, for example, LP (Low Pressure) -CVD. The gate electrode 27 is, for example, polysilicon into which a high concentration impurity is introduced.

Next, an interlayer insulating film forming step is performed as a step (S80). In this step (S80), referring to FIG. 7, interlayer insulating film 21 made of silicon dioxide (SiO ₂ ) is formed so as to surround gate electrode 27 together with gate oxide film 15 by, eg, CVD.

Next, an ohmic electrode forming step is performed as a step (S90). In this step (S90), referring to FIG. 7, first, gate oxide film 15 and interlayer insulating film 21 are removed by etching in a region where source electrode 16 is to be formed. Thereby, a region where the source region 14 and the contact region 18 are exposed is formed. Then, a metal film (not shown) made of Ni, for example, is formed in the region. On the other hand, a metal film (not shown) made of Ni is similarly formed on the main surface 10b of the epitaxial wafer 10. Thereafter, the epitaxial wafer 10 is annealed, whereby at least a part of the metal film is silicided. Thereby, as shown in FIG. 8, source electrode 16 is formed on main surface 10a of epitaxial wafer 10, and drain electrode 20 is formed on main surface 10b. Note that source electrode 16 and drain electrode 20 are preferably made of a material capable of forming ohmic contact with silicon carbide layer 5 and silicon carbide substrate 11, for example, nickel silicon (Ni _x Si _y ), titanium, for example. It is preferably composed of at least one material selected from the group consisting of silicon (Ti _x Si _y ), aluminum silicon (Al _x Si _y ), and titanium aluminum silicon (Ti _x Al _y Si _z ) (x, y , Z> 0).

  Next, a pad electrode forming step is performed as a step (S100). In this step (S100), referring to FIG. 8, source pad electrode 19 made of a conductor such as aluminum (Al) or gold (Au) is covered with source electrode 16 and interlayer insulating film 21, for example, by vapor deposition. Formed. Similarly to the source pad electrode 19, a back surface pad electrode 23 made of aluminum (Al), gold (Au), or the like is formed so as to cover the drain electrode 20. As described above, the steps (S10) to (S100) are sequentially performed, so that a plurality of MOSFETs 80 and 81 (elements) having the source pad electrode 19 and the gate pad electrode 22 are formed as shown in FIG. The MOSFETs 80 and 81 have, for example, a rectangular shape with side lengths L1 and L2 of 10 mm or less (preferably 5 mm or less, more preferably 2 mm or less). 7 and 8, the description of the defect portion 40 existing inside the silicon carbide layer 5 is omitted.

  Next, a defective element determination step is performed as a step (S110). In this step (S110), referring to FIG. 9, a defective element is determined from among the plurality of MOSFETs 80 and 81 based on the positional information of the defective portion 40 determined in the photoluminescence measurement step (S60). More specifically, as indicated by hatching in FIG. 9, MOSFET 81 in which defective portion 40 is formed inside silicon carbide layer 5 is determined as a defective element.

  Next, a withstand pressure measurement process (on-wafer measurement process) is performed as a process (S120). In this step (S120), withstand voltage measurement is performed on the other MOSFETs 80 excluding the MOSFET 81 determined as a defective element among the plurality of MOSFETs 80 and 81. That is, the MOSFET 81 which is a defective element is excluded from the object of the withstand voltage measurement in advance. Hereinafter, details of the pressure resistance measurement will be described with reference to FIG.

  First, a tray 2 filled with a fluorine-based inert liquid 30 having high insulating properties such as Fluorinert (registered trademark) is prepared. A stage 3 is disposed at the bottom of the tray 2. Next, the epitaxial wafer 10 on which the MOSFETs 80 and 81 are formed is placed on the stage 3. As a result, the epitaxial wafer 10 is immersed in the fluorine-based inert liquid 30 as shown in FIG. Further, as shown in FIG. 10, the back surface pad electrode 23 formed on the main surface 10 b of the epitaxial wafer 10 is in contact with the stage 3.

  Next, as shown in FIG. 10, the needle 4 </ b> A of the probe 4 contacts the source pad electrode 19, and the needle 4 </ b> B contacts the gate pad electrode 22. Next, a predetermined voltage is applied between the probe 4 and the stage 3, and the current value flowing at that time is measured. Then, the breakdown voltage of the MOSFET 80 is measured based on whether or not the measured current value exceeds a certain threshold value. This withstand voltage measurement is performed, for example, at room temperature. After the pressure resistance measurement is completed, the epitaxial wafer 10 is taken out from the fluorine-based inert liquid 30. Thereafter, the surface of the epitaxial wafer 10 is subjected to a cleaning and drying process.

  Next, a dividing step is performed as a step (S130). In this step (S130), referring to FIG. 11, after the pressure resistance measurement is completed, the epitaxial wafer 10 is diced. As a result, the plurality of MOSFETs 80 and 81 are divided into the respective MOSFETs 80 and 81.

  Next, a sorting step is performed as a step (S140). In this step (S140), the non-defective product and the defective product are selected in the divided MOSFETs 80 and 81. More specifically, the MOSFET 81 determined as a defective element in the step (S110) and the MOSFET 80 in which a breakdown voltage failure is detected in the step (S120) are determined as defective products, and the other MOSFETs 80 are determined as non-defective products. Then, the MOSFET 80 determined to be non-defective is incorporated into the semiconductor module in a subsequent mounting process. By performing steps (S10) to (S140) as described above, the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to this embodiment, the silicon carbide layer 5 after ion implantation is irradiated with the excitation light P <b> 1, and the defect portion 40 existing inside the silicon carbide layer 5 is irradiated. Photoluminescence measurements are performed by detecting the light P2 emitted due to it. Thereby, the presence of defect 40 in silicon carbide layer 5 can be easily confirmed. The photograph in FIG. 14 is a PL image obtained by irradiating the silicon carbide layer 5 after ion implantation with excitation light P1 and detecting the light P2 (λ = 950 nm) emitted at that time. As shown in the PL image, the region 50 where the defect 40 is present can be observed separately from other regions. Then, the MOSFET 81 formed in the region including the defective portion 40 can be determined as a defective element, and the defective element can be excluded from the object of the withstand voltage measurement. Thereby, the measurement time can be shortened by reducing the measurement parameter in the pressure resistance measurement step (S120). Further, by adopting the PL measurement, it is possible to detect the defective portion 40 in a non-destructive manner without requiring many steps. Therefore, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, the entire process can be made more efficient by reducing the time for measuring the breakdown voltage.

  In the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, the photoluminescence measurement is performed after the gate oxide film 15 is formed on the silicon carbide layer 5. Therefore, in addition to the defect portion 40 introduced into the silicon carbide layer 5 at the time of ion implantation, the defect portion 40 introduced at the time of forming the gate oxide film 15 can also be detected.

(Embodiment 2)
Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 2, which is another embodiment of the present invention, will be described. The method for manufacturing the silicon carbide semiconductor device according to the second embodiment is basically performed by the same process as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, and has the same effect. However, the method for manufacturing the silicon carbide semiconductor device according to the second embodiment differs from the method for manufacturing the silicon carbide semiconductor device according to the first embodiment at the timing when the photoluminescence measurement step is performed.

  Referring to FIG. 12, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, first, steps (S150) to (S180) are performed in the same manner as steps (S10) to (S40) of the first embodiment. Is done. Thereby, epitaxial wafer 10 in which body region 13, source region 14 and contact region 18 are formed in silicon carbide layer 5 is obtained (FIG. 3).

  Next, a photoluminescence measurement step is performed as a step (S190). In this step (S190), as in the step (S60) of the first embodiment, the position coordinates of the defect portion 40 introduced into the silicon carbide layer 5 at the time of ion implantation are determined (FIG. 5).

  Next, a gate oxide film forming step is performed as a step (S200). In this step (S200), gate oxide film 15 is formed on silicon carbide layer 5 as in step (S50) of the first embodiment (FIG. 4). As described above, in this embodiment, the gate oxide film 15 is formed on the silicon carbide layer 5 after the impurity regions such as the body region 13, the source region 14 and the contact region 18 are formed in the silicon carbide layer 5. Before the photoluminescence measurement step (S190) is performed. Thereafter, steps (S210) to (S280) are performed in the same manner as steps (S70) to (S140) of the first embodiment, and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, after the impurity region is formed in silicon carbide layer 5, the photo process is performed before gate oxide film 15 is formed on silicon carbide layer 5. A luminescence measurement step is performed. Thereby, silicon carbide layer 5 caused by defective portion 40 is compared with the case where the photoluminescence measurement is performed after formation of gate oxide film 15 as in the method of manufacturing the silicon carbide semiconductor device according to the first embodiment. It is possible to more reliably detect the light P2 emitted from the. As a result, the position coordinates of defect portion 40 existing inside silicon carbide layer 5 can be determined more reliably.

(Embodiment 3)
Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 3 which is still another embodiment of the present invention will be described. The method for manufacturing the silicon carbide semiconductor device according to the third embodiment is basically performed by the same process as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, and has the same effect. However, the method for manufacturing the silicon carbide semiconductor device according to the third embodiment differs from the method for manufacturing the silicon carbide semiconductor device according to the first embodiment in that the breakdown voltage measurement is performed by chip measurement rather than on-wafer measurement. .

  Referring to FIG. 13, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, first, steps (S290) to (S390) are performed in the same manner as steps (S10) to (S110) of the first embodiment. Is done. Thereby, a plurality of MOSFETs 80 and 81 are formed, and MOSFET 81 in which defective portion 40 is introduced into silicon carbide layer 5 is determined as a defective element (FIG. 9).

  Next, a dividing step is performed as a step (S400). In this step (S400), like the step (S130) of the first embodiment, the epitaxial wafer 10 is diced to divide the plurality of MOSFETs 80 and 81 into the respective MOSFETs 80 and 81 (FIG. 11). .

  Next, a withstand voltage measurement step (chip measurement step) is performed as a step (S410). In this step (S410), withstand voltage measurement is performed on the element (chip) divided in the step (S400). At this time, as in the first embodiment, the withstand voltage measurement is performed only for the other MOSFETs 80 excluding the MOSFET 81 determined as a defective element in the step (S390).

  Next, a sorting step is performed as a step (S420). In this step (S420), as in the step (S140) of the first embodiment, the MOSFET 81 determined as a defective element in the step (S390) and the MOSFET 80 in which the breakdown voltage is detected in the step (S410) are defective. The other MOSFET 80 is determined as a non-defective product. By performing the above steps (S290) to (S420), the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed. Thus, the pressure resistance measurement by on-wafer measurement as in the first embodiment is not limited, and the pressure resistance measurement by chip measurement can also be adopted as in the present embodiment.

  It should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is shown not by the embodiments described above but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.

  The method for manufacturing a silicon carbide semiconductor device according to one aspect of the present invention can be particularly advantageously applied to a method for manufacturing a silicon carbide semiconductor device that requires process efficiency.

2 tray 3 stage 4 probe 4A, 4B needle 5 silicon carbide layer 10 epitaxial wafer 10a, 10b main surface 11 silicon carbide substrate 11a main surface 12 drift region 13 body region 14 source region 15 gate oxide film 16 source electrode 18 contact region 19 source Pad electrode 20 Drain electrode 21 Interlayer insulating film 22 Gate pad electrode 23 Back pad electrode 27 Gate electrode 30 Fluorine-based inert liquid 40 Defect 50 Area 80, 81 MOSFET
L1, L2 length OF orientation flat P1 excitation light P2 light W maximum width

Claims (9)

Preparing an epitaxial wafer including a silicon carbide substrate having a main surface and a silicon carbide layer formed by epitaxial growth on the main surface;
Forming an impurity region by ion implantation in the silicon carbide layer;
After the silicon carbide layer in which the impurity region is formed is irradiated with excitation light having a wavelength of 400 nm or less from the principal surface side, the wavelength is longer than 400 nm and the defect portion existing in the silicon carbide layer is present. A photoluminescence measurement step for determining a position coordinate of the defect in the main surface by detecting light emitted due to the light;
A step of forming a plurality of elements by forming an insulating film and an electrode on the epitaxial wafer after the photoluminescence measurement step;
Determining a defective element in which the defect portion is introduced into the silicon carbide layer among the plurality of elements based on the position coordinates of the defect portion determined in the photoluminescence measurement step;
A method for manufacturing a silicon carbide semiconductor device, comprising: a withstand voltage measurement step of measuring a withstand voltage of the other elements excluding the defective element among the plurality of elements. A step of forming a gate oxide film on the silicon carbide layer in which the impurity region is formed;
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the photoluminescence measurement step is performed after the gate oxide film is formed on the silicon carbide layer. A step of forming a gate oxide film on the silicon carbide layer in which the impurity region is formed;
2. The silicon carbide semiconductor according to claim 1, wherein the photoluminescence measurement step is performed after the impurity region is formed in the silicon carbide layer and before the gate oxide film is formed on the silicon carbide layer. 3. Device manufacturing method.   4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the photoluminescence measurement step, the light having a wavelength of 500 nm or more and 1000 nm or less is detected. 5.   The defect portion according to any one of claims 1 to 4, wherein when the shape is observed by detecting the light from the main surface side in the photoluminescence measurement step, the defect portion has a maximum width of 1 μm or more. A method for manufacturing a silicon carbide semiconductor device according to claim 1. After the breakdown voltage measuring step, a dividing step of dividing the plurality of elements into each of the elements,
The carbonization according to any one of claims 1 to 5, further comprising a step of selecting a non-defective product and a defective product including the defective device among the plurality of divided devices after the dividing step. A method for manufacturing a silicon semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the silicon carbide substrate has a diameter of 150 mm or more.   8. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the element has a quadrangular shape with a side length of 10 mm or less.   The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the silicon carbide layer is made of 4H-type or 6H-type silicon carbide.