WO2014185192A1 - Method for manufacturing silicon carbide semiconductor device and semiconductor module, silicon carbide semiconductor device, and semiconductor module - Google Patents

Method for manufacturing silicon carbide semiconductor device and semiconductor module, silicon carbide semiconductor device, and semiconductor module Download PDF

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Publication number
WO2014185192A1
WO2014185192A1 PCT/JP2014/060156 JP2014060156W WO2014185192A1 WO 2014185192 A1 WO2014185192 A1 WO 2014185192A1 JP 2014060156 W JP2014060156 W JP 2014060156W WO 2014185192 A1 WO2014185192 A1 WO 2014185192A1
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Prior art keywords
silicon carbide
semiconductor device
carbide semiconductor
substrate
region
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PCT/JP2014/060156
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French (fr)
Japanese (ja)
Inventor
光彦 酒井
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住友電気工業株式会社
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Publication of WO2014185192A1 publication Critical patent/WO2014185192A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Definitions

  • the present invention relates to a silicon carbide semiconductor device and a method for manufacturing a semiconductor module, and a silicon carbide semiconductor device and a semiconductor module.
  • Patent Document 1 Japanese Patent Laid-Open No. 5-322961 discloses a method of measuring the pressure resistance by putting an inert liquid in a test tank opened on the side where a probe is arranged.
  • a semiconductor module is manufactured by mounting the separated individual chips on a module substrate.
  • withstand voltage measurement it is difficult to perform withstand voltage measurement on each separated chip, and thus withstand voltage measurement has been performed in a wafer state before separation.
  • the present invention has been made in view of the above problems, and one object thereof is to provide a method for manufacturing a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device capable of improving the manufacturing yield of a semiconductor module. It is to provide a method for manufacturing a semiconductor module to be implemented. Another object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing breakage of the semiconductor module and a semiconductor module including the silicon carbide semiconductor device.
  • a method for manufacturing a silicon carbide semiconductor device includes a step of preparing a substrate made of silicon carbide, a step of forming a plurality of element portions on the substrate, and forming a first groove portion between the plurality of element portions. And a step of measuring the breakdown voltage of the element portion and a step of separating the plurality of element portions inside the first groove after the step of measuring the breakdown voltage of the element portion.
  • a method of manufacturing a semiconductor module according to the present invention includes a step of manufacturing a silicon carbide semiconductor device by the method of manufacturing a silicon carbide semiconductor device according to the present invention, a step of preparing a module substrate, and silicon carbide on the module substrate. A step of mounting a semiconductor device.
  • a silicon carbide semiconductor device includes a substrate made of silicon carbide and an element portion formed on the substrate.
  • a step portion is formed on at least one end face of the substrate and the element portion.
  • a semiconductor module according to the present invention includes the silicon carbide semiconductor device according to the present invention.
  • the manufacturing yield of the semiconductor module can be improved. Moreover, according to the silicon carbide semiconductor device and semiconductor module according to this invention, damage to a semiconductor module can be suppressed.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a semiconductor module according to a first embodiment.
  • 1 is a schematic cross sectional view showing a structure of a silicon carbide semiconductor device according to a first embodiment.
  • 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 3 is a flowchart schematically showing a method for manufacturing the semiconductor module according to the first embodiment. It is the schematic for demonstrating the process (S10) and process (S20) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. It is the schematic for demonstrating the process (S30) and process (S40) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. 7 is a schematic diagram for illustrating a step (S50) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is the schematic for demonstrating the process (S60) and process (S70) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1.
  • FIG. 7 is a schematic diagram for illustrating a step (S80) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is a schematic sectional drawing which shows the structure of a pressure
  • FIG. 6 is a schematic diagram for illustrating a step (S100) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a schematic cross sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment.
  • FIG. 7 is a schematic cross sectional view showing a configuration of a silicon carbide semiconductor device according to a third embodiment.
  • 12 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to a third embodiment.
  • FIG. 11 is a schematic diagram for illustrating a step (S240) in the method for manufacturing a silicon carbide semiconductor device according to the third embodiment.
  • a method for manufacturing a silicon carbide semiconductor device includes a step of preparing a substrate made of silicon carbide, a step of forming a plurality of element portions on the substrate, and a first portion between the plurality of element portions. After the step of forming the groove portion, the step of measuring the breakdown voltage of the element portion, and the step of measuring the breakdown voltage of the element portion, a step of separating the plurality of element portions inside the first groove portion is provided.
  • the present inventor has found that in a conventional method for manufacturing a silicon carbide semiconductor device, a defect is found in the inspection of the semiconductor module even if the defect is not confirmed in the breakdown voltage measurement in the wafer state, and as a result, the manufacturing yield of the semiconductor module decreases.
  • As a result when separating into individual chips after measuring the pressure resistance in the wafer state, defective chips are generated due to defects in dicing processing, etc., and the defective yields of the semiconductor modules are mounted by mounting the defective chips on the module substrate.
  • the present invention has been conceived.
  • a plurality of element portions are formed on a substrate, a first groove portion is formed between the plurality of element portions, and the inside of the first groove portion.
  • the element part is separated.
  • the breakdown voltage of the element portion is measured after the formation of the first groove portion and before the element portion is separated. Thereby, it can be separated into individual element parts after confirming whether or not the element part is defective due to the formation of the first groove part.
  • the manufacturing yield of the semiconductor module can be improved.
  • the manufacturing yield of the semiconductor module can be improved.
  • an epitaxial growth layer may be formed on the substrate in the step of forming the element portion.
  • the first groove portion reaching from the epitaxial growth layer to the substrate may be formed.
  • the first groove portion is formed so as to reach the substrate from the epitaxial growth layer, only the substrate in the first groove portion is subjected to a cutting process or the like in the step of separating the element portion, so that the element portion may be damaged. Can be lowered. As a result, it is possible to reduce the possibility that a defect is found in the inspection of the semiconductor module and the manufacturing yield is lowered.
  • an epitaxial growth layer having a conductivity type of the first conductivity type is formed on the substrate, and the first conductivity is formed in the epitaxial growth layer.
  • An impurity region of a second conductivity type that is a conductivity type different from the type may be formed.
  • the first groove portion reaching a position deeper than the bottom portion of the impurity region may be formed.
  • the first groove portion When the first groove portion is formed so as to reach a position deeper than the bottom portion of the impurity region, most of the portion operating as an element can be separated. For this reason, in the step of separating the element portion, only a portion that is not directly related to the operation of the element is processed, and the possibility that the element portion is damaged can be reduced. As a result, it is possible to further reduce the possibility that a defect is found in the inspection of the semiconductor module and the manufacturing yield is lowered.
  • a second groove portion having a width smaller than that of the first groove portion may be formed inside the first groove portion.
  • the method for manufacturing the silicon carbide semiconductor device includes a step of forming a protective film on the wall surface of the first groove portion after the step of measuring the breakdown voltage of the element portion and before the step of separating the element portion. Furthermore, you may provide. Thereby, the damage which a silicon carbide semiconductor device receives in the process of isolate
  • the method for manufacturing a silicon carbide semiconductor device may further include a step of selecting a non-defective product and a defective product among the plurality of element portions after the step of separating the element portions. Thereby, it is possible to more reliably prevent the silicon carbide semiconductor device including the defective element portion from being mounted on the module substrate.
  • a method for manufacturing a semiconductor module according to an embodiment of the present invention includes a step of manufacturing a silicon carbide semiconductor device by a method of manufacturing a silicon carbide semiconductor device according to the above embodiment, a step of preparing a module substrate, And a step of mounting the silicon carbide semiconductor device.
  • the silicon carbide semiconductor device is manufactured by the method for manufacturing the silicon carbide semiconductor device according to the above embodiment, the silicon carbide semiconductor device including the defective element portion Can be prevented from being mounted on the module substrate. Therefore, according to the method for manufacturing a semiconductor module according to the embodiment of the present invention, the manufacturing yield of the semiconductor module can be improved.
  • a silicon carbide semiconductor device includes a substrate made of silicon carbide and an element portion formed on the substrate.
  • a step portion is formed on at least one end face of the substrate and the element portion.
  • a step portion is formed on the end face. Therefore, the distance between the element portions of the silicon carbide semiconductor device (chip) when mounted on the module substrate can be made larger than that of the silicon carbide semiconductor device in which the step portion is not formed. Thereby, generation
  • the first region that is the region on the element portion side when viewed from the step portion has a smaller width than the second region that is the region on the substrate side when viewed from the step portion. May be.
  • the end face in the first region may be inclined so that the first region spreads toward the second region side. Thereby, it can be set as the structure which can ease electric field concentration more.
  • the silicon carbide semiconductor device according to the above embodiment may further include a protective film formed on the end face. Thereby, a silicon carbide semiconductor device in which damage is suppressed can be obtained.
  • the semiconductor module according to the embodiment of the present invention includes the silicon carbide semiconductor device according to the present embodiment. Therefore, according to the semiconductor module according to the embodiment of the present invention, it is possible to suppress damage to the module due to discharge between the mounted individual silicon carbide semiconductor devices (chips).
  • the semiconductor module 1 mainly includes a module substrate 2, a terminal 3, and a plurality of MOSFETs 10A.
  • the module substrate 2 includes an insulating substrate (not shown), a heat sink (not shown) as a heat sink made of metal, and the like.
  • the plurality of MOSFETs 10 ⁇ / b> A are arranged on the surface 2 ⁇ / b> A of the module substrate 2 and are connected to each other by the wiring 4.
  • the terminal 3 is connected to the MOSFET 10 ⁇ / b> A by the wiring 4.
  • MOSFET 10A is a silicon carbide semiconductor device according to the present embodiment.
  • the semiconductor module 1 may be sealed with a resin (not shown).
  • MOSFET 10A includes a silicon carbide substrate 20, an epitaxial growth layer 30, an oxide film 40, a source electrode 50 and a gate electrode 60 (element portion) formed on one main surface 20A of silicon carbide substrate 20. ) And the drain electrode 70 are mainly provided.
  • a drift region 31 In the epitaxial growth layer 30, a drift region 31, a body region 32, a source region 33, and a contact region 34 are formed.
  • the thickness of the MOSFET 10A is 50 ⁇ m or more and 600 ⁇ m or less, preferably 100 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the epitaxial growth layer 30 is 2 ⁇ m or more and 50 ⁇ m or less, preferably 5 ⁇ m or more and 35 ⁇ m or less.
  • the drift region 31 is formed on one main surface 20A of the silicon carbide substrate 20.
  • Drift region 31 has an n-type conductivity by including an n-type impurity such as N (nitrogen).
  • the body region 32 is formed in the epitaxial growth layer 30 so as to include the main surface 30A.
  • Body region 32 has a p-type conductivity by including a p-type impurity such as Al (aluminum) or B (boron).
  • the thickness of the body region 32 is not less than 0.1 ⁇ m and not more than 50 ⁇ m, preferably not less than 1 ⁇ m and not more than 3 ⁇ m.
  • the source region 33 is formed in the body region 32 so as to include the main surface 30A.
  • Source region 33 includes an n-type impurity such as P (phosphorus), for example, so that conductivity type is n-type, similar to drift region 31.
  • the source region 33 has a higher n-type impurity concentration than the drift region 31.
  • the contact region 34 includes the main surface 30 ⁇ / b> A and is formed in the body region 32 so as to be adjacent to the source region 33. Similar to body region 32, contact region 34 has a p-type conductivity by containing a p-type impurity. Contact region 34 has a higher p-type impurity concentration than body region 32.
  • Oxide film 40 is formed to cover part of main surface 30A.
  • the oxide film 40 is made of, for example, SiO 2 (silicon dioxide).
  • the gate electrode 60 is made of a conductive material such as polysilicon doped with impurities or aluminum, and is formed on the oxide film 40 in contact therewith.
  • the gate electrode 60 is formed so as to extend from one source region 33 to the other source region 33 under the gate electrode 60.
  • Source electrode 50 is formed on main surface 30 ⁇ / b> A so as to be in contact with source region 33 and contact region 34.
  • the source electrode 50 is made of a material capable of making ohmic contact with the source region 33, for example, Ni x Si y (nickel silicide), Ti x Si y (titanium silicide), Al x Si y (aluminum silicide), and Ti x Al. It is made of y Si z (titanium aluminum silicide) or the like and is electrically connected to the source region 33.
  • drain electrode 70 is formed on the other main surface 20B of the silicon carbide substrate 20. Drain electrode 70 is made of, for example, the same material as source electrode 50 and is electrically connected to silicon carbide substrate 20.
  • Step portion 13 is formed on end surface 11 of MOSFET 10A (end surface 11 of silicon carbide substrate 20).
  • the end surface 11 is a surface at the side end portion of the MOSFET 10A, and is a surface that intersects (orthogonally) the main surfaces 20A and 30A as shown in FIG.
  • the region on the element portion (epitaxial growth layer 30, oxide film 40, source electrode 50, and gate electrode 60) side when viewed from step portion 13 is first region A1, and silicon carbide is viewed from step portion 13.
  • a region on the substrate 20 side is a second region A2. As shown in FIG.
  • the width of the first region A1 (the width in the direction along the surface 20B of the silicon carbide substrate 20) is smaller than the width of the second region A2, and the width difference on the one end face 11 side.
  • W1 is 1 ⁇ m or more and 100 ⁇ m or less, preferably 5 ⁇ m or more and 50 ⁇ m or less, for example 70 ⁇ m.
  • stepped portion 13 is formed to be located on the side of silicon carbide substrate 20 as viewed from bottom surface 32 ⁇ / b> A of body region 32, and contact surface 20 ⁇ / b> A between silicon carbide substrate 20 and epitaxial growth layer 30. Is formed so as to be located on the silicon carbide substrate 20 side when viewed from the side. Further, the formation position of the stepped portion 13 is not limited to this. For example, the stepped portion 13 is formed so as to be located on the silicon carbide substrate 20 side when viewed from the bottom surface 32A and on the epitaxial growth layer 30 side when viewed from the contact surface 20A. Also good. In this case, the step portion 13 is formed on the end surface 11 of the epitaxial growth layer 30.
  • MOSFET 10A in a state where the voltage applied to gate electrode 60 is less than the threshold voltage, that is, in the off state, even if a voltage is applied between source electrode 50 and drain electrode 70, body region 32 drifts.
  • the pn junction formed with the region 31 is reverse-biased and becomes non-conductive.
  • a voltage equal to or higher than the threshold voltage is applied to the gate electrode 60, an inversion layer is formed in the channel region of the body region 32 (the body region 32 below the gate electrode 60).
  • the source region 33 and the drift region 31 are electrically connected, and a current flows between the source electrode 50 and the drain electrode 70.
  • the MOSFET 10A operates.
  • MOSFET (10A) according to the present embodiment is manufactured by performing steps (S10) to (S110).
  • steps (S120) to (S140) are performed to manufacture semiconductor module 1 according to the present embodiment. .
  • a silicon carbide substrate preparation step is performed as a step (S10).
  • silicon carbide substrate 20 having a conductivity type of n type (first conductivity type) is prepared by slicing an ingot (not shown) made of, for example, 4H—SiC. Is done.
  • step (S20) an epitaxial growth layer forming step is performed.
  • epitaxial growth layer 30 having an n conductivity type is formed on main surface 20A of silicon carbide substrate 20.
  • an ion implantation step is performed.
  • this step (S30) referring to FIG. 6, first, for example, aluminum (Al) ions are implanted into a region including main surface 30A of epitaxial growth layer 30 to thereby form body region 32 (impurity in epitaxial growth layer 30). Region) is formed.
  • the conductivity type of the body region 32 is p-type (second conductivity type).
  • phosphorus (P) ions are implanted at a depth shallower than the Al ion implantation depth in a region including main surface 30 ⁇ / b> A, thereby forming source region 33.
  • Al ions are implanted into a region adjacent to source region 33 and including main surface 30 ⁇ / b> A, thereby forming contact region 34 having a depth equivalent to that of source region 33.
  • a region where none of the body region 32, the source region 33, and the contact region 34 is formed becomes a drift region 31.
  • an activation annealing step is performed as a step (S40).
  • this step (S40) referring to FIG. 6, by heating silicon carbide substrate 20 on which epitaxially grown layer 30 including drift region 31, body region 32, source region 33 and contact region 34 is formed, the above step is performed.
  • the impurities introduced in (S30) are activated. As a result, desired carriers are generated in the region where the impurity is introduced.
  • an oxide film forming step is performed as a step (S50).
  • this step (S50) referring to FIG. 7, for example, by heating silicon carbide substrate 20 on which epitaxially grown layer 30 is formed in an oxygen-containing atmosphere, SiO 2 so as to cover main surface 30A of epitaxially grown layer 30 is covered.
  • An oxide film 40 made of 2 (silicon dioxide) is formed.
  • gate electrode 60 made of polysilicon is formed so as to be in contact with oxide film 40 by, for example, LPCVD (Low Pressure Chemical Vapor Deposition).
  • LPCVD Low Pressure Chemical Vapor Deposition
  • an ohmic electrode forming step is performed.
  • oxide film 40 is removed in a region where source electrode 50 is to be formed, and a region where source region 33 and contact region 34 are exposed is formed.
  • a film made of, for example, Ni is formed in the region.
  • a film made of, for example, Ni is formed on main surface 20B of silicon carbide substrate 20.
  • an alloying heat treatment is performed, and at least a part of the Ni film is silicided, whereby the source electrode 50 and the drain electrode 70 are formed.
  • element portion 80 including epitaxial growth layer 30, oxide film 40, source electrode 50, and gate electrode 60 on main surface 20A of silicon carbide substrate 20 is performed. A plurality of are formed.
  • a first dicing step is performed.
  • this step (S80) referring to FIG. 9, by performing dicing processing on epitaxial growth layer 30 and silicon carbide substrate 20 from the main surface 30A side, first groove portion 90 is formed between a plurality of element portions 80. Is formed.
  • the width W2 of the first groove portion 90 is, for example, 300 ⁇ m or less.
  • the first groove 90 may be formed so as to reach from the epitaxial growth layer 30 to the silicon carbide substrate 20 as shown in FIG. More specifically, bottom wall surface 90 ⁇ / b> A reaches a position deeper than bottom surface 32 ⁇ / b> A (bottom portion) of body region 32, and silicon carbide substrate 20 as viewed from contact surface 20 ⁇ / b> A between silicon carbide substrate 20 and epitaxial growth layer 30.
  • the first groove portion 90 may be formed so as to be located on the side.
  • a pressure resistance measuring step is performed.
  • the withstand voltages of the plurality of element portions 80 formed in the above steps (S20) to (S70) are measured.
  • voltage resistant measuring apparatus used in this process (S90) is demonstrated.
  • the pressure resistance measuring device 100 includes an airtight container 110, a camera 112, a stage 120, a probe 130, a voltage source 134, a gate controller 135, an inlet 140, and an outlet 150.
  • the heater 160 and the sensor 170 are provided.
  • the stage 120 is provided in the hermetic container 110 and is for supporting the silicon carbide substrate 20.
  • Stage 120 may have a vacuum chuck 121 for fixing silicon carbide substrate 20.
  • the probe 130 is provided in the airtight container 110.
  • One of the functions of the probe 130 is to obtain an electrical connection with the source electrode 50 by contacting the source electrode 50 (see FIG. 9).
  • the probe 130 may have a base 131 and needles 132 and 133, for example. Each of the needles 132 and 133 is for obtaining an electrical connection with the source electrode 50 and the gate electrode 60 (see FIG. 9), and is attached to the base 131.
  • the stage 120 is configured to be movable in the airtight container 110 by being provided on the moving mechanism 122. Accordingly, the stage 120 and the probe 130 are configured to be relatively displaceable. In other words, the probe 130 is configured to be movable relative to the stage 120.
  • the moving mechanism 122 is preferably a so-called XYZ stage that enables three-dimensional displacement.
  • the introduction port 140 is provided in the hermetic container 110 and is for introducing gas into the hermetic container 110.
  • the discharge port 150 is provided in the hermetic container 110 and is for discharging gas from the hermetic container 110.
  • Each of the inlet 140 and the outlet 150 has gate valves 141 and 151.
  • the heater 160 is for heating the silicon carbide substrate 20.
  • the heater 160 is disposed in the hermetic container 110 and may be disposed in the stage 120.
  • a heater power supply 161 disposed outside the hermetic container 110 may be connected to the heater 160.
  • the sensor 170 is provided in the hermetic container 110 in order to detect the dew point temperature in the hermetic container 110.
  • the sensor 170 may be a dew point thermometer designed specifically for direct measurement of the dew point temperature, or has a thermometer and a hygrometer to calculate the dew point temperature from the temperature and humidity. May be.
  • the sensor 170 may be connected to a reading unit 171 provided outside the hermetic container 110.
  • the voltage source 134 is connected to the probe 130. Specifically, the voltage source 134 is connected to apply a voltage between the needle 132 of the probe 130 and the stage 120.
  • the voltage that can be generated by the voltage source 134 is preferably about 600 V or more, more preferably about 1 kV or more, and further preferably about 3 kV or more.
  • the gate control unit 135 is connected so as to apply a voltage between the needles 132 and 133 of the probe 130.
  • the gate control unit 135 only needs to be capable of generating a voltage that can control the gate voltage of the element unit 80 (see FIG. 9).
  • the hermetic container 110 has a window 111 that transmits light so that the position of the element unit 80 (see FIG. 9) can be observed from the outside of the hermetic container 110.
  • the window 111 is made of a material that transmits light to a sufficient extent for this purpose, for example, glass or transparent resin.
  • the window 111 is preferably provided with a light shielding portion (not shown) for performing light shielding so that light does not enter through the window 111 during pressure resistance measurement.
  • This light-shielding portion is, for example, a cover that can be attached and detached outside the window 111 or a shutter provided outside or inside the window 111.
  • Camera 112 is arranged so that silicon carbide substrate 20 can be observed through window 111, as indicated by a broken line in FIG.
  • silicon carbide substrate 20 is supported in hermetic container 110. Specifically, silicon carbide substrate 20 is carried into airtight container 110 and further placed on stage 120. Thereby, the potential of drain electrode 70 located on the back surface of silicon carbide substrate 20 is set to the potential of stage 120 (see FIG. 11). Silicon carbide substrate 20 is fixed to stage 120. This fixing can be performed by the vacuum chuck 121.
  • the movement of the moving mechanism 122 causes a relative displacement between the stage 120 and the probe 130, so that the needles 132 and 133 are brought into contact with the source electrode 50 and the gate electrode 60, respectively, as shown in FIG. .
  • a voltage is supplied to the probe 130 while the probe 130 is in contact with the source electrode 50.
  • a voltage is supplied between the needle 132 of the probe 130 and the stage 120.
  • a voltage for measuring the withstand voltage is applied between the drain electrode 70 and the source electrode 50. This voltage is about 600V or more, for example.
  • the gate voltage is adjusted by the gate controller 135 as necessary. Thereby, the breakdown voltage of the element unit 80 (see FIG. 9) is measured.
  • a second dicing step is performed as a step (S100).
  • element portions 80 are separated in first groove portion 90 by further dicing the silicon carbide substrate 20. More specifically, the element portions 80 are separated from each other by forming the second groove portion 91 inside the first groove portion 90.
  • the width W3 of the second groove 91 is smaller than the width W2 of the first groove 90, and may be 100 ⁇ m or less, for example, 70 ⁇ m.
  • "Second groove portion 91" may be formed so as to penetrate silicon carbide substrate 20 in the thickness direction as shown in FIG. 12, and part of silicon carbide substrate 20 (a portion including main surface 20B). May be formed so as to remain.
  • second groove portion 91 is formed so as to leave a part of silicon carbide substrate 20, element portions 80 are completely separated from each other by applying a predetermined stress to silicon carbide substrate 20 thereafter. be able to.
  • a sorting step is performed.
  • this step (S110) after being separated into the individual element portions 80 in the step (S100), those determined as good products and those determined as defective in the pressure resistance measurement in the step (S90) are selected. Is done.
  • this step (S110) is not an essential step in the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to reliably mount only the MOSFET including the element portion 80 determined to be non-defective by carrying out this step. it can. As a result, the module manufacturing yield can be improved.
  • steps (S10) to (S110) as described above, MOSFET 10A is manufactured, and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.
  • a method for manufacturing a semiconductor module according to the present embodiment will be described.
  • a step (S120) a device preparation step is performed.
  • MOSFET 10A is manufactured by the method for manufacturing the silicon carbide semiconductor device according to the present embodiment.
  • the module substrate 2 is prepared by performing the step (S130) along with the step (S120) (see FIG. 1).
  • a device mounting step is performed as a step (S140).
  • a step (S140) referring to FIG. 1, a plurality of MOSFETs 10A are arranged on surface 2A of module substrate 2.
  • the MOSFETs 10 ⁇ / b> A or the MOSFET 10 ⁇ / b> A and the terminal 3 are electrically connected by the wiring 4.
  • the MOSFET 10A is mounted on the module substrate 2.
  • a plurality of element portions 80 are formed on silicon carbide substrate 20, and first groove portion 90 is formed between the plurality of element portions 80.
  • the plurality of element parts 80 are separated inside the first groove part 90.
  • the breakdown voltage of the element unit 80 is measured after the formation of the first groove 90 and before the element unit 80 is separated.
  • the manufacturing yield of the semiconductor module can be improved.
  • the manufacturing yield of the semiconductor module can be improved.
  • the step portion 13 is formed on the end face 11. Therefore, the distance between chips when mounted on the module substrate 2 as shown in FIG. 1 can be made larger than that of a MOSFET in which the step portion 13 is not formed. Thereby, generation
  • Embodiment 2 which is another embodiment of the present invention will be described.
  • the silicon carbide semiconductor device according to the present embodiment basically has the same configuration as MOSFET 10A according to the above-described first embodiment, operates in the same manner, and has the same effects.
  • the silicon carbide semiconductor device according to the present embodiment is different from MOSFET 10A in the configuration of first region A1.
  • end surface 11A in first region A1 is inclined so that first region A1 extends toward second region A2. .
  • an angle ⁇ exceeding 90 ° is formed by the main surface 30A and the end surface 11A of the epitaxial growth layer 30.
  • Embodiment 3 which is still another embodiment of the present invention will be described.
  • the silicon carbide semiconductor device according to the present embodiment basically has the same configuration as MOSFET 10A according to the above-described first embodiment, operates in the same manner, and has the same effects.
  • the silicon carbide semiconductor device according to the present embodiment differs from MOSFET 10A in that a protective film is formed on the end surface.
  • MOSFET 10C as the silicon carbide semiconductor device according to the present embodiment further includes a passivation film 92 (protective film) formed on end surface 11A and stepped portion 13 of first region A1.
  • the passivation film 92 is made of, for example, silicon dioxide (SiO 2 ), and is formed so as to be connected to the oxide film 40. Thereby, compared with the case where the said passivation film 92 is not formed, the damage which MOSFET10C receives can be suppressed.
  • steps (S150) to (S230) are performed similarly to steps (S10) to (S90) of the first embodiment.
  • element portion 80 is formed on silicon carbide substrate 20 as shown in FIG. 9, and the pressure resistance measurement of element portion 80 is completed.
  • a passivation film forming step is performed.
  • passivation film 92 made of silicon dioxide (SiO 2 ) is formed on bottom wall surface 90A and side wall surface 90B of first groove 90 by, for example, P (Plasma) -CVD. It is formed so as to cover.
  • steps (S250) and (S260) are performed in the same manner as steps (S100) and (S110) of the first embodiment, and MOSFET 10C according to the present embodiment is manufactured.
  • the method for manufacturing a silicon carbide semiconductor device and a semiconductor module of the present invention can be applied particularly advantageously in a method for manufacturing a silicon carbide semiconductor device and a semiconductor module that are required to improve the manufacturing yield of the semiconductor module.
  • the silicon carbide semiconductor device and the semiconductor module of the present invention can be particularly advantageously applied to a silicon carbide semiconductor device and a semiconductor module that are required to suppress damage to the semiconductor module.

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Abstract

A method for manufacturing a silicon carbide semiconductor device is provided with: a step in which a silicon carbide substrate (20) is prepared; a step in which a plurality of element sections (80) are formed on the silicon carbide substrate (20); a step in which a first groove section (90) is formed between the plurality of element sections (80); a step in which the breakdown voltage of the element sections (80) is measured; and a step in which, after the step in which the breakdown voltage of the element sections (80) is measured, the plurality of element sections (80) are separated within the first groove section (90).

Description

炭化珪素半導体装置および半導体モジュールの製造方法、ならびに炭化珪素半導体装置および半導体モジュールSilicon carbide semiconductor device, semiconductor module manufacturing method, silicon carbide semiconductor device, and semiconductor module
　本発明は、炭化珪素半導体装置および半導体モジュールの製造方法、ならびに炭化珪素半導体装置および半導体モジュールに関する。 The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a semiconductor module, and a silicon carbide semiconductor device and a semiconductor module.
　ＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）などの炭化珪素半導体装置においては、耐圧は重要な特性のひとつである。そのため、炭化珪素半導体装置の製造方法では、炭化珪素からなる基板上に複数の素子を形成した後、当該素子に対して耐圧測定が実施される場合がある。たとえば特開平５－３２２９６１号公報（以下、特許文献１という）では、プローブが配置される側に開口した試験槽に、不活性液体を入れて耐圧を測定する方法が開示されている。 In a silicon carbide semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the breakdown voltage is one of important characteristics. Therefore, in the method for manufacturing a silicon carbide semiconductor device, after a plurality of elements are formed on a substrate made of silicon carbide, withstand voltage measurement may be performed on the elements. For example, Japanese Patent Laid-Open No. 5-322961 (hereinafter referred to as Patent Document 1) discloses a method of measuring the pressure resistance by putting an inert liquid in a test tank opened on the side where a probe is arranged.
特開平５－３２２９６１号公報JP-A-5-322961
　従来の炭化珪素半導体装置の製造方法では、炭化珪素基板上に複数の素子が形成された後に当該素子の耐圧が測定され、その後ダイシング加工により個々のチップに分離される。そして、分離された個々のチップをモジュール基板上に実装することにより半導体モジュールが製造される。このように、従来では分離された個々のチップに対して耐圧測定を実施することは困難であるため、分離前のウェハ状態において耐圧測定が実施されていた。 In a conventional method for manufacturing a silicon carbide semiconductor device, after a plurality of elements are formed on a silicon carbide substrate, the breakdown voltage of the elements is measured, and then separated into individual chips by dicing. Then, a semiconductor module is manufactured by mounting the separated individual chips on a module substrate. As described above, conventionally, it is difficult to perform withstand voltage measurement on each separated chip, and thus withstand voltage measurement has been performed in a wafer state before separation.
　この場合、ウェハ状態での耐圧測定では不良が確認されなくても個々のチップが実装された半導体モジュールの検査において不良が発見されることがあり、これにより半導体モジュールの製造歩留まりが低下するという問題がある。また、従来の半導体モジュールでは動作時に個々のチップ間に沿面放電が発生する場合があり、これによりモジュールが破損するという問題もある。 In this case, even when the breakdown voltage measurement in the wafer state is not confirmed, a defect may be found in the inspection of the semiconductor module on which the individual chip is mounted, thereby reducing the manufacturing yield of the semiconductor module. There is. Further, in a conventional semiconductor module, creeping discharge may occur between individual chips during operation, which causes a problem that the module is damaged.
　本発明は、上記課題に鑑みてなされたものであり、その一の目的は、半導体モジュールの製造歩留まりを向上させることが可能な炭化珪素半導体装置の製造方法および当該炭化珪素半導体装置の製造方法が実施される半導体モジュールの製造方法を提供することである。また、本発明の他の目的は、半導体モジュールの破損を抑制することが可能な炭化珪素半導体装置および当該炭化珪素半導体装置を備える半導体モジュールを提供することである。 The present invention has been made in view of the above problems, and one object thereof is to provide a method for manufacturing a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device capable of improving the manufacturing yield of a semiconductor module. It is to provide a method for manufacturing a semiconductor module to be implemented. Another object of the present invention is to provide a silicon carbide semiconductor device capable of suppressing breakage of the semiconductor module and a semiconductor module including the silicon carbide semiconductor device.
　本発明に従った炭化珪素半導体装置の製造方法は、炭化珪素からなる基板を準備する工程と、基板上に複数の素子部を形成する工程と、複数の素子部の間に第１溝部を形成する工程と、素子部の耐圧を測定する工程と、素子部の耐圧を測定する工程の後、第１溝部の内部において複数の素子部を分離する工程とを備えている。 A method for manufacturing a silicon carbide semiconductor device according to the present invention includes a step of preparing a substrate made of silicon carbide, a step of forming a plurality of element portions on the substrate, and forming a first groove portion between the plurality of element portions. And a step of measuring the breakdown voltage of the element portion and a step of separating the plurality of element portions inside the first groove after the step of measuring the breakdown voltage of the element portion.
　本発明に従った半導体モジュールの製造方法は、上記本発明に従った炭化珪素半導体装置の製造方法により炭化珪素半導体装置を製造する工程と、モジュール基板を準備する工程と、モジュール基板上に炭化珪素半導体装置を実装する工程とを備えている。 A method of manufacturing a semiconductor module according to the present invention includes a step of manufacturing a silicon carbide semiconductor device by the method of manufacturing a silicon carbide semiconductor device according to the present invention, a step of preparing a module substrate, and silicon carbide on the module substrate. A step of mounting a semiconductor device.
　本発明に従った炭化珪素半導体装置は、炭化珪素からなる基板と、基板上に形成された素子部とを備えている。基板および素子部の少なくとも一方の端面には、段差部が形成されている。本発明に従った半導体モジュールは、上記本発明に従った炭化珪素半導体装置を備えている。 A silicon carbide semiconductor device according to the present invention includes a substrate made of silicon carbide and an element portion formed on the substrate. A step portion is formed on at least one end face of the substrate and the element portion. A semiconductor module according to the present invention includes the silicon carbide semiconductor device according to the present invention.
　本発明に従った炭化珪素半導体装置および半導体モジュールの製造方法によれば、半導体モジュールの製造歩留まりを向上させることができる。また、本発明に従った炭化珪素半導体装置および半導体モジュールによれば、半導体モジュールの破損を抑制することができる。 According to the silicon carbide semiconductor device and the method for manufacturing a semiconductor module according to the present invention, the manufacturing yield of the semiconductor module can be improved. Moreover, according to the silicon carbide semiconductor device and semiconductor module according to this invention, damage to a semiconductor module can be suppressed.
実施の形態１に係る半導体モジュールの構造を示す概略断面図である。1 is a schematic cross-sectional view showing a structure of a semiconductor module according to a first embodiment. 実施の形態１に係る炭化珪素半導体装置の構造を示す概略断面図である。1 is a schematic cross sectional view showing a structure of a silicon carbide semiconductor device according to a first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を概略的に示すフローチャートである。3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る半導体モジュールの製造方法を概略的に示すフローチャートである。3 is a flowchart schematically showing a method for manufacturing the semiconductor module according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ１０）および工程（Ｓ２０）を説明するための概略図である。It is the schematic for demonstrating the process (S10) and process (S20) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ３０）および工程（Ｓ４０）を説明するための概略図である。It is the schematic for demonstrating the process (S30) and process (S40) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ５０）を説明するための概略図である。FIG. 7 is a schematic diagram for illustrating a step (S50) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ６０）および工程（Ｓ７０）を説明するための概略図である。It is the schematic for demonstrating the process (S60) and process (S70) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ８０）を説明するための概略図である。FIG. 7 is a schematic diagram for illustrating a step (S80) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 耐圧測定装置の構成を示す概略断面図である。It is a schematic sectional drawing which shows the structure of a pressure | voltage resistant measuring apparatus. 耐圧測定方法を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating a pressure | voltage resistant measuring method. 実施の形態１に係る炭化珪素半導体装置の製造方法における工程（Ｓ１００）を説明するための概略図である。FIG. 6 is a schematic diagram for illustrating a step (S100) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態２に係る炭化珪素半導体装置の構成を示す概略断面図である。FIG. 6 is a schematic cross sectional view showing a configuration of a silicon carbide semiconductor device according to a second embodiment. 実施の形態３に係る炭化珪素半導体装置の構成を示す概略断面図である。FIG. 7 is a schematic cross sectional view showing a configuration of a silicon carbide semiconductor device according to a third embodiment. 実施の形態３に係る炭化珪素半導体装置の製造方法を概略的に示すフローチャートである。12 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to a third embodiment. 実施の形態３に係る炭化珪素半導体装置の製造方法における工程（Ｓ２４０）を説明するための概略図である。FIG. 11 is a schematic diagram for illustrating a step (S240) in the method for manufacturing a silicon carbide semiconductor device according to the third embodiment.
　（本発明の実施の形態の説明）
　まず、本発明の実施の形態の内容を列記して説明する。本発明の実施の形態に係る炭化珪素半導体装置の製造方法は、炭化珪素からなる基板を準備する工程と、基板上に複数の素子部を形成する工程と、複数の素子部の間に第１溝部を形成する工程と、素子部の耐圧を測定する工程と、素子部の耐圧を測定する工程の後、第１溝部の内部において複数の素子部を分離する工程とを備えている。 (Description of Embodiment of the Present Invention)
First, the contents of the embodiment of the present invention will be listed and described. A method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention includes a step of preparing a substrate made of silicon carbide, a step of forming a plurality of element portions on the substrate, and a first portion between the plurality of element portions. After the step of forming the groove portion, the step of measuring the breakdown voltage of the element portion, and the step of measuring the breakdown voltage of the element portion, a step of separating the plurality of element portions inside the first groove portion is provided.
　本発明者は、従来の炭化珪素半導体装置の製造方法において、ウェハ状態での耐圧測定では不良が確認されなかった場合でも半導体モジュールの検査において不良が発見され、その結果半導体モジュールの製造歩留まりが低下する原因について鋭意検討を行った。その結果、ウェハ状態での耐圧測定後個々のチップに分離する際にダイシング加工の不具合などに起因して不良チップが発生し、当該不良チップをモジュール基板上に実装することで半導体モジュールの製造歩留まりが低下することを見出し、本発明に想到した。 The present inventor has found that in a conventional method for manufacturing a silicon carbide semiconductor device, a defect is found in the inspection of the semiconductor module even if the defect is not confirmed in the breakdown voltage measurement in the wafer state, and as a result, the manufacturing yield of the semiconductor module decreases. We conducted an intensive study on the cause of this. As a result, when separating into individual chips after measuring the pressure resistance in the wafer state, defective chips are generated due to defects in dicing processing, etc., and the defective yields of the semiconductor modules are mounted by mounting the defective chips on the module substrate. Has been found, the present invention has been conceived.
　本発明の実施の形態に係る炭化珪素半導体装置の製造方法では、基板上に複数の素子部が形成され、当該複数の素子部の間に第１溝部が形成され、当該第１溝部の内部において素子部が分離される。また、第１溝部の形成後であって素子部を分離する前に当該素子部の耐圧が測定される。これにより、第１溝部の形成に起因した素子部の不良発生の有無を確認した上で個々の素子部に分離することができる。そして、良品であることが確認された素子部を含む炭化珪素半導体装置のみを実装することにより、半導体モジュールの製造歩留まりを向上させることができる。このように、本発明の実施の形態に係る炭化珪素半導体装置の製造方法によれば、半導体モジュールの製造歩留まりを向上させることができる。 In the method for manufacturing a silicon carbide semiconductor device according to the embodiment of the present invention, a plurality of element portions are formed on a substrate, a first groove portion is formed between the plurality of element portions, and the inside of the first groove portion. The element part is separated. Further, the breakdown voltage of the element portion is measured after the formation of the first groove portion and before the element portion is separated. Thereby, it can be separated into individual element parts after confirming whether or not the element part is defective due to the formation of the first groove part. Then, by mounting only the silicon carbide semiconductor device including the element portion that has been confirmed to be a non-defective product, the manufacturing yield of the semiconductor module can be improved. Thus, according to the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention, the manufacturing yield of the semiconductor module can be improved.
　上記実施の形態に係る炭化珪素半導体装置の製造方法において、素子部を形成する工程では、基板上にエピタキシャル成長層が形成されてもよい。また、第１溝部を形成する工程では、エピタキシャル成長層から基板にまで到達する第１溝部が形成されてもよい。 In the method for manufacturing the silicon carbide semiconductor device according to the above embodiment, an epitaxial growth layer may be formed on the substrate in the step of forming the element portion. In the step of forming the first groove portion, the first groove portion reaching from the epitaxial growth layer to the substrate may be formed.
　エピタキシャル成長層から基板にまで到達するように第１溝部を形成した場合には、素子部を分離する工程では第１溝部内の基板のみが切断加工などを受けるため、素子部が損傷を受ける可能性を低くすることができる。その結果、半導体モジュールの検査において不良が発見され、製造歩留まりが低下する可能性を低減することができる。 When the first groove portion is formed so as to reach the substrate from the epitaxial growth layer, only the substrate in the first groove portion is subjected to a cutting process or the like in the step of separating the element portion, so that the element portion may be damaged. Can be lowered. As a result, it is possible to reduce the possibility that a defect is found in the inspection of the semiconductor module and the manufacturing yield is lowered.
　上記実施の形態に係る炭化珪素半導体装置の製造方法において、素子部を形成する工程では、基板上に導電型が第１導電型であるエピタキシャル成長層が形成され、かつ、エピタキシャル成長層内に第１導電型と異なる導電型である第２導電型の不純物領域が形成されてもよい。また、第１溝部を形成する工程では、不純物領域の底部よりも深い位置にまで到達する第１溝部が形成されてもよい。 In the method for manufacturing the silicon carbide semiconductor device according to the above embodiment, in the step of forming the element portion, an epitaxial growth layer having a conductivity type of the first conductivity type is formed on the substrate, and the first conductivity is formed in the epitaxial growth layer. An impurity region of a second conductivity type that is a conductivity type different from the type may be formed. In the step of forming the first groove portion, the first groove portion reaching a position deeper than the bottom portion of the impurity region may be formed.
　不純物領域の底部よりも深い位置にまで到達するように第１溝部を形成した場合には、実質的に素子として動作する部分の殆どを分離した状態にすることができる。そのため、素子部を分離する工程では素子の動作に直接的な関連性の低い部分のみを加工することになり、素子部が損傷を受ける可能性を低減することができる。その結果、半導体モジュールの検査において不良が発見され、製造歩留まりが低下する可能性をより低減することができる。 When the first groove portion is formed so as to reach a position deeper than the bottom portion of the impurity region, most of the portion operating as an element can be separated. For this reason, in the step of separating the element portion, only a portion that is not directly related to the operation of the element is processed, and the possibility that the element portion is damaged can be reduced. As a result, it is possible to further reduce the possibility that a defect is found in the inspection of the semiconductor module and the manufacturing yield is lowered.
　上記実施の形態に係る炭化珪素半導体装置の製造方法において、素子部を分離する工程では、第１溝部の内部において第１溝部よりも幅が小さい第２溝部が形成されてもよい。これにより、第１溝部により分離された素子部が、素子部を分離する工程において損傷を受ける可能性をより確実に低減することができる。 In the method for manufacturing the silicon carbide semiconductor device according to the above embodiment, in the step of separating the element portion, a second groove portion having a width smaller than that of the first groove portion may be formed inside the first groove portion. Thereby, the possibility that the element part separated by the first groove part may be damaged in the step of separating the element part can be more reliably reduced.
　上記実施の形態に係る炭化珪素半導体装置の製造方法は、素子部の耐圧を測定する工程の後、素子部を分離する工程の前に、第１溝部の壁面上に保護膜を形成する工程をさらに備えていてもよい。これにより、素子部を分離する工程において炭化珪素半導体装置が受ける損傷を抑制することができる。 The method for manufacturing the silicon carbide semiconductor device according to the embodiment includes a step of forming a protective film on the wall surface of the first groove portion after the step of measuring the breakdown voltage of the element portion and before the step of separating the element portion. Furthermore, you may provide. Thereby, the damage which a silicon carbide semiconductor device receives in the process of isolate | separating an element part can be suppressed.
　上記実施の形態に係る炭化珪素半導体装置の製造方法は、素子部を分離する工程の後、複数の素子部のうち良品と不良品とを選別する工程をさらに備えていてもよい。これにより、不良品の素子部を含む炭化珪素半導体装置がモジュール基板上に実装されることをより確実に防止することができる。 The method for manufacturing a silicon carbide semiconductor device according to the above-described embodiment may further include a step of selecting a non-defective product and a defective product among the plurality of element portions after the step of separating the element portions. Thereby, it is possible to more reliably prevent the silicon carbide semiconductor device including the defective element portion from being mounted on the module substrate.
　本発明の実施の形態に係る半導体モジュールの製造方法は、上記実施の形態に係る炭化珪素半導体装置の製造方法により炭化珪素半導体装置を製造する工程と、モジュール基板を準備する工程と、モジュール基板上に炭化珪素半導体装置を実装する工程とを備えている。 A method for manufacturing a semiconductor module according to an embodiment of the present invention includes a step of manufacturing a silicon carbide semiconductor device by a method of manufacturing a silicon carbide semiconductor device according to the above embodiment, a step of preparing a module substrate, And a step of mounting the silicon carbide semiconductor device.
　本発明の実施の形態に係る半導体モジュールの製造方法では、上記実施の形態に係る炭化珪素半導体装置の製造方法により炭化珪素半導体装置が製造されるため、不良品の素子部を含む炭化珪素半導体装置がモジュール基板上に実装されることを防止することができる。したがって、本発明の実施の形態に係る半導体モジュールの製造方法によれば、半導体モジュールの製造歩留まりを向上させることができる。 In the method for manufacturing a semiconductor module according to the embodiment of the present invention, since the silicon carbide semiconductor device is manufactured by the method for manufacturing the silicon carbide semiconductor device according to the above embodiment, the silicon carbide semiconductor device including the defective element portion Can be prevented from being mounted on the module substrate. Therefore, according to the method for manufacturing a semiconductor module according to the embodiment of the present invention, the manufacturing yield of the semiconductor module can be improved.
　本発明の実施の形態に係る炭化珪素半導体装置は、炭化珪素からなる基板と、基板上に形成された素子部とを備えている。基板および素子部の少なくとも一方の端面には、段差部が形成されている。 A silicon carbide semiconductor device according to an embodiment of the present invention includes a substrate made of silicon carbide and an element portion formed on the substrate. A step portion is formed on at least one end face of the substrate and the element portion.
　本発明の実施の形態に係る炭化珪素半導体装置では、端面に段差部が形成されている。そのため、当該段差部が形成されていない炭化珪素半導体装置に比べて、モジュール基板上に実装した場合の炭化珪素半導体装置（チップ）の素子部間の距離をより大きくすることができる。これにより、実装された個々のチップ間における放電の発生を抑制することができる。したがって、本発明の実施の形態に係る炭化珪素半導体装置によれば、半導体モジュールの破損を抑制することができる。 In the silicon carbide semiconductor device according to the embodiment of the present invention, a step portion is formed on the end face. Therefore, the distance between the element portions of the silicon carbide semiconductor device (chip) when mounted on the module substrate can be made larger than that of the silicon carbide semiconductor device in which the step portion is not formed. Thereby, generation | occurrence | production of the discharge between each mounted chip | tip can be suppressed. Therefore, according to the silicon carbide semiconductor device according to the embodiment of the present invention, damage to the semiconductor module can be suppressed.
　上記実施の形態に係る炭化珪素半導体装置において、段差部から見て素子部側の領域である第１領域は、段差部から見て基板側の領域である第２領域よりも幅が小さくなっていてもよい。これにより、実装時のチップ間の距離を、素子部側の領域である第１領域において特に大きくすることができる。その結果、半導体モジュールの破損をより効果的に抑制することができる。 In the silicon carbide semiconductor device according to the above embodiment, the first region that is the region on the element portion side when viewed from the step portion has a smaller width than the second region that is the region on the substrate side when viewed from the step portion. May be. Thereby, the distance between the chips at the time of mounting can be particularly increased in the first region which is the region on the element portion side. As a result, damage to the semiconductor module can be suppressed more effectively.
　上記実施の形態に係る炭化珪素半導体装置において、第１領域における上記端面は、第１領域が第２領域側に向かって広がるように傾斜していてもよい。これにより、電界集中をより緩和することが可能な構造にすることができる。 In the silicon carbide semiconductor device according to the above embodiment, the end face in the first region may be inclined so that the first region spreads toward the second region side. Thereby, it can be set as the structure which can ease electric field concentration more.
　上記実施の形態に係る炭化珪素半導体装置は、上記端面上に形成された保護膜をさらに備えていてもよい。これにより、損傷が抑制された炭化珪素半導体装置を得ることができる。 The silicon carbide semiconductor device according to the above embodiment may further include a protective film formed on the end face. Thereby, a silicon carbide semiconductor device in which damage is suppressed can be obtained.
　本発明の実施の形態に係る半導体モジュールは、上記本実施の形態に係る炭化珪素半導体装置を備えている。したがって、本発明の実施の形態に係る半導体モジュールによれば、実装された個々の炭化珪素半導体装置（チップ）間の放電によるモジュールの破損を抑制することができる。 The semiconductor module according to the embodiment of the present invention includes the silicon carbide semiconductor device according to the present embodiment. Therefore, according to the semiconductor module according to the embodiment of the present invention, it is possible to suppress damage to the module due to discharge between the mounted individual silicon carbide semiconductor devices (chips).
　（本発明の実施の形態の詳細）
　次に、本発明の実施の形態の具体例を図面を参照しつつ説明する。なお、以下の図面において同一または相当する部分には同一の参照番号を付し、その説明は繰り返さない。 (Details of the embodiment of the present invention)
Next, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
　（実施の形態１）
　まず、本発明の一実施の形態である実施の形態１に係る半導体モジュールおよび炭化珪素半導体装置について説明する。図１を参照して、本実施の形態に係る半導体モジュール１は、モジュール基板２と、端子３と、複数のＭＯＳＦＥＴ１０Ａとを主に備えている。モジュール基板２は、絶縁基板（図示しない）や金属からなるヒートシンクとしての放熱板（図示しない）などを含んでいる。複数のＭＯＳＦＥＴ１０Ａは、モジュール基板２の表面２Ａ上に配置されており、配線４により互いに接続されている。端子３は、配線４によりＭＯＳＦＥＴ１０Ａと接続されている。ＭＯＳＦＥＴ１０Ａは、本実施の形態に係る炭化珪素半導体装置である。なお、半導体モジュール１は、図示しない樹脂により封止されていてもよい。 (Embodiment 1)
First, a semiconductor module and a silicon carbide semiconductor device according to the first embodiment which is an embodiment of the present invention will be described. With reference to FIG. 1, the semiconductor module 1 according to the present embodiment mainly includes a module substrate 2, a terminal 3, and a plurality of MOSFETs 10A. The module substrate 2 includes an insulating substrate (not shown), a heat sink (not shown) as a heat sink made of metal, and the like. The plurality of MOSFETs 10 </ b> A are arranged on the surface 2 </ b> A of the module substrate 2 and are connected to each other by the wiring 4. The terminal 3 is connected to the MOSFET 10 </ b> A by the wiring 4. MOSFET 10A is a silicon carbide semiconductor device according to the present embodiment. The semiconductor module 1 may be sealed with a resin (not shown).
　図２を参照して、ＭＯＳＦＥＴ１０Ａは、炭化珪素基板２０と、当該炭化珪素基板２０の一方の主面２０Ａ上に形成されたエピタキシャル成長層３０、酸化膜４０、ソース電極５０およびゲート電極６０（素子部）と、ドレイン電極７０とを主に備えている。エピタキシャル成長層３０には、ドリフト領域３１と、ボディ領域３２と、ソース領域３３と、コンタクト領域３４とが形成されている。 Referring to FIG. 2, MOSFET 10A includes a silicon carbide substrate 20, an epitaxial growth layer 30, an oxide film 40, a source electrode 50 and a gate electrode 60 (element portion) formed on one main surface 20A of silicon carbide substrate 20. ) And the drain electrode 70 are mainly provided. In the epitaxial growth layer 30, a drift region 31, a body region 32, a source region 33, and a contact region 34 are formed.
　ＭＯＳＦＥＴ１０Ａの厚みは、５０μｍ以上６００μｍ以下であり、好ましくは１００μｍ以上２００μｍ以下である。エピタキシャル成長層３０の厚みは、２μｍ以上５０μｍ以下であり、好ましくは５μｍ以上３５μｍ以下である。 The thickness of the MOSFET 10A is 50 μm or more and 600 μm or less, preferably 100 μm or more and 200 μm or less. The thickness of the epitaxial growth layer 30 is 2 μm or more and 50 μm or less, preferably 5 μm or more and 35 μm or less.
　ドリフト領域３１は、炭化珪素基板２０の一方の主面２０Ａ上に形成されている。ドリフト領域３１は、たとえばＮ（窒素）などのｎ型不純物を含むことにより、導電型がｎ型となっている。 The drift region 31 is formed on one main surface 20A of the silicon carbide substrate 20. Drift region 31 has an n-type conductivity by including an n-type impurity such as N (nitrogen).
　ボディ領域３２は、主面３０Ａを含むようにエピタキシャル成長層３０内に形成されている。ボディ領域３２は、たとえばＡｌ（アルミニウム）やＢ（硼素）などのｐ型不純物を含むことにより導電型がｐ型となっている。ボディ領域３２の厚みは０．１μｍ以上５０μｍ以下であり、好ましくは１μｍ以上３μｍ以下である。 The body region 32 is formed in the epitaxial growth layer 30 so as to include the main surface 30A. Body region 32 has a p-type conductivity by including a p-type impurity such as Al (aluminum) or B (boron). The thickness of the body region 32 is not less than 0.1 μm and not more than 50 μm, preferably not less than 1 μm and not more than 3 μm.
　ソース領域３３は、主面３０Ａを含むようにボディ領域３２内に形成されている。ソース領域３３は、たとえばＰ（リン）などのｎ型不純物を含むことにより、ドリフト領域３１と同様に導電型がｎ型となっている。ソース領域３３は、ドリフト領域３１よりもｎ型不純物の濃度が高くなっている。 The source region 33 is formed in the body region 32 so as to include the main surface 30A. Source region 33 includes an n-type impurity such as P (phosphorus), for example, so that conductivity type is n-type, similar to drift region 31. The source region 33 has a higher n-type impurity concentration than the drift region 31.
　コンタクト領域３４は、主面３０Ａを含み、ソース領域３３と隣接するようにボディ領域３２内に形成されている。コンタクト領域３４は、ボディ領域３２と同様にｐ型不純物を含むことにより導電型がｐ型となっている。コンタクト領域３４は、ボディ領域３２よりもｐ型不純物の濃度が高くなっている。 The contact region 34 includes the main surface 30 </ b> A and is formed in the body region 32 so as to be adjacent to the source region 33. Similar to body region 32, contact region 34 has a p-type conductivity by containing a p-type impurity. Contact region 34 has a higher p-type impurity concentration than body region 32.
　酸化膜４０は、主面３０Ａの一部を覆うように形成されている。酸化膜４０は、たとえばＳｉＯ２（二酸化珪素）からなっている。 Oxide film 40 is formed to cover part of main surface 30A. The oxide film 40 is made of, for example, SiO 2 (silicon dioxide).
　ゲート電極６０は、たとえば不純物が添加されたポリシリコンや、アルミニウムなどの導電体からなっており、酸化膜４０上に接触して形成されている。ゲート電極６０は、当該ゲート電極６０下において一方のソース領域３３から他方のソース領域３３にまで延在するように形成されている。 The gate electrode 60 is made of a conductive material such as polysilicon doped with impurities or aluminum, and is formed on the oxide film 40 in contact therewith. The gate electrode 60 is formed so as to extend from one source region 33 to the other source region 33 under the gate electrode 60.
　ソース電極５０は、主面３０Ａ上においてソース領域３３およびコンタクト領域３４に接触するように形成されている。ソース電極５０は、ソース領域３３に対してオーミック接触することができる材料、たとえばＮｉｘＳｉｙ（ニッケルシリサイド）、ＴｉｘＳｉｙ（チタンシリサイド）、ＡｌｘＳｉｙ（アルミシリサイド）およびＴｉｘＡｌｙＳｉｚ（チタンアルミシリサイド）などからなっており、ソース領域３３に対して電気的に接続されている。 Source electrode 50 is formed on main surface 30 </ b> A so as to be in contact with source region 33 and contact region 34. The source electrode 50 is made of a material capable of making ohmic contact with the source region 33, for example, Ni x Si y (nickel silicide), Ti x Si y (titanium silicide), Al x Si y (aluminum silicide), and Ti x Al. It is made of y Si z (titanium aluminum silicide) or the like and is electrically connected to the source region 33.
　ドレイン電極７０は、炭化珪素基板２０の他方の主面２０Ｂ上に形成されている。ドレイン電極７０は、たとえばソース電極５０と同様の材料からなっており、炭化珪素基板２０に対して電気的に接続されている。 The drain electrode 70 is formed on the other main surface 20B of the silicon carbide substrate 20. Drain electrode 70 is made of, for example, the same material as source electrode 50 and is electrically connected to silicon carbide substrate 20.
　ＭＯＳＦＥＴ１０Ａの端面１１（炭化珪素基板２０の端面１１）には段差部１３が形成されている。端面１１は、ＭＯＳＦＥＴ１０Ａの側端部における面であり、図２に示すように主面２０Ａ，３０Ａに対して交差（直交）する面である。ＭＯＳＦＥＴ１０Ａでは、段差部１３から見て素子部（エピタキシャル成長層３０、酸化膜４０、ソース電極５０およびゲート電極６０）側の領域が第１領域Ａ１となっており、また段差部１３から見て炭化珪素基板２０側の領域が第２領域Ａ２となっている。図２に示すように、第１領域Ａ１の幅（炭化珪素基板２０の表面２０Ｂに沿った方向における幅）は第２領域Ａ２の幅よりも小さくなっており、一方の端面１１側における幅差Ｗ１は１μｍ以上１００μｍ以下であり、好ましくは５μｍ以上５０μｍ以下であり、たとえば７０μｍである。 Step portion 13 is formed on end surface 11 of MOSFET 10A (end surface 11 of silicon carbide substrate 20). The end surface 11 is a surface at the side end portion of the MOSFET 10A, and is a surface that intersects (orthogonally) the main surfaces 20A and 30A as shown in FIG. In MOSFET 10A, the region on the element portion (epitaxial growth layer 30, oxide film 40, source electrode 50, and gate electrode 60) side when viewed from step portion 13 is first region A1, and silicon carbide is viewed from step portion 13. A region on the substrate 20 side is a second region A2. As shown in FIG. 2, the width of the first region A1 (the width in the direction along the surface 20B of the silicon carbide substrate 20) is smaller than the width of the second region A2, and the width difference on the one end face 11 side. W1 is 1 μm or more and 100 μm or less, preferably 5 μm or more and 50 μm or less, for example 70 μm.
　段差部１３は、図２に示すように、ボディ領域３２の底面３２Ａから見て炭化珪素基板２０側に位置するように形成されており、また炭化珪素基板２０とエピタキシャル成長層３０との接触面２０Ａから見て炭化珪素基板２０側に位置するように形成されている。また、段差部１３の形成位置はこれに限定されず、たとえば底面３２Ａから見て炭化珪素基板２０側に位置し、かつ接触面２０Ａから見てエピタキシャル成長層３０側に位置するように形成されていてもよい。この場合、段差部１３はエピタキシャル成長層３０の端面１１に形成される。 As shown in FIG. 2, stepped portion 13 is formed to be located on the side of silicon carbide substrate 20 as viewed from bottom surface 32 </ b> A of body region 32, and contact surface 20 </ b> A between silicon carbide substrate 20 and epitaxial growth layer 30. Is formed so as to be located on the silicon carbide substrate 20 side when viewed from the side. Further, the formation position of the stepped portion 13 is not limited to this. For example, the stepped portion 13 is formed so as to be located on the silicon carbide substrate 20 side when viewed from the bottom surface 32A and on the epitaxial growth layer 30 side when viewed from the contact surface 20A. Also good. In this case, the step portion 13 is formed on the end surface 11 of the epitaxial growth layer 30.
　次に、本実施の形態に係るＭＯＳＦＥＴ１０Ａの動作について説明する。図２を参照して、ゲート電極６０に印加された電圧が閾値電圧未満の状態、すなわちオフ状態では、ソース電極５０とドレイン電極７０との間に電圧が印加されても、ボディ領域３２とドリフト領域３１との間に形成されるｐｎ接合が逆バイアスとなり、非導通状態となる。一方、ゲート電極６０に閾値電圧以上の電圧が印加されると、ボディ領域３２のチャネル領域（ゲート電極６０下のボディ領域３２）に反転層が形成される。その結果、ソース領域３３とドリフト領域３１とが電気的に接続され、ソース電極５０とドレイン電極７０との間に電流が流れる。以上のようにして、ＭＯＳＦＥＴ１０Ａは動作する。 Next, the operation of MOSFET 10A according to the present embodiment will be described. Referring to FIG. 2, in a state where the voltage applied to gate electrode 60 is less than the threshold voltage, that is, in the off state, even if a voltage is applied between source electrode 50 and drain electrode 70, body region 32 drifts. The pn junction formed with the region 31 is reverse-biased and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 60, an inversion layer is formed in the channel region of the body region 32 (the body region 32 below the gate electrode 60). As a result, the source region 33 and the drift region 31 are electrically connected, and a current flows between the source electrode 50 and the drain electrode 70. As described above, the MOSFET 10A operates.
　次に、本実施の形態に係る半導体モジュールおよび炭化珪素半導体装置の製造方法について説明する。本実施の形態に係る炭化珪素半導体装置の製造方法では、図３を参照して、工程（Ｓ１０）～（Ｓ１１０）が実施されることにより上記本実施の形態に係るＭＯＳＦＥＴ１０Ａが製造される。また、本実施の形態に係る半導体モジュールの製造方法では、図４を参照して、工程（Ｓ１２０）～（Ｓ１４０）が実施されることにより上記本実施の形態に係る半導体モジュール１が製造される。 Next, a method for manufacturing the semiconductor module and the silicon carbide semiconductor device according to the present embodiment will be described. In the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, referring to FIG. 3, MOSFET (10A) according to the present embodiment is manufactured by performing steps (S10) to (S110). In the method for manufacturing a semiconductor module according to the present embodiment, referring to FIG. 4, steps (S120) to (S140) are performed to manufacture semiconductor module 1 according to the present embodiment. .
　図３を参照して、本実施の形態に係る炭化珪素半導体装置の製造方法では、まず、工程（Ｓ１０）として、炭化珪素基板準備工程が実施される。この工程（Ｓ１０）では、図５を参照して、たとえば４Ｈ－ＳｉＣからなるインゴット（図示しない）をスライスすることにより、導電型がｎ型（第１導電型）である炭化珪素基板２０が準備される。 Referring to FIG. 3, in the method for manufacturing a silicon carbide semiconductor device according to the present embodiment, first, a silicon carbide substrate preparation step is performed as a step (S10). In this step (S10), referring to FIG. 5, silicon carbide substrate 20 having a conductivity type of n type (first conductivity type) is prepared by slicing an ingot (not shown) made of, for example, 4H—SiC. Is done.
　次に、工程（Ｓ２０）として、エピタキシャル成長層形成工程が実施される。この工程（Ｓ２０）では、図５を参照して、炭化珪素基板２０の主面２０Ａ上において導電型がｎ型であるエピタキシャル成長層３０が形成される。 Next, as a step (S20), an epitaxial growth layer forming step is performed. In this step (S20), referring to FIG. 5, epitaxial growth layer 30 having an n conductivity type is formed on main surface 20A of silicon carbide substrate 20.
　次に、工程（Ｓ３０）として、イオン注入工程が実施される。この工程（Ｓ３０）では、図６を参照して、まず、たとえばアルミニウム（Ａｌ）イオンがエピタキシャル成長層３０の主面３０Ａを含む領域に注入されることにより、エピタキシャル成長層３０内にボディ領域３２（不純物領域）が形成される。ボディ領域３２の導電型はｐ型（第２導電型）である。次に、たとえばリン（Ｐ）イオンが主面３０Ａを含む領域において、上記Ａｌイオンの注入深さよりも浅い深さで注入されることにより、ソース領域３３が形成される。次に、たとえばＡｌイオンが、ソース領域３３に隣接し主面３０Ａを含む領域に注入されることにより、ソース領域３３と同等の深さを有するコンタクト領域３４が形成される。また、エピタキシャル成長層３０において、ボディ領域３２、ソース領域３３およびコンタクト領域３４がいずれも形成されない領域はドリフト領域３１となる。 Next, as a step (S30), an ion implantation step is performed. In this step (S30), referring to FIG. 6, first, for example, aluminum (Al) ions are implanted into a region including main surface 30A of epitaxial growth layer 30 to thereby form body region 32 (impurity in epitaxial growth layer 30). Region) is formed. The conductivity type of the body region 32 is p-type (second conductivity type). Next, for example, phosphorus (P) ions are implanted at a depth shallower than the Al ion implantation depth in a region including main surface 30 </ b> A, thereby forming source region 33. Next, for example, Al ions are implanted into a region adjacent to source region 33 and including main surface 30 </ b> A, thereby forming contact region 34 having a depth equivalent to that of source region 33. In the epitaxial growth layer 30, a region where none of the body region 32, the source region 33, and the contact region 34 is formed becomes a drift region 31.
　次に、工程（Ｓ４０）として、活性化アニール工程が実施される。この工程（Ｓ４０）では、図６を参照して、ドリフト領域３１、ボディ領域３２、ソース領域３３およびコンタクト領域３４を含むエピタキシャル成長層３０が形成された炭化珪素基板２０を加熱することにより、上記工程（Ｓ３０）において導入された不純物が活性化される。これにより、不純物が導入された領域において所望のキャリアが生成する。 Next, an activation annealing step is performed as a step (S40). In this step (S40), referring to FIG. 6, by heating silicon carbide substrate 20 on which epitaxially grown layer 30 including drift region 31, body region 32, source region 33 and contact region 34 is formed, the above step is performed. The impurities introduced in (S30) are activated. As a result, desired carriers are generated in the region where the impurity is introduced.
　次に、工程（Ｓ５０）として、酸化膜形成工程が実施される。この工程（Ｓ５０）では、図７を参照して、たとえば酸素を含む雰囲気中においてエピタキシャル成長層３０が形成された炭化珪素基板２０を加熱することにより、エピタキシャル成長層３０の主面３０Ａを覆うようにＳｉＯ２（二酸化珪素）からなる酸化膜４０が形成される。 Next, an oxide film forming step is performed as a step (S50). In this step (S50), referring to FIG. 7, for example, by heating silicon carbide substrate 20 on which epitaxially grown layer 30 is formed in an oxygen-containing atmosphere, SiO 2 so as to cover main surface 30A of epitaxially grown layer 30 is covered. An oxide film 40 made of 2 (silicon dioxide) is formed.
　次に、工程（Ｓ６０）として、ゲート電極形成工程が実施される。この工程（Ｓ６０）では、図８を参照して、たとえばＬＰＣＶＤ（Ｌｏｗ　Ｐｒｅｓｓｕｒｅ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法により、酸化膜４０上に接触するようにポリシリコンからなるゲート電極６０が形成される。 Next, as a step (S60), a gate electrode forming step is performed. In this step (S60), referring to FIG. 8, gate electrode 60 made of polysilicon is formed so as to be in contact with oxide film 40 by, for example, LPCVD (Low Pressure Chemical Vapor Deposition).
　次に、工程（Ｓ７０）として、オーミック電極形成工程が実施される。この工程（Ｓ７０）では、図８を参照して、まず、ソース電極５０を形成すべき領域において酸化膜４０が除去され、ソース領域３３およびコンタクト領域３４が露出した領域が形成される。そして、当該領域において、たとえばＮｉからなる膜が形成される。一方、炭化珪素基板２０の主面２０Ｂ上に、たとえばＮｉからなる膜が形成される。その後、合金化熱処理が施され、上記Ｎｉからなる膜の少なくとも一部がシリサイド化されることにより、ソース電極５０およびドレイン電極７０が形成される。このように上記工程（Ｓ２０）～（Ｓ７０）が実施されることにより、炭化珪素基板２０の主面２０Ａ上において、エピタキシャル成長層３０、酸化膜４０、ソース電極５０およびゲート電極６０を含む素子部８０が複数形成される。 Next, as a step (S70), an ohmic electrode forming step is performed. In this step (S70), referring to FIG. 8, first, oxide film 40 is removed in a region where source electrode 50 is to be formed, and a region where source region 33 and contact region 34 are exposed is formed. In the region, a film made of, for example, Ni is formed. On the other hand, a film made of, for example, Ni is formed on main surface 20B of silicon carbide substrate 20. Thereafter, an alloying heat treatment is performed, and at least a part of the Ni film is silicided, whereby the source electrode 50 and the drain electrode 70 are formed. By performing steps (S20) to (S70) as described above, element portion 80 including epitaxial growth layer 30, oxide film 40, source electrode 50, and gate electrode 60 on main surface 20A of silicon carbide substrate 20 is performed. A plurality of are formed.
　次に、工程（Ｓ８０）として、第１ダイシング工程が実施される。この工程（Ｓ８０）では、図９を参照して、主面３０Ａ側からエピタキシャル成長層３０および炭化珪素基板２０に対してダイシング加工を施すことにより、複数の素子部８０同士の間に第１溝部９０が形成される。第１溝部９０の幅Ｗ２は、たとえば３００μｍ以下である。 Next, as a step (S80), a first dicing step is performed. In this step (S80), referring to FIG. 9, by performing dicing processing on epitaxial growth layer 30 and silicon carbide substrate 20 from the main surface 30A side, first groove portion 90 is formed between a plurality of element portions 80. Is formed. The width W2 of the first groove portion 90 is, for example, 300 μm or less.
　この工程（Ｓ８０）では、図９に示すようにエピタキシャル成長層３０から炭化珪素基板２０にまで到達するように第１溝部９０が形成されてもよい。より具体的には、底壁面９０Ａが、ボディ領域３２の底面３２Ａ（底部）よりも深い位置にまで到達し、かつ炭化珪素基板２０とエピタキシャル成長層３０との接触面２０Ａから見て炭化珪素基板２０側に位置するように第１溝部９０が形成されてもよい。 In this step (S80), the first groove 90 may be formed so as to reach from the epitaxial growth layer 30 to the silicon carbide substrate 20 as shown in FIG. More specifically, bottom wall surface 90 </ b> A reaches a position deeper than bottom surface 32 </ b> A (bottom portion) of body region 32, and silicon carbide substrate 20 as viewed from contact surface 20 </ b> A between silicon carbide substrate 20 and epitaxial growth layer 30. The first groove portion 90 may be formed so as to be located on the side.
　次に、工程（Ｓ９０）として、耐圧測定工程が実施される。この工程（Ｓ９０）では、上記工程（Ｓ２０）～（Ｓ７０）において形成された複数の素子部８０の耐圧が測定される。まず、この工程（Ｓ９０）において用いられる耐圧測定装置の構造について説明する。 Next, as a step (S90), a pressure resistance measuring step is performed. In this step (S90), the withstand voltages of the plurality of element portions 80 formed in the above steps (S20) to (S70) are measured. First, the structure of the pressure | voltage resistant measuring apparatus used in this process (S90) is demonstrated.
　図１０を参照して、耐圧測定装置１００は、気密容器１１０と、カメラ１１２と、ステージ１２０と、プローブ１３０と、電圧源１３４と、ゲート制御部１３５と、導入口１４０と、排出口１５０と、ヒータ１６０と、センサ１７０とを備えている。 Referring to FIG. 10, the pressure resistance measuring device 100 includes an airtight container 110, a camera 112, a stage 120, a probe 130, a voltage source 134, a gate controller 135, an inlet 140, and an outlet 150. The heater 160 and the sensor 170 are provided.
　ステージ１２０は、気密容器１１０内に設けられており、炭化珪素基板２０を支持するためのものである。ステージ１２０は、炭化珪素基板２０を固定するための真空チャック１２１を有していてもよい。 The stage 120 is provided in the hermetic container 110 and is for supporting the silicon carbide substrate 20. Stage 120 may have a vacuum chuck 121 for fixing silicon carbide substrate 20.
　プローブ１３０は気密容器１１０内に設けられている。プローブ１３０の機能の一つは、ソース電極５０（図９参照）に接触することによってソース電極５０との電気的接続を得ることである。プローブ１３０は、たとえば、基部１３１と針１３２および１３３とを有してもよい。針１３２および１３３のそれぞれはソース電極５０およびゲート電極６０（図９参照）との電気的接続を得るためのものであり、基部１３１に取り付けられている。 The probe 130 is provided in the airtight container 110. One of the functions of the probe 130 is to obtain an electrical connection with the source electrode 50 by contacting the source electrode 50 (see FIG. 9). The probe 130 may have a base 131 and needles 132 and 133, for example. Each of the needles 132 and 133 is for obtaining an electrical connection with the source electrode 50 and the gate electrode 60 (see FIG. 9), and is attached to the base 131.
　ステージ１２０は移動機構１２２上に設けられることで、気密容器１１０内において移動可能に構成されている。これによりステージ１２０とプローブ１３０とが相対的に変位可能に構成されている。言い換えれば、プローブ１３０はステージ１２０に対して相対的に移動可能に構成されている。移動機構１２２は、好ましくは、３次元的な変位を可能とする、いわゆるＸＹＺステージである。 The stage 120 is configured to be movable in the airtight container 110 by being provided on the moving mechanism 122. Accordingly, the stage 120 and the probe 130 are configured to be relatively displaceable. In other words, the probe 130 is configured to be movable relative to the stage 120. The moving mechanism 122 is preferably a so-called XYZ stage that enables three-dimensional displacement.
　導入口１４０は、気密容器１１０に設けられており、気密容器１１０内にガスを導入するためのものである。排出口１５０は、気密容器１１０に設けられており、気密容器１１０からガスを排出するためのものである。導入口１４０および排出口１５０のそれぞれはゲート弁１４１および１５１を有する。 The introduction port 140 is provided in the hermetic container 110 and is for introducing gas into the hermetic container 110. The discharge port 150 is provided in the hermetic container 110 and is for discharging gas from the hermetic container 110. Each of the inlet 140 and the outlet 150 has gate valves 141 and 151.
　ヒータ１６０は炭化珪素基板２０を加熱するためのものである。ヒータ１６０は気密容器１１０内に配置されており、ステージ１２０内に配置されていてもよい。ヒータ１６０には、気密容器１１０の外部に配置されたヒータ電源１６１が接続されていてもよい。 The heater 160 is for heating the silicon carbide substrate 20. The heater 160 is disposed in the hermetic container 110 and may be disposed in the stage 120. A heater power supply 161 disposed outside the hermetic container 110 may be connected to the heater 160.
　センサ１７０は、気密容器１１０内の露点温度を検出するために、気密容器１１０内に設けられている。センサ１７０は、露点温度を直接測定可能なように専用に設計された露点温度計であってもよく、あるいは、温度および湿度から露点温度を算出するために温度計および湿度計を有するものであってもよい。センサ１７０は、気密容器１１０の外部に設けられた読取部１７１と接続されていてもよい。 The sensor 170 is provided in the hermetic container 110 in order to detect the dew point temperature in the hermetic container 110. The sensor 170 may be a dew point thermometer designed specifically for direct measurement of the dew point temperature, or has a thermometer and a hygrometer to calculate the dew point temperature from the temperature and humidity. May be. The sensor 170 may be connected to a reading unit 171 provided outside the hermetic container 110.
　電圧源１３４はプローブ１３０に接続されている。具体的には電圧源１３４は、プローブ１３０の針１３２と、ステージ１２０との間に電圧を加えるように接続されている。電圧源１３４が発生可能な電圧は、好ましくは６００Ｖ程度以上であり、より好ましくは１ｋＶ程度以上であり、さらに好ましくは３ｋＶ程度以上である。 The voltage source 134 is connected to the probe 130. Specifically, the voltage source 134 is connected to apply a voltage between the needle 132 of the probe 130 and the stage 120. The voltage that can be generated by the voltage source 134 is preferably about 600 V or more, more preferably about 1 kV or more, and further preferably about 3 kV or more.
　ゲート制御部１３５は、プローブ１３０の針１３２および１３３の間に電圧を加えるように接続されている。ゲート制御部１３５は、素子部８０（図９参照）のゲート電圧を制御できる程度の電圧を発生可能なものであればよい。 The gate control unit 135 is connected so as to apply a voltage between the needles 132 and 133 of the probe 130. The gate control unit 135 only needs to be capable of generating a voltage that can control the gate voltage of the element unit 80 (see FIG. 9).
　気密容器１１０は、気密容器１１０の外部から素子部８０（図９参照）の位置が観測可能となるように、光を透過する窓１１１を有する。窓１１１は、この目的に十分な程度に光を透過する材料から作られており、たとえばガラスまたは透明樹脂から作られている。窓１１１には、耐圧測定時に窓１１１を介して光が入射しないように遮光を行なうための遮光部（図示せず）が設けられることが好ましい。この遮光部は、たとえば、窓１１１の外側において着脱され得るカバー、または、窓１１１の外側または内側に設けられたシャッターである。カメラ１１２は、図１０中の破線で示すように、窓１１１を介して炭化珪素基板２０を観察し得るように配置されている。 The hermetic container 110 has a window 111 that transmits light so that the position of the element unit 80 (see FIG. 9) can be observed from the outside of the hermetic container 110. The window 111 is made of a material that transmits light to a sufficient extent for this purpose, for example, glass or transparent resin. The window 111 is preferably provided with a light shielding portion (not shown) for performing light shielding so that light does not enter through the window 111 during pressure resistance measurement. This light-shielding portion is, for example, a cover that can be attached and detached outside the window 111 or a shutter provided outside or inside the window 111. Camera 112 is arranged so that silicon carbide substrate 20 can be observed through window 111, as indicated by a broken line in FIG.
　次に、耐圧測定装置１００を用いた耐圧測定方法について、図１０および図１１を参照して説明する。まず、気密容器１１０内に炭化珪素基板２０が支持される。具体的には、炭化珪素基板２０が気密容器１１０内に搬入され、さらにステージ１２０上に載置される。これにより炭化珪素基板２０の裏面に位置するドレイン電極７０の電位がステージ１２０の電位とされる（図１１参照）。また炭化珪素基板２０がステージ１２０に固定される。この固定は、真空チャック１２１によって行われ得る。 Next, a pressure resistance measuring method using the pressure resistance measuring apparatus 100 will be described with reference to FIG. 10 and FIG. First, silicon carbide substrate 20 is supported in hermetic container 110. Specifically, silicon carbide substrate 20 is carried into airtight container 110 and further placed on stage 120. Thereby, the potential of drain electrode 70 located on the back surface of silicon carbide substrate 20 is set to the potential of stage 120 (see FIG. 11). Silicon carbide substrate 20 is fixed to stage 120. This fixing can be performed by the vacuum chuck 121.
　次に、移動機構１２２の駆動によってステージ１２０とプローブ１３０との間の相対変位が生じることにより、図１１に示すように、針１３２および１３３のそれぞれがソース電極５０およびゲート電極６０に接触させられる。このようにしてソース電極５０にプローブ１３０が接触させられつつ、プローブ１３０に電圧が供給される。具体的には、プローブ１３０の針１３２とステージ１２０との間に電圧が供給される。これによりドレイン電極７０およびソース電極５０の間に、耐圧測定のための電圧が印加される。この電圧は、たとえば６００Ｖ程度以上である。また必要に応じてゲート制御部１３５によってゲート電圧が調整される。これにより素子部８０（図９参照）の耐圧が測定される。 Next, the movement of the moving mechanism 122 causes a relative displacement between the stage 120 and the probe 130, so that the needles 132 and 133 are brought into contact with the source electrode 50 and the gate electrode 60, respectively, as shown in FIG. . In this way, a voltage is supplied to the probe 130 while the probe 130 is in contact with the source electrode 50. Specifically, a voltage is supplied between the needle 132 of the probe 130 and the stage 120. As a result, a voltage for measuring the withstand voltage is applied between the drain electrode 70 and the source electrode 50. This voltage is about 600V or more, for example. Further, the gate voltage is adjusted by the gate controller 135 as necessary. Thereby, the breakdown voltage of the element unit 80 (see FIG. 9) is measured.
　次に、工程（Ｓ１００）として、第２ダイシング工程が実施される。この工程（Ｓ１００）では、図１２を参照して、炭化珪素基板２０に対してさらにダイシング加工を施すことにより、第１溝部９０において素子部８０同士が分離される。より具体的には、第１溝部９０の内部において第２溝部９１が形成されることにより、素子部８０同士が分離される。図１２に示すように、第２溝部９１の幅Ｗ３は第１溝部９０の幅Ｗ２よりも小さく、１００μｍ以下であってもよく、たとえば７０μｍである。また、「第２溝部９１」は、図１２に示すように炭化珪素基板２０を厚み方向に貫通するように形成されたものでもよく、炭化珪素基板２０の一部（主面２０Ｂを含む部分）を残存させるように形成されたものでもよい。なお、第２溝部９１が炭化珪素基板２０の一部を残存させるように形成された場合には、その後炭化珪素基板２０に対して所定の応力を加えることにより素子部８０同士を完全に分離することができる。 Next, a second dicing step is performed as a step (S100). In this step (S100), referring to FIG. 12, element portions 80 are separated in first groove portion 90 by further dicing the silicon carbide substrate 20. More specifically, the element portions 80 are separated from each other by forming the second groove portion 91 inside the first groove portion 90. As shown in FIG. 12, the width W3 of the second groove 91 is smaller than the width W2 of the first groove 90, and may be 100 μm or less, for example, 70 μm. "Second groove portion 91" may be formed so as to penetrate silicon carbide substrate 20 in the thickness direction as shown in FIG. 12, and part of silicon carbide substrate 20 (a portion including main surface 20B). May be formed so as to remain. When second groove portion 91 is formed so as to leave a part of silicon carbide substrate 20, element portions 80 are completely separated from each other by applying a predetermined stress to silicon carbide substrate 20 thereafter. be able to.
　次に、工程（Ｓ１１０）として、選別工程が実施される。この工程（Ｓ１１０）では、上記工程（Ｓ１００）において個々の素子部８０に分離された後、上記工程（Ｓ９０）の耐圧測定において良品と判断されたものと不良品と判断されたものとが選別される。この工程（Ｓ１１０）は、本発明の炭化珪素半導体装置の製造方法において必須の工程ではないが、これを実施することにより良品と判断された素子部８０を含むＭＯＳＦＥＴのみを確実に実装することができる。その結果、モジュール製造の歩留まりを向上させることができる。以上のようにして工程（Ｓ１０）～（Ｓ１１０）が実施されることにより上記ＭＯＳＦＥＴ１０Ａが製造され、本実施の形態に係る炭化珪素半導体装置の製造方法が完了する。 Next, as a step (S110), a sorting step is performed. In this step (S110), after being separated into the individual element portions 80 in the step (S100), those determined as good products and those determined as defective in the pressure resistance measurement in the step (S90) are selected. Is done. Although this step (S110) is not an essential step in the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to reliably mount only the MOSFET including the element portion 80 determined to be non-defective by carrying out this step. it can. As a result, the module manufacturing yield can be improved. By performing steps (S10) to (S110) as described above, MOSFET 10A is manufactured, and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.
　次に、本実施の形態に係る半導体モジュールの製造方法について説明する。図４を参照して、本実施の形態に係る半導体モジュールの製造方法では、まず、工程（Ｓ１２０）として、デバイス準備工程が実施される。この工程（Ｓ１２０）では、上記本実施の形態に係る炭化珪素半導体装置の製造方法によりＭＯＳＦＥＴ１０Ａが製造される。また、工程（Ｓ１２０）と並んで工程（Ｓ１３０）が実施されることにより、モジュール基板２が準備される（図１参照）。 Next, a method for manufacturing a semiconductor module according to the present embodiment will be described. Referring to FIG. 4, in the method for manufacturing a semiconductor module according to the present embodiment, first, as a step (S120), a device preparation step is performed. In this step (S120), MOSFET 10A is manufactured by the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. Further, the module substrate 2 is prepared by performing the step (S130) along with the step (S120) (see FIG. 1).
　工程（Ｓ１２０）および（Ｓ１３０）が完了した後、工程（Ｓ１４０）としてデバイス実装工程が実施される。この工程（Ｓ１４０）では、図１を参照して、モジュール基板２の表面２Ａ上において複数のＭＯＳＦＥＴ１０Ａが配置される。そして、ＭＯＳＦＥＴ１０Ａ同士、またはＭＯＳＦＥＴ１０Ａと端子３とが配線４により電気的に接続される。このようにしてモジュール基板２上にＭＯＳＦＥＴ１０Ａが実装される。以上のようにして工程（Ｓ１２０）～（Ｓ１４０）が実施されることにより上記半導体モジュール１が製造され、本実施の形態に係る半導体モジュールの製造方法が完了する。 After the steps (S120) and (S130) are completed, a device mounting step is performed as a step (S140). In this step (S140), referring to FIG. 1, a plurality of MOSFETs 10A are arranged on surface 2A of module substrate 2. The MOSFETs 10 </ b> A or the MOSFET 10 </ b> A and the terminal 3 are electrically connected by the wiring 4. In this way, the MOSFET 10A is mounted on the module substrate 2. By performing steps (S120) to (S140) as described above, the semiconductor module 1 is manufactured, and the manufacturing method of the semiconductor module according to the present embodiment is completed.
　以上のように、本実施の形態に係る炭化珪素半導体装置の製造方法では、炭化珪素基板２０上に複数の素子部８０が形成され、複数の素子部８０の間に第１溝部９０が形成され、第１溝部９０の内部において複数の素子部８０が分離される。また、第１溝部９０の形成後であって素子部８０を分離する前に素子部８０の耐圧が測定される。これにより、第１溝部９０の形成に起因した素子部８０の不良発生の有無を確認した上で個々の素子部８０に分離することができる。そして、良品であることが確認された素子部８０を含むＭＯＳＦＥＴ１０Ａのみを実装することで、半導体モジュールの製造歩留まりを向上させることができる。このように、本実施の形態に係る炭化珪素半導体装置および半導体モジュールの製造方法によれば、半導体モジュールの製造歩留まりを向上させることができる。 As described above, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, a plurality of element portions 80 are formed on silicon carbide substrate 20, and first groove portion 90 is formed between the plurality of element portions 80. The plurality of element parts 80 are separated inside the first groove part 90. Further, the breakdown voltage of the element unit 80 is measured after the formation of the first groove 90 and before the element unit 80 is separated. As a result, it is possible to separate each element unit 80 after confirming whether or not the element unit 80 is defective due to the formation of the first groove 90. Then, by mounting only the MOSFET 10A including the element unit 80 that has been confirmed to be non-defective, the manufacturing yield of the semiconductor module can be improved. Thus, according to the silicon carbide semiconductor device and the method for manufacturing a semiconductor module according to the present embodiment, the manufacturing yield of the semiconductor module can be improved.
　また、本実施の形態に係るＭＯＳＦＥＴ１０Ａでは、端面１１において段差部１３が形成されている。そのため、当該段差部１３が形成されていないＭＯＳＦＥＴに比べて、図１に示すようにモジュール基板２上に実装した場合のチップ間の距離をより大きくすることができる。これにより、実装された個々のチップ間における放電の発生を抑制することができる。したがって、本実施の形態に係るＭＯＳＦＥＴ１０および半導体モジュール１によれば、チップ間の放電によるモジュールの破損を抑制することができる。 Further, in the MOSFET 10A according to the present embodiment, the step portion 13 is formed on the end face 11. Therefore, the distance between chips when mounted on the module substrate 2 as shown in FIG. 1 can be made larger than that of a MOSFET in which the step portion 13 is not formed. Thereby, generation | occurrence | production of the discharge between each mounted chip | tip can be suppressed. Therefore, according to MOSFET 10 and semiconductor module 1 according to the present embodiment, damage to the module due to discharge between chips can be suppressed.
　（実施の形態２）
　次に、本発明の他の実施の形態である実施の形態２について説明する。本実施の形態に係る炭化珪素半導体装置は、基本的には上記実施の形態１に係るＭＯＳＦＥＴ１０Ａと同様の構成を備え、同様に動作し、同様の効果を奏する。しかし、本実施の形態に係る炭化珪素半導体装置は、第１領域Ａ１の構成において上記ＭＯＳＦＥＴ１０Ａとは異なっている。 (Embodiment 2)
Next, Embodiment 2 which is another embodiment of the present invention will be described. The silicon carbide semiconductor device according to the present embodiment basically has the same configuration as MOSFET 10A according to the above-described first embodiment, operates in the same manner, and has the same effects. However, the silicon carbide semiconductor device according to the present embodiment is different from MOSFET 10A in the configuration of first region A1.
　図１３を参照して、本実施の形態に係る炭化珪素半導体装置であるＭＯＳＦＥＴ１０Ｂでは、第１領域Ａ１における端面１１Ａは、第１領域Ａ１が第２領域Ａ２に向かって広がるように傾斜している。これにより、エピタキシャル成長層３０の主面３０Ａおよび端面１１Ａにより、９０°を超える角θが形成されている。これにより、当該角θが９０°である上記実施の形態１の場合に比べて電界集中をより緩和し易い構造にすることができる。 Referring to FIG. 13, in MOSFET 10B which is the silicon carbide semiconductor device according to the present embodiment, end surface 11A in first region A1 is inclined so that first region A1 extends toward second region A2. . Thereby, an angle θ exceeding 90 ° is formed by the main surface 30A and the end surface 11A of the epitaxial growth layer 30. Thereby, it is possible to achieve a structure in which the electric field concentration is more easily relaxed than in the case of the first embodiment in which the angle θ is 90 °.
　（実施の形態３）
　次に、本発明のさらに他の実施の形態である実施の形態３について説明する。本実施の形態に係る炭化珪素半導体装置は、基本的には上記実施の形態１に係るＭＯＳＦＥＴ１０Ａと同様の構成を備え、同様に動作し、同様の効果を奏する。しかし、本実施の形態に係る炭化珪素半導体装置は、端面上に保護膜が形成されている点において上記ＭＯＳＦＥＴ１０Ａとは異なっている。 (Embodiment 3)
Next, Embodiment 3 which is still another embodiment of the present invention will be described. The silicon carbide semiconductor device according to the present embodiment basically has the same configuration as MOSFET 10A according to the above-described first embodiment, operates in the same manner, and has the same effects. However, the silicon carbide semiconductor device according to the present embodiment differs from MOSFET 10A in that a protective film is formed on the end surface.
　図１４を参照して、本実施の形態に係る炭化珪素半導体装置であるＭＯＳＦＥＴ１０Ｃは、第１領域Ａ１の端面１１Ａおよび段差部１３上に形成されたパッシベーション膜９２（保護膜）をさらに備えている。パッシベーション膜９２は、たとえば二酸化珪素（ＳｉＯ２）などからなり、酸化膜４０と繋がるように形成されている。これにより、当該パッシベーション膜９２が形成されない場合に比べて、ＭＯＳＦＥＴ１０Ｃが受ける損傷を抑制することができる。 Referring to FIG. 14, MOSFET 10C as the silicon carbide semiconductor device according to the present embodiment further includes a passivation film 92 (protective film) formed on end surface 11A and stepped portion 13 of first region A1. . The passivation film 92 is made of, for example, silicon dioxide (SiO 2 ), and is formed so as to be connected to the oxide film 40. Thereby, compared with the case where the said passivation film 92 is not formed, the damage which MOSFET10C receives can be suppressed.
　次に、本実施の形態に係る炭化珪素半導体装置の製造方法について説明する。図１５を参照して、まず、上記実施の形態１の工程（Ｓ１０）～（Ｓ９０）と同様に工程（Ｓ１５０）～（Ｓ２３０）が実施される。これにより、図９に示すように炭化珪素基板２０上に素子部８０が形成され、当該素子部８０の耐圧測定が完了した状態となる。 Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described. Referring to FIG. 15, first, steps (S150) to (S230) are performed similarly to steps (S10) to (S90) of the first embodiment. Thereby, element portion 80 is formed on silicon carbide substrate 20 as shown in FIG. 9, and the pressure resistance measurement of element portion 80 is completed.
　次に、工程（Ｓ２４０）として、パッシベーション膜形成工程が実施される。この工程（Ｓ２４０）では、図１６を参照して、たとえばＰ（Ｐｌａｓｍａ）－ＣＶＤ法などにより、二酸化珪素（ＳｉＯ２）からなるパッシベーション膜９２が第１溝部９０の底壁面９０Ａおよび側壁面９０Ｂ上を覆うように形成される。そして、工程（Ｓ２４０）が完了した後に上記実施の形態１の工程（Ｓ１００）および（Ｓ１１０）と同様に工程（Ｓ２５０）および（Ｓ２６０）が実施され、上記本実施の形態に係るＭＯＳＦＥＴ１０Ｃが製造される。 Next, as a step (S240), a passivation film forming step is performed. In this step (S240), referring to FIG. 16, passivation film 92 made of silicon dioxide (SiO 2 ) is formed on bottom wall surface 90A and side wall surface 90B of first groove 90 by, for example, P (Plasma) -CVD. It is formed so as to cover. Then, after step (S240) is completed, steps (S250) and (S260) are performed in the same manner as steps (S100) and (S110) of the first embodiment, and MOSFET 10C according to the present embodiment is manufactured. The
　今回開示された実施の形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiment disclosed this time is illustrative in all respects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　本発明の炭化珪素半導体装置および半導体モジュールの製造方法は、半導体モジュールの製造歩留まりを向上させることが要求される炭化珪素半導体装置および半導体モジュールの製造方法において、特に有利に適用され得る。また、本発明の炭化珪素半導体装置および半導体モジュールは、半導体モジュールの破損を抑制することが要求される炭化珪素半導体装置および半導体モジュールにおいて、特に有利に適用され得る。 The method for manufacturing a silicon carbide semiconductor device and a semiconductor module of the present invention can be applied particularly advantageously in a method for manufacturing a silicon carbide semiconductor device and a semiconductor module that are required to improve the manufacturing yield of the semiconductor module. In addition, the silicon carbide semiconductor device and the semiconductor module of the present invention can be particularly advantageously applied to a silicon carbide semiconductor device and a semiconductor module that are required to suppress damage to the semiconductor module.
　１　半導体モジュール、２　モジュール基板、２Ａ　表面、３　端子、４　配線、１０　ＭＯＳＦＥＴ、１１，１１Ａ，１１Ｂ　端面、１３　段差部、２０　炭化珪素基板、２０Ａ　主面，接触面、３０　エピタキシャル成長層、３１　ドリフト領域、３２　ボディ領域、３２Ａ　底面、３３　ソース領域、３４　コンタクト領域、４０　酸化膜、５０　ソース電極、６０　ゲート電極、７０　ドレイン電極、８０　素子部、９０　第１溝部、９０Ａ　底壁面、９０Ｂ　側壁面、９１　第２溝部、９２　パッシベーション膜、１００　耐圧測定装置、１１０　気密容器、１１１　窓、１１２　カメラ、１２０　ステージ、１２１　真空チャック、１２２　移動機構、１３０　プローブ、１３１　基部、１３２　針、１３４　電圧源、１３５　ゲート制御部、１４０　導入口、１４１　ゲート弁、１５０　排出口、１６０　ヒータ、１６１　ヒータ電源、１７０　センサ、１７１　読取部、Ａ１　第１領域、Ａ２　第２領域、Ｗ１　幅差、Ｗ２，Ｗ３　幅。 1 semiconductor module, 2 module substrate, 2A surface, 3 terminal, 4 wiring, 10 MOSFET, 11, 11A, 11B end face, 13 stepped portion, 20 silicon carbide substrate, 20A main surface, contact surface, 30 epitaxial growth layer, 31 drift region , 32 body region, 32A bottom surface, 33 source region, 34 contact region, 40 oxide film, 50 source electrode, 60 gate electrode, 70 drain electrode, 80 element part, 90 first groove, 90A bottom wall surface, 90B side wall surface, 91 Second groove part, 92 passivation film, 100 pressure resistance measuring device, 110 airtight container, 111 window, 112 camera, 120 stage, 121 vacuum chuck, 122 moving mechanism, 130 probe, 131 base, 132 needle, 134 voltage source, 135 Gate control unit, 140 inlet, 141 a gate valve, 150 outlet, 160 a heater, 161 a heater power source, 170 sensor, 171 reader, A1 first area, A2 second area, W1 width difference, W2, W3 width.

Claims (12)

  1. 　炭化珪素からなる基板を準備する工程と、
    　前記基板上に複数の素子部を形成する工程と、
    　前記複数の素子部の間に第１溝部を形成する工程と、
    　前記素子部の耐圧を測定する工程と、
    　前記素子部の耐圧を測定する工程の後、前記第１溝部の内部において前記複数の素子部を分離する工程とを備える、炭化珪素半導体装置の製造方法。     Preparing a substrate made of silicon carbide;
    Forming a plurality of element portions on the substrate;
    Forming a first groove portion between the plurality of element portions;
    Measuring the breakdown voltage of the element portion;
    And a step of separating the plurality of element portions inside the first groove portion after the step of measuring the breakdown voltage of the element portion.
  2. 　前記素子部を形成する工程では、前記基板上にエピタキシャル成長層が形成され、
    　前記第１溝部を形成する工程では、前記エピタキシャル成長層から前記基板にまで到達する前記第１溝部が形成される、請求項１に記載の炭化珪素半導体装置の製造方法。     In the step of forming the element portion, an epitaxial growth layer is formed on the substrate,
    2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the first groove portion, the first groove portion reaching from the epitaxial growth layer to the substrate is formed.
  3. 　前記素子部を形成する工程では、前記基板上に導電型が第１導電型であるエピタキシャル成長層が形成され、かつ、前記エピタキシャル成長層内に前記第１導電型と異なる導電型である第２導電型の不純物領域が形成され、
    　前記第１溝部を形成する工程では、前記不純物領域の底部よりも深い位置にまで到達する前記第１溝部が形成される、請求項１に記載の炭化珪素半導体装置の製造方法。     In the step of forming the element portion, an epitaxial growth layer having a conductivity type of the first conductivity type is formed on the substrate, and a second conductivity type having a conductivity type different from the first conductivity type in the epitaxial growth layer. Impurity regions are formed,
    2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the first groove portion, the first groove portion reaching a position deeper than a bottom portion of the impurity region is formed.
  4. 　前記素子部を分離する工程では、前記第１溝部の内部において前記第１溝部よりも幅が小さい第２溝部が形成される、請求項１～３のいずれか１項に記載の炭化珪素半導体装置の製造方法。 The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein in the step of separating the element portion, a second groove portion having a width smaller than that of the first groove portion is formed in the first groove portion. Manufacturing method.
  5. 　前記素子部の耐圧を測定する工程の後、前記素子部を分離する工程の前に、前記第１溝部の壁面上に保護膜を形成する工程をさらに備える、請求項１～４のいずれか１項に記載の炭化珪素半導体装置の製造方法。 5. The method according to claim 1, further comprising a step of forming a protective film on the wall surface of the first groove portion after the step of measuring the breakdown voltage of the element portion and before the step of separating the element portion. A method for manufacturing the silicon carbide semiconductor device according to the item.
  6. 　前記素子部を分離する工程の後、前記複数の素子部のうち良品と不良品とを選別する工程をさらに備える、請求項１～５のいずれか１項に記載の炭化珪素半導体装置の製造方法。 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of selecting a non-defective product and a defective product among the plurality of device portions after the step of separating the device portion. .
  7. 　請求項１～６のいずれか１項に記載の炭化珪素半導体装置の製造方法により炭化珪素半導体装置を製造する工程と、
    　モジュール基板を準備する工程と、
    　前記モジュール基板上に前記炭化珪素半導体装置を実装する工程とを備える、半導体モジュールの製造方法。     A step of manufacturing a silicon carbide semiconductor device by the method of manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6,
    Preparing a module substrate; and
    Mounting the silicon carbide semiconductor device on the module substrate.
  8. 　炭化珪素からなる基板と、
    　前記基板上に形成された素子部とを備え、
    　前記基板および前記素子部の少なくとも一方の端面には、段差部が形成されている、炭化珪素半導体装置。     A substrate made of silicon carbide;
    And an element portion formed on the substrate,
    A silicon carbide semiconductor device, wherein a step portion is formed on at least one end face of the substrate and the element portion.
  9. 　前記段差部から見て前記素子部側の領域である第１領域は、前記段差部から見て前記基板側の領域である第２領域よりも幅が小さい、請求項８に記載の炭化珪素半導体装置。 9. The silicon carbide semiconductor according to claim 8, wherein a width of a first region, which is a region on the element portion side when viewed from the stepped portion, is smaller than a second region which is a region on the substrate side when viewed from the stepped portion. apparatus.
  10. 　前記第１領域における前記端面は、前記第１領域が前記第２領域側に向かって広がるように傾斜している、請求項９に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 9, wherein the end surface in the first region is inclined so that the first region spreads toward the second region.
  11. 　前記端面上に形成された保護膜をさらに備える、請求項８～１０のいずれか１項に記載の炭化珪素半導体装置。 11. The silicon carbide semiconductor device according to claim 8, further comprising a protective film formed on the end face.
  12. 　請求項８～１１のいずれか１項に記載の炭化珪素半導体装置を備える、半導体モジュール。 A semiconductor module comprising the silicon carbide semiconductor device according to any one of claims 8 to 11.
PCT/JP2014/060156 2013-05-16 2014-04-08 Method for manufacturing silicon carbide semiconductor device and semiconductor module, silicon carbide semiconductor device, and semiconductor module WO2014185192A1 (en)

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