JP2004186536A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device, and especially realize the miniaturization of the device, and further provide a method for manufacturing the same. <P>SOLUTION: A conducting channel is provided in a chip side face, and is connected to the source electrode on the chip surface. The chip is bonded immovable to a header by using a conductive adhesive agent, and the conductive adhesive agent rising from the chip side and the conducting channel in the chip side face are connected to each other. Now that connection is established between the source electrode and the header, the source electrode is grounded when the header is made into a GND terminal. External miniaturization is thereby achieved because the design dispenses with a wire bonding area. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same that realize miniaturization of the device.
[0002]
[Prior art]
Field-effect transistors (MOSFETs) can be broadly classified according to whether a current flows in the vertical direction or in the element surface direction. The former is called a vertical element, and the latter is called a horizontal element. The vertical element is often used as an individual element handling particularly high power, because one of the main electrodes is on the back surface of the semiconductor element and has excellent current-carrying capacity per unit area. On the other hand, a horizontal element is suitable for integration because all the electrodes can be arranged on one surface, and is often used as a constituent element of an integrated circuit.
[0003]
FIG. 6 shows a cross-sectional view of a conventional lateral MOSFET. The MOSFET 115 has an n-type source region 103 and an n-type drain region 102 diffused on its surface by a self-alignment (self-alignment) technique to form a channel region on the surface of the p-type substrate 101 immediately below the gate electrode 107. .
[0004]
Both the source region 103 and the drain region 102 are formed by implanting ions into the surface of the substrate 101 and then thermally diffusing them, and are connected to the source electrode 111 and the drain electrode 110, respectively (for example, see Patent Document 1).
[0005]
Next, the operation principle of this MOSFET will be described with reference to FIG. A source terminal S and a drain terminal D are led out from the source electrode and the drain electrode, respectively, and the gate electrode is insulated from the p substrate by a silicon oxide film or the like. Even if a voltage is applied between the drain and the source in this state, no current flows because the two n regions are separated by the p region.
[0006]
When a positive voltage is applied to the gate electrode, electrons, which are negative charges contained in the p-substrate, although small, are attracted to the gate via the insulating film, and the polarity of the semiconductor at the boundary with the insulating film is inverted, so that the channel is An area is formed. As a result, the drain region-substrate-source region is continuous with the n-type semiconductor, and a current flows according to the polarity of the voltage applied between the drain and the source.
[0007]
At this time, if there is a potential difference between the ground potential of the gate and the ground potential of the source,
The cells in the chip operate unevenly, causing an increase in leak current, a decrease in breakdown strength, and the like.
[0008]
[Patent Document 1]
JP-A-11-284187 (Page 2, FIG. 2)
[0009]
[Problems to be solved by the invention]
FIG. 8A illustrates an example of a semiconductor device in which the source electrode 111 and the substrate 101 are short-circuited. As shown in FIG. 6, after forming an element diffusion region and an electrode connected to each region on the wafer, the scribe line 108 is cut and divided into individual MOSFET chips 115.
[0010]
The back surface of each chip 115 is fixed to the header 116a of the lead, and the source pad electrode 111P connected to the source electrode 111 is wire-bonded to the header 116a. The gate pad electrode 107P connected to the gate electrode 107 is wire-bonded to the lead 116b serving as a gate terminal, and the drain pad electrode 110P connected to the drain electrode is wire-bonded to the lead 116c serving as a drain terminal.
[0011]
By connecting the source electrode having the GND potential to this header, the potential difference between the ground potential of the gate and the ground potential of the source is eliminated, and the MOSFET cell operates uniformly.
[0012]
In the wire bonding, bonding is performed by carrying the bonding wire 118 onto the chip 115 by the capillary 150. As shown in FIG. 8B, the tip of the capillary 150 has a diameter φ of, for example, about 200 μm. For example, in the case of source wire bonding, the bonding wire 118 is fixed to the chip 115 and then moved to the header 116 a to fix the wire. I do. At this time, if the capillary 150 comes into contact with the chip 115, the chip 115 is destroyed, and this contact must be avoided. Therefore, a space of about 400 μm square is required as the wire bond area 130 in the header 116a.
[0013]
However, at present, the miniaturization of the chip is progressing, and the chip size of the small one is shrinking to 0.3 mm square. Securing the wire bond area 130 of about 400 μm square on the header in such a chip is a major factor in preventing the miniaturization of the external shape from proceeding.
[0014]
[Means for Solving the Problems]
The present invention has been made in view of the above problem, and firstly, an element region provided on a surface of a semiconductor substrate, a plurality of electrodes connected to the element region, and connected to at least one of the electrodes provided on a side wall of the substrate. The problem is solved by having a semiconductor chip including a conductive path and a lead for fixing the chip, exposing a conductive adhesive for fixing the chip from an end of the chip and connecting the conductive path. is there.
[0015]
Second, a source region and a drain region of the opposite conductivity type provided on the surface of the one conductivity type substrate, a source electrode and a drain electrode contacting the source region and the drain region, and a substrate surface between the source region and the drain region A semiconductor chip including a gate electrode provided through an insulating film, a conductive path provided on a side surface of the substrate and connected to the source electrode, and a lead for fixing the chip, and fixing the chip. This problem is solved by exposing a conductive adhesive from an end of the substrate and connecting the conductive path to the conductive path.
[0016]
Further, the lead is applied with a GND potential.
[0017]
The conductive path is formed by attaching a conductive material to the side surface of the chip.
[0018]
Further, the conductive path is an impurity diffusion region provided on a side surface of the chip.
[0019]
Third, a step of forming an element diffusion region on the substrate, a step of forming a groove on a scribe line of the substrate, and forming a conductive path covering the inner wall of the groove and connecting to a part of the element diffusion region And a step of cutting the scribe line, fixing individual semiconductor chips to leads with a conductive adhesive, and connecting the conductive adhesive exposed from the chip end to the conductive path. Is what you do.
[0020]
The groove is formed by anisotropic etching to a depth that does not reach the back surface of the substrate.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5, taking an n-channel MOSFET chip as an example.
[0022]
The semiconductor device of the present invention includes a MOSFET chip 15 having a conductive path 12 on a side wall, a lead 16 and a conductive adhesive 17 as shown in FIG.
[0023]
As shown in FIG. 1B, the MOSFET chip 15 has a substrate 1 of one conductivity type, a source region 3 and a drain region 2, a source electrode 11 and a drain electrode 10, a gate electrode 7, and a conductive path 12.
[0024]
The substrate 1 is a p-type semiconductor substrate, on which a source region 3 and a drain region 2 are provided by diffusing an n-type impurity by a known method. Source electrode 11 and drain electrode 10 are in contact with source region 3 and drain region 2.
[0025]
The gate electrode 7 is provided on the surface of the substrate 1 between the source region 3 and the drain region 2 via the gate insulating film 6. By applying a voltage to the gate electrode 7, a channel region is formed on the substrate surface between the source region 3 and the drain region 2 immediately below the gate electrode 7.
[0026]
The source electrode 11 and the drain electrode 10 are arranged in a shape in which the comb teeth are engaged, and the gate electrode 7 is arranged between the respective comb teeth. The semiconductor material (for example, polysilicon) forming the gate electrode 7 extends outside the element diffusion region 20 and connects to the gate pad electrode 7P, and the drain electrode 10 also extends to the drain pad electrode 10P outside the element region 20. Connected. The source electrode 11 extends from the element diffusion region and is patterned so as to substantially surround the outer periphery of the element diffusion region 20.
[0027]
The conductive path 12 is provided on each side surface of the MOSFET chip 15 having the above-described components. After forming the element diffusion region 20 in the state of a wafer, it is provided using a scribe line when dividing into individual chips 15 by dicing. The conductive path 12 is a region in which a conductive material such as a metal or polysilicon doped with impurities is adhered to the side surface of the chip 15 or a region where a high concentration impurity is diffused to the side surface of the chip 15. Since the conductive path 12 is a substitute for a wire bond for setting the source electrode 11 to the GND potential, the conductive path 12 is connected to the source electrode 11 extending around the outer periphery of the chip 15, and at least one line is provided along the side surface of the chip 15. Preferably, a plurality is arranged. In order for the GND potential of the entire chip 15 to be uniform, it is desirable to provide the GND potential evenly from the entire periphery.
[0028]
The conductive path 12 does not reach the back surface of the chip 15 due to the manufacturing process of the semiconductor device, which will be described later. That is, it is provided on the side surface of the chip 15 extending from the front surface of the chip 15 and 20 μm to 50 μm above the back surface of the chip.
[0029]
Further, the MOSFET chip 15 is mounted on the header 16a of the lead 16 as shown in FIG. 1A, and the back surface of the chip 15 is fixed to the header 16a by a conductive adhesive 17 such as solder or epoxy resin.
[0030]
At this time, the conductive adhesive 17 protrudes from the fixing region of the chip 15 and rises to the chip end by about 20 μm to 50 μm to be fixed. As a result, the conductive path 12 provided on the side surface of the chip 15 comes into contact, and the source electrode 11 on the surface of the chip 15 is connected to the header 16a. That is, the source electrode 11 and the header 16a can be connected without using a wire bond.
[0031]
FIG. 2 shows a plan view in which the chip 15 is mounted.
[0032]
The chip is fixed to the header 16a as described above, and the source electrode 11 and the header 16a are connected through the conductive path 12. The gate pad electrode 7P is connected to the lead 16b serving as the gate terminal G by a bonding wire, and the drain pad electrode 10P is connected to the lead 16c serving as the drain terminal D by a bonding wire. The header 16 a is a source terminal S, to which a GND potential is applied as before, and a GDN potential is applied to the source electrode 11. Further, it is molded with the resin layer 19 and the like to obtain a finished product.
[0033]
Conventionally, as shown in FIG. 8A, the source electrode 11 and the header 16a are connected by the bonding wire 118 and the capillary 150 is used. Therefore, it is necessary to secure a space of about 400 μm square as a wire bond region on the header. , Which hindered the miniaturization of the external shape. However, according to the present embodiment, it is only necessary to secure a minimum area necessary for fixing the chip, the outer shape can be largely shrunk, and there is an advantage that it can be mounted on a small outer shape.
[0034]
Further, the bonding wire of the source electrode 11 is not required, and the cost can be reduced.
[0035]
Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 3 to 5, taking an n-channel MOSFET chip as an example.
[0036]
The method of manufacturing a semiconductor device according to the present invention includes a step of forming an element diffusion region 20 on a substrate, a step of forming a groove 9 on a scribe line 8 of the substrate, and a part of the element diffusion region 20 covering an inner wall of the groove 9. Forming a conductive path 12 connected to the semiconductor chip, cutting the scribe line 8 to separate the semiconductor chip 15 into individual semiconductor chips 15, and fixing the semiconductor chip 15 to a lead 16 with a conductive adhesive 17 to form a conductive path 12 and a conductive path. Connecting the adhesive 17.
[0037]
First step (FIG. 3A): a step of forming the element diffusion region 20 on the substrate 1 by a known method.
[0038]
First, the p-type silicon semiconductor substrate 1 is oxidized at about 800 ° C., and a gate oxide film 6 having a thickness of about several hundred degrees is formed by a driving voltage. Next, polysilicon is deposited on the gate oxide film 6 to reduce the resistance by introducing impurities, and is left on the gate oxide film 6 between the planned source region 3 and the planned drain region 2. The gate electrode 7 is formed by patterning. Further, the entire surface is thermally oxidized to cover the gate electrode 7 with the gate oxide film 6.
[0039]
After that, the oxide film on both ends of the gate electrode 7 is removed to expose the semiconductor substrate 1, and an n-type impurity is ion-implanted and then thermally diffused to form the source region 3 and the drain region 2. Preferably, a p + -type region 4 is provided around the source region 3 so that a channel region formed immediately below the gate electrode 7 is grounded at the same potential as the source electrode 11. An annular element 5 for reducing the resistance is formed, and an element diffusion region 20 of the MOSFET is formed.
[0040]
Second step (FIG. 3B): a step of forming a groove 9 on the scribe line 8 of the substrate 1.
[0041]
A groove 9 is formed on the scribe line 8 to form the conductive path 12. A region other than the groove 9 is masked, and the groove 9 is formed substantially perpendicular to the surface of the substrate 1 by anisotropic etching using plasma. The groove 9 is formed at a depth of 20 μm to 50 μm above the rear surface so as not to reach the rear surface of the substrate 1 because chips are individually separated when reaching the rear surface of the substrate 1 and the subsequent steps become complicated. The groove 9 becomes a conductive path 12 in a later step. 20 μm to 50 μm above the back surface is the distance required for the conductive adhesive to swell from the end of the chip 15 to the side surface of the chip 15 and connect to the conductive path 12. This is because the contact with the agent may be poor, and if a groove is formed below (deeply) below 20 μm, the strength of the wafer cannot be maintained in the subsequent manufacturing process.
[0042]
Further, isotropic etching using a mixed solution of hydrofluoric acid and nitric acid may be used. However, in the case of isotropic etching, etching proceeds in the horizontal direction at the same length as the depth direction, so that a groove of 100 μm is formed. In that case, a scribe line of 200 μm is required. Since the scribe line is generally about 100 μm to 150 μm, it depends on the thickness of the wafer (usually about 100 μm to 400 μm), but if a deep groove is to be formed, anisotropic etching is preferable.
[0043]
Third step (FIG. 3C): a step of forming a conductive path 12 that covers the inner wall of the groove 9 and is connected to a part of the element diffusion region 20.
[0044]
A source electrode 11 and a drain electrode 10 that are in contact with the source region 3 and the drain region 2 are formed by, for example, sputtering metal on the entire surface. At the same time, a conductive path 12 is formed on the inner wall of the groove 9. The source electrode 11 extending from the element diffusion region 20 so as to surround the outer periphery thereof and the conductive path 12 on the inner wall of the trench 9 are formed using a patterned mask having a desired shape. The drain pad electrode 10P is also patterned at the same time.
[0045]
Here, as shown in FIGS. 4A and 4B, the conductive path 12 is not limited to metal but may be polysilicon 12a doped with impurities. Polysilicon 12a is deposited so as to cover the inner wall of groove 9, drain electrode 10 and source electrode 11 are formed, and source electrode 11 and conductive path 12 are connected.
[0046]
Further, as shown in FIGS. 4C and 4D, the conductive path 12 may be a region having high conductivity by injecting and diffusing a high concentration impurity into the inner wall of the groove. In this case, after forming the groove 9, the impurity diffusion region 12b is formed on at least the side wall of the groove 9 by oblique ion implantation or the like. Thereafter, a drain electrode 10 and a source electrode 11 are formed, and the source electrode 11 and the conductive path 12 are connected.
[0047]
Fourth step (FIG. 5): scribe line 8 is cut and separated into individual semiconductor chips 15, semiconductor chip 15 is fixed to leads 16a by conductive adhesive 17, and conductive paths 12 and conductive adhesive 17 are connected. Process.
[0048]
The remaining scribe lines 8 are cut and separated into individual semiconductor chips 15 (FIG. 5A). In this state, as shown in FIG. 1 or FIG. 5B, a plurality of conductive paths 12 connected to the source electrode 11 on the chip surface extend on the chip side surface. Next, the individual semiconductor chips 15 are fixed to the lead headers 16a in the assembling process. For fixing, a conductive adhesive 17 such as solder or epoxy resin is used, and an amount of about 30 μm in thickness is supplied and fixed. As a result, the conductive adhesive 17 bulges from the end of the chip 15 to the side surface of the chip 15 and is fixed, and comes into contact with the conductive path 12. As described above, since the conductive path 12 is provided at a depth of 20 μm to 50 μm above the chip back surface, the height is sufficient to make contact with the conductive adhesive 17. Accordingly, the source electrode 11 and the header can be connected without using a bonding wire, and it is not necessary to secure a wire bond area.
[0049]
Further, the lead 16b serving as the gate terminal G and the gate pad electrode 7P are connected to the lead 16c serving as the drain terminal D and the drain pad electrode 10P by bonding wires 18, respectively. Get.
[0050]
【The invention's effect】
According to the present invention, a space of about 400 μm square required for wire bonding between a source electrode and a header can be omitted. Although the conventional structure for securing the wire bond area has not been able to reduce the outer shape even if the chip has been miniaturized, according to the present invention, only the chip fixing region is sufficient, and the outer shape can be significantly reduced.
[0051]
Further, since a bonding wire for the source electrode is not required, there is an advantage that the cost can be reduced.
[Brief description of the drawings]
FIGS. 1A and 1B are a perspective view and a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 2 is a plan view illustrating a semiconductor device of the present invention.
FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.
FIG. 6 is a cross-sectional view illustrating a conventional semiconductor device.
FIG. 7 is a conceptual diagram illustrating a semiconductor device of the related art and the present invention.
8A and 8B are a plan view and a side view illustrating a conventional semiconductor device.
[Explanation of symbols]
Reference Signs List 1 semiconductor substrate 2 drain region 3 source region 4 P + type region 5 annular 6 gate insulating film 7 gate electrode 7P gate pad electrode 8 scribe line 9 groove 10 drain electrode 10P drain pad electrode 11 source electrode 12 conductive path 12a polysilicon 12b impurity diffusion Region 15 Semiconductor chip 16 Lead 16a Header 16b Lead 16c Lead 18 Bonding wire 19 Resin layer 20 Element diffusion region 101 Semiconductor substrate 102 Drain region 103 Source region 104 P + type region 105 Annular 106 Gate insulating film 107 Gate electrode 107P Gate pad electrode 108 Scribe Line 110 Drain electrode 110P Drain pad electrode 111 Source electrode 111P Source pad electrode 115 Semiconductor chip 116 Lead 116a Header 11 6b Lead 116c Lead 118 Bonding wire 119 Resin layer 120 Element diffusion region 130 Wire bond region 120 Capillary

Claims (7)

An element region provided on the surface of the semiconductor substrate;
A plurality of electrodes connected to the element region,
A semiconductor chip comprising a conductive path provided on the substrate side wall and connected to at least one of the electrodes;
A lead for fixing the chip,
A semiconductor device, wherein a conductive adhesive for fixing the chip is exposed from an end of the chip and connected to the conductive path. A source region and a drain region of the opposite conductivity type provided on the surface of the one conductivity type substrate,
A source electrode and a drain electrode that are in contact with the source region and the drain region,
A gate electrode provided on a substrate surface between the source region and the drain region via an insulating film;
A semiconductor chip comprising a conductive path provided on a side surface of the substrate and connected to the source electrode;
A lead for fixing the chip,
A semiconductor device, wherein a conductive adhesive for fixing the chip is exposed from an end of the substrate and connected to the conductive path. The semiconductor device according to claim 1, wherein a GND potential is applied to the lead. 3. The semiconductor device according to claim 1, wherein the conductive path is formed by attaching a conductive material to a side surface of the chip. The semiconductor device according to claim 1, wherein the conductive path is an impurity diffusion region provided on a side surface of the chip. Forming an element diffusion region on the substrate;
Forming a groove on a scribe line of the substrate;
Forming a conductive path covering the groove inner wall and connecting to a part of the element diffusion region;
A step of cutting the scribe line, fixing individual semiconductor chips to leads with a conductive adhesive, and connecting the conductive adhesive exposed from an end of the chip to the conductive path. Device manufacturing method. 7. The method according to claim 6, wherein the groove is formed by anisotropic etching to a depth that does not reach the back surface of the substrate.

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