JP2020068298A - Semiconductor package, mounting board and electronic equipment - Google Patents

Abstract

To provide a technique advantageous for mounting a semiconductor package having a large number of pins and a high density of pins.SOLUTION: A semiconductor package is provided that houses a semiconductor chip, the semiconductor package comprises a facing surface facing a wiring board, and one or more first terminals and one or more first wiring patterns connected to the first terminals are arranged on the facing surface, and when the semiconductor package is mounted on the wiring board, the first wiring pattern intersects a second wiring pattern arranged on the surface of the wiring board facing the semiconductor package in an orthogonal projection to the facing surface, and is electrically insulated from the second wiring pattern.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor package, a mounting board, and an electronic device.

  As the number of pins in a semiconductor package increases and the density of pins increases, the wiring density of a wiring board on which a semiconductor package having a higher number of pins and higher density of pins (sometimes referred to as a high-density package) is mounted increases. However, it is becoming difficult to secure a wiring space immediately below and around the high-density package. Patent Document 1 discloses that a package surface wiring is formed on the package surface of a semiconductor package.

JP, 2003-101186, A

  In order to secure the wiring space of the wiring board accompanying the mounting of the high-density package, it is necessary to suppress an increase in the manufacturing cost such as an increase in the design cost of the wiring pattern and a further multilayered wiring board. In the configuration disclosed in Patent Document 1, the package surface wiring can be connected to the wiring board only at the outer edge of the semiconductor package, and the degree of freedom in designing the wiring pattern of the wiring board can be limited.

  It is an object of the present invention to provide a technique that is advantageous for mounting a semiconductor package having a large number of pins and a high density of pins.

  In view of the above problems, a semiconductor package according to an embodiment of the present invention is a semiconductor package in which a semiconductor chip is housed, and the semiconductor package has a facing surface facing the wiring board, and one or more facing surfaces are provided. The first terminal and one or more first wiring patterns connected to the first terminal are arranged, and when the semiconductor package is mounted on the wiring board, the first wiring pattern has a facing surface. In the orthogonal projection, the wiring board intersects with the second wiring pattern arranged on the surface of the wiring board facing the semiconductor package, and is electrically insulated from the second wiring pattern.

  The above-mentioned means provides a technique advantageous for mounting a semiconductor package having a large number of pins and a high density of pins.

The figure which shows the structural example of the semiconductor package which concerns on embodiment of this invention. The figure which shows the structural example of the semiconductor package which concerns on embodiment of this invention. The figure which shows the structural example of the semiconductor package which concerns on embodiment of this invention. The figure which shows the structural example of the semiconductor package which concerns on embodiment of this invention.

  Hereinafter, specific embodiments of a semiconductor package according to the present invention will be described with reference to the accompanying drawings. Each drawing is only a schematic drawing described for the purpose of explaining the structure or configuration, and the dimensions of each member shown in the drawings do not necessarily reflect the actual size. Further, in the following description and drawings, common reference numerals are given to common configurations over a plurality of drawings. Therefore, common configurations will be described with reference to a plurality of drawings, and description of configurations having common reference numerals will be appropriately omitted.

  A semiconductor package according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing a configuration example of a mounting board 250 in which the semiconductor package 100 of the present embodiment is mounted on a wiring board 200.

  As shown in FIGS. 1A and 1B, the semiconductor package 100 accommodates a semiconductor chip 150 inside the semiconductor package 100. The semiconductor package 100 also includes a facing surface 101 that faces the wiring board 200. On the facing surface 101 of the semiconductor package 100, one or more terminals 111 and one or more wiring patterns 121 connected to the terminals 111 are arranged.

  The terminals 111 may be terminals that are electrically insulated from the semiconductor chip 150 before the semiconductor package 100 is mounted on the wiring board 200. In other words, the terminal 111 may be a terminal that is not electrically connected to the semiconductor chip 150 housed inside the semiconductor package 100 via a conductor or the like that penetrates the facing surface 101 of the semiconductor package 100. In addition, when the semiconductor package 100 is mounted on a wiring board, the terminal 111 may or may not be connected to the semiconductor chip 150 via any wiring pattern.

  As shown in FIGS. 1A and 1B, the wiring pattern 121 is provided on the semiconductor package 100 of the wiring board 200 in an orthogonal projection to the facing surface 101 when the semiconductor package 100 is mounted on the wiring board 200. The wiring pattern 222 arranged on the facing surface 201 intersects. In other words, the wiring pattern 121 and the wiring pattern 222 partially overlap each other in the orthogonal projection on the facing surface 101. The wiring pattern 121 is electrically insulated from the wiring pattern 222. Here, when the semiconductor package 100 is mounted on the wiring board 200, as shown in FIGS. 1A and 1B, the semiconductor package 100 is mounted on the surface 201 of one wiring board 200. It is not limited to implementation. For example, the case where the semiconductor package 100 is built in a multilayer board such as a multilayer board in which another wiring board is laminated on the wiring board 200 on which the semiconductor package 100 is mounted. Good.

  Here, as shown in FIGS. 1A and 1B, the wiring pattern 121 may be a wiring pattern that electrically connects the terminals 111 to each other. Further, the terminal 111 may be connected to the terminal 211 arranged on the surface 201 of the wiring board 200 facing the semiconductor package 100. That is, the wiring pattern 121 may connect the wiring patterns 221 arranged on the surface 201 of the wiring board 200 so as to straddle the wiring pattern 222 arranged on the surface 201 of the wiring board 200. This eliminates the need to intersect the wiring pattern 221 and the wiring pattern 222 by using another layer of the wiring board 200. There is a margin in securing the wiring space of wiring board 200, the degree of freedom in designing the wiring pattern is improved, and further multilayering of wiring board 200 can be suppressed.

  As shown in FIG. 1A, the wiring pattern 121 may be arranged inside the outer edge of the facing surface 101 of the semiconductor package 100. Further, as shown in FIG. 1B, the wiring pattern 121 may pass through the upper surface 102 of the semiconductor package 100 on the side opposite to the facing surface 101. FIG. 1A shows only the wiring pattern 121 arranged on the facing surface 101 of the semiconductor package 100, and FIG. 1B shows only the wiring pattern 121 passing through the upper surface 102 of the semiconductor package 100. Has been done. However, the present invention is not limited to this, and even if one semiconductor package 100 is provided with the wiring pattern 121 arranged inside the outer edge of the facing surface 101 and the wiring pattern 121 passing through the upper surface 102. Good.

  Further, as shown in FIG. 1B, in the wiring pattern 121a that passes through the upper surface 102 of the wiring pattern 121, at least a part of the portion arranged on the upper surface 102 has the width of the wiring pattern other than that. It may be wider than the part. When the semiconductor package 100 is mounted on the wiring board 200, the wiring pattern 121a may be connected to the ground terminal of the mounting substrate 250 via the terminals 111 and 211. Accordingly, the wiring pattern 121a may function as a shield layer against noise output from the semiconductor chip 150 housed in the semiconductor package 100 or incident on the semiconductor chip 150.

  Further, in the semiconductor package 100, as shown in FIG. 2A, on the facing surface 101, one or more terminals 113, terminals 112 electrically connected to the semiconductor chip 150, terminals 113 and terminals 112. And a wiring pattern 122 for connecting to and may be arranged. Here, the terminal 112 is a terminal electrically connected to the semiconductor chip 150 housed inside the semiconductor package 100 via a conductor or the like penetrating the facing surface 101 of the semiconductor package 100. On the other hand, the terminal 113 is a terminal that is not electrically connected to the semiconductor chip 150 without the wiring pattern 122 before the semiconductor package 100 is mounted on the wiring board 200. The wiring pattern 122 may intersect with the wiring pattern 222 arranged on the surface 201 of the wiring board 200 like the wiring pattern 122a, or may not intersect with the wiring pattern 222 like the wiring pattern 122b. Good. That is, the wiring pattern 122 may partially overlap the wiring pattern 222 arranged on the surface 201 of the wiring board 200, or may not overlap. The wiring pattern 122 may be electrically insulated from the wiring pattern 222 when the semiconductor package 100 is mounted on the wiring board 200. Here, the terminals 111, 112, and 113 may be terminals intended to be connected to the terminal 211 or the like provided on the wiring board 200. In addition, for example, the terminals 111, 112, and 113 may be portions that are wider than the wiring patterns 121, 122, and 123 at the ends of the wiring patterns 121, 122, and 123.

  As shown in FIG. 2A, the wiring pattern 122 may be arranged inside the outer edge of the facing surface 101 of the semiconductor package 100. In addition, the wiring pattern 122 may include a wiring pattern that passes through the upper surface 102 of the semiconductor package 100 on the side opposite to the facing surface 101, as shown in FIG. 2B.

  Further, as shown in FIG. 2B, the wiring pattern 123 for connecting the terminals 112 connected to the semiconductor chip 150 before the semiconductor package 100 is mounted on the wiring pattern 122 is arranged on the semiconductor package 100. May be. The wiring pattern 123 may be arranged inside the outer edge of the facing surface 101, as shown in FIG. 2B, or may be a wiring pattern that passes through the upper surface 102, which will be described later.

  As shown in FIGS. 2A and 2B, wiring patterns 122 and 123 are arranged on the semiconductor package 100. As a result, there is a margin in securing the wiring space with respect to the securing of the wiring space of the wiring board accompanying the mounting of the high-density semiconductor package, and it becomes possible to improve the degree of freedom in designing the wiring pattern.

  Another arrangement example of the terminals 111, 112, 113 and the wiring patterns 121, 122, 123 arranged in the semiconductor package will be further described with reference to FIGS. The semiconductor package 300 shown in FIG. 3 is an example of a BGA (Ball Grid Array) package. The semiconductor package 400 shown in FIGS. 4A to 4C is an example of a QFN (Quad Flat No lead package). 1 (a) and 1 (b) described above shows the semiconductor package 100 in which the terminals 111 and the wiring patterns 121 are arranged, and FIGS. 2 (a) and 2 (b) shows the terminals 112 and 113 and wiring. The semiconductor package 100 in which the patterns 122 and 123 are arranged is shown, respectively. However, the present invention is not limited to this, and the terminals 111, 112, 113 and the wiring patterns 121, 122, 123 may be arranged in combination in one semiconductor package.

  As shown in FIG. 3, one or more terminals 111 electrically insulated from the semiconductor chip 150 and the semiconductor chip 150 are electrically connected to the facing surface 101 of the semiconductor package 300 facing the wiring board. A plurality of terminals 112 are arranged. In addition, one or more terminals 113 electrically connected to the semiconductor chip 150 via the wiring pattern 122 are arranged on the facing surface 101. The terminal 112 is a terminal formed of a conductor penetrating the facing surface 101 of the semiconductor package 300 in the BGA package.

  The wiring pattern 121 connecting the terminals 111 to each other may be a linear wiring pattern such as the wiring pattern 121b shown in FIG. Further, the wiring pattern 121 may be provided with a meander pattern for equalizing the electrical wiring length in consideration of signal delay and the like, like the wiring pattern 121c shown in FIG. Since the meander pattern, which requires a large wiring space, is arranged on the semiconductor package 100, there is a margin in the wiring space of the wiring board 200.

  The wiring pattern 122 for connecting any one of the plurality of terminals 112 to the terminal 113 is, as shown in FIG. 3, in the orthogonal projection to the facing surface 101, the terminal arranged at the outermost edge of the plurality of terminals 112. The wiring patterns 122c and 122d arranged inside are included. The wiring pattern 122 may include a meander pattern like the wiring pattern 122d. Further, the wiring pattern 122 is, in the orthogonal projection to the facing surface 101, a portion arranged between the terminal arranged at the outermost edge of the plurality of terminals 112 and the outer edge of the facing surface 101, as shown in FIG. 3. Wiring patterns 122e and 122f having Here, the region between the terminal 112 arranged at the outermost edge and the outer edge of the facing surface 101 is a line connecting the points farthest from the center of the facing surface 101 of the outermost terminals of the plurality of terminals 112. And the outer edge of the facing surface 101.

  In the wiring pattern 123 that connects the terminals 112 to each other, as in the wiring pattern 123a shown in FIG. 3, at least a part of the wiring pattern may be wider than the other parts. For example, the wiring pattern 123a is arranged to radiate the heat generated in the semiconductor chip 150 housed in the semiconductor package 300. Therefore, the area of the wiring pattern 123a in the orthogonal projection with respect to the facing surface 101 may be, for example, 10 times or more, or 20 times or more the area of each of the terminals 111 to 113. Here, the area of each of the terminals 111 to 113 may be an average value of the area of each of the terminals 111 to 113 in the orthogonal projection to the facing surface 101, or may be the largest of the terminals 111 to 113. It may be the area. Further, the wiring pattern 123a may be connected to the ground terminal among the plurality of terminals 112. Accordingly, the wiring pattern 123a may function as a shield layer against noise output from the semiconductor chip housed in the semiconductor package 300 or incident on the semiconductor chip.

  Although not shown in FIG. 3, even if the wiring patterns 121 and 123 have a portion arranged between the outermost terminal of the plurality of terminals 112 and the outer edge of the facing surface 101. Good. In addition, at least a part of the wiring patterns 121 and 122 may have a width wider than that of the other parts. Furthermore, the wiring pattern 123 may include a meander pattern.

  In this way, the semiconductor package 300 mounted on the wiring board 200 arranges the wiring patterns 121 to 123. As a result, even if the semiconductor package 300 has a large number of pins and a high density, there is a margin in securing the wiring space of the wiring board 200, the degree of freedom in designing the wiring pattern is improved, and the wiring board 200 is further improved. Multiple layers can be suppressed. In addition, the terminals 111 and 113 for connecting to the terminals of the wiring board 200 can be arranged in a wide range on the facing surface 101 of the semiconductor package 100 except a place where the terminals 112 connected to the semiconductor chip 150 are arranged. Therefore, the degree of freedom in designing the wiring pattern of wiring board 200 is improved as compared with the structure disclosed in Patent Document 1. As described above, in the orthogonal projection on the facing surface 101, the wiring patterns 121 to 123 and the wiring pattern 222 arranged on the surface 201 of the wiring board 200 may include an overlapping portion. Thereby, the two conductive layers of the wiring board 200 can be used, and the portions where the respective conductor patterns 301 must intersect can be suppressed, so that a wiring space is secured and the wiring board 200 is prevented from being multilayered. Easier to do.

  Here, the wiring patterns 121 to 123 may be formed at the same time when the terminals 111 and 113 are formed. Therefore, the terminals 111 and 113 may be formed of the same material as the wiring patterns 121 to 123. Further, the thickness of the terminals 111 and 113 from the facing surface 101 and the thickness of the wiring patterns 121 to 123 from the facing surface 101 may be the same.

  Next, the terminals 111 to 113 and the wiring patterns 121 to 123 arranged in the QFN semiconductor package 400 shown in FIGS. 4A to 4C will be described. In the semiconductor package 400, the wiring patterns 122 and 123 are formed not only on the facing surface 101 of the semiconductor package 400 but also on the upper surface 102 on the side opposite to the facing surface 101 and on the side surface 103 between the facing surface 101 and the upper surface 102. There is. Although the terminals 111 and the wiring patterns 121 are omitted in FIGS. 4A to 4C, the terminals 111 and the wiring patterns 121 may be arranged as described above.

  Like the wiring pattern 123b shown in FIGS. 4A and 4B, the wiring pattern 123 extends from the terminal 112 to the upper surface 102 of the semiconductor package 100 opposite to the upper surface 102 through the side surface 103. Good. As shown in FIG. 4A, the wiring pattern 123a may connect two or more terminals 112 to each other. Further, as shown in FIG. 4A, the width of the wiring pattern may be wider than the other portions in at least a part of the upper surface 102 of the wiring pattern 123a. For example, the wiring pattern 123b is arranged to dissipate heat generated by the semiconductor chip 150 housed in the semiconductor package 400. Therefore, the area of the wiring pattern 123b is, for example, 10 times or more, 20 times or more, or 50 times or more of the area of each of the terminals 111 to 113 in the orthogonal projection to the facing surface 101. Good. Here, the area of each of the terminals 111 to 113 may be an average value of the area of each of the terminals 111 to 113 in the orthogonal projection to the facing surface 101, or may be the largest of the terminals 111 to 113. It may be the area. The portion of the wiring pattern 123b where the wiring width is wide is disposed on the upper surface 102 of the semiconductor package 400. Therefore, it is possible to radiate heat more efficiently than the wiring pattern 123a arranged on the facing surface 101 of the semiconductor package 300 described above. The wiring pattern 123b may be connected to the ground terminal of the plurality of terminals 112. Accordingly, the wiring pattern 123b may function as a shield layer against noise output from the semiconductor chip 150 housed in the semiconductor package 400 or incident on the semiconductor chip 150.

  Further, the semiconductor package 400 further includes a terminal 114 arranged on the upper surface 102 opposite to the facing surface 101, and a wiring pattern 124 for electrically connecting any one of the plurality of terminals 112 to the terminal 114. You may have it. The terminal 114 may be used to contact the probe when checking the operation of the semiconductor chip 150 mounted on the semiconductor package 400, for example. By disposing the terminals 114 on the upper surface 102 of the semiconductor package 400, it is not necessary to dispose terminals for checking the operation of the semiconductor chip 150 on the wiring board 200.

  The area of the terminal 114 may be larger than the area of each of the terminals 111 to 113. Here, the area of each of the terminals 111 to 113 may be an average value of the area of each of the terminals 111 to 113 in the orthogonal projection to the facing surface 101, or may be the largest of the terminals 111 to 113. It may be the area. By enlarging the terminal 114, a user who checks the operation of the semiconductor chip 150 can easily contact the probe. Further, it becomes possible to radiate the heat generated in the semiconductor chip 150 housed in the semiconductor package 400.

  The wiring pattern 124 and the terminal 114 may be simultaneously formed by plating or printing. Therefore, the wiring pattern 124 and the terminal 114 may be formed of the same material. The wiring patterns 124 and the terminals 114 may have the same thickness from the upper surface 102. The wiring pattern 124 and the terminal 114 may be formed of the same material as the wiring patterns 121 to 123 or the like, or may be formed to have the same thickness.

  Further, the wiring pattern 123 may be arranged inside the outer edge of the facing surface 101 of the semiconductor package 400, as in the wiring pattern 123c shown in FIG. As shown in FIG. 4C, the semiconductor package 400 may include a wiring pattern 122 arranged inside the outer edge of the facing surface 101. The wiring pattern 122 may include a meander pattern like the wiring pattern 122g.

  In the semiconductor package 400, as in the case of the semiconductor packages 100 and 300 described above, even when the semiconductor package 400 has a large number of pins and a high density, there is a margin in securing a wiring space of the wiring board 200, and a wiring pattern is formed. The degree of freedom in design can be improved.

  As shown in FIGS. 1A to 2B, the semiconductor packages 100, 300 and 400 are mounted on the surface 201 of the wiring board 200. The terminals 111 to 113 are appropriately connected to the terminals 211 arranged on the surface 201 of the wiring board 200 facing the semiconductor packages 100, 300, 400. Wiring board 200 may be a rigid wiring board or a flexible wiring board.

  Further, another terminal or wiring pattern may be provided between the semiconductor package 100, 300, 400 and the surface 201 of the wiring board 200. The wiring patterns 221 and 222 provided on the surface 201 of the wiring board 200 pass through the terminals and wiring patterns arranged between the semiconductor packages 100, 300 and 400 and the surface 201 of the wiring board 200, and the semiconductor package 100. , 300, 400 may be connected to the semiconductor chip 150 housed inside. Further, even if terminals and wiring patterns arranged between the semiconductor packages 100, 300 and 400 and the surface 201 of the wiring board 200 intersect with the wiring patterns 221 and 222 provided on the surface 201 of the wiring board 200. Good.

The mounting board 250 including the wiring board 200 on which the semiconductor packages 100, 300, 400 are mounted may be assembled in various electronic devices such as a camera, a display, a personal computer, a printer, and an image sensor. The semiconductor packages 100, 300, and 400 shown in this embodiment improve the degree of freedom in designing the wiring pattern of the wiring board 200, and can suppress the design cost and the manufacturing cost. As a result, in an electronic device in which the mounting board 250 including the wiring board 200 on which the semiconductor packages 100, 300, 400 are mounted is assembled, the flexibility of designing the wiring board 200 is improved, and the performance is improved and the manufacturing cost is reduced. Suppression is realized.

  Although the embodiments and examples according to the present invention have been described above, it goes without saying that the present invention is not limited to these embodiments and examples, and the embodiments described above are included without departing from the gist of the present invention. Can be appropriately changed and combined. For example, in the above, the BGA package and the QFN are shown as examples of the semiconductor package, but the present invention is not limited to this. For example, the present invention can be applied to various packages such as a QFP (Quad Flat Package) in which a terminal (terminal 112) connected to the semiconductor chip 150 is arranged on the side surface 103 of the semiconductor package. Further, it is needless to say that the individual terms described in the present specification are merely used for the purpose of explaining the present invention, and the present invention is not limited to the strict meaning of the terms. The equivalent may be included.

100, 300, 400: semiconductor package, 111-114: terminal, 121-124: wiring pattern

Claims (11)

A semiconductor package containing a semiconductor chip,
The semiconductor package has a facing surface facing the wiring board,
One or more first terminals and one or more first wiring patterns connected to the first terminals are arranged on the facing surface,
When the semiconductor package is mounted on the wiring board, the first wiring pattern and a second wiring pattern arranged on a surface of the wiring board facing the semiconductor package in an orthogonal projection to the facing surface. A semiconductor package, which intersects and is electrically insulated from the second wiring pattern.   The semiconductor package according to claim 1, wherein the first terminal is electrically insulated from the semiconductor chip. The semiconductor package further includes a plurality of second terminals electrically connected to the semiconductor chip, and one or more third wiring patterns connected to any one of the plurality of second terminals. Prepare,
The said 3rd wiring pattern does not intersect the said 2nd wiring pattern in the orthogonal projection with respect to the said opposing surface, when the said semiconductor package is mounted in the said wiring board, The claim | item 1 or 2 characterized by the above-mentioned. Semiconductor package. The third wiring pattern includes a wiring pattern that passes through an upper surface on a side opposite to the opposite surface,
In the wiring pattern passing through the upper surface of the third wiring pattern, the width of the wiring pattern is wider than other portions in at least a part of the portion arranged on the upper surface. Item 5. A semiconductor package according to item 3. A semiconductor package containing a semiconductor chip,
The semiconductor package has a facing surface facing the wiring board,
One or more first terminals, a plurality of second terminals electrically connected to the semiconductor chip, and one of the first terminals and the plurality of second terminals on the facing surface; One or more first wiring patterns for connecting the
A semiconductor package, wherein the first terminal is not electrically connected to the semiconductor chip without interposing the first wiring pattern. The first wiring pattern includes a wiring pattern that passes through an upper surface opposite to the facing surface,
In the wiring pattern passing through the upper surface of the first wiring pattern, the width of the wiring pattern is wider than other portions in at least a part of the portion arranged on the upper surface. Item 6. The semiconductor package according to item 5.   A fourth aspect in which the semiconductor package electrically connects a third terminal arranged on an upper surface on a side opposite to the facing surface, and any one of the plurality of second terminals to the third terminal. 7. The semiconductor package according to claim 3, further comprising:   The semiconductor package according to claim 7, wherein the third terminal is larger than the first terminal.   9. The thickness of each of the first terminals from the facing surface and the thickness of the first wiring pattern from the facing surface are the same. The semiconductor package according to item 1.   A mounting board comprising: a wiring board; and the semiconductor package according to any one of claims 1 to 9 mounted on the wiring board.   An electronic device comprising the mounting substrate according to claim 10.

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