JP2020043249A - Multilayer wiring structure, component mounting multilayer wiring structure, multilayer wiring board, and component mounting multilayer wiring board - Google Patents

Abstract

To provide high quality multilayer wiring structure and component mounting multilayer wiring structure, capable of mounting electronic components stably.SOLUTION: A multilayer wiring structure includes a multilayer wiring layer where first to N-th (N is an integer of 2 or more) wiring layers are laminated in this order, each isolation layer for electrically separating two wiring layers adjoining in the lamination direction, and an interlayer connection part for electrically connecting at least two wiring layers out of the multilayer wiring layer. When viewing downward in the lamination direction of the multilayer wiring layer from N-th wiring layer side, a conductor pattern constituting any one of the first to N-th wiring layers exists below a part of a conductor pattern constituting the N-th wiring layer, but a conductor pattern constituting any one of the first to (N-1)th wiring layers does not exist below other part of the conductor pattern constituting the N-th wiring layer, and a part of the isolation layer is set thick so that the height positions of the conductor pattern of the N-th wiring layer substantially match in the lamination direction.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a multilayer wiring structure, a component mounting multilayer wiring structure, a multilayer wiring board, and a component mounting multilayer wiring board.

  In the past, as electronic devices have become more sophisticated, smaller, thinner, and lighter, there has been a demand for smaller, more pins, and finer pitch external terminals to be incorporated into electronic devices. I have. Further, when such an electronic component is mounted on a printed wiring board via a large number of external terminals, a large number of electrodes and wirings for connecting the large number of external terminals are required. Furthermore, in order to provide a large number of electrodes and wirings on a printed wiring board in which the mounting area of electronic components has become smaller due to miniaturization, in addition to forming the electrodes and wirings in a fine size, in addition to forming between the electrodes and wirings, It is necessary to reduce the gap (pitch). That is, there is a strong demand for a printed wiring board on which high-density wiring processing has been performed.

  In recent years, multilayer wiring boards have been used as printed wiring boards capable of realizing higher-density wiring processing. Examples of the multilayer wiring board include a printed board having a multilayer structure in which a wiring layer including a conductor pattern and an insulating layer are alternately stacked from the lower layer, and a via (interlayer connecting body) provided in a thickness direction of the insulating layer. ), The wiring layers provided so as to face each other in the vertical direction in the lamination direction of the insulating layers are electrically connected to each other. By using such a multilayer wiring board, wiring paths can be secured not only in the in-plane direction of the board but also in the stacking direction, and higher-density wiring design can be realized.

  In such a multilayer wiring board, an electrode for electrically connecting an electronic device via its external terminal is provided on the surface layer. For example, a semiconductor chip as an electronic component is flip-chip connected by face-down mounting to a counter electrode on the substrate side via a solder bump provided on the back surface.

JP 2014-179518 A

  In a multilayer wiring board, it is necessary to arrange a large number of conductor patterns at a high density in the stacking direction and in the in-plane direction of each layer without short-circuiting each other. I have no choice. Therefore, when the multilayer wiring board is viewed along the stacking direction, a state where the region where the conductor pattern exists in one wiring layer and the region where the conductor pattern exists in the other wiring layer does not partially overlap. Become. In such a method of manufacturing a multilayer wiring board, for example, a step of forming a conductor pattern as a wiring layer and a step of forming an insulating layer covering the wiring layer by, for example, a spin coating method are repeatedly performed. In the insulating layer formed in this manner, the height position of the wiring layer on the region where the conductor pattern exists is different from the height position on the region where the conductor pattern does not exist. Then, since the conductor patterns are stacked on the insulating layers having different height positions, the height positions of the electrodes provided on the surface layer of the multilayer wiring board are different.

  Generally, in a multilayer wiring board, in order to stably mount an electronic component such as a semiconductor chip on a surface, it is desirable that the height positions of a plurality of electrodes provided on a surface layer be substantially the same. However, as described above, since the height positions of the plurality of electrodes provided on the surface layer do not substantially match, the electronic component cannot be mounted stably.

  In view of the above problems, the present disclosure provides a high-quality multilayer wiring structure, a component mounting multilayer wiring structure, a multilayer wiring board, and a component mounting multilayer wiring board that can stably mount an electronic component. For one purpose.

  In order to solve the above problem, as one embodiment of the present disclosure, a multilayer wiring layer in which first to Nth (N is an integer of 2 or more) wiring layers are stacked in this order, and the multilayer wiring layer Insulating layers for electrically separating between two wiring layers adjacent to each other in the stacking direction, and an interlayer connecting portion for electrically connecting at least two wiring layers of the multilayer wiring layers When viewed from the N-th wiring layer side toward the lower side in the stacking direction of the multilayer wiring layer, the first to N-th -1 wiring layer, there is a conductor pattern constituting one of the wiring layers, but below the other part of the conductor pattern constituting the N-th wiring layer, the first to N-1th wiring layers There is no conductor pattern constituting any of the wiring layers, As the height position in the stacking direction of the conductor pattern of the N wiring layers substantially coincide, the multilayer wiring structure in which a part of the insulating layer is formed in thickness is provided.

  In the multilayer wiring structure, NM (M is 1 or more and N−M) of the first to N−1th wiring layers is provided below the one of the conductor patterns forming the Nth wiring layer in the stacking direction. The conductor pattern constituting each of the wiring layers is located, and the first to first wiring patterns are provided below the other conductor patterns constituting the Nth wiring layer in the stacking direction. The conductor pattern forming each of NL (L is larger than M and an integer of 2 or more and N or less) wiring layers of the (N-1) th wiring layer is located, In order to make the height positions of the N wiring layers in the stacking direction of the conductor patterns substantially coincide with each other, the L-M insulating layers located below the one of the conductor patterns forming the Nth wiring layer in the stacking direction are arranged. A part may be thick.

  In the above multilayer wiring structure, N is 3, and the third wiring layer is located between the first wiring layer and the second wiring layer such that the height position of the third wiring layer in the laminating direction of the conductor patterns substantially coincides with each other. The insulating layer and / or a part of the insulating layer located between the second wiring layer and the third wiring layer may be configured to be thick, and the insulating layer may be electrically connected to the N-th wiring layer. A plurality of electrodes to be connected may be further provided.

  As one embodiment of the present disclosure, a component-mounted multilayer wiring structure including the multilayer wiring structure and at least one electronic component electrically connected to the electrode and mounted is provided.

  As one embodiment of the present disclosure, a substrate having a first surface and a second surface facing the first surface, a first multilayer wiring structure provided on the first surface side of the substrate, and the substrate A second multilayer wiring structure provided on the second surface side, and a conductor provided so as to penetrate in a thickness direction of the substrate. A multilayer wiring structure, wherein the second multilayer wiring structure is the multilayer wiring structure, and the first to Nth wiring layers of the multilayer wiring layers forming the first multilayer wiring structure are arranged in this order. The first to Nth wiring layers of the multilayer wiring layers which are stacked on the first surface of the substrate and constitute the second multilayer wiring structure are arranged in this order on the second surface of the substrate. The first wiring layer of the multilayer wiring layers that are stacked and constitute the first multilayer wiring structure; And the multilayer wiring layer and the first wiring layer that constitutes the serial second multilayer wiring structure, the multilayer wiring board through the conductor are electrically connected to each other is provided. In the multilayer wiring substrate, a plurality of first electrodes electrically connected to the N-th wiring layer of the multilayer wiring layer forming the first multilayer wiring structure, and the second multilayer wiring structure are formed. A plurality of second electrodes electrically connected to the N-th wiring layer of the multilayer wiring layer.

  As one embodiment of the present disclosure, there is provided a component-mounted multilayer wiring board including the multilayer wiring board and at least one electronic component connected to and mounted on the first electrode. The component mounting multilayer wiring board may further include at least one electronic component connected and mounted to the second electrode.

  According to the present disclosure, it is possible to provide a high-quality multilayer wiring structure and a component mounting multilayer wiring structure capable of stably mounting an electronic component.

FIG. 1 is a schematic sectional view illustrating a multilayer wiring board according to the first embodiment of the present disclosure. FIG. 2 is a schematic sectional view illustrating a multilayer wiring board according to the second embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view illustrating a multilayer wiring board according to the third embodiment of the present disclosure. FIG. 4 is a schematic sectional view illustrating a multilayer wiring board according to the fourth embodiment of the present disclosure. FIG. 5 is a schematic sectional view illustrating a multilayer wiring board according to a fifth embodiment of the present disclosure. FIG. 6 is a process diagram illustrating a method for manufacturing a multilayer wiring board according to an embodiment of the present disclosure. FIG. 7 is a process diagram illustrating a method for manufacturing a multilayer wiring board according to an embodiment of the present disclosure, and is a process diagram illustrating a process that follows the process diagram of FIG. 6. FIG. 8 is a reference diagram illustrating a configuration example of a multilayer wiring board that appears as a difference in height position in the stacking direction of two conductor patterns located on the outermost layer.

  An embodiment of the present disclosure will be described with reference to the drawings. In the drawings attached to this specification, the shape, scale, aspect ratio, and the like of each part may be changed or exaggerated from the actual thing in order to facilitate understanding.

  In this specification and the like, a numerical range represented by using “to” means a range including the numerical values described before and after “to” as the lower limit and the upper limit, respectively. In this specification and the like, terms such as “film”, “sheet”, and “plate” are not distinguished from one another based on a difference in name. For example, “plate” is a concept that also includes members that can be generally called “sheets” and “films”.

[First Embodiment]
The multilayer wiring board according to the first embodiment of the present disclosure will be described below with reference to the drawings. FIG. 1 is a schematic sectional view illustrating a multilayer wiring board according to the first embodiment. A schematic configuration of the multilayer wiring board 1 according to the first embodiment will be described. The multilayer wiring board 1 includes a multilayer wiring structure 1A which comprises a multilayer wiring layer W _LM top surface 10 first wiring layer in _H W _L1 and the second wiring layer W _L2 of the substrate 10 are laminated in this order. In the multilayer wiring structure 1A, the insulating layer 21 is located between the first wiring layer _WL1 and the second wiring layer _WL2, and the insulating layer 22 is located on the second wiring layer _WL2 . The electrode 41 and the electrode 42 are provided on the insulating layer 22 serving as the surface layer of the multilayer wiring structure 1A.

The first wiring layer _WL1 is composed of a conductor pattern 11, and the second wiring layer _WL2 is composed of a conductor pattern 12 and a conductor pattern 13. The conductor pattern 11 is located on the upper surface 10 _H of the substrate 10. The conductor pattern 12 and the conductor pattern 13 are located at a predetermined distance from each other in an in-plane direction on the insulating layer 21. Vias 31 are provided on the conductor pattern 11 as interlayer connection portions. Further, the electrode 41 is continuously located on the upper surface of the conductor pattern 12, and the electrode 42 is continuously located on the upper surface of the conductor pattern 13. Hereinafter, each of these components will be described in detail below.

  The “substrate” in the first embodiment is not an abbreviation of an electronic circuit board, but means a plate serving as a base for manufacturing the multilayer wiring board 1. That is, as long as the wiring layer and the insulating layer can be laminated to form the multilayer wiring structure 1A, the substrate 10 may not be an essential component. The type of the substrate 10 is not particularly limited, and examples thereof include a glass epoxy substrate, a glass substrate, and a silicon substrate. The size, thickness, and the like of the substrate 10 can be appropriately set according to the desired size of the multilayer wiring substrate 1, the size and number of electronic components mounted on the multilayer wiring substrate 1, and the like. Electronic components that can be mounted on the multilayer wiring board 1 in the first embodiment include, for example, active elements such as relays, transistors, and integrated circuits (Integrated Circuits (IC)), as well as passive elements such as resistors, capacitors, and inductors. And the like. Further, in the first embodiment, a multilayer wiring structure on which at least one of the electronic components exemplified above is mounted is referred to as a “component-mounted multilayer wiring structure”.

  The conductor patterns 11 and 12 are made of a conductive material such as copper (Cu), nickel (Ni), and gold (Ag). In the first embodiment, the conductor pattern 11 and the conductor pattern 12 are connected via the conductive via 31 and the electrode 41 is continuous on the upper surface of the conductor pattern 13. And the electrode 41 can be electrically connected (FIG. 1).

  Similarly to the conductor patterns 11 and 12, the conductor pattern 13 is made of a conductive material such as copper (Cu), nickel (Ni), and gold (Au). In the first embodiment, since the electrode 42 is continuous on the upper surface of the conductor pattern 13, the conductor pattern 12 and the electrode 41 can be electrically connected (FIG. 1). The width, thickness, and the like of the conductor patterns 11, 12, and 13 are appropriately set according to the size of the multilayer wiring board 1, the size and number of electronic components mounted on the multilayer wiring board 1, and the like. obtain.

The insulating layer 21 and the insulating layer 22 are made of a photosensitive resin material such as a photosensitive polyimide resin, a photosensitive epoxy resin, and a photosensitive acrylic resin. The photosensitive resin material may have a negative type photosensitivity or a positive type photosensitivity. Insulating layer 21 is located on the upper surface 10 _H of the substrate 10 to cover the conductor pattern 11, the insulating layer 22 is positioned on the upper surface of the insulating layer 21 to cover the conductive pattern 12 and conductive pattern 13 . A predetermined area 21 _W (hereinafter, referred to as a “thick area”) of the insulating layer 21 covering the conductor pattern 11 is a predetermined area 21 _L (hereinafter, referred to as “thick area”) covering the upper surface 10 _{H of the} substrate 10 on which the conductor pattern 11 is not provided. It is referred to as a “thin region”.) Furthermore, the insulating layer 21, the thick regions 21 _W, at a portion across the thin area 21 _L in the plane direction, has a thick portion 21 _T a portion except for the thin region 21 _L is configured thicker . In the present embodiment, the thick portion _21T is configured such that the height position in the stacking direction thereof substantially matches the height position of the thick region _{21W in} the stacking direction. In the first embodiment, the conductor pattern 12 is located on the upper surface of the thick region 21 _W, the conductor pattern 13 is located on the upper surface of the thick portion 21 _T. According to the above configuration in the first embodiment, the height position in the stacking direction of the conductor patterns 12 and the height position in the stacking direction of the conductor patterns 13 can be substantially matched.

  The vias 31 are made of a conductive material such as copper (Cu), nickel (Ni), gold (Au) or the like, similarly to the conductor patterns. The dimensions and depth (height) of the vias 31 are not particularly limited, but include the desired size of the multilayer wiring board 1, the size and number of the conductor patterns 11 to 13, the thickness of each insulating layer, and the like. May be set as appropriate. The via 31 may be formed by plating the wall surface of a through hole formed in the insulating layer 21 with the conductive material, or may be formed by filling the through hole with the conductive material. Is also good.

  The electrode 41 and the electrode 42 are made of a metal material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and solder. The electrode 41 and the electrode 42 can be electrically connected to external terminals of an electronic component such as a semiconductor chip mounted on the multilayer wiring board 1. The dimensions and thickness of the electrodes 41 and 42 and the shape and height of the bumps protruding from the upper surface of the insulating layer 22, which is the outermost layer, are determined as long as the electronic components can be stably mounted on the multilayer wiring board 1. However, the present invention is not limited to the embodiment shown in FIG. Although not shown, UBM (Under Barrier Metal) may be provided between each electrode and each wiring.

FIG. 8 shows a multilayer wiring board 1 ′ in which the height difference in the stacking direction appears in the insulating layer 22 ″ as the surface layer because the thick portion 21 _T is not provided in the insulating layer 21 ″. FIG. In FIG. 8, “difference D” is exaggerated for easy understanding, but is not drawn as a difference that actually occurs. Referring to FIG. 8, on the basis of a comparison of a multilayer wiring board which is not thick portion 21 _T is formed in the insulating layer 21 'is described in detail operational effects of the thick portion 21 _T in the first embodiment.

In the multilayer wiring board 1 ′ shown in FIG. 8, the conductor pattern 11 is provided on a portion of the upper surface 10 _H of the substrate 10 corresponding to immediately below the electrode 41 in the laminating direction, but corresponds to immediately below the electrode 42 in the laminating direction. The conductor pattern 11 is not provided in the portion. Therefore, when the insulating layer 21 ″ is provided so as to cover the conductor pattern 11 in the process of forming the multilayer wiring board 1 ′, the height of the insulating layer 21 ″ covering the conductor pattern 11 immediately below the electrode 41 in the stacking direction is set. The position is higher by the thickness of the conductor pattern 11 than the height position of the insulating layer 21 ″ immediately below the electrode 42 in the stacking direction.

  When the conductor pattern 12 connected to the conductor pattern 11 via the via 31 is provided on the insulating layer 21 ″ in this state, and the conductor pattern 13 is provided on the insulating layer 21 ″ immediately below the electrode 42 in the stacking direction, the conductor A difference D in the height position in the stacking direction appears between the pattern 12 and the conductor pattern 13 (FIG. 8). Therefore, a difference in height position appears between the electrode 41 provided on the upper surface of the conductor pattern 12 and the electrode 42 provided on the upper surface of the conductor pattern 13. In such a case, it is difficult to stably mount the electronic component via the two electrodes having the difference in height position.

On the other hand, according to the multilayer wiring board 1 of the first embodiment, as described above, the thick portion 21 _T which part of the insulating layer 21 is configured thicker in the stacking direction just below the electrode 42 is provided Thus, the height positions of the two conductor patterns 12 and 13 formed on the insulating layer 21 can be substantially matched (FIG. 1). Therefore, the height positions of the electrodes 41 and the electrodes 42 on which the electronic components can be mounted are also substantially the same, and the high-quality multilayer wiring board 1 on which the electronic components can be stably mounted can be realized. Incidentally, the difference between the height position of the conductor pattern 12 and 13, for example in the range of 0Myuemu～3myuemu, preferably as a 1.5μm or less, it is preferable that the thick portion 21 _T is provided. By adjusting the height difference within the above range, the electronic component can be mounted substantially parallel to the surface layer of the multilayer wiring board 1. If the difference between the height positions exceeds 3 μm, when the electronic component is mounted on the multilayer wiring board 1, a connection failure between the electronic component and the multilayer wiring board 1 may easily occur.

[Second embodiment]
FIG. 2 is a schematic sectional view illustrating a multilayer wiring board according to the second embodiment of the present disclosure. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The multilayer wiring board 1 in the second embodiment, provided with a multilayer wiring structure 1A which comprises a multilayer wiring layer W _LM three layers of the first to third wiring layers W _L1 to _W-L3 are stacked, the third wiring layer conductor patterns 13 constituting the W _L3 that the thick portion 23 _T of the insulating layer 23 portion is configured to thickness positioned in the stacking direction just under the (electrode 42) is provided is different from the first embodiment I have. In the multilayer wiring board 1 in the second embodiment, the first wiring layer W _L1 second wiring layer W _L2 is provided between the third wiring layer W _L3, the second wiring layer W _L2, the conductor It is composed of a pattern 14. The insulating layer 23 is located between the second wiring layer _WL2 and the third wiring layer _WL3 .

Conductor pattern 14 is located on the thick region 21 _W of the insulating layer 21. Vias 32 as interlayer connection portions are provided on the conductor pattern 14, and the insulating layer 23 is located on the upper surface of the insulating layer 21 so as to cover the conductor pattern 14. The thick region of the insulating layer 23 covering the conductor pattern 14 is thicker than the thin region 21 _L covering the upper surface of the insulating layer 21 where the conductor pattern 14 is not provided. Furthermore, the insulating layer 23, a thickened region 23 _W, in the thinner portions 23 _L spaced (region covering the thin region 21 _L) portion in-plane direction, the portion excluding the thin region 23 _L is configured thicker It has a thick portion 23 _T consisting of Te. The thick portion 23 _T is the height position in the stacking direction, is configured to a height position substantially coincides with the stacking direction of the thickened region 23 _W on the conductor pattern 14. In the second embodiment, the conductor pattern 12 is located on the upper surface of the thick region 23 _W, the conductor pattern 13 is located on the upper surface of the thick portion 23 _T. According to the above configuration in the second embodiment, the height position in the stacking direction of the conductor patterns 12 and the height position in the stacking direction of the conductor patterns 13 can be substantially matched. The insulating layer 23 can be made of a photosensitive resin material such as a photosensitive polyimide resin, a photosensitive epoxy resin, and a photosensitive acrylic resin, like the insulating layers 21 and 22.

  The conductor pattern 14 is made of a conductive material such as copper (Cu), nickel (Ni), and gold (Au), like the conductor patterns 11, 12, and 13. In the second embodiment, the conductor pattern 11 and the conductor pattern 14 are connected via the via 31, the conductor pattern 14 and the conductor pattern 12 are connected via the via 32, and the electrode 41 is continuously formed on the conductor pattern 12. By doing so, the conductor pattern 11, the conductor pattern 14, the conductor pattern 12, and the electrode 41 can be electrically connected to each other (FIG. 2).

  The via 32 is made of a conductive material such as, for example, copper (Cu), nickel (Ni), and gold (Au), like the via 31. The size (for example, width and depth) of the via 32 is not particularly limited, but depends on the desired size of the multilayer wiring board 1, the size and pitch of each conductor pattern, the thickness of each insulating layer, and the like. It can be set appropriately. The via 32 may be formed by plating the wall surface of a through hole formed in the insulating layer 23 with the conductive material, or may be formed by filling the through hole with the conductive material. Is also good.

According to the multilayer wiring board 1 of the second embodiment, since the thick portion 23 _T which part of the insulating layer 23 is configured thicker in the stacking direction just below the electrode 42 is provided, the insulating layer 23 above (FIG. 2). Therefore, the height positions of the electrodes 41 and the electrodes 42 on which the electronic components can be mounted are also substantially the same, and the high-quality multilayer wiring board 1 on which the electronic components can be stably mounted can be realized.

Although the multilayer wiring board 1 in the second embodiment has been described as including the multilayer wiring structure 1A including the multilayer wiring layer _{WLM formed} by laminating three wiring layers, the present invention is not limited to this. Instead, a multilayer wiring board including a multilayer wiring structure including a multilayer wiring layer in which four or more wiring layers are stacked may be used.

[Third embodiment]
FIG. 3 is a schematic cross-sectional view illustrating a multilayer wiring board according to the third embodiment of the present disclosure. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Third multilayer wiring board 1 in the embodiment, the conductor constituting the electrode 43, the conductor patterns 16 constituting the second wiring layer W _L2, and the first wiring layer W _L1 adjacent to the electrode 42 in a plan view of the insulating layer 22 It is different from the multilayer wiring board 1 in the first embodiment in that the pattern 15 is provided and that the conductor pattern 16 is electrically connected to the conductor pattern 15 via a via 33 as an interlayer connection. .

The conductor pattern 15 is located at a portion at a predetermined distance from the conductor pattern 11 in the in-plane direction of the upper surface 10 _H of the substrate 10. The conductor pattern 12, the conductor pattern 13, and the conductor pattern 16 are located at a predetermined distance from each other in an in-plane direction on the insulating layer 21. The electrode 43 is located continuously on the upper surface of the conductor pattern 16.

  Similarly to the conductor patterns 11, 12, and 13, the conductor patterns 15 and 16 are also made of a conductive material such as copper (Cu), nickel (Ni), and gold (Au). In the third embodiment, the conductor pattern 15, the conductor pattern 16, and the electrode 43 are connected by connecting the conductor pattern 15 and the conductor pattern 16 via the via 33 and arranging the electrode 43 on the conductor pattern 16. Can be electrically connected to each other (FIG. 3).

In the third embodiment, predetermined regions of the insulating layer 21 that cover the conductor pattern 11 and the conductor pattern 15 are thick regions 21 _W1 and 21 _W2 , respectively, and the region between the thick region 21 _W1 and the thick portion 21 _T is thin. each region between the thick portion 21 _T and the thick region 21 _W2 are the thinner portions 21 _L1, 21 _L2. The thick region 21 _W2 is thicker than the thin regions 21 _L1 and 21 _L2 , and the height position of the thick region 21 _{W2 in} the laminating direction substantially coincides with the height position of the thick region 21 _{W1 in} the laminating direction. ing. Thick portion 21 _T is the height position in the stacking direction, are configured to substantially match the height position in the stacking direction of the thick region 21 _W1, 21 _W2. In the third embodiment, the conductor pattern 12 is located on the upper surface of the thick region 21 _W1, the conductor pattern 13 is located on the upper surface of the thick portion 21 _T, the conductor pattern 16 is located on the upper surface of the thick region 21 _W2 are doing. According to the above configuration in the third embodiment, the height positions of the conductor patterns 12, 13, 16 in the laminating direction can be substantially matched.

  The via 33 is made of a conductive material such as copper (Cu), nickel (Ni), or gold (Au), like the via 31. The size (for example, width and depth) of the via 33 is not particularly limited, but depends on the desired size of the multilayer wiring board 1, the size and pitch of each conductor pattern, the thickness of each insulating layer, and the like. It can be set appropriately. The via 33 may be formed by plating the conductive material on the wall surface of a through hole formed in the insulating layer 21, similarly to the via 31, or by filling the conductive material into the through hole. It may be made of.

  The electrode 43 is made of, for example, a metal material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), and solder, like the electrodes 41 and 42. The electrodes 41, 42, and 43 can be electrically connected to external terminals of electronic components such as a semiconductor chip mounted on the multilayer wiring board 1. The dimensions and thickness of the electrodes 41, 42, and 43, and the shape and height of the bumps protruding from the upper surface of the insulating layer 22, which is the outermost layer, allow the electronic components to be stably mounted on the multilayer wiring board 1. However, the present invention is not limited to the embodiment shown in FIG. Although not shown, UBM (Under Barrier Metal) may be provided between each electrode and each wiring.

According to the multilayer wiring board 1 of the third embodiment, the thick portion 21 _T in which a part of the insulating layer 21 is thickened is provided immediately below the electrode 42 in the stacking direction. The height positions of the three conductor patterns 12, 13 and 16 formed in FIG. For this reason, the height positions of the electrodes 41, the electrodes 42, and the electrodes 43 on which the electronic components can be mounted are also substantially the same, and the high-quality multilayer wiring board 1 on which the electronic components can be stably mounted can be realized. it can.

  The multilayer wiring board 1 according to the third embodiment has been described as including the multilayer wiring structure 1A in which three electrodes 41, 42, and 43 are arranged in parallel on the insulating layer 22 as the surface layer. The present invention is not limited to this, and may be a multilayer wiring board including a multilayer wiring structure in which four or more electrodes are arranged in parallel on the insulating layer 22 as the surface layer.

[Fourth embodiment]
FIG. 4 is a schematic sectional view illustrating a multilayer wiring board according to the fourth embodiment of the present disclosure. The same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. The multilayer wiring board 1 in the fourth embodiment, that it includes a multilayer wiring structure 1A which comprises a multilayer wiring layer W _LM three layers of the first to third wiring layers W _L1 to _W-L3 are stacked is first It is common to the multilayer wiring board 1 in the two embodiments. The multilayer wiring board 1 according to the fourth embodiment includes an electrode 43 adjacent to the electrode 42 in plan view, and the third point is that the conductor pattern 16 and the conductor pattern 15 are located below the electrode 43 in the stacking direction. It is common to the multilayer wiring board 1 in the embodiment. On the other hand, the multilayer wiring board 1 in the fourth embodiment, a thick portion 21 _T which part of the insulating layer 21 is formed of a thick located in the stacking direction under the electrodes 43 are located, the electrodes 42 of which part is located is thick portion 23 _T consisting configured to the thickness of the insulating layer 23 located in the stacking direction downward, that it has a thickened region 23 _W2 covering the conductor pattern 15 is first This is different from each of the multilayer wiring boards 1 in the first to third embodiments. In the multilayer wiring board 1 according to the fourth embodiment, the thick portion _21T is located between the first wiring layer _WL1 and the second wiring layer _WL2, and the thick portion _23T is located between the second wiring layer _WL2 and the second wiring layer _WL2 . It is located between the third wiring layer _WL3 . In the fourth embodiment, a predetermined region of the insulating layer 23 covering the conductor pattern 14 is defined as a thick region _23W1 .

In the fourth embodiment, the thick portion 21 _T, in-plane direction of the insulating layer 21 is located at a thin region 21 _L from thickened region 21 _W. The thick portion _21T is configured such that the height position in the stacking direction thereof substantially coincides with the height position of the thick region _{21W in} the stacking direction. In the fourth embodiment, the insulating layer 23 is located on the upper surface of the insulating layer 21 so as to cover the conductor patterns 14 and 15. The thick region 23 _W1 covering the conductor pattern 14 and the thick region 23 _W2 covering the conductor pattern 15 in the insulating layer 23 are thin regions 23 _L1 covering the upper surface of the insulating layer 21 where the conductor patterns 14 and 15 are not provided. _, 23 _Thicker than _L2 . Furthermore, the insulating layer 23, a portion held between the thinner portions 23 _L1 and thinner portions 23 _L2 has a thick portion 23 _T consisting configured thickened. In the fourth embodiment, the thick portion 23 _T, the height position in the stacking direction is configured to substantially coincide with the height position in each of the stacking direction of the thickened region 23 _W1 and thickness region 23 _w2 ing. In the fourth embodiment, the conductor pattern 14 is located on the upper surface of the thick region 21 _W, the conductor pattern 15 that is positioned on the upper surface of the thick portion 21 _T, the height in the stacking direction of the conductor pattern 14 located And the height position of the conductor pattern 15 in the stacking direction can be substantially matched. In the fourth embodiment, the conductor pattern 12 is located on the upper surface of the thick region 23 _W1, the conductor pattern 13 is located on the upper surface of the thick portion 23 _T, the conductor pattern 16 on the upper surface of the thick region 23 _W2 By being located, it is possible to make the height positions of the conductor patterns 12, 13, 16 in the lamination direction substantially coincide.

According to the configuration in the fourth embodiment, since the thick portion 21 _T which part of the insulating layer 21 is formed of thicker in the stacking direction just below the electrode 43 is provided, on the insulating layer 21 The height positions of the two conductor patterns 14 and 15 to be formed can be substantially matched (FIG. 4). Furthermore, according to the configuration in the fourth embodiment, since the thick portion 23 _T which part of the insulating layer 23 is formed of thicker in the stacking direction just below the electrode 42 is provided, the insulating layer 23 The height positions of the three conductor patterns 12, 13, 16 formed thereon can be substantially matched (FIG. 4). For this reason, the height positions of the electrodes 41, the electrodes 42, and the electrodes 43 on which the electronic components can be mounted are also substantially the same, and the high-quality multilayer wiring board 1 on which the electronic components can be stably mounted can be provided. it can. Incidentally, the difference between the height position of the conductor pattern 14 and 15, for example in the range of 0Myuemu～3myuemu, preferably as a 1.5μm or less, it is preferable that the thick portion 21 _T is provided. Similarly, the difference between the height position of the conductor pattern 12, 13, 16 is, for example, in the range of 0Myuemu～3myuemu, preferably so that 1.5μm or less, it is preferable that the thick portion 23 _T is provided . By adjusting the difference in height position within each of the above ranges, the electronic component can be mounted substantially parallel to the surface layer of the multilayer wiring board 1. If the difference between the height positions exceeds 3 μm, when the electronic component is mounted on the multilayer wiring board 1, a connection failure between the electronic component and the multilayer wiring board 1 may easily occur.

Although the multilayer wiring board 1 according to the fourth embodiment has been described as including the multilayer wiring structure 1A including the multilayer wiring layer _{WLM formed} by laminating three wiring layers, the present invention is not limited to this. Instead, a multilayer wiring board including a multilayer wiring structure including a multilayer wiring layer in which four or more wiring layers are stacked may be used. The multilayer wiring board 1 according to the fourth embodiment has been described as including the multilayer wiring structure 1A in which three electrodes 41, 42, and 43 are arranged in parallel on the insulating layer 22 as the surface layer. However, the present invention is not limited to this, and may be a multilayer wiring board including a multilayer wiring structure in which four or more electrodes are arranged in parallel on an insulating layer 22 as a surface layer.

Further, in the fourth embodiment, two conductor patterns (conductor patterns 11 and 14) are located below the conductor pattern 12 forming the third wiring layer _WL3 in the stacking direction, and the third wiring layer _WL3 is formed. One conductor pattern (conductor pattern 15) is located below the lamination direction of the conductor pattern 16 to be laminated, and a part (the meat) of the insulating layer 23 located below the lamination direction of the conductor pattern 13 forming the third wiring layer _WL3. The thick portion 23 _T ) is formed to be thick, and a part (thick portion 21 _T ) of the insulating layer 21 located below the conductor pattern 16 in the stacking direction is formed to be thick. It is not limited to this. For example, instead of the configuration of the fourth embodiment, one conductor pattern is located below the conductor pattern 12 in the stacking direction, and two conductor patterns are located below the conductor pattern 13 in the stacking direction. Even in a mode in which a part of the insulating layer 21 located below the lamination direction is configured to be thick and a part of the insulating layer 23 located below the conductive pattern 16 in the lamination direction is configured to be thick. Good.

  In a multilayer wiring board including a multilayer wiring layer in which four or more wiring layers, for example, the first to fourth wiring layers are stacked in this order, the lamination of one conductor pattern forming the fourth wiring layer Each of the conductor patterns constituting the first to third wiring layers is located downward in the direction, and two of the first to third wiring layers are located below the other conductor pattern constituting the fourth wiring layer in the stacking direction. Are arranged, and the conductor pattern constituting any one of the first to third wiring layers is located in the laminating direction of still another conductor pattern constituting the fourth wiring layer. It may be in a form. In this case, a part of the insulating layer located between the wiring layers may be configured to have a large thickness so that the height positions of the respective conductor patterns constituting the fourth wiring layer in the laminating direction substantially coincide with each other.

[Fifth Embodiment]
FIG. 5 is a schematic sectional view illustrating the multilayer wiring board 1 according to the fifth embodiment. The same components as those of the above-described embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. The multilayer wiring board 1 in the fifth embodiment, the through-hole via 10 _TH is provided to penetrate in the thickness direction of the substrate 10, the first multilayer wiring structure 1A which comprises a multilayer wiring layer W _LM1 on the upper surface 10 _H of the substrate 10 It is provided, having a structure in which the second multilayer wiring structure 1B provided comprising a multilayer wiring layer W _LM2 on the lower surface 10 _L of the substrate 10. The through-hole via 10 _TH is formed by plating a conductive material on the wall surface of a through-hole penetrating in the thickness direction of the substrate 10. For example, a conductive material such as copper (Cu), nickel (Ni), and gold (Au) is used. It is composed of materials. Through-hole via 10 _TH serves as a conductor for electrically connecting the conductor pattern 61 of the conductor pattern 11 and the multilayer wiring layer W _LM2 of the wiring layer W _LM1. As the multi-layer wiring layer W _LM1 adopts the same configuration as the multilayer wiring layer W _LM in the multi-layer wiring board 1 in the first embodiment. As the multilayer wiring layer _WLM2 in the fifth embodiment, a multilayer structure obtained by inverting the multilayer wiring layer _WLM1 with the substrate 10 as a boundary is adopted, but is adopted for the sake of simplicity of explanation. However, the present invention is not limited to this structure, and various laminated structures can be appropriately set. The conductor constituting the multilayer wiring board 1 of the present disclosure is not limited to the through-hole via _10TH , and may be a filled via in which the conductive material is filled in the through-hole. Good.

The multilayer wiring layer W _LM2 includes a first wiring layer W _L1B and a second wiring layer W _{L2B which} are sequentially stacked from the lower surface 10 _L side of the substrate 10, and a first wiring layer _{WL 1B} and a second wiring layer _{WL 2B} are formed. The insulating layer 61 is located therebetween, and the insulating layer 62 is located so as to cover the second wiring layer _WL2B . The electrode 81 and the electrode 82 are provided on the surface layer of the second multilayer wiring structure 1B. The first wiring layer _WL1B is composed of a conductor pattern 51, and the second wiring layer _WL2B is composed of a conductor pattern 52 and a conductor pattern 53. Conductor pattern 51 is located on the lower surface 10 _L of the substrate 10. The conductor pattern 52 and the conductor pattern 53 are located at a predetermined distance from each other in an in-plane direction on the insulating layer 61. Vias 34 are provided on the conductor pattern 51 as interlayer connection portions. The electrode 81 is continuously located on the upper surface of the conductor pattern 52, and the electrode 82 is continuously located on the upper surface of the conductor pattern 53. The via 34 is made of a conductive material such as copper (Cu), nickel (Ni), or gold (Au), like the via 31. The size (for example, width and depth) of the via 34 is not particularly limited, but depends on the desired size of the multilayer wiring board 1, the size and pitch of each conductor pattern, the thickness of each insulating layer, and the like. It can be set appropriately. The via 34 may be formed by plating the wall surface of a through hole formed in the insulating layer 61 with the conductive material, or may be formed by filling the through hole with the conductive material. Is also good.

The insulating layers 61 and 62 are made of a photosensitive resin material such as a photosensitive polyimide resin, a photosensitive epoxy resin, and a photosensitive acrylic resin. Insulating layer 61 is located on the lower surface 10 _L of the substrate 10 to cover the conductor pattern 51, the insulating layer 62 is located on the upper surface of the insulating layer 61 to cover the conductive pattern 52 and conductive pattern 53 . In the insulating layer 61, the thickness area 61 _W covering the conductor pattern 51 is thicker than the thinner portions 61 _L covering the lower surface 10 _L of the substrate 10 on which the conductor pattern 51 is not provided. Furthermore, the insulating layer 61, the thickened region 61 _W, has a thick portion 61 _T to sites in the plane direction across the thin region 61 _L is configured to thick. In the fifth embodiment, the thick portion 61 _T is the height position in the stacking direction, are configured to substantially match the height position in the stacking direction of the thickened region 61 _W. In the fifth embodiment, the conductor pattern 52 is located on the upper surface of the thick region 61 _W, the conductor pattern 53 is located on the upper surface of the thick portion 61 _T.

According to the configuration in the fifth embodiment, since the thick portion 61 _T a part of the insulating layer 61 is formed of thicker in the stacking direction just below the electrode 82 is provided, on the insulating layer 61 The height positions of the two conductor patterns 52 and 53 to be formed in the laminating direction can be substantially matched (FIG. 5). Therefore, the height positions of the electrodes 81 and the electrodes 82 on which the electronic components can be mounted are also substantially the same, and the high-quality multilayer wiring board 1 on which the electronic components can be stably mounted can be realized. Incidentally, the difference between the height position of the conductor pattern 52 and 53, for example in the range of 0Myuemu～3myuemu, preferably as a 1.5μm or less, it is preferable that the thick portion 61 _T is provided. By adjusting the difference in height position within the above range, the electronic component can be mounted substantially parallel to the surface layer of the multilayer wiring board 1. If the difference between the height positions exceeds 3 μm, when the electronic component is mounted on the multilayer wiring board 1, a connection failure between the electronic component and the multilayer wiring board 1 may easily occur.

  The electronic components that can be mounted on the multilayer wiring board 1 in the fifth embodiment include, for example, active elements such as relays, transistors, and integrated circuits (Integrated Circuits (IC)), as well as passive elements such as resistors, capacitors, and inductors. And the like. In the fifth embodiment, a multilayer wiring board in which at least one of the electronic components exemplified above is electrically connected to each electrode and mounted is referred to as a “component mounted multilayer wiring board”. . When the multilayer wiring board 1 according to the fifth embodiment is used, one of the electronic components is electrically connected to and mounted on the electrode 41 and the electrode 42 (first electrode), and the electrode 81 and the electrode 82 (second electrode) are used. A component-mounted multilayer wiring board in which one of the electronic components is electrically connected to and mounted on the electrode). Also, for example, one of the electronic components is electrically connected and mounted on the electrodes 41 and 42 (first electrode), and the electronic component is mounted on the electrodes 81 and 82 (second electrode). A component mounting multilayer wiring board may be used.

The multilayer wiring board 1 in the fifth embodiment, includes a multilayer wiring layer W _LM1 consisting two wiring layers on the upper surface 10 _H of the substrate 10, a multilayer wiring layer W _LM2 consisting two wiring layers lower surface of the substrate 10 Although the multi-layer wiring board 1 provided for 10 _L has been described, the present invention is not limited to this, and a multi-layer wiring board including three or more wiring layers laminated on both sides of the board 10 may be used. There may be. The multilayer wiring board 1 according to the fifth embodiment includes a multilayer wiring structure 1A in which two electrodes 41 and 42 are arranged in parallel on an insulating layer 22 as a surface layer, and an electrode 81 on an insulating layer 62 as a surface layer. 82, the multilayer wiring board 1 including the multilayer wiring structure 1B in which two electrodes are arranged in parallel has been described. However, the present invention is not limited to this. A multilayer wiring board including a multilayer wiring structure in which electrodes are arranged in parallel and a multilayer wiring structure in which three or more electrodes are arranged in parallel on an insulating layer 62 as a surface layer may be used.

[Manufacturing method of multilayer wiring board]
6 is a process diagram illustrating a method for manufacturing a multilayer wiring board (multilayer wiring structure) according to an embodiment of the present disclosure, and FIG. 7 is a process diagram following the manufacturing process in FIG. Hereinafter, a method for manufacturing the multilayer wiring board 1 in the first embodiment will be described as an example.

First, as the substrate 10, providing a substrate for the main material of glass epoxy having a desired thickness and size, the upper surface 10 _H of the substrate 10 to form a conductive pattern 11 (FIG. 6 (A)). For forming the conductive pattern 11, an alloy containing these, such as copper (Cu), nickel (Ni), and gold (Au), is preferably used. As a method for forming the conductive pattern 11, for example, a resist pattern for electroplating is formed on the upper surface 10 formed by the conductive seed layer on a _H of the substrate 10, electroplated with a desired thickness on the resist opening portion of the pattern And then removing the resist pattern and the unnecessary conductive seed layer. As a method for forming a conductive seed layer on the upper surface 10 _H of the substrate 10, for example, a sputtering method or an electroless plating method and the like. Alternatively, the conductive pattern may be formed by forming a conductive layer on the upper surface 10 _H of the substrate 10, forming a resist pattern on the conductive layer, and then etching using the resist pattern as a mask. The resist pattern can be formed by exposing and developing a dry film resist or a liquid resist. Note that the substrate 10 is not limited to the above-described substrate mainly composed of glass epoxy, and a substrate mainly composed of glass, silicon, or the like can be suitably used.

Then, so as to cover the conductive pattern 11, the upper surface 10 _H of the substrate 10, for example, spin coating, dip coating, spray coating, a negative type photosensitive resin solution was applied by a method such as bar coating, a photosensitive resin coating A film 21 'is formed (FIG. 6B). Examples of the photosensitive resin solution include a photosensitive resin solution containing a photosensitive polyimide resin, a photosensitive epoxy resin, a photosensitive acrylic resin, or the like as a photosensitive resin material. In this embodiment, the height of the region of the photosensitive resin coating film 21 ′ (hereinafter, referred to as “thick region”) 21 ′ _W covering the upper surface of the conductor pattern 11 in the stacking direction is determined by the conductor pattern 11. The predetermined area (hereinafter, referred to as “thin area”) 21 ′ _L of the photosensitive resin coating film 21 ′ covering the upper surface 10 _{H of the} substrate 10 which is not formed is higher than the height position in the stacking direction.

Next, using a multi-tone mask 100 having a transmissive portion 100t, a semi-transmissive portion 100h, and a light-shielding portion 100s, a photosensitive member having a cured portion 21'd, a semi-cured portion 21'h, and an uncured portion 21'n is used. The conductive resin layer _21′Y is formed (FIG. 6C). As the multi-tone mask 100, for example, a half-tone mask or a gray-tone mask can be used. In the present embodiment, the light shielding portion 100s is "to correspond to a portion of _{is W,} the multi-tone mask 100 photosensitive resin film 21 'thickened region 21 is positioned above the. After that, the photosensitive resin coating film 21 'is exposed through the multi-tone mask 100. The photosensitive resin coating 21 ′ corresponding to the transmission part 100t is cured by the exposure light transmitted through the transmission part 100t to form a cured part 21′d. In addition, a part of the resin constituting the photosensitive resin coating film 21 ′ corresponding to the semi-transmissive portion 100h is cured by a part of the exposure light transmitted through the semi-transmissive portion 100h, and other resins except the cured portion are used. The resin remains in an uncured state and becomes a semi-cured portion 21'h. On the other hand, when the exposure light is shielded by the light shielding portion 100s, the portion of the photosensitive resin coating film 21 'corresponding to the light shielding portion 100s becomes an uncured portion 21'n.

Thereafter, by performing development processing of the photosensitive resin layer 21 _'Y, an insulating layer 21 having a through-hole 21 _H and thick portion 21 _T (FIG. 6 (D)). In this embodiment, the developing process, 'the through-hole 21 _H next is removed uncured portion 21'n of _Y, the photosensitive resin layer 21' photosensitive resin layer 21 cured portion 21'd wall thickness of _Y This is the part _21T . On the other hand, among the semi-curing section 21'h of the photosensitive resin layer 21 _'Y, the resin portion which remains in the uncured state described above is removed by development processing. As a result, the thickness of the portion of the insulating layer 21 corresponding to the semi-cured portion 21′h after the resin portion remaining in an uncured state is removed by the development process is changed to the photosensitive resin layer 21 before the development process. 'It becomes thinner than the thickness of _Y. Specifically, an insulating layer 21 portions corresponding to the semi-curing section 21'h, the portion covering the upper surface 10 _H of the substrate 10 on which the conductor pattern 11 is not formed, may be formed into a thin film with respect to the thick portion 21 _T . Further, an insulating layer 21 portions corresponding to the semi-curing section 21'h, (excluding the through hole 21 _H) of the conductor pattern 11 to cover a region (hereinafter referred to as "thickened region".) 21 _W is, before carrying out the development process thinner than the photosensitive resin layer 21 'thickness of _Y. As a result, the height position of the thick region _{21W in} the stacking direction substantially coincides with the height position of the thick portion _{21T in} the stacking direction (FIG. 6D).

Note that, in the present embodiment, the photosensitive resin coating film 21 ′ made of a negative photosensitive resin solution is exposed and developed through the multi-tone mask 100 to form the through-hole 21 _H and the thickness. but in which the insulating layer 21 having a part 21 _T is formed, this is not limited, as the photosensitive resin film 21 ', using those composed of the photosensitive resin solution of a positive You may.

Next, the conductive pattern 12 is formed on the upper surface of the thick region 21 _W of the insulating layer 21 while filling the conductive material into the through hole 21 _H to form the via 31, and the conductive pattern is formed on the upper surface of the thick portion 21 _T. 13 (FIG. 7A). The via 31, the conductor pattern 12, and the conductor pattern 13 can be formed in the same manner as the conductor pattern 11 described above. For forming the via 31, the conductor pattern 12, and the conductor pattern 13, an alloy containing these, such as copper (Cu), nickel (Ni), and gold (Au), is preferably used.

  Thereafter, an insulating layer 22 is formed so as to cover the conductor patterns 12 and 13 (FIG. 7B). The insulating layer 22 can be formed by a so-called coating method in which an epoxy resin solution or the like is applied by a method such as spin coating, dip coating, spray coating, or bar coating, dried, and then heat-cured.

Next, a through hole 22 _H1 penetrating the insulating layer 22 in the thickness direction is formed so that a part of the upper surface of the conductor pattern 12 is exposed, and a part of the upper surface of the conductor pattern 13 is exposed such that A through hole 22 _H2 penetrating in the thickness direction of the insulating layer 22 is formed (FIG. 7C). The through-hole 22 _H1 and the through-hole 22 _H2 can be formed by, for example, forming a desired resist pattern on the insulating layer 22 and etching with a desired etchant using the resist pattern as a mask.

Next, the electrode 41 is formed by filling the through hole 22 _H1 with a conductive material, and the electrode 42 is formed by filling the through hole 22 _H2 with a conductive material (FIG. 7D). The electrodes 41 and 42 are made of a material (eg, copper (Cu), nickel (Ni), gold (Au), lead-tin alloy, or the like) that forms the electrodes 41 and 42, for example, by electroplating, electroless plating, or the like. Can be formed. Through the above steps, the multilayer wiring board 1 in which the height positions of the conductor pattern 12 (electrode 41) and the conductor pattern 13 (electrode 42) are substantially the same can be formed.

  The embodiments described above are described for facilitating the understanding of the present disclosure, and are not described for limiting the present disclosure. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present disclosure.

  In the multilayer wiring board 1 in each of the above embodiments, as shown in FIGS. 1 to 5, an aspect is depicted in which the insulating layer located substantially immediately below the lamination direction of the conductor pattern located on the surface layer is configured to be thick. However, the present invention is not limited to this mode. For example, as long as the height of the conductor pattern located on the surface layer can be substantially matched, at least a part of the conductor pattern located on the surface layer is formed so that the insulating layer located below the lamination direction is thick. Good. That is, even if the insulating layer is not located immediately below the laminating direction of the conductor pattern located on the surface layer, the thickness of the insulating layer at the position displaced in the in-plane direction (left and right direction in the drawing) of the predetermined layer from the position immediately below the laminating direction May be configured.

  Hereinafter, the present disclosure will be described in more detail with reference to Examples and Test Examples, but the present disclosure is not limited to the following Examples and the like.

[Example 1]
A glass substrate having a thickness of 500 μm is prepared as the substrate 10, and a conductive seed layer (film thickness 0.25 μm) containing Cu as a conductive material is formed on one surface of the glass substrate by sputtering, and then used for plating. Was spinner-coated, exposed using a photomask for the conductor pattern 11 of the first wiring layer _WL1 , and developed to form a 3 μm-thick resist pattern. Subsequently, a 3 μm-thick Cu plating was applied to the resist opening by electrolytic copper plating, and then the unnecessary conductive seed layer was removed by soft etching to form a first wiring layer _WL 1 having the conductor pattern 11.

Then, so as to cover the conductive pattern 11, the upper surface 10 _H of the substrate 10, a negative photosensitive polyimide resin solution was spinner coated to form a photosensitive resin film 21 '. Subsequently, through a half-tone mask as a multi-tone mask 100, of the surface of the photosensitive resin film 21 ', and shield the through hole 21 _H formation region, exposing the thick portions 21 _T forming area the thinner portions 21 _L-formed region half exposure and a photosensitive resin layer 21 _'Y. Then developed to form an insulating layer 21 having a through-hole 21 _H and thick portion 21 _T.

Next, a conductive seed layer (0.25 μm in thickness) containing Cu as a conductive material was formed on the upper surface of the insulating layer 21 by sputtering. Subsequently, a liquid resist for plating is applied on the seed layer formed on the upper surface of the insulating layer 21 and is exposed through a photomask for the conductor patterns 12 and 13 of the second wiring layer _WL2. The resist was developed to form a resist pattern having a thickness of 3 μm. Subsequently, Cu plating with a thickness of 3 μm was applied to the through-hole 21 _H of the insulating layer 21 and the opening of the resist by electrolytic copper plating.

Next, the resist pattern is peeled off from the conductive seed layer formed on the upper surface of the insulating layer 21, and unnecessary unnecessary conductive seed layers other than the Cu-plated portion are removed by soft etching. vias 31, and forming a second wiring layer W _L2 having a conductor pattern 12 and the conductor pattern 13, and a multilayer wiring structure by forming an insulating layer 22 patterned thereon.

  Subsequently, an electrode 41 and an electrode 42 having a bump height of 3 μm protruding from the upper surface of the insulating layer 22 were formed in the opening of the insulating layer 22 by electroless plating. As described above, a desired multilayer wiring board 1 was manufactured.

[Comparative Example 1]
A negative photosensitive polyimide resin solution is spin-coated on the upper surface 10 _H of the substrate 10 so as to cover the conductor pattern 11 to form a photosensitive resin coating film, and the photosensitive resin film is exposed through a photomask for the through hole 21 _H. of the surface of sexual resin film, shields the through-hole 21 _H formation region, the other region by exposing a photosensitive resin layer, and developed, other that an insulating layer 21 having a through hole 21 _H In the same manner as in Example 1, a multilayer wiring board 1 ′ was manufactured.

[Test example]
The multilayer wiring board 1 according to Example 1 was cut in the laminating direction at a portion where the electrodes 41 and 42 were formed. Then, the two cut surfaces are observed using an SEM (JWS-7855S manufactured by JEOL Ltd.), and the height position in the stacking direction of each conductor pattern (conductor patterns 12 and 13) where each electrode is located is located. Was measured, the difference between the height positions of the two electrodes in the stacking direction was 1.0 μm.

  Similarly, the multilayer wiring board 1 ′ according to Comparative Example 1 was cut in the laminating direction at the portions where the electrodes 41 and 42 were formed. Then, the two cut surfaces are observed using an SEM (JWS-7855S manufactured by JEOL Ltd.), and the height position in the stacking direction of each conductor pattern (conductor patterns 12 and 13) where each electrode is located is located. Was measured, the difference in height between the two electrodes in the stacking direction was 3.2 μm.

From the above test results, it was confirmed that in the multilayer wiring board 1 of Example 1, the difference between the height positions of the electrodes 41 and 42 was suppressed to a range of 0 μm to 3 μm. For this reason, like the multilayer wiring board 1 of the first embodiment, after forming the photosensitive resin coating film 21 ′, the photosensitive resin coating film 21 ′ is formed via the multi-tone mask 100 (halftone mask). On the surface, the through-hole 21 _H formation planned area is shielded from light, the thick portion 21 _T formation planned region is exposed, and the thin region 21 _L planned formation region is semi-exposed to form the photosensitive resin layer 21 ″ and developed. a through hole 21 by forming the insulating layer 21 having a _H and a thick portion 21 _T, lamination of the conductor pattern 12 that electrically conductive material in the through-hole 21 _H is formed so as to be continuous to the via 31 formed by filling a height position in the direction, and the height position in the stacking direction of the conductor pattern 13 formed is formed on the thick portion 21 _T, but substantially coincide, as a result, electrode 41 is continuously formed in the conductor pattern 12 Height in the stacking direction of The height position in the stacking direction of the electrodes 42 formed continuously with the electrode 13 is substantially the same, so that the electronic component is stably mounted on the multilayer wiring board 1 via the electrodes 41 and 42. It is thought that it is possible.

1 ... multilayer wiring board 1A ... multilayer wiring structure _{W LM, W LM1, W LM2} ... wiring layer _{W L1, W L2, W L3} , W L1B, W L2B ... wiring layer 11,12,13,14,15, 16, 51, 52, 53 ... conductor patterns 21, 22, 23 ... insulating layers 31, 32, 33 ... vias (interlayer connection parts)
41, 42, 43 ... electrodes

Claims (9)

A multilayer wiring layer in which first to Nth (N is an integer of 2 or more) wiring layers are stacked in this order;
An insulating layer for electrically separating between two wiring layers adjacent to each other in the stacking direction of the multilayer wiring layers;
An interlayer connection portion for electrically connecting at least two wiring layers of the multilayer wiring layer,
When viewed from the Nth wiring layer side downward in the stacking direction of the multilayer wiring layer, the first to (N-1) th wiring layers are located below a part of the conductor pattern forming the N wiring layer. Of the first to (N-1) th wiring layers below the other portion of the conductor pattern forming the N-th wiring layer. There is no conductor pattern that constitutes one of the wiring layers,
A multilayer wiring structure in which a part of the insulating layer is thick so that the height position of the N-th wiring layer in the laminating direction of the conductor pattern is substantially the same. Below the one of the first to (N-1) th wiring layers, NM (M is an integer of 1 or more and N-1 or less) below the one conductor pattern forming the Nth wiring layer in the laminating direction. The conductor pattern forming each of the wiring layers is located;
N-L (L is larger than M and is an integer of 2 or more and N or less) of the first to (N-1) -th wiring layers below the other conductor pattern forming the N-th wiring layer in the stacking direction. The conductor pattern forming each of the wiring layers is located,
The LM insulation layers located below the one conductor pattern forming the N-th wiring layer in the stacking direction such that the height positions of the N-th wiring layer in the stacking direction of the conductor patterns are substantially the same. The multilayer wiring structure according to claim 1, wherein a part of the layer is configured to be thick. N is 3,
The insulating layer and / or the second wiring layer and the third wiring layer located between the first and second wiring layers are arranged such that the height position of the third wiring layer in the stacking direction of the conductor pattern is substantially the same. The multilayer wiring structure according to claim 1, wherein a part of the insulating layer located between the wiring layer and the wiring layer is configured to be thick. The multilayer wiring structure according to claim 1, further comprising a plurality of electrodes electrically connected to the N-th wiring layer. A multilayer wiring structure according to claim 4,
A component-mounted multilayer wiring structure, comprising: at least one electronic component electrically connected to the electrode and mounted. A substrate having a first surface and a second surface facing the first surface;
A first multilayer wiring structure provided on the first surface side of the substrate;
A second multilayer wiring structure provided on the second surface side of the substrate;
A conductor provided so as to penetrate in the thickness direction of the substrate,
The first multilayer wiring structure is the multilayer wiring structure according to any one of claims 1 to 3,
The second multilayer wiring structure is the multilayer wiring structure according to any one of claims 1 to 3,
The first to N-th wiring layers of the multilayer wiring layers constituting the first multilayer wiring structure are stacked on the first surface of the substrate in this order;
The first to N-th wiring layers of the multilayer wiring layers forming the second multilayer wiring structure are stacked in this order on the second surface of the substrate,
The first wiring layer of the multilayer wiring layer forming the first multilayer wiring structure and the first wiring layer of the multilayer wiring layer forming the second multilayer wiring structure are connected via the conductor. Multilayer wiring boards electrically connected to each other. A plurality of first electrodes electrically connected to the N-th wiring layer of the multilayer wiring layer forming the first multilayer wiring structure;
7. The multilayer wiring board according to claim 6, further comprising: a plurality of second electrodes electrically connected to the N-th wiring layer of the multilayer wiring layer forming the second multilayer wiring structure. A multilayer wiring board according to claim 7,
At least one electronic component connected to the first electrode and mounted. The component-mounted multilayer wiring board according to claim 8, further comprising at least one electronic component connected to the second electrode and mounted.

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