JP2020009492A5 - - Google Patents

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Publication number
JP2020009492A5
JP2020009492A5 JP2019183022A JP2019183022A JP2020009492A5 JP 2020009492 A5 JP2020009492 A5 JP 2020009492A5 JP 2019183022 A JP2019183022 A JP 2019183022A JP 2019183022 A JP2019183022 A JP 2019183022A JP 2020009492 A5 JP2020009492 A5 JP 2020009492A5
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JP
Japan
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page
data
cache line
main memory
cache
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JP2019183022A
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Japanese (ja)
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JP6944983B2 (ja
JP2020009492A (ja
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Priority claimed from US15/236,171 external-priority patent/US10037173B2/en
Priority claimed from US15/235,495 external-priority patent/US10152427B2/en
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Publication of JP2020009492A5 publication Critical patent/JP2020009492A5/ja
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JP2019183022A 2016-08-12 2019-10-03 ハイブリッドメモリ管理 Active JP6944983B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US15/236,171 US10037173B2 (en) 2016-08-12 2016-08-12 Hybrid memory management
US15/235,495 2016-08-12
US15/236,171 2016-08-12
US15/235,495 US10152427B2 (en) 2016-08-12 2016-08-12 Hybrid memory management
JP2017156543A JP2018026136A (ja) 2016-08-12 2017-08-14 ハイブリッドメモリ管理

Related Parent Applications (1)

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JP2017156543A Division JP2018026136A (ja) 2016-08-12 2017-08-14 ハイブリッドメモリ管理

Publications (3)

Publication Number Publication Date
JP2020009492A JP2020009492A (ja) 2020-01-16
JP2020009492A5 true JP2020009492A5 (OSRAM) 2020-09-24
JP6944983B2 JP6944983B2 (ja) 2021-10-06

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JP2017156543A Pending JP2018026136A (ja) 2016-08-12 2017-08-14 ハイブリッドメモリ管理
JP2019183022A Active JP6944983B2 (ja) 2016-08-12 2019-10-03 ハイブリッドメモリ管理

Family Applications Before (1)

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JP2017156543A Pending JP2018026136A (ja) 2016-08-12 2017-08-14 ハイブリッドメモリ管理

Country Status (6)

Country Link
US (1) US10037173B2 (OSRAM)
EP (2) EP3291097A3 (OSRAM)
JP (2) JP2018026136A (OSRAM)
CN (2) CN107729168A (OSRAM)
DE (2) DE202017104840U1 (OSRAM)
TW (1) TWI643073B (OSRAM)

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CN118318429A (zh) 2021-08-11 2024-07-09 安法布里卡公司 用于使用流级别传输机制进行拥塞控制的系统和方法
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