JP2019521408A5 - - Google Patents

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Publication number
JP2019521408A5
JP2019521408A5 JP2018555743A JP2018555743A JP2019521408A5 JP 2019521408 A5 JP2019521408 A5 JP 2019521408A5 JP 2018555743 A JP2018555743 A JP 2018555743A JP 2018555743 A JP2018555743 A JP 2018555743A JP 2019521408 A5 JP2019521408 A5 JP 2019521408A5
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JP
Japan
Prior art keywords
cache
request
thread
access
sampling
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JP2018555743A
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English (en)
Japanese (ja)
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JP6701380B2 (ja
JP2019521408A (ja
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Priority claimed from US15/180,806 external-priority patent/US10073785B2/en
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Publication of JP2019521408A5 publication Critical patent/JP2019521408A5/ja
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Publication of JP6701380B2 publication Critical patent/JP6701380B2/ja
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JP2018555743A 2016-06-13 2016-09-15 アップ／ダウンプリフェッチャ Active JP6701380B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/180,806 US10073785B2 (en) 2016-06-13 2016-06-13 Up/down prefetcher
US15/180,806 2016-06-13
PCT/US2016/051850 WO2017218025A1 (en) 2016-06-13 2016-09-15 Up/down prefetcher

Publications (3)

Publication Number Publication Date
JP2019521408A JP2019521408A (ja) 2019-07-25
JP2019521408A5 true JP2019521408A5 (enExample) 2019-10-24
JP6701380B2 JP6701380B2 (ja) 2020-05-27

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ID=60572679

Family Applications (1)

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JP2018555743A Active JP6701380B2 (ja) 2016-06-13 2016-09-15 アップ／ダウンプリフェッチャ

Country Status (5)

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US (1) US10073785B2 (enExample)
JP (1) JP6701380B2 (enExample)
KR (1) KR102464788B1 (enExample)
CN (1) CN109196487B (enExample)
WO (1) WO2017218025A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6627629B2 (ja) * 2016-04-14 2020-01-08 富士通株式会社 演算処理装置、および演算処理装置の制御方法
WO2019127487A1 (zh) 2017-12-29 2019-07-04 华为技术有限公司 一种数据预取方法、装置和存储设备
US10963249B2 (en) * 2018-11-02 2021-03-30 International Business Machines Corporation Processor prefetcher mode governor for switching between prefetch modes
US20210182214A1 (en) * 2019-12-17 2021-06-17 Advanced Micro Devices, Inc. Prefetch level demotion
CN114625672A (zh) * 2020-12-11 2022-06-14 超威半导体(上海)有限公司 用于快速数据访问的统一高速缓存系统
KR102874947B1 (ko) * 2025-05-23 2025-10-23 주식회사 블루타일랩 영상 처리 초기 지연 방지를 위한 지능형 웜업 시스템 및 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484239B1 (en) 1997-12-29 2002-11-19 Intel Corporation Prefetch queue
US6275918B1 (en) 1999-03-16 2001-08-14 International Business Machines Corporation Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold
US6643743B1 (en) * 2000-03-31 2003-11-04 Intel Corporation Stream-down prefetching cache
US6907520B2 (en) 2001-01-11 2005-06-14 Sun Microsystems, Inc. Threshold-based load address prediction and new thread identification in a multithreaded microprocessor
US7238218B2 (en) * 2004-04-06 2007-07-03 International Business Machines Corporation Memory prefetch method and system
US20070239940A1 (en) * 2006-03-31 2007-10-11 Doshi Kshitij A Adaptive prefetching
JP2008102745A (ja) * 2006-10-19 2008-05-01 Toshiba Corp 命令キャッシュメモリのプリフェッチ機構
US8914617B2 (en) * 2009-12-26 2014-12-16 Intel Corporation Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register
US8762649B2 (en) 2010-03-29 2014-06-24 Via Technologies, Inc. Bounding box prefetcher
US8291172B2 (en) * 2010-04-27 2012-10-16 Via Technologies, Inc. Multi-modal data prefetcher
US8583894B2 (en) 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US8909866B2 (en) * 2012-11-06 2014-12-09 Advanced Micro Devices, Inc. Prefetching to a cache based on buffer fullness
CN103226521B (zh) * 2013-04-18 2016-03-02 浙江大学 多模式数据预取装置及其管理方法
GB2515076B (en) 2013-06-13 2020-07-15 Advanced Risc Mach Ltd A data processing apparatus and method for handling retrieval of instructions from an instruction cache

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