JP6701380B2 - アップ／ダウンプリフェッチャ - Google Patents

アップ／ダウンプリフェッチャ Download PDF

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Publication number
JP6701380B2
JP6701380B2 JP2018555743A JP2018555743A JP6701380B2 JP 6701380 B2 JP6701380 B2 JP 6701380B2 JP 2018555743 A JP2018555743 A JP 2018555743A JP 2018555743 A JP2018555743 A JP 2018555743A JP 6701380 B2 JP6701380 B2 JP 6701380B2
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Japan
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cache
request
access
cache line
prefetch
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JP2018555743A
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English (en)
Japanese (ja)
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JP2019521408A (ja
JP2019521408A5 (enExample
Inventor
エヴァン ジョーンズ ３世 ウィリアム
エヴァン ジョーンズ ３世 ウィリアム
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2019521408A5 publication Critical patent/JP2019521408A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6026—Prefetching based on access pattern detection, e.g. stride based prefetch

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2018555743A 2016-06-13 2016-09-15 アップ／ダウンプリフェッチャ Active JP6701380B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/180,806 US10073785B2 (en) 2016-06-13 2016-06-13 Up/down prefetcher
US15/180,806 2016-06-13
PCT/US2016/051850 WO2017218025A1 (en) 2016-06-13 2016-09-15 Up/down prefetcher

Publications (3)

Publication Number Publication Date
JP2019521408A JP2019521408A (ja) 2019-07-25
JP2019521408A5 JP2019521408A5 (enExample) 2019-10-24
JP6701380B2 true JP6701380B2 (ja) 2020-05-27

Family

ID=60572679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018555743A Active JP6701380B2 (ja) 2016-06-13 2016-09-15 アップ／ダウンプリフェッチャ

Country Status (5)

Country Link
US (1) US10073785B2 (enExample)
JP (1) JP6701380B2 (enExample)
KR (1) KR102464788B1 (enExample)
CN (1) CN109196487B (enExample)
WO (1) WO2017218025A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6627629B2 (ja) * 2016-04-14 2020-01-08 富士通株式会社 演算処理装置、および演算処理装置の制御方法
WO2019127487A1 (zh) 2017-12-29 2019-07-04 华为技术有限公司 一种数据预取方法、装置和存储设备
US10963249B2 (en) * 2018-11-02 2021-03-30 International Business Machines Corporation Processor prefetcher mode governor for switching between prefetch modes
US20210182214A1 (en) * 2019-12-17 2021-06-17 Advanced Micro Devices, Inc. Prefetch level demotion
CN114625672A (zh) * 2020-12-11 2022-06-14 超威半导体(上海)有限公司 用于快速数据访问的统一高速缓存系统
KR102874947B1 (ko) * 2025-05-23 2025-10-23 주식회사 블루타일랩 영상 처리 초기 지연 방지를 위한 지능형 웜업 시스템 및 방법

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6484239B1 (en) 1997-12-29 2002-11-19 Intel Corporation Prefetch queue
US6275918B1 (en) 1999-03-16 2001-08-14 International Business Machines Corporation Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold
US6643743B1 (en) * 2000-03-31 2003-11-04 Intel Corporation Stream-down prefetching cache
US6907520B2 (en) 2001-01-11 2005-06-14 Sun Microsystems, Inc. Threshold-based load address prediction and new thread identification in a multithreaded microprocessor
US7238218B2 (en) * 2004-04-06 2007-07-03 International Business Machines Corporation Memory prefetch method and system
US20070239940A1 (en) * 2006-03-31 2007-10-11 Doshi Kshitij A Adaptive prefetching
JP2008102745A (ja) * 2006-10-19 2008-05-01 Toshiba Corp 命令キャッシュメモリのプリフェッチ機構
US8914617B2 (en) * 2009-12-26 2014-12-16 Intel Corporation Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register
US8762649B2 (en) 2010-03-29 2014-06-24 Via Technologies, Inc. Bounding box prefetcher
US8291172B2 (en) * 2010-04-27 2012-10-16 Via Technologies, Inc. Multi-modal data prefetcher
US8583894B2 (en) 2010-09-09 2013-11-12 Advanced Micro Devices Hybrid prefetch method and apparatus
US8909866B2 (en) * 2012-11-06 2014-12-09 Advanced Micro Devices, Inc. Prefetching to a cache based on buffer fullness
CN103226521B (zh) * 2013-04-18 2016-03-02 浙江大学 多模式数据预取装置及其管理方法
GB2515076B (en) 2013-06-13 2020-07-15 Advanced Risc Mach Ltd A data processing apparatus and method for handling retrieval of instructions from an instruction cache

Also Published As

Publication number Publication date
US20170357587A1 (en) 2017-12-14
WO2017218025A1 (en) 2017-12-21
US10073785B2 (en) 2018-09-11
CN109196487B (zh) 2020-07-14
KR102464788B1 (ko) 2022-11-08
JP2019521408A (ja) 2019-07-25
KR20190008274A (ko) 2019-01-23
CN109196487A (zh) 2019-01-11

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