JP2019511045A5 - - Google Patents
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- Publication number
- JP2019511045A5 JP2019511045A5 JP2018545297A JP2018545297A JP2019511045A5 JP 2019511045 A5 JP2019511045 A5 JP 2019511045A5 JP 2018545297 A JP2018545297 A JP 2018545297A JP 2018545297 A JP2018545297 A JP 2018545297A JP 2019511045 A5 JP2019511045 A5 JP 2019511045A5
- Authority
- JP
- Japan
- Prior art keywords
- write
- write address
- cache
- address
- execution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 15
- 238000006243 chemical reaction Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/057,121 US20170255569A1 (en) | 2016-03-01 | 2016-03-01 | Write-allocation for a cache based on execute permissions |
| US15/057,121 | 2016-03-01 | ||
| PCT/US2017/016971 WO2017151280A1 (en) | 2016-03-01 | 2017-02-08 | Write-allocation for a cache based on execute permissions |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019511045A JP2019511045A (ja) | 2019-04-18 |
| JP2019511045A5 true JP2019511045A5 (enExample) | 2020-03-05 |
| JP6960933B2 JP6960933B2 (ja) | 2021-11-05 |
Family
ID=58018350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018545297A Active JP6960933B2 (ja) | 2016-03-01 | 2017-02-08 | 実行許可に基づくキャッシュのライトアロケーション（Ｗｒｉｔｅ−Ａｌｌｏｃａｔｉｏｎ） |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20170255569A1 (enExample) |
| EP (1) | EP3423946B1 (enExample) |
| JP (1) | JP6960933B2 (enExample) |
| KR (1) | KR102846691B1 (enExample) |
| CN (1) | CN108604210B (enExample) |
| ES (1) | ES2903162T3 (enExample) |
| SG (1) | SG11201806067SA (enExample) |
| TW (1) | TW201734807A (enExample) |
| WO (1) | WO2017151280A1 (enExample) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10114768B2 (en) * | 2016-08-29 | 2018-10-30 | Intel Corporation | Enhance memory access permission based on per-page current privilege level |
| US10713177B2 (en) | 2016-09-09 | 2020-07-14 | Intel Corporation | Defining virtualized page attributes based on guest page attributes |
| US11010309B2 (en) * | 2018-05-18 | 2021-05-18 | Intel Corporation | Computer system and method for executing one or more software applications, host computer device and method for a host computer device, memory device and method for a memory device and non-transitory computer readable medium |
| CN111124267B (zh) * | 2018-10-31 | 2023-10-31 | 伊姆西Ip控股有限责任公司 | 数据写入的方法、设备和计算机程序产品 |
| US11360905B2 (en) * | 2019-05-24 | 2022-06-14 | Texas Instmments Incorporated | Write merging on stores with different privilege levels |
| CN112559389B (zh) * | 2019-09-25 | 2025-02-25 | 阿里巴巴集团控股有限公司 | 存储控制装置、处理装置、计算机系统和存储控制方法 |
| WO2021103020A1 (zh) * | 2019-11-29 | 2021-06-03 | 华为技术有限公司 | 缓存存储器和分配写操作的方法 |
| CN111831587A (zh) * | 2020-04-17 | 2020-10-27 | 北京奕斯伟计算技术有限公司 | 数据写入方法、装置和电子设备 |
| US20220194366A1 (en) * | 2020-12-22 | 2022-06-23 | Mobileye Vision Technologies Ltd. | Access control mechanism in cache coherent integrated circuit |
| US12093181B2 (en) * | 2022-06-28 | 2024-09-17 | Advanced Micro Devices, Inc. | Allocation control for cache |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606687A (en) * | 1993-10-07 | 1997-02-25 | Sun Microsystems, Inc. | Method and apparatus for optimizing supervisor mode store operations in a data cache |
| EP0651332B1 (en) * | 1993-10-29 | 2001-07-18 | Advanced Micro Devices, Inc. | Linearly addressable microprocessor cache |
| US6119151A (en) * | 1994-03-07 | 2000-09-12 | International Business Machines Corp. | System and method for efficient cache management in a distributed file system |
| US6263407B1 (en) * | 1998-02-17 | 2001-07-17 | International Business Machines Corporation | Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode |
| EP0989496B1 (en) * | 1998-09-01 | 2005-04-27 | Texas Instruments Incorporated | Improved memory hierarchy for processors and coherence protocol therefor |
| US6412043B1 (en) * | 1999-10-01 | 2002-06-25 | Hitachi, Ltd. | Microprocessor having improved memory management unit and cache memory |
| JP2003044358A (ja) * | 2001-07-31 | 2003-02-14 | Mitsubishi Electric Corp | キャッシュメモリ制御装置 |
| EP1304620A1 (en) * | 2001-10-17 | 2003-04-23 | Texas Instruments Incorporated | Cache with selective write allocation |
| US6990502B2 (en) * | 2003-02-26 | 2006-01-24 | Microsoft Corporation | Reviewing cached user-group information in connection with issuing a digital rights management (DRM) license for content |
| US7437510B2 (en) * | 2005-09-30 | 2008-10-14 | Intel Corporation | Instruction-assisted cache management for efficient use of cache and memory |
| US20070079070A1 (en) * | 2005-09-30 | 2007-04-05 | Arm Limited | Cache controller |
| US7805588B2 (en) * | 2005-10-20 | 2010-09-28 | Qualcomm Incorporated | Caching memory attribute indicators with cached memory data field |
| US8606998B2 (en) * | 2006-08-24 | 2013-12-10 | Advanced Micro Devices, Inc. | System and method for instruction-based cache allocation policies |
| US7949834B2 (en) * | 2007-01-24 | 2011-05-24 | Qualcomm Incorporated | Method and apparatus for setting cache policies in a processor |
| US8275971B2 (en) * | 2008-08-27 | 2012-09-25 | International Business Machines Corporation | Method and apparatus for managing software controlled cache of translating the physical memory access of a virtual machine between different levels of translation entities |
| US8621184B1 (en) * | 2008-10-31 | 2013-12-31 | Netapp, Inc. | Effective scheduling of producer-consumer processes in a multi-processor system |
| US8621149B2 (en) * | 2009-12-23 | 2013-12-31 | Intel Corporation | Controlling access to a cache memory using privilege level information |
| US8504777B2 (en) * | 2010-09-21 | 2013-08-06 | Freescale Semiconductor, Inc. | Data processor for processing decorated instructions with cache bypass |
| US20130179642A1 (en) * | 2012-01-10 | 2013-07-11 | Qualcomm Incorporated | Non-Allocating Memory Access with Physical Address |
| US9158685B2 (en) * | 2012-09-11 | 2015-10-13 | Apple Inc. | System cache with cache hint control |
| US8819342B2 (en) * | 2012-09-26 | 2014-08-26 | Qualcomm Incorporated | Methods and apparatus for managing page crossing instructions with different cacheability |
| GB2526849B (en) * | 2014-06-05 | 2021-04-14 | Advanced Risc Mach Ltd | Dynamic cache allocation policy adaptation in a data processing apparatus |
| US9335943B2 (en) * | 2014-06-30 | 2016-05-10 | Intel Corporation | Method and apparatus for fine grain memory protection |
| US9767040B2 (en) * | 2015-08-31 | 2017-09-19 | Salesforce.Com, Inc. | System and method for generating and storing real-time analytics metric data using an in memory buffer service consumer framework |
-
2016
- 2016-03-01 US US15/057,121 patent/US20170255569A1/en not_active Abandoned
-
2017
- 2017-02-08 KR KR1020187024970A patent/KR102846691B1/ko active Active
- 2017-02-08 JP JP2018545297A patent/JP6960933B2/ja active Active
- 2017-02-08 EP EP17705003.6A patent/EP3423946B1/en active Active
- 2017-02-08 SG SG11201806067SA patent/SG11201806067SA/en unknown
- 2017-02-08 WO PCT/US2017/016971 patent/WO2017151280A1/en not_active Ceased
- 2017-02-08 ES ES17705003T patent/ES2903162T3/es active Active
- 2017-02-08 CN CN201780010875.1A patent/CN108604210B/zh active Active
- 2017-02-24 TW TW106106528A patent/TW201734807A/zh unknown
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