KR102846691B1 - 실행 허가들에 기반하는 캐시에 대한 기입-할당 - Google Patents

실행 허가들에 기반하는 캐시에 대한 기입-할당

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Publication number
KR102846691B1
KR102846691B1 KR1020187024970A KR20187024970A KR102846691B1 KR 102846691 B1 KR102846691 B1 KR 102846691B1 KR 1020187024970 A KR1020187024970 A KR 1020187024970A KR 20187024970 A KR20187024970 A KR 20187024970A KR 102846691 B1 KR102846691 B1 KR 102846691B1
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write
cache
address
execution
permissions
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KR20180117629A (ko
Inventor
토마스 앤드류 사토리우스
제임스 노리스 디펜더퍼
마이클 윌리엄 모로우
제프리 토드 브리지스
마이클 스캇 맥클베인
로드니 웨인 스미스
케니스 앨런 닥서
토마스 필립 스피어
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퀄컴 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G06F2212/6046—Using a specific cache allocation policy other than replacement policy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62—Details of cache specific to multiprocessor cache arrangements
    • G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/684—TLB miss handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Storage Device Security (AREA)
KR1020187024970A 2016-03-01 2017-02-08 실행 허가들에 기반하는 캐시에 대한 기입-할당 Active KR102846691B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/057,121 US20170255569A1 (en) 2016-03-01 2016-03-01 Write-allocation for a cache based on execute permissions
US15/057,121 2016-03-01
PCT/US2017/016971 WO2017151280A1 (en) 2016-03-01 2017-02-08 Write-allocation for a cache based on execute permissions

Publications (2)

Publication Number Publication Date
KR20180117629A KR20180117629A (ko) 2018-10-29
KR102846691B1 true KR102846691B1 (ko) 2025-08-13

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Country Status (9)

Country Link
US (1) US20170255569A1 (enExample)
EP (1) EP3423946B1 (enExample)
JP (1) JP6960933B2 (enExample)
KR (1) KR102846691B1 (enExample)
CN (1) CN108604210B (enExample)
ES (1) ES2903162T3 (enExample)
SG (1) SG11201806067SA (enExample)
TW (1) TW201734807A (enExample)
WO (1) WO2017151280A1 (enExample)

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US10114768B2 (en) * 2016-08-29 2018-10-30 Intel Corporation Enhance memory access permission based on per-page current privilege level
US10713177B2 (en) 2016-09-09 2020-07-14 Intel Corporation Defining virtualized page attributes based on guest page attributes
US11010309B2 (en) * 2018-05-18 2021-05-18 Intel Corporation Computer system and method for executing one or more software applications, host computer device and method for a host computer device, memory device and method for a memory device and non-transitory computer readable medium
CN111124267B (zh) * 2018-10-31 2023-10-31 伊姆西Ip控股有限责任公司 数据写入的方法、设备和计算机程序产品
US11360905B2 (en) * 2019-05-24 2022-06-14 Texas Instmments Incorporated Write merging on stores with different privilege levels
CN112559389B (zh) * 2019-09-25 2025-02-25 阿里巴巴集团控股有限公司 存储控制装置、处理装置、计算机系统和存储控制方法
WO2021103020A1 (zh) * 2019-11-29 2021-06-03 华为技术有限公司 缓存存储器和分配写操作的方法
CN111831587A (zh) * 2020-04-17 2020-10-27 北京奕斯伟计算技术有限公司 数据写入方法、装置和电子设备
US20220194366A1 (en) * 2020-12-22 2022-06-23 Mobileye Vision Technologies Ltd. Access control mechanism in cache coherent integrated circuit
US12093181B2 (en) * 2022-06-28 2024-09-17 Advanced Micro Devices, Inc. Allocation control for cache

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US5623619A (en) 1993-10-29 1997-04-22 Advanced Micro Devices, Inc. Linearly addressable microprocessor cache
US20030101320A1 (en) * 2001-10-17 2003-05-29 Gerard Chauvel Cache with selective write allocation
US20070094475A1 (en) * 2005-10-20 2007-04-26 Bridges Jeffrey T Caching memory attribute indicators with cached memory data field
US20080052466A1 (en) 2006-08-24 2008-02-28 Advanced Micro Devices, Inc. System and method for instruction-based cache allocation policies

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US5623619A (en) 1993-10-29 1997-04-22 Advanced Micro Devices, Inc. Linearly addressable microprocessor cache
US20030101320A1 (en) * 2001-10-17 2003-05-29 Gerard Chauvel Cache with selective write allocation
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US20080052466A1 (en) 2006-08-24 2008-02-28 Advanced Micro Devices, Inc. System and method for instruction-based cache allocation policies

Also Published As

Publication number Publication date
EP3423946B1 (en) 2021-12-15
WO2017151280A1 (en) 2017-09-08
JP2019511045A (ja) 2019-04-18
TW201734807A (zh) 2017-10-01
CN108604210B (zh) 2022-08-19
EP3423946A1 (en) 2019-01-09
BR112018067341A2 (pt) 2019-01-08
KR20180117629A (ko) 2018-10-29
SG11201806067SA (en) 2018-09-27
US20170255569A1 (en) 2017-09-07
JP6960933B2 (ja) 2021-11-05
HK1254828A1 (zh) 2019-07-26
CN108604210A (zh) 2018-09-28
ES2903162T3 (es) 2022-03-31

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