JP2019200732A - Data processing device, bandwidth guarantee method in data processing device, and program - Google Patents

Abstract

To allocate bandwidth efficiently to each bus master while guaranteeing the bandwidth of each bus master which requires bandwidth guarantee.SOLUTION: Disclosed is a data processing device which includes the steps of: detecting a bandwidth indicating the degree of access to the bus by each bus master; comparing a threshold set as a bandwidth threshold with the detected bandwidth; determining the priority of each bus master based on the comparison; and arbitrating the access request of each bus master based on the determined priority.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a data processing device, a bandwidth guarantee method in the data processing device, and a program.

  In recent years, with the speeding up of the electrophotographic process, the processing speed requirement of the controller of the digital multi-function peripheral is increasing. Further, along with the evolution of semiconductor processes, various image processing functions such as scanning, printing, and rendering and system control functions are integrated into one chip as SoC (System on Chip). Similarly, memories such as DRAMs connected to the SoC have been integrated into one chip. Therefore, a large number of functions access a single memory simultaneously and at high speed, and the memory bandwidth is tight.

  However, even in such a situation, it is required to guarantee a memory bandwidth necessary for processing in processing that requires real-time properties such as scan image processing, print image processing, and UI drawing processing. As a method for guaranteeing a memory bandwidth for real-time processing, a method of arbitrating access of a bus master connected to a memory via a system bus based on the priority of each bus master is well known. That is, by adding a high priority to a bus master that requires bandwidth guarantee, the bus master can use the memory bandwidth preferentially.

  By the way, in order to increase the productivity of the digital multi-function peripheral, it is required to prevent the processing speed of the entire system from being lowered by providing a memory bandwidth as much as possible even in non-real-time processing. However, in the bus arbitration to which the above-described priority is added, there is a possibility that the bus master for real-time processing to which the high priority is added occupies a memory band even during its own operation. .

  Conventionally, for example, Patent Document 1 describes a technique for restricting access by a bus master set to a high priority when such a problem occupies a certain band or more when the band occupies a certain bandwidth or more. ing. By adopting such a method, it is possible to efficiently access memory even to low-priority bus masters that perform non-real-time processing while guaranteeing the bandwidth of high-priority bus masters that perform real-time processing and the like. It becomes.

JP 2014-160341 A

  However, in recent integrated memory and bus systems, there are multiple real-time bus masters at the same time. Therefore, simply adding priority as in the prior art guarantees bandwidth when there is an access conflict between high-priority bus masters. It may not be possible.

  On the other hand, since the buffer memory capacity of an SRAM or the like mounted on the SoC has increased, even a bus master for real-time processing can suppress the occupied memory bandwidth depending on the buffer availability. However, the conventional bus system in which the priority is fixed has a problem that the memory bandwidth cannot be efficiently allocated in accordance with the operation status of each bus master.

  An object of the present invention is to solve at least one of the problems of the prior art.

  An object of the present invention is to provide a technique capable of efficiently allocating a bandwidth to each bus master while guaranteeing a bandwidth of access to the bus by a plurality of bus masters.

In order to achieve the above object, a data processing apparatus according to an aspect of the present invention has the following arrangement. That is,
A data processing device,
Band detection means for detecting a band indicating the degree of access to the bus by each bus master;
Setting means for setting a threshold of the band;
A comparing means for comparing the threshold set by the setting means with the band detected by the band detecting means;
Arbitration means for determining the priority of each bus master based on the comparison by the comparison means and arbitrating the access request of each bus master based on the determined priority.

  According to the present invention, there is an effect that a bandwidth can be efficiently allocated to each bus master while guaranteeing a bandwidth of access to the bus by a plurality of bus masters.

  Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar components are denoted by the same reference numerals.

The accompanying drawings are included in the specification, constitute a part thereof, show an embodiment of the present invention, and are used together with the description to explain the principle of the present invention.
The block diagram explaining the structure of the controller (control part) of the data processor which concerns on embodiment. The block diagram explaining the structure of the priority control part which concerns on embodiment. The block diagram explaining the structure of the arbiter which concerns on embodiment. The figure which shows the threshold value example of the zone | band set in the threshold value setting part which concerns on embodiment. 6 is a flowchart for explaining a procedure of priority control by a priority control unit according to the embodiment. 6 is a flowchart for explaining processing for determining the priority in S505 of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments do not limit the present invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the present invention. .

  FIG. 1 is a block diagram illustrating a configuration of a controller (control unit) 180 of the data processing apparatus according to the embodiment.

  The memory controller 190 is a controller for controlling the memory 191 functioning as a work memory for system control of the controller 180 and data processing. The CPU 101 is a processor that controls the entire system of the data processing apparatus, and performs data processing in response to a user operation instruction from a UI (user interface) 105 or a job execution command from an external apparatus (not shown) on the LAN 104. Control the device centrally. A UIC (user interface controller) 102 notifies the CPU 101 of operation acceptance from the UI 105. A LANC (network control unit) 103 transmits and receives network packets on the LAN 104. The register IF (interface) 106 is an interface for register setting and the like for each module in the controller 180. The CPU 101 performs register setting for each module via the interconnect 100 and the register IF 106. The interconnect 100 arbitrates bus access from the CPU 101, UIC 102, and LANC 103 by a round robin method or the like, and then accesses the memory 191 or the register IF 106 in accordance with address information.

  The scanner 111 reads an image of a document using a line sensor and outputs image data obtained thereby to the scanner IF 112 together with a synchronization signal. The scanner IF 112 receives the image data in synchronization with the synchronization signal, and outputs it to the subsequent module. Further, the scanner IF 112 instructs the scanner 111 to start reading an image according to the control from the CPU 101. The correction processing unit 113 performs image correction processing such as shading correction, MTF correction, and gamma correction on the image data obtained by the scanner 111 reading. The compression unit 114 compresses image data by an encoding process such as JPEG. The DMAC 110 writes the image data compressed by the compression unit 114 to the work area secured in the memory 191 by the CPU 101 by DMA.

  Here, a series of data processing by the scanner IF 112, the correction processing unit 113, the compression unit 114, and the DMAC 110 is real-time processing performed in accordance with the image reading operation of the scanner 111. That is, after the original reading start instruction from the CPU 101, the scanner 111 performs an image reading operation independently. Therefore, it is necessary for the speed of a series of data processing to exceed the speed of image data input from the scanner 111, and when the processing speed falls, image data disappears (overrun). More specifically, when the internal SRAM buffer (not shown) of the series of processing modules 112 to 114 is full and the DMAC 110 cannot output image data, overrun occurs when new image data is input from the scanner 111. . Here, the situation where the DMAC 110 cannot output image data indicates that the arbiter 160 is waiting for an access request from the DMAC 110 to the memory 191. As a factor for waiting for access from the DMAC 111, there is memory access by other bus masters. The arbiter 160 will be described in detail with reference to FIG.

  The renderer 121 renders PDL (Print Description Language) input from an external device (not shown) on the LAN 104 by RIP (Raster Image Processing). The compression unit 122 compresses the rendered image data. The DMAC 120 reads the PDL expanded on the memory 191 by the CPU 101 and writes back the compressed rendering image data to a predetermined area of the memory 191. A series of data processing by the renderer 121 and the compression unit 122 is non-real time processing. However, in order to improve productivity as a data processing apparatus, it is desirable that the memory 191 can be accessed at high speed in the series of rendering processes.

  The disk IF 131 spools the above-described compressed scanned image data or rendered image data from the memory 191 to the disk 132 via the DMAC 130. The spooled compressed data is expanded in the memory 191 again.

  The decompressing unit 141 reads and decompresses the compressed data expanded in the memory 191 via the DMAC 140. The conversion processing unit 142 is a color space conversion process that converts an arbitrary color space such as RGB or YUV to a CMYK color space, or a halftone that converts gradation representation of image data from density gradation to area gradation. Processing is performed to generate image data for printing. The printer 144 is, for example, a tandem electrophotographic printer engine, and has, for example, four photosensitive drums (not shown) arranged in the order of Y, M, C, and K. The printer IF 143 transfers the image data for printing to the printer 144 according to the synchronization signal from the printer 144. The printer 144 shifts the exposure timing in advance in the order of M, C, and K in order from Y that first transfers the toner image to the transfer body, so that the time difference until the transfer body reaches each photosensitive drum, That is, the color shift is absorbed. Therefore, the printer IF 143 once writes the print image data to the memory 191 via the DMAC 150, and then reads the print image data by shifting the timing for each color plate in the order of Y, M, C, and K. The data is output to the printer 144.

  Here, a series of processing by the decompression unit 141, the conversion processing unit 142, the printer IF 143, and the DMACs 140 and 150 is real-time processing performed in accordance with an image data transfer request from the printer 144. Therefore, a series of data processing speeds must be higher than the image data transfer request from the printer 144, and if the processing speed falls, image data disappears (underrun). As in the case of the scan processing described above, the state of the internal SRAM buffer (not shown) of the series of processing modules 141 to 143 and the extent to which the access request of the DMACs 140 and 150 is waited are the factors causing the underrun. In the printing process, since the printing image data can be spooled to the memory 191 once, it is particularly important whether the reading of the printing image data by the DMAC 150 is in time for the image data transfer request of the printer 144.

  The priority control unit 170 monitors the bus transaction of each bus master (M0 to M5) connected to the memory controller 190 via the arbiter 160 and performs priority control on the arbiter 160.

  FIG. 2 is a block diagram illustrating the configuration of the priority control unit 170 according to the embodiment.

  The band detection unit 200 monitors the bus transaction of each bus master (M0 to M5), and calculates a band indicating the degree to which each bus master accesses the bus. The bus bandwidth is calculated by totaling the number of transfer bytes of the established transactions within the measurement period set by the CPU 101 in advance. The bandwidth value calculated in this way is an average transfer amount per fixed period. Further, by continuously updating this transfer amount for each cycle, the moving average of the data transfer amount of the bus master during execution of a certain job (for example, copying or printing) is calculated. Alternatively, it may be updated at specific intervals instead of updating every cycle. The band detection unit 200 starts the band detection when the CPU 101 instructs the start. Note that the bandwidth detection unit 200 may perform bandwidth detection for each read and write channel as long as the read protocol and the write channel are separate bus protocols.

  The threshold setting unit 210 sets a bandwidth threshold for each bus master or each channel by the CPU 101. The threshold setting unit 210 will be described in detail with reference to FIG. The comparison unit 220 compares the bus bandwidth detected for each bus master or for each channel with the threshold set in the threshold setting unit 210. The priority determination unit 230 determines the priority of each bus master or each channel based on the comparison result of the comparison unit 220 and notifies the arbiter 160 of the priority. A control flow for determining the priority from the detection of the bus bandwidth by the priority control unit 170 will be described in detail with reference to FIG.

  FIG. 3 is a block diagram illustrating the configuration of the arbiter 160 according to the embodiment.

  The arbiter 160 has three levels of priority from “# 0” to “# 2” as priorities that can be assigned to each bus master. In the embodiment, the priority “# 0” is the highest priority, and the priority “# 2” is the lowest priority. The arbiter 160 has queues 310, 311 and 312 corresponding to the priorities “# 0” to “# 2”, respectively. The switch 300 distributes access requests from the bus masters (M0 to M5) to the queues 310 to 312 according to the priority set by the priority control unit 170. The queues 310 to 312 include multi-stage FIFOs for queuing access requests.

  In the embodiment, the queues 310 to 312 are configured to include a FIFO in the embodiment. However, for access requests having the same priority, the order in which the queues are queued by the round robin method or the like is not used for the FIFO. Mediation may be performed. Further, the number of stages in the queue may be different for each priority.

  When a bus access request occurs, the access request is accepted if the queue is not full, and the access request is not accepted if the queue is full. For bus masters having the same priority, it is possible to accept access requests evenly, which means that the bandwidth is equally allocated to bus masters having the same priority. However, how much bandwidth can be obtained in actual data transfer depends on the frequency with which the bus master issues an access request and the amount of data included in one access request.

  In some bus masters, an access request is not accepted, in other words, a state where access is awaited. In this state, if the internal SRAM buffer of the bus master (for example, DMAC 110 to compression unit 114) performing processing in the pipeline becomes full, pipeline installation occurs. Further, as described above, if there is a new data input or data transfer request from the scanner 111 or the printer 144, an overrun or underrun is caused.

  If the access request can be accepted, the memory controller 190 notifies the request indicating that the access request queued for any of the queues can be accepted via the selector 320. Upon receiving a request from the memory controller 190, each queue reads the queued access request and transfers it to the memory controller 190 if it is not empty. The selector 320 does not notify the request from the memory controller 190 to the low priority queue unless the high priority queue is empty. That is, the queue 310 having the highest priority can receive a request notification from the memory controller 190 regardless of the state of the other low priority queues. On the other hand, the low priority queues 311 and 312 cannot receive a request notification from the memory controller 190 unless all the queues with higher priority than the queues are empty. Note that the configuration of the arbiter shown in FIG. 3 is merely an example, and is not limited to the configuration of the embodiment.

  FIG. 4 is a diagram illustrating an example of a bandwidth threshold set in the threshold setting unit 210 according to the embodiment. 4A to 4D show examples of threshold setting, and a lower threshold and an upper threshold for each bus master are set. The upper limit threshold is an upper limit use bandwidth allowed for a certain bus master, and the lower limit threshold is a minimum bandwidth guaranteed for a certain bus master. The priority control unit 170 dynamically controls the priority of the bus master so that the used bandwidth of each bus master falls within the upper and lower thresholds.

  FIG. 4A is a diagram illustrating a first setting example of the band threshold value.

  In FIG. 4A, a lower limit threshold and an upper limit threshold are set for each master (M0 to M5). As an example, the lower threshold is set to a low value “0” for a bus master for non-real-time processing, such as rendering M2. On the other hand, even in the case of a bus master for non-real-time processing, a high value is set as the upper limit threshold so that the productivity of the data processing apparatus is not lowered. For masters that perform real-time processing, such as scan M1 and printer M5, the bandwidth is guaranteed by setting the lower threshold value to a high value. The values that are actually set are values that add some margin to the data transfer rate required by the scanner 111 and the printer 144, the throughput of each module, the SRAM buffer capacity of each module, and the like. . A bus master (for example, M5) set with a lower threshold value larger than 0 [MB / s], when the bandwidth detected by the bandwidth detector 200 falls below the lower threshold, the priority determiner 230 sets the priority of the bus master M5. Raised dynamically. When the priority increases, it becomes possible to issue an access request with priority to the other bus masters M0 to M4, thereby guaranteeing a minimum bandwidth value.

  In the case of performing the control as described above, if the period in which the bus master M5 has not issued an access request continues, the priority will endlessly increase. However, if the access request is not issued when the priority of the bus master M5 is increased, the situation does not cause a situation in which the bandwidth of the other bus masters M0 to M4 is tightened. Alternatively, the priority determination unit 230 may change the priority only for a bus master in which a valid transaction has occurred.

  The bus master M5 whose priority has been raised may temporarily or chronically occupy a band that is higher than the band that is originally required depending on the operation state and the state of the internal SRAM buffer. For example, in order to fill the empty space in the internal SRAM buffer of the printer IF 143, a read access request is issued more than necessary. Therefore, when the use bandwidth of the bus master M5 exceeds the upper limit threshold, the priority control unit 170 dynamically lowers the priority of the bus master M5. Thereby, the priority of the bus master M5 becomes equal to the other bus masters M0 to M4. As a result, the memory band occupied by the bus master M5 is also assigned to other bus masters. Also, if the bandwidth used is below the lower limit value among other bus masters (for example, M1), the priority of the bus master M1 is dynamically raised. In this way, the priority control unit 170 dynamically switches the priority so that the bus master with insufficient bandwidth has a high priority.

  4B to 4D show other setting examples of threshold values. In any example, the upper limit threshold and the lower limit threshold are set in the same manner as in FIG.

  FIG. 4B shows an example in which the upper threshold and the lower threshold are set to have a plurality of thresholds. In the embodiment, two values, the intermediate threshold value and the maximum threshold value, are set. Regarding the values underlined with bold lines in the drawing, the intermediate threshold value and the maximum threshold value are set to different values for the bus master M5. Weights are given to the intermediate threshold value and the maximum threshold value, respectively.

  The priority control unit 170 changes the priority of the bus master M5 according to the weight when the bus master M5 exceeds the range of the upper threshold and the lower threshold. For example, when the weight exceeds the range of the intermediate threshold value “1”, the priority is changed by one level. Furthermore, when the range of the maximum threshold value having a weight of “2” is exceeded, the priority is changed in two steps. Thus, by setting threshold values in stages, priority control by the priority control unit 170 can be performed more finely.

  4C to 4D are examples in which an upper limit and a lower limit threshold are set for each condition type.

  In FIG. 4C, the type of access request is set as the condition type, and each has an upper limit and a lower limit threshold depending on whether it is a read request or a write request. For example, for the bus master M5, the print image data is spooled to some extent in the memory 191, so there may be no problem even if the write request is delayed. In such a case, the write request bandwidth is set to be lowered.

  FIG. 4D is an example in which two periods are set as the condition type, and the upper limit and the lower limit threshold are switched in each period. For example, for the two real-time processing bus masters M1 and M5, the total value of the bus masters M1 and M5 in each period is set to be a certain value or less. As a result, the bandwidth allocated to the bus masters M1 and M5 can be time-division multiplexed. Further, the above two periods are set in consideration of the internal SRAM buffer capacity of each module, the image reading speed of the scanner 111 and the printer 144, the printing speed, and the like. As a result, it is possible to perform control so that the total bandwidth of the bus masters M1 and M5 does not exceed the allowable bandwidth of the memory 191.

  As described above, as shown in FIGS. 4A to 4D, several setting methods are conceivable for the upper limit and the lower limit threshold. When FIG. 4A is the most basic threshold value setting method, priority is controlled more finely by setting threshold values stepwise in FIG. 4B than in FIG. 4A. It becomes possible. Compared to FIG. 4A, in FIG. 4C, by setting a threshold according to the read / write access type, it is possible to allocate a band in accordance with the operation of the data processing apparatus. Further, in FIG. 4D compared to FIG. 4A, the period is divided and a threshold value is set for each period, so that the bands are time-division multiplexed and the bands of a plurality of real-time processing bus masters are increased. It can be guaranteed.

  FIG. 5 is a flowchart illustrating a priority control procedure by the priority control unit 170 according to the embodiment. 5 is a process executed by the priority control unit 170. The procedure shown in FIG. 5 is a priority control procedure for a certain bus master. When there are bus masters M0 to M5 as in this embodiment, the same procedure is executed in parallel for each bus master.

  In S501, the priority of the bus master is set to an initial value. The initial priority value here is arbitrary, and as an example, the initial priority values of all the bus masters are set to the lowest priority. In step S502, the upper and lower threshold values described with reference to FIG. 4 are determined. As described with reference to FIG. 4, the threshold value is held in the threshold value setting unit 210 of the priority control unit 170. However, the threshold value to be set may be set in advance by the CPU 101, for example, read from a ROM or the like. It may be configured. In step S503, detection of the bus master band is started.

  In step S504, the detected band is acquired. As described with reference to FIG. 2, the timing for acquiring the band may be every cycle or may be acquired every certain cycle. In step S505, the priority is determined based on the bandwidth acquired in step S504 and the threshold value determined in step S502. The process of S505 will be described in detail with reference to the flowchart of FIG. In step S506, the priority determined in step S505 is notified to the arbiter 160. The process advances to step S507 to determine whether or not to end the band detection process. If the band detection process is to be continued, the process returns to step S504. If the band detection process is to be ended, the process ends.

  FIG. 6 is a flowchart for explaining the process of determining the priority in S505 of FIG.

  FIG. 6A shows a priority determination process when a set of upper and lower limits is set in S502, which corresponds to the case of FIG. 4A.

  In S601, it is determined whether the detected band is below the lower limit threshold. If it is determined in S601 that the detected band is below the lower limit threshold, the process proceeds to S602 and the priority is increased by one level. On the other hand, if it is determined in S601 that the detected band is not lower than the lower limit threshold, the process proceeds to S603. In S603, it is determined whether the detected band exceeds the upper threshold. If it is determined in S603 that the detected bandwidth exceeds the upper limit threshold, the process proceeds to S604 and the priority is lowered by one level. On the other hand, if it is determined in S603 that the detected bandwidth does not exceed the upper limit threshold value, this process ends.

  FIG. 6B shows a priority determination process when a plurality of upper and lower thresholds are set with a weight W in S502, and this corresponds to the case of FIG. 4B.

  In step S610, the subsequent processing in steps S611 to 614 is repeated for all weights with the loop variable as the weight W. In the example of FIG. 4B, since two weights are set, the process is repeated for two types of weights W = 1 and W = 2. In S611, it is determined whether or not the detected band is below the lower limit threshold in the weight W. If it is determined in S611 that the detected band is below the lower limit threshold for the weight W, the process proceeds to S612 and the priority is increased by W levels. On the other hand, if it is determined in S611 that the detected band is not below the lower limit threshold in the weight W, the process proceeds to S613. In S613, it is determined whether the detected band exceeds the upper limit threshold value in the weight W. If it is determined in S613 that the detected band is higher than the upper limit threshold value for the weight W, the process proceeds to S614, the priority is lowered by W levels, and the process proceeds to S610. On the other hand, if it is determined in S613 that the detected band does not exceed the upper limit threshold in the weight W, the process returns to S610. In S610, the weight W is updated, the control flow in S611 to S613 is repeated, and when the processing is completed for all weights, this processing is terminated.

  FIG. 6C shows a priority determination process when a plurality of upper and lower threshold values are set for each condition type in S502, and corresponds to the cases of FIGS. 4C and 4D. .

  In S620, the subsequent processing in S621 to S624 is repeated for all condition types with the loop variable as type T. In the example of FIG. 4C, the processing is repeated for two types of transaction types T = read and T = write.

  In S621, if it is determined that the detected band is below the lower limit threshold in Type T, the process proceeds to S622, and the priority is increased by one step, and the process proceeds to S622. If it is determined in S621 that the detected band is not lower than the lower limit threshold in type T, the process proceeds to S623. In S623, it is determined whether or not the detected band exceeds the upper limit threshold value for Type T. If it is determined in S623 that the detected band exceeds the upper limit threshold value for Type T, the process proceeds to S624, the priority is lowered by one step, and the process proceeds to S620. On the other hand, if it is determined in S623 that the detected band does not exceed the upper limit threshold for Type T, the process returns to S620. In S620, the type T is updated, and the control flow in S621 to S623 is repeated. When the processing is completed for all types, this processing ends.

  As described above, according to the embodiment, the priority of each bus master can be dynamically controlled. As a result, even when bus masters that have been statically set as high priority in the past compete with each other, the priority is changed according to the actual bandwidth of each bus master. As a result, it is possible to guarantee bandwidth while suppressing unnecessary bandwidth occupation by the bus master. Furthermore, it is possible to efficiently allocate a bandwidth to a bus master that has been statically set to have a low priority.

(Other embodiments)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, in order to make the scope of the present invention public, the following claims are attached.

  160 ... Arbiter, 170 ... Priority control unit, 200 ... Bandwidth detection unit, 210 ... Threshold setting unit, 220 ... Comparison unit, 230 ... Priority determination unit

Claims (11)

A data processing device,
Band detection means for detecting a band indicating the degree of access to the bus by each bus master;
Setting means for setting a threshold of the band;
A comparing means for comparing the threshold set by the setting means with the band detected by the band detecting means;
Arbitration means for determining the priority of each bus master based on the comparison by the comparison means, and for arbitrating the access request of each bus master based on the determined priority;
A data processing apparatus comprising: The threshold includes an upper limit threshold and a lower limit threshold of the band,
The comparing means compares the band detected by the band detecting means with each of the upper threshold and the lower threshold;
The mediation means lowers the priority when the detected band exceeds the upper limit threshold, and increases the priority when the detected band falls below the lower limit threshold. Item 4. The data processing device according to Item 1. The threshold value includes an upper limit threshold value and a lower limit threshold value of the plurality of weighted bands,
The comparing means compares the band detected by the band detecting means with each of an upper limit threshold value and a lower limit threshold value of the plurality of weighted bands,
The mediation means lowers the priority when the detected band exceeds the upper limit threshold, and increases the priority when the detected band falls below the lower limit threshold. Item 3. A data processing apparatus according to Item 2.   The arbitration means lowers the priority according to the weighting when the detected band exceeds the upper limit threshold, and reduces the priority when the detected band falls below the lower limit threshold. The data processing apparatus according to claim 3, wherein the data processing apparatus increases the weight according to weighting. The threshold includes an upper limit threshold and a lower limit threshold of the band according to the type of access,
The comparison unit compares the band detected by the band detection unit with each of an upper limit threshold and a lower limit threshold of the band according to the type of access,
The mediation means lowers the priority when the detected band exceeds the upper limit threshold, and increases the priority when the detected band falls below the lower limit threshold. Item 3. A data processing apparatus according to Item 2.   6. The data processing apparatus according to claim 5, wherein the access type includes read and write.   The data processing apparatus according to claim 6, wherein an upper limit threshold and a lower limit threshold of the band in the case of the read are larger than an upper limit threshold and a lower limit threshold of the band in the case of the write. The threshold includes an upper limit threshold and a lower limit threshold of the band according to the period of access,
The comparison unit compares the band detected by the band detection unit with each of an upper limit threshold and a lower limit threshold of the band according to the period of access;
The mediation means lowers the priority when the detected band exceeds the upper limit threshold, and increases the priority when the detected band falls below the lower limit threshold. Item 3. A data processing apparatus according to Item 2.   The data processing according to any one of claims 1 to 8, wherein the bandwidth detection unit detects the bandwidth based on a total number of transfer bytes of bus transactions of the bus masters in a predetermined period. apparatus. A bandwidth guarantee method in a data processing device including a plurality of bus masters,
A band detection step of detecting a band indicating the degree of access to the bus by each bus master;
A setting step for setting a threshold of the band;
A comparison step of comparing the threshold set in the setting step with the band detected in the band detection step;
Based on the comparison by the comparison step, the priority of each bus master is determined, and based on the determined priority, an arbitration step of arbitrating the access request of each bus master;
A bandwidth guarantee method comprising:   The program for functioning a computer as each means of the information processing apparatus of any one of Claims 1 thru | or 9.

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