JP2019200679A - Image forming apparatus, band monitoring device, and band monitoring method - Google Patents

Abstract

To make it possible to sufficiently acquire band information in a desired state, while reducing the capacity of an information storage unit that holds the band information.SOLUTION: An image forming apparatus has a memory that is accessed by a plurality of bus masters, and comprises: band acquisition means that is connected to a bus between a memory controller that controls the memory and the bus masters, and acquires band information on the bus and stores the information in an information storage unit; and control means that receives input of a start instruction signal that is output in association with execution of data transfer in the bus. When the start instruction signal is input, the control means controls the band acquisition means connected to the bus associated with the input start instruction signal to start acquisition of the band information.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image forming apparatus, a band monitoring apparatus, and a band monitoring method.

  There is known an image forming apparatus such as a digital multi-function peripheral having various functions such as a scanner function, a printer function, a copy function, a network communication function, and a FAX transmission / reception function. Functional operations in the digital multifunction peripheral are normally controlled by an image input / output control unit called a controller. In order to reduce costs, the controller integrates a CPU and a plurality of function processing units that realize the above-described functions in one chip. In addition, main memories for transferring image data and the like when realizing each function have also been integrated, and the amount of access to the main memory has increased greatly.

  One of the factors that increase the amount of access to the main memory is speeding up of scan processing and print processing. Processing such as scan processing and print processing is a process that requires real-time processing that cannot be stopped until input / output of a page being processed is completed at least once the operation is started. As a controller, it is desirable that access to the main memory for image processing that requires real-time processing always process non-real-time processing in parallel as much as possible while guaranteeing a certain transfer bandwidth.

  In other words, the controller is created so as not to cause a situation in which the transfer bandwidth of access to the main memory for image processing that requires real-time processing cannot be guaranteed. For example, sufficient memory transfer performance is ensured by using a high-frequency, multi-bit width memory that can sufficiently guarantee memory transfer performance even when all functions are operated. However, using a memory with a high operating frequency leads to an increase in cost and power consumption. Also, using a multi-bit memory leads to an increase in the chip unit price due to an increase in the number of pins in the chip.

  In view of this, a method has been proposed for securing a transfer band to the main memory in real-time processing while suppressing the increase in frequency and the number of bits of the memory. For example, Patent Literature 1 includes a functional unit that performs non-real-time processing and a bandwidth monitor that can monitor a transfer bandwidth between main memories, and performs a non-real-time processing when a preset transfer bandwidth is exceeded. A technology for suppressing access requests from the Internet has been proposed. With this technique, it is possible to suppress the transfer band related to the non-real-time process and to guarantee the transfer band related to the real-time process by controlling not to accept the access from the functional unit that performs the non-real-time process.

JP 2014-160341 A

  In the conventional bandwidth monitor, an instruction to start the bandwidth information acquisition operation is issued by the CPU, and the acquired bandwidth information is stored in an information storage unit such as an SRAM. However, the CPU cannot accurately grasp the timing when the band information is actually acquired. For example, taking scan processing in a multifunction device as an example, after the scan processing start operation is performed, the scanner is started, the image is actually input to the controller, image processing is performed, and output to the memory Has a time lag.

  For this reason, it has been necessary to instruct the conventional bandwidth monitor to start the bandwidth information acquisition operation before the bandwidth information is acquired. In this case, sufficient information can be held under the condition where the desired bus transfer is being performed, and it is sufficient to acquire bandwidth information during the time lag from the start instruction by the CPU until the actual data transfer is performed. It is necessary to mount an information storage unit having a capacity capable of holding information. However, an increase in the capacity of an information storage unit such as an SRAM leads to an increase in chip cost. An object of the present invention is to sufficiently acquire band information in a desired state while suppressing the capacity of an information storage unit that holds band information.

  An image forming apparatus according to the present invention is an image forming apparatus having a memory accessed by a plurality of bus masters, and is connected to a bus between a memory controller that controls the memory and the bus master, Band acquisition means for acquiring band information and holding it in the information storage unit, and a start instruction signal output along with data transfer on the bus are input, and when the start instruction signal is input, Control means for controlling the bandwidth acquisition means of the bus associated in response to the start instruction signal to start acquisition of the bandwidth information.

  According to the present invention, it is possible to reduce the acquisition period of useless band information, and to sufficiently acquire band information in a desired state while suppressing the capacity of the information storage unit that holds the band information.

1 is a diagram illustrating a configuration example of an image forming apparatus according to an embodiment of the present invention. It is a figure which shows the structural example of the controller part in 1st Embodiment. It is a figure which shows the structural example of the zone | band monitor in 1st Embodiment. It is a figure explaining the zone | band monitoring operation | movement in 1st Embodiment. It is a flowchart which shows the operation example of the zone | band monitor in 1st Embodiment. It is a figure which shows the structural example of the controller part in 2nd Embodiment. It is a figure which shows the structural example of the zone | band monitor in 2nd Embodiment. 10 is a timing chart for explaining a bandwidth monitoring operation in the second embodiment. It is a flowchart which shows the operation example of the zone | band monitor in 2nd Embodiment. It is a figure which shows the structural example of the zone | band monitor in 3rd Embodiment. It is a timing chart explaining the zone | band monitoring operation | movement in 3rd Embodiment. It is a flowchart which shows the operation example of the zone | band monitor in 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
A first embodiment of the present invention will be described.
<Image forming apparatus>
FIG. 1 is a block diagram illustrating a configuration example of an image forming apparatus according to an embodiment of the present invention. The image forming apparatus 100 according to the present embodiment includes a scanner unit 110, a controller unit 120, an operation unit 130, and a printer unit 140.

  The scanner unit 110 optically reads a document image and converts it into image data. The scanner unit 110 includes a document feeding unit 111 having a function for conveying a document sheet, and a document reading unit 112 having a function for reading a document image. The printer unit 140 conveys the recording paper, prints the image data thereon as a visible image, and discharges the recording paper out of the apparatus. The printer unit 140 includes a transfer fixing unit 141 having a function of transferring and fixing image data onto a recording sheet, a paper feeding unit 142 having a function of supplying a plurality of types of recording sheets, and sorting and stapling the printed recording sheets. And a paper discharge unit 143 having a function of outputting to the outside of the apparatus.

  The controller unit 120 is electrically connected to the scanner unit 110 and the printer unit 140 and further connected to the network 150 so as to be communicable. The network 150 is, for example, a communication network such as a local area network (LAN) or an integrated services digital network (ISDN), the Internet / intranet, or the like. The controller unit 120 controls the scanner unit 110 and the printer unit 140, for example. When the controller unit 120 controls the scanner unit 110 and the printer unit 140, the image forming apparatus 100 provides a copy function, a scanner function, a printer function, and the like.

  For example, the controller unit 120 provides a copy function by controlling the scanner unit 110 to read image data of a document and controlling the printer unit 140 to output the image data to a recording sheet. Further, for example, the controller unit 120 converts image data read from the scanner unit 110 into code data, and transmits the code data to a host computer (not shown) via the network 150 to provide a scanner function. For example, the controller unit 120 converts code data received from a host computer (not shown) via the network 150 into image data, and the printer unit 140 outputs the image data to recording paper to provide a printer function.

  Also, under the control of the controller unit 120, for example, a FAX reception function for receiving and printing data from a communication line network such as ISDN, and a FAX transmission function for transmitting scanned data to a communication line network such as ISDN are provided. Processing such as scanning processing, printing processing, and FAX transmission / reception processing is called a job, and the image forming apparatus 100 processes these jobs according to instructions. The operation unit 130 is connected to the controller unit 120 and is configured by a liquid crystal touch panel, for example, and provides a user interface for operating the image forming apparatus 100.

<Controller part>
FIG. 2 is a block diagram illustrating a configuration example of the controller unit 120 according to the first embodiment. Note that the controller unit 120 described below and the respective functional units therein are configured by hardware circuits. A CPU (Central Processing Unit) 200 is a processor that controls the entire system. The CPU 200 comprehensively controls processes related to jobs such as print processing and scan processing in accordance with an operating system (OS) and control program developed in a RAM (Random Access Memory) 270.

  A ROM controller (ROMC) 210 is a control module for accessing a ROM (Read Only Memory) 211 that stores a boot program of the system. When the image forming apparatus 100 is powered on, the CPU 200 accesses the ROM 211 via the ROM controller 210, reads the boot program, and executes the boot process.

  A network interface (NW_IF) 220 is connected to the network 150 and inputs / outputs information such as image data to / from an external host computer or the like. Interconnects (InterConnect) 230 and 231 are interconnects that connect the CPU and each processing unit to the memory controller (MEMC) 260.

  The memory controller 260 is a control module for accessing the RAM 270 in which system control programs and image data are stored. The memory controller 260 includes buffers (BUFFER) 261, 262, 263, 264 and a bus conversion unit (BUS_CONVERTER) 265. The memory controller 260 has a register for setting and controlling the RAM 270, and this register is accessible from the CPU 200.

  The buffers 261 to 264 are buffers for temporarily buffering reception data and transmission data for the corresponding DMA (Direct Memory Access) controller (DMAC) and the interconnect. Each of the buffers 261 to 264 has at least a buffer size (storage capacity) corresponding to the amount of data that can be burst transferred at one time on each of the buses 290 to 293 connected thereto. Note that the buffers 261 to 264 also serve as asynchronous buffers when the operating frequency of the buses 290 to 293 and the operating frequency of the bus conversion unit 265 are different. The bus conversion unit 265 has an arbitration function. For example, the bus conversion unit 265 arbitrates the access right of each of the buffers 261 to 264 by round robin. The bus conversion unit 265 performs protocol conversion for accessing the RAM 270.

  The RAM 270 is a memory as a main memory in the system, and is assumed to be configured by an SDRAM (Synchronous Dynamic Random Access Memory) in this example. The RAM 270 is a system work memory for the operation of the CPU 200 and an image memory for storing image data. Note that the RAM 270 is not limited to the one configured by SDRAM, and may be configured by another memory.

  The DMACs 240, 241, 242, 243, 244, 245, and 246 are DMA controllers serving as memory access masters (bus masters) that access the RAM 270 via the memory controller 260. The DMACs 240 to 246 perform data transfer between the corresponding processing units 250 to 256 and the RAM 270. Each of the DMACs 240 to 246 is controlled by the CPU 200 and has, for example, a function to control which memory address data is read from and written to, and the timing at which DMA transfer is performed.

  The CPU 200 also controls a scan processing unit 250, a rotation processing unit 251, a scaling processing unit 252, a RIP processing unit 253, a compression processing unit 254, an expansion processing unit 255, and a print processing unit 256 that perform predetermined image processing. Is done. In the following description of each of the processing units 250 to 256, it is assumed that image data is uncompressed image data, and compressed image data is image data compressed by some compression means.

  The scan processing unit 250 performs predetermined image processing on the image data input from the scanner unit 110 in accordance with the setting by the CPU 200, and outputs the image processed image data to the DMAC 240. The scan processing unit 250 performs image processing such as shading correction processing, MTF correction processing, input gamma correction, and filter processing. The rotation processing unit 251 performs rotation processing such as 90 degrees, 180 degrees, and 270 degrees on the image data input from the DMAC 241 according to the setting by the CPU 200, and outputs the rotated image data to the DMAC 241.

  The scaling processing unit 252 scales the image data input from the DMAC 242 to an arbitrary magnification such as 1/2 times or 1/4 times according to the setting by the CPU 200, and the scaled image data is transferred to the DMAC 242. Output. The RIP processing unit 253 performs rendering processing on the PDL image input from the DMAC 243 according to the setting by the CPU 200, and outputs the rendered image data to the DMAC 243. The compression processing unit 254 performs image compression processing such as JPEG and JBIG on the image data input from the DMAC 244 according to the setting by the CPU 200, and outputs the obtained compressed image data to the DMAC 244.

  The decompression processing unit 255 performs decompression processing on the compressed image data such as JPEG and JBIG input from the DMAC 245 according to the setting by the CPU 200, and outputs the decompressed image data to the DMAC 245. The print processing unit 256 performs predetermined image processing on the image data input from the DMAC 245 according to the setting by the CPU 200, and outputs the image processed image data to the printer unit 140. The print processing unit 256 performs image processing such as color space conversion processing, filter processing, and halftone processing, for example.

  Here, the DMAC 240, the interconnect 231, the DMAC 246, the interconnect 230, and the memory controller 260 are connected by buses 290, 291, 292, and 293, respectively. The interconnect 231 and the DMACs 241 to 245 are connected by buses 294, 295, 296, 297, and 298, respectively. For example, an AXI (Advance eXtensible Interface) bus, which is a standard bus, is applied to the buses 290 to 298.

  The bandwidth monitor 280 monitors the amount of data transferred on the buses 290 to 293 and acquires bandwidth information of the monitoring target bus. The bandwidth information in the present embodiment includes information on the amount of data transferred by data transfer performed on the monitoring target bus within each period divided by a certain time interval. The band monitor 280 can individually acquire the band information of each of the buses 290 to 293. The total bandwidth derived from the bandwidth information of each bus acquired by the bandwidth monitor 280 is the used memory bandwidth for the RAM 270. Band information acquired by the band monitor 280 is held in an SRAM (Static Random Access Memory) 281 and can be read from the CPU 200. The SRAM 281 is an example of an information storage unit.

  Further, the bandwidth monitor 280 is configured to be able to specify the timing at which the bandwidth information is acquired and started to be written into the SRAM 281. The method for specifying the timing for acquiring the band information and starting writing to the SRAM 281 can be controlled by inputting a control signal for notifying the timing to start acquiring the band information to the band monitor, in addition to the method of instructing the CPU 200 to start writing. It is configured as follows. In the present embodiment, the control signal 282 is input from the scan processing unit 250 to the band monitor 280 and the control signal 283 is input from the print processing unit 256 to the band monitor 280 as control signals for notifying the timing for starting acquisition of band information. Is done. The control signals 282 and 283 are signals that are output when data transfer is performed on a bus, for example. The control signal 282 is, for example, a vertical synchronization signal (SVSYNC) output from the scan processing unit 250, and the control signal 283 is, for example, a vertical synchronization signal (PVSYNC) output from the print processing unit 256.

  The bandwidth monitor 280 is also configured to be able to specify the timing at which the acquisition of bandwidth information is stopped and the writing to the SRAM 281 is stopped. A signal indicating the end of data transfer on the bus, such as a DMAC transfer end interrupt, is input to the bandwidth monitor 280 as a control signal for designating the stop timing. In this embodiment, a control signal 284 is input to the band monitor 280 from the DMAC 240 connected to the scan processing unit 250, and a control signal 285 is input to the band monitor 280 from the DMAC 246 connected to the print processing unit 256.

  The control signal 284 is, for example, a transfer end interrupt signal (INT_SPageEnd) output from the DMAC 240, and the control signal 285 is, for example, a transfer end interrupt signal (INT_PPageEnd) output from the DMAC 246. The transfer end interrupt signal (INT_SPageEnd) is an interrupt signal that is asserted when the DMAC 240 completes data transfer for one page. The transfer end interrupt signal (INT_PPageEnd) is an interrupt signal that is asserted when the DMAC 246 completes data transfer for one page.

  Hereinafter, as an example, it is assumed that the control signal 282 is a vertical synchronization signal (SVSYNC) related to scan processing, and the control signal 283 is a vertical synchronization signal (PVSYNC) related to print processing. Further, it is assumed that the control signal 284 is the DMAC 240 transfer end interrupt signal (INT_SPageEnd), and the control signal 285 is the DMAC 246 transfer end interrupt signal (INT_PPageEnd).

<Bandwidth monitor>
FIG. 3 is a block diagram illustrating a configuration example of the bandwidth monitor 280 according to the first embodiment. In FIG. 3, the same components as those shown in FIG. 2 are denoted by the same reference numerals. Note that the bandwidth monitor 280 described below and the respective functional units therein are configured by hardware circuits. The band monitor 280 includes a timing determination unit 300, a register unit 301, band acquisition units 302, 303, 304, and 305, a multiplexer (MUX) 306, and an SRAM interface (SRAM I / F) 307.

  The timing determination unit 300 controls the acquisition start and the acquisition stop of the band information by the band acquisition units 302 to 305 based on the external input signal. The timing determination unit 300 is an example of a control unit. The timing determination unit 300 receives a vertical synchronization signal (SVSYNC) 282 and a vertical synchronization signal (PVSYNC) 283 as start instruction signals for instructing start of band information acquisition. The timing determination unit 300 is supplied with a transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240 and a transfer end interrupt signal (INT_PPageEnd) 285 of the DMAC 246 as stop instruction signals for instructing to stop acquiring the band information. In addition, a control signal 310 for instructing start and stop of acquisition of band information is input from the register unit 301 to the timing determination unit 300.

  When the timing determination unit 300 receives any of the start instruction signals 282 and 283 and the control signal 310 that are input, the timing determination unit 300 starts acquisition of bandwidth information of the associated bus according to the input signal. . In addition, when the timing determination unit 300 receives any one of the stop instruction signals 284 and 285 and the control signal 310 that are input, the timing determination unit 300 acquires the bandwidth information of the associated bus according to the input signal. Stop.

  For example, when the vertical determination signal (SVSYNC) 282 is input to the timing determination unit 300, the band acquisition unit 302 that acquires the band information of the bus 290 between the scan processing unit 250 and the memory controller 260 acquires the band information. Control to start. In addition, the timing determination unit 300 controls the bandwidth information acquired by the bandwidth acquisition unit 302 to be written to the SRAM 281 as the information storage unit via the SRAM I / F 307. When receiving the transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240, the timing determination unit 300 controls the band acquisition unit 302 to stop acquiring the band information of the bus 290.

  The register unit 301 holds various setting values of the bandwidth monitor 280. In addition, the register unit 301 receives control of band information acquisition start and acquisition stop by the CPU 200 and notifies the timing determination unit 300 through the control signal 310.

  The bandwidth acquisition unit 302 acquires bandwidth information of the connected bus 290. The band acquisition unit 302 is controlled to start and stop acquisition of band information in response to a control signal from the timing determination unit 300. The bandwidth acquisition unit 302 acquires a data transfer amount by data transfer performed by the bus 290 within a certain time interval, and outputs the acquired data transfer amount to the SRAM 281 as bandwidth information together with the acquisition time. The band acquisition units 303 to 305 are configured in the same manner as the band acquisition unit 302, and the buses for acquiring band information are different. The band acquisition unit 303 acquires the band information of the bus 291, the band acquisition unit 304 acquires the band information of the bus 292, and the band acquisition unit 304 acquires the band information of the bus 293.

  In each of the band acquisition units 302 to 305, the time interval (acquisition time) related to the acquisition of band information may be constant or may be variably set by the CPU 200. In addition to the amount of data transfer, information that accompanies data transfer such as a master ID may be acquired at the same time. Further, as the band information to be output to the SRAM 281, the acquired band information may be output as it is, or may be output after being calculated as a band value. In this case, the band acquisition units 302 to 305 include a band calculation unit (not shown) inside.

  When the access to the bandwidth monitor 280 from the CPU 200 occurs, the multiplexer 306 determines whether the access is to the register unit 301 or the SRAM 281 and controls the access destination. The SRAM I / F 307 is an interface for accessing the internal module of the bandwidth monitor 280 and the SRAM 281 from the CPU 200.

<Acquisition of bandwidth information and control of writing to SRAM>
With reference to FIG. 4A to FIG. 4C, the band monitoring operation in the first embodiment will be described. FIG. 4A is a block diagram illustrating a configuration example of the scan processing unit 250 and the DMAC 240 when the present embodiment is applied. The scan processing unit 250 includes various functional units for performing predetermined image processing on input image data. FIG. 4A illustrates an example in which the scan processing unit 250 includes a shading correction unit 403, a gamma correction unit 404, and a filter processing unit 405.

  The scan processing unit 250 receives image data of an image read by the scanner unit 110. In the read image, generally, the start of one page is controlled by a vertical synchronization signal related to image formation, and the start of one line is controlled by a horizontal synchronization signal. In this embodiment, the vertical synchronization signal input from the scanner unit 110 is the SVSYNC_IN signal 400, the horizontal synchronization signal is the SHSYNC_IN signal 401, and the actual image data signal is the SDATA_IN signal 402.

  The image data input to the scan processing unit 250 is subjected to various image processing in the scan processing unit 250 and then output to the DMAC 240. In this example, image data is output from the scan processing unit 250 to the DMAC 240 by the SVSYNC_C signal, the SHSYNC_C signal, and the SDATA_C signal. The DMAC 240 writes image data to the RAM 270 via the memory controller 260.

  Here, the vertical synchronization signal (SVSYNC) 282 is a signal for outputting the SVSYNC_C signal, which is the vertical synchronization signal output from the scan processing unit 250, to the band monitor 280. The vertical synchronization signal (SVSYNC) 282 is input to the timing determination unit 300 of the band monitor 280 and is used as a control signal for controlling the start timing of band information acquisition to the band acquisition unit 302 that acquires the band information of the bus 290. Is called.

  The transfer end interrupt signal (INT_SPageEnd) 284 is an interrupt signal that is asserted when the DMAC 240 completes outputting data for one page. The transfer end interrupt signal (INT_SPageEnd) 284 is input to the timing determination unit 300 of the band monitor 280 and is used as a control signal for controlling the timing of stopping the acquisition of the band information to the band acquisition unit 302 that acquires the band information of the bus 290. used.

  Next, the control of the timing for acquiring the band information and writing it to the SRAM 281 will be described using the configuration shown in FIG. 4A as an example. FIG. 4B is a timing chart illustrating an example in which the CPU 200 instructs the band monitor 280 to start acquiring band information when the scan process is executed and data is written to the RAM 270 by the DMAC 240.

  At time t41, the CPU 200 receives a scan job start operation and issues a start instruction to the scanner unit 110 under desired scanning conditions. In addition, the CPU 200 instructs the bandwidth monitor 280 to start obtaining bandwidth information. In response to the acquisition start instruction, the bandwidth monitor 280 controls the timing determination unit 300 so that the bandwidth acquisition unit 302 starts acquiring bandwidth information. The band acquisition unit 302 starts acquiring the band information of the bus 290 and storing the acquired band information in the SRAM 281.

  At time t <b> 42, the vertical synchronization signal (SVSYNC) 282 is output from the scan processing unit 250. Accordingly, the scanner activation period is between time t41 and t42, and the activation of the scanner unit 110 that has received the activation instruction of the CPU 200 at time t42 is completed and scanning is started. That is, data transfer on the bus 290 is not performed between times t41 and t42, and time t42 is a timing at which the image data processed by the scan processing unit 250 starts to be output from the scan processing unit 250 to the DMAC 240. .

  At time t43, the DMAC 240 finishes writing all the image data to the RAM 270, and asserts a transfer end interrupt signal (INT_SPageEnd) 284 indicating that the writing is completed. When the transfer end interrupt signal (INT_SPageEnd) 284 is asserted, the bandwidth monitor 280 controls the timing determination unit 300 to stop the bandwidth acquisition unit 302 from acquiring bandwidth information. The band acquisition unit 302 stops acquiring the band information of the bus 290 and storing the band information in the SRAM 281.

  FIG. 4C is a timing chart showing an example in which the start of band information acquisition in the band monitor 280 is instructed by the vertical synchronization signal (SVSYNC) 282 when scan processing is performed and data is written to the RAM 270 by the DMAC 240. is there. At time t41, the CPU 200 receives a scan job start operation and issues a start instruction to the scanner unit 110 under desired scanning conditions. In the example shown in FIG. 4C, unlike the example shown in FIG. 4B, the CPU 200 does not instruct the bandwidth monitor 280 to start obtaining bandwidth information.

  At time t <b> 42, the vertical synchronization signal (SVSYNC) 282 is output from the scan processing unit 250. Accordingly, the scanner activation period is between time t41 and t42, the activation of the scanner unit 110 that has received the activation instruction of the CPU 200 is completed at time t42, the scan is started, and the image data image-processed by the scan processing unit 250 is Output to the DMAC 240 starts. The vertical synchronization signal (SVSYNC) 282 output from the scan processing unit 250 is input to the band monitor 280. The band monitor 280 receives the vertical synchronization signal (SVSYNC) 282 and controls the timing determination unit 300 so that the band acquisition unit 302 starts acquiring band information. The band acquisition unit 302 starts acquiring the band information of the bus 290 and storing the acquired band information in the SRAM 281.

  At time t43, the DMAC 240 finishes writing all the image data to the RAM 270, and asserts a transfer end interrupt signal (INT_SPageEnd) 284 indicating that the writing is completed. When the transfer end interrupt signal (INT_SPageEnd) 284 is asserted, the bandwidth monitor 280 controls the timing determination unit 300 to stop the bandwidth acquisition unit 302 from acquiring bandwidth information. The band acquisition unit 302 stops acquiring the band information of the bus 290 and storing the band information in the SRAM 281.

  Here, in the example shown in FIGS. 4B and 4C, the data transfer on the bus 290 is actually performed during the bus transfer period between times t42 and t43. However, in the example shown in FIG. 4B, the bandwidth monitor 280 starts acquiring bandwidth information at time t41. Therefore, in order to perform such an operation, even if the bandwidth information acquired in the period from time t41 to t42 when data transfer does not occur is written on the bus 290, the capacity of the bandwidth can be acquired in the period until time t43. It is necessary to mount the SRAM 281.

  On the other hand, in the example shown in FIG. 4C, the vertical synchronization signal (SVSYNC) 282 output from the scan processing unit 250 is input as a start instruction signal for instructing start of band information acquisition in the band monitor 280. doing. Therefore, it is possible to reduce the useless period of time t41 to t42 regarding the acquisition of the band information, and to acquire the band information only in the bus transfer period of time t42 to t43 in which data transfer is actually performed on the bus 290. . Accordingly, since the bandwidth information is not acquired during the scanner activation period, the bandwidth information during the bus transfer period can be sufficiently acquired even when a smaller capacity SRAM is used than when the activation control of the bandwidth monitor 280 is performed by the CPU 200. It becomes possible.

<Band information acquisition and SRAM write control flow>
FIG. 5 is a flowchart showing an operation example of the bandwidth monitor 280 in the first embodiment. FIG. 5 shows an example in which the band monitor 280 starts acquiring band information by the vertical synchronization signal (SVSYNC) 282.

  In step S501, the timing determination unit 300 of the band monitor 280 determines whether or not the vertical synchronization signal (SVSYNC) 282 from the scan processing unit 250 has been input. When it is determined that the vertical synchronization signal (SVSYNC) 282 is not input (No in step S501), the timing determination unit 300 repeats the determination in step S501 until the vertical synchronization signal (SVSYNC) 282 is input. When the timing determination unit 300 determines that the vertical synchronization signal (SVSYNC) 282 has been input (Yes in step S501), the process proceeds to step S502.

  In step S502, in response to the input of the vertical synchronization signal (SVSYNC) 282, the timing determination unit 300 controls the band acquisition unit 302 to start acquiring the band information of the bus 290. Then, the band acquisition unit 302 starts acquiring the band information of the bus 290 and saving the acquired band information in the SRAM 281. Thereafter, the bandwidth acquisition unit 302 acquires the bandwidth information of the bus 290 in units of a certain time interval, and controls the process of writing the acquired bandwidth information to the SRAM 281 so as to stop the acquisition of the bandwidth information in step S505. Repeat until

  In step S503, the timing determination unit 300 determines whether or not the SRAM 281 to which band information is written is in a full state in which no more band information can be written. When the timing determination unit 300 determines that the SRAM 281 is full (Yes in step S503), the process proceeds to step S505. On the other hand, when the timing determination unit 300 determines that the SRAM 281 is not full (No in step S503), the process proceeds to step S504.

  In step S504, the timing determination unit 300 determines whether or not the transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240 is input. If the timing determination unit 300 determines that the transfer end interrupt signal (INT_SPageEnd) 284 has not been input (No in step S504), the bandwidth information needs to be continuously acquired, and thus the process proceeds to step S503. On the other hand, when the timing determination unit 300 determines that the transfer end interrupt signal (INT_SPageEnd) 284 is input (Yes in step S504), the process proceeds to step S505.

  Note that the order of determining whether the SRAM 281 is full in steps S503 and S504 and determining whether the transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240 is input is in no particular order. After determining whether or not the transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240 is input, it may be determined whether or not the SRAM 281 is full.

  In step S505, the timing determination unit 300 controls the band acquisition unit 302 to stop acquiring the band information in response to satisfying the condition for stopping the band information acquisition. As a result, the band acquisition unit 302 stops acquiring the band information of the bus 290 and stops writing the band information to the SRAM 281.

  As described above, taking scan processing as an example, acquisition of band information is started by the vertical synchronization signal (SVSYNC) 282 from the scan processing unit 250, and acquisition of band information is stopped by the transfer end interrupt signal (INT_SPageEnd) 284 from the DMAC 240. Explained. The present embodiment is not limited to scan processing, and can be similarly applied to print processing. In the print processing, the acquisition of the band information of the bus 292 is started by the vertical synchronization signal (PVSYNC) 283 from the print processing unit 256, and the acquisition of the band information of the bus 292 is stopped by the transfer end interrupt signal (INT_PPageEnd) 285 from the DMAC 246. To do.

  According to the first embodiment, the start of band information acquisition by the band monitor 280 is controlled by the control signal that notifies the timing to start the band information acquisition. For example, in the scan process, the start of band information acquisition by the band monitor 280 is controlled by the vertical synchronization signal (SVSYNC) 282 output from the scan processing unit 250. As a result, it is possible to reduce the useless bandwidth information acquisition period compared to when the CPU 200 controls the start of bandwidth information acquisition, and the bandwidth information acquisition is limited to the bus transfer period in which data transfer is actually performed on the bus. Is possible. For this reason, since bandwidth information is not acquired during the startup period, it is possible to acquire sufficient bandwidth information even when using a smaller capacity SRAM than when the CPU 200 controls the startup of the bandwidth monitor 280. . Therefore, it is possible to sufficiently acquire the band information in the bus transfer period in a desired state while suppressing the capacity of the information storage unit that holds the band information.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment, the band information acquisition start timing of the band monitor 280 is controlled by the vertical synchronization signal, so that it is narrowed down to the bus transfer period compared to the case where the CPU 200 controls the band information acquisition start. An example is shown in which bandwidth information can be acquired.

  In the second embodiment described below, an operation status signal indicating validity / invalidity of a functional module is used at the start timing of band information acquisition. As a result, even when data transfer is performed by a bus master that does not use a synchronization signal such as the vertical synchronization signal (SVSYNC) 282, it is possible to acquire band information narrowed down to a bus transfer period in which data transfer is actually performed. It is possible to narrow down the period for acquiring information. In the following description, differences from the first embodiment will be described, and description of the same elements as those in the first embodiment will be omitted.

<Controller part>
FIG. 6 is a block diagram illustrating a configuration example of the controller unit 120 according to the second embodiment. In FIG. 6, components having the same functions as those shown in FIG. Note that the controller unit 120 and each function unit in the second embodiment described below are also configured by hardware circuits.

  A bus master that does not use a synchronization signal described in the present embodiment is a process in which functional modules that do not require a synchronization signal, such as the processing units 251 to 255 shown in FIG. It is a module that performs. The operation status signal 600 is a bus in which signals indicating operation states of the DMACs 241 to 245 connected to the processing units 251 to 255 are collected. The DMAC operation status signal 600 is a summary of at least an enable signal indicating that transfer processing is possible, which is output when the DMAC performs data transfer, and an interrupt signal output when transfer processing is completed. It is a thing.

For example, INT_PageEnd signals 601 to 605 shown in FIG. 6 are transfer end interrupt signals output from the DMACs 241 to 245, and are input to the band monitor 280 as control signals that specify the timing for stopping the acquisition of band information. It is assumed that INT_PageEnds 601 to 605 are collected into the operation status signal 600 and input to the band monitor 280.
Others are the same as the controller unit 120 in the first embodiment shown in FIG.

<Bandwidth monitor>
FIG. 7 is a block diagram illustrating a configuration example of the bandwidth monitor 280 according to the second embodiment. In FIG. 7, components having the same functions as those shown in FIG. 3 are given the same reference numerals, and redundant descriptions are omitted. Note that the bandwidth monitor 280 in the second embodiment, which will be described below, and the respective functional units therein are also configured by hardware circuits.

  In the bandwidth monitor 280 according to the second embodiment, the operation status signal 600 is further input to the timing determination unit 300. When receiving the enable signal included in the operation status signal 600, the timing determination unit 300 starts acquiring the band information of the corresponding bus 291 and controls the band acquisition unit 303 to write the acquired band information to the SRAM 281. . When the timing determination unit 300 receives the transfer end interrupt signal included in the operation status signal 600, the timing determination unit 300 controls the band acquisition unit 303 to stop acquiring the band information of the bus 291.

<Acquisition of bandwidth information and control of writing to SRAM>
FIG. 8 is a timing chart showing an example in which the band monitor 280 in the second embodiment is instructed to start obtaining band information in the band monitor 280 by an operation status signal. In the following, the DMAC 241 is described as an example, but the same applies to the other DMACs 242 to 245. Further, here, a read operation in which the DMAC reads data from the RAM 270 will be described as an example.

  At time t81, the CPU 200 instructs the DMAC 241 to start up. In response to the activation instruction, the DMAC 241 asserts an enable signal (DMAC_ENB), which is its own operation status signal, to a high level and requests the memory controller 260 for data. In response to the data transfer request from the DMAC 241, the memory controller 260 reads data corresponding to the data transfer request from the RAM 270 and starts transfer to the DMAC 241. The enable signal (DMAC_ENB) is input to the timing determination unit 300 included in the band monitor 280 as the operation status signal 600. When the operation status signal 600 is input, the timing determination unit 300 controls the band acquisition unit 303 corresponding to the bus S291 to start acquiring the band information. The band acquisition unit 303 starts acquiring the band information of the bus 291 and saving the acquired band information in the SRAM 281.

  At time t82, the DMAC 241 asserts a transfer end interrupt signal (INT_PageEnd) indicating that all image data has been received. The asserted transfer end interrupt signal (INT_PageEnd) is input to the timing determination unit 300 of the band monitor 280 via the operation status signal 600. When the transfer end interrupt signal (INT_PageEnd) is input, the timing determination unit 300 controls the band acquisition unit 303 corresponding to the bus 291 to stop acquiring the band information. The bandwidth acquisition unit 303 stops acquiring the bandwidth information of the bus 291 and saving the bandwidth information in the SRAM 281.

<Band information acquisition and SRAM write control flow>
FIG. 9 is a flowchart showing an operation example of the bandwidth monitor 280 in the second embodiment. FIG. 9 shows an example in which the band monitor 280 starts acquiring band information by an enable signal included in the operation status signal and stops acquiring band information by a transfer end interrupt signal. Hereinafter, the DMAC 241 is described as an example, but the same applies to the other DMACs 242 to 245.

  In step S901, the timing determination unit 300 included in the bandwidth monitor 280 determines whether or not the DMAC 241 enable signal (DMAC_ENB) included in the operation status signal is input. When it is determined that the enable signal (DMAC_ENB) is not input (No in step S901), the timing determination unit 300 repeats the determination in step S901 until the enable signal (DMAC_ENB) is input. If the timing determination unit 300 determines that the enable signal (DMAC_ENB) has been input (Yes in step S901), the process proceeds to step S902.

  In step S902, the timing determination unit 300 controls the band acquisition unit 303 to start acquiring the band information of the bus 291 in response to the input of the enable signal (DMAC_ENB). Then, the bandwidth acquisition unit 303 starts acquiring the bandwidth information of the bus 290 and saving the acquired bandwidth information in the SRAM 281. Thereafter, the bandwidth acquisition unit 303 controls the acquisition of the bandwidth information of the bus 291 in units of a certain time interval, and the process of writing the acquired bandwidth information to the SRAM 281 is stopped in step S905. Repeat until

  In step S903, the timing determination unit 300 determines whether or not the SRAM 281 to which band information is written is in a full state. When the timing determination unit 300 determines that the SRAM 281 is full (Yes in step S903), the process proceeds to step S905. On the other hand, when the timing determination unit 300 determines that the SRAM 281 is not full (No in step S903), the process proceeds to step S904.

  In step S904, the timing determination unit 300 determines whether the transfer end interrupt signal (INT_PageEnd) of the DMAC 241 has been input. If the timing determination unit 300 determines that the transfer end interrupt signal (INT_PageEnd) has not been input (No in step S904), the bandwidth information needs to be continuously acquired, and thus the process proceeds to step S903. On the other hand, if the timing determination unit 300 determines that the transfer end interrupt signal (INT_PageEnd) has been input (Yes in step S904), the process proceeds to step S905.

  Note that the order in which it is determined whether or not the SRAM 281 is full in steps S903 and S904 and whether or not the transfer end interrupt signal (INT_PageEnd) of the DMAC 241 is input is in no particular order. After determining whether or not the DMAC 241 transfer end interrupt signal (INT_PageEnd) is input, it may be determined whether or not the SRAM 281 is full.

  In step S905, the timing determination unit 300 controls the band acquisition unit 303 to stop acquiring the band information in response to satisfying the condition for stopping the band information acquisition. As a result, the band acquisition unit 303 stops acquiring the band information of the bus 291 and stops writing the band information to the SRAM 281.

  According to the second embodiment, acquisition of band information by the band monitor 280 is started by a DMAC enable signal included in the operation status signal, and acquisition of band information is stopped by a DMAC transfer end interrupt signal. As a result, even when data is transferred by a bus master that does not use a synchronization signal, it is possible to acquire bandwidth information only during the bus transfer period during which data is actually transferred on the bus, and bus transfer that acquires bandwidth information. It becomes possible to narrow down the period. Accordingly, sufficient bandwidth information can be acquired even with a small capacity SRAM, and the bandwidth information during the bus transfer period in a desired state can be sufficiently obtained while suppressing the capacity of the information storage unit holding the bandwidth information. It can be acquired.

  In this embodiment, the case where the operation status signal of the DMAC is used as a start instruction signal for starting acquisition of band information has been described as an example. However, the operation status signal of a functional module other than the DMAC may be used as the start instruction signal. good.

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the third embodiment, the bandwidth information acquisition condition is set when a plurality of buses are operating in competition, and by detecting a plurality of start instruction signals, only when a plurality of bus masters are in a competition state Control to obtain bandwidth information. In the following description, differences from the above-described embodiment will be described, and description of the same elements as those in the above-described embodiment will be omitted. The controller unit 120 in the third embodiment is the same as the controller unit 120 in the second embodiment shown in FIG.

<Bandwidth monitor>
FIG. 10 is a block diagram illustrating a configuration example of the bandwidth monitor 280 in the third embodiment. 10, components having the same functions as those shown in FIGS. 3 and 7 are denoted by the same reference numerals, and redundant description is omitted. The bandwidth monitor 280 according to the third embodiment determines the contention state of a plurality of bus masters from a plurality of start instruction signals, and starts acquiring bandwidth information when it is determined that the state is a contention state. Note that the bandwidth monitor 280 in the third embodiment shown in FIG. 10 and the respective functional units therein are also configured by hardware circuits.

  In the present embodiment, a condition for the bandwidth monitor to determine that it is in a competitive state and start obtaining bandwidth information is set in the register unit 301 by the CPU 200. The competition condition notification signal 1000 is a control signal that notifies the timing determination unit 300 of a condition for starting acquisition of the band information set in the register unit 301. The condition of the competition state set in the register unit 301 is set by selecting two or more of the buses 290 to 293 capable of band observation. The set bus combination is notified to the timing determination unit 300 by the competition condition notification signal 1000. Then, when a start instruction signal corresponding to the notified bus combination is input, the timing determination unit 300 starts to acquire the band information to the band acquisition unit that acquires the notified band information of the bus. To control. In addition, when at least one stop instruction signal corresponding to the notified bus is input, the timing determination unit 300 acquires the band information to all the band acquisition units that acquire the band information of the notified bus. Control to stop.

<Acquisition of bandwidth information and control of writing to SRAM>
FIG. 11 is a timing chart illustrating an example in which the bandwidth monitor 280 according to the third embodiment is configured to acquire bandwidth information when the bus 290 and the bus 292 are in a competitive state. Note that a case where the bus 290 and the bus 292 operate simultaneously includes, for example, a copy job that performs scan processing and print processing.

  At time t111, the CPU 200 sets a bus combination that is a competitive condition in the register unit 301 of the bandwidth monitor 280. A combination of buses may be arbitrarily set, or may be selected and set from predetermined combinations. At time t112, the CPU 200 receives a copy job start operation and issues a start instruction to the scanner unit 110 under a desired scan condition. At time t113, the CPU 200 receives a copy job start operation and issues a start instruction to the printer unit 140 under desired print conditions.

  At time t <b> 114, the vertical synchronization signal (SVSYNC) 282 is output from the scan processing unit 250. Here, the band monitor 280 holds that the vertical synchronization signal (SVSYNC) 282 is input, but does not start the acquisition of the band information because it does not satisfy the bus competition condition for starting the band information acquisition.

  Thereafter, a vertical synchronization signal (PVSYNC) 283 is input to the print processing unit 256 at time t115. Here, the bandwidth monitor 280 determines that the contention operation has started based on the bus combination set as the contention condition at time t111, and starts obtaining the bandwidth information of the bus 290 and the bus 292. Specifically, the timing determination unit 300 controls the band acquisition units 302 and 304 to start acquiring band information. Then, the band acquisition units 302 and 304 start acquiring the band information of the buses 290 and 292 and storing the acquired band information in the SRAM 281.

  At time t116, the DMAC 240 finishes writing all the image data to the RAM 270, and asserts a transfer end interrupt signal (INT_SPageEnd) 284 indicating that the writing is completed. The timing determination unit 300 controls the band acquisition units 302 and 304 to stop acquiring the band information because the set bus contention condition is not satisfied because the data transfer on the bus 290 is completed. I do. The bandwidth acquisition units 302 and 304 stop acquiring the bandwidth information of the buses 290 and 292 and save the bandwidth information in the SRAM 281.

  At time t117, the DMAC 246 asserts a transfer end interrupt signal (INT_PPageEnd) 285 indicating that all image data has been received. In the present embodiment, the acquisition of the band information has already been stopped at the previous time t116. Therefore, only the asserted transfer end interrupt signal (INT_PPageEnd) 285 is input to the timing determination unit 300, and the bandwidth acquisition units 302 and 304 corresponding to the transfer end interrupt signal (INT_PPageEnd) 285 are not controlled.

  By configuring as described above, it becomes possible to acquire bandwidth information only when a plurality of buses are competing. Therefore, even when a plurality of band information is acquired simultaneously, the time for acquiring the band information can be shortened, so that sufficient band information can be acquired with a small capacity SRAM.

<Band information acquisition and SRAM write control flow>
FIG. 12 is a flowchart showing an operation example of the bandwidth monitor 280 in the third embodiment. FIG. 12 illustrates an example in which the bandwidth monitor 280 determines the bus contention state and starts acquiring bandwidth information. In the following description, the simultaneous operation of the scan process and the print process will be described as an example of a competing operation. Needless to say, what can be set as a combination is not limited to this.

  In step S <b> 1201, the CPU 200 sets a bus combination that is a competitive condition in the register unit 301 of the bandwidth monitor 280. Here, the simultaneous operation of the bus 290 and the bus 292 is set as the competition condition. In step S1202, the timing determination unit 300 included in the band monitor 280 confirms whether or not the vertical synchronization signal (SVSYNC) 282 is input. In step S1203, the timing determination unit 300 confirms whether or not the vertical synchronization signal (PVSYNC) 283 signal is input.

  In step S1204, the timing determination unit 300 determines whether or not the bus contention condition for starting the acquisition of the band information is satisfied based on the results confirmed in steps S1202 and S1203. When the timing determination unit 300 determines that the bus competition condition is satisfied (Yes in step S1204), the process proceeds to step S1205, and when the timing determination unit 300 determines that the bus competition condition is not satisfied (No in step S1204). The process returns to step S1202.

  In step S1205, in response to the determination in step S1204 that the bus competition condition is satisfied, the timing determination unit 300 performs control so as to start obtaining the bandwidth information of each bus set as the competition condition in step S1201. I do. Specifically, the timing determination unit 300 controls the band acquisition units 302 and 304 to start acquiring the band information of the buses 290 and 292, and the band acquisition units 302 and 304 acquire and acquire the band information. The storage of the band information in the SRAM 281 is started. Thereafter, the band acquisition units 302 and 304 repeat the process of acquiring the band information in units of a certain time interval and writing it to the SRAM 281 until it is controlled to stop the acquisition of the band information in step S1209.

  In step S1206, the timing determination unit 300 determines whether or not the SRAM 281 to which band information is written is in a full state. When the timing determination unit 300 determines that the SRAM 281 is full (Yes in step S1206), the process proceeds to step S1209. On the other hand, when the timing determination unit 300 determines that the SRAM 281 is not full (No in step S1206), the process proceeds to step S1207.

  In step S1207, the timing determination unit 300 determines whether or not the transfer end interrupt signal (INT_SPageEnd) 284 of the DMAC 240 is input. When the timing determination unit 300 determines that the transfer end interrupt signal (INT_SPageEnd) 284 is not input (No in step S1206), the process proceeds to step S1208. On the other hand, if the timing determination unit 300 determines that the transfer end interrupt signal (INT_SPageEnd) 284 is input (Yes in step S1207), the process proceeds to step S1209.

  In step S1208, the timing determination unit 300 determines whether or not the transfer end interrupt signal (INT_PPageEnd) 285 of the DMAC 246 is input. If the timing determination unit 300 determines that the transfer end interrupt signal (INT_PPageEnd) 285 has not been input (No in step S1208), the bandwidth information needs to be continuously acquired, and thus the process proceeds to step S1206. On the other hand, if the timing determination unit 300 determines that the transfer end interrupt signal (INT_PPageEnd) 285 has been input (Yes in step S1208), the process proceeds to step S1209.

  Note that the processes in steps S1206, S1207, and S1208 are executed in any order, and may be executed in a different order from the example shown in FIG.

  In step S1209, the timing determination unit 300 controls the band acquisition units 302 and 304 to stop acquiring the band information in response to satisfying the condition for stopping the band information acquisition. As a result, the band acquisition units 302 and 304 stop acquiring the band information of the buses 290 and 292, and stop writing the band information to the SRAM 281.

  According to the third embodiment, the bandwidth information acquisition condition is set when a plurality of buses compete and operate, and a plurality of start instruction signals are detected. Band information can be acquired only at times. Therefore, even when a plurality of band information is acquired simultaneously, the band information acquisition time can be shortened, so that sufficient band information can be acquired even with a small capacity SRAM. Therefore, it is possible to sufficiently acquire the band information in a desired state while suppressing the capacity of the information storage unit that holds the band information.

  Note that the above-described first to third embodiments are not limited to being applied alone, and may be applied by appropriately combining the above-described embodiments.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100: Image forming apparatus 110: Scanner part 120: Controller part 140: Printer part 200: CPU 240-246: DMA controller 250: Scan processing part 256: Print processing part 260: Memory controller 270: RAM 280: Bandwidth monitor 281: SRAM 290 to 293: Bus 300: Timing determination unit 301: Register unit 302 to 305: Band acquisition unit 306: Multiplexer 307: SRAM interface

Claims (10)

An image forming apparatus having a memory accessed by a plurality of bus masters,
Band acquisition means connected to a bus between the memory controller for controlling the memory and the bus master, acquiring band information of the bus and holding it in an information storage unit;
When a start instruction signal output along with data transfer on the bus is input, and the start instruction signal is input, the band of the bus associated in accordance with the input start instruction signal An image forming apparatus comprising: a control unit that controls the acquisition unit to start acquiring the band information.   The image forming apparatus according to claim 1, wherein the start instruction signal is a vertical synchronization signal related to image formation.   The image forming apparatus according to claim 1, wherein the start instruction signal is an enable signal indicating that the bus master can perform transfer processing.   The control means receives a stop instruction signal that is output upon completion of data transfer on the bus, and when the stop instruction signal is input, is associated with the input stop instruction signal. The image forming apparatus according to claim 1, wherein the bandwidth acquisition unit of the bus is controlled to stop acquiring the bandwidth information.   When the start instruction signal of a plurality of preset buses is input, the control unit starts to acquire the band information to the band acquisition unit of all the set buses. The image forming apparatus according to claim 1, wherein the image forming apparatus is controlled.   The control means is a stop instruction signal output upon completion of data transfer on the bus, and when the stop instruction signal of any of the set buses is input, The image forming apparatus according to claim 5, wherein the band acquisition unit of all the set buses is controlled to stop acquiring the band information.   The plurality of bus masters include: a bus master that writes image data obtained by scanning processing to the memory; and a bus master that reads image data to be printed from the memory. The image forming apparatus according to claim 1.   The plurality of bus masters include a bus master that reads image data from the memory and writes the image data subjected to predetermined image processing to the memory. The image forming apparatus described. Band acquisition means connected to a bus between a memory controller for controlling a memory accessed by a plurality of bus masters and the bus master, acquiring bandwidth information of the bus and holding it in an information storage unit;
When a start instruction signal output along with data transfer on the bus is input, and the start instruction signal is input, the band of the bus associated in accordance with the input start instruction signal A bandwidth monitoring apparatus comprising: control means for controlling the obtaining means to start obtaining the bandwidth information. When the start instruction signal that is output along with the data transfer on the bus between the memory controller that controls the memory accessed by a plurality of bus masters and the bus master is input, the input that is input A step of controlling the bandwidth acquisition means connected to the bus associated in response to the instruction signal to start acquisition of bandwidth information of the bus;
The bandwidth monitoring method comprising: the bandwidth acquisition means controlled to start acquiring the bandwidth information of the bus, acquiring the bandwidth information of the bus and holding it in an information storage unit.

Images