JP2019197919A - Electronic device - Google Patents

Abstract

To improve reliability of an electronic device on which a semiconductor device is mounted.SOLUTION: An electronic device comprises a wiring board provided with: first wiring to which a first external terminal is connected; and second wiring to which a second external terminal is connected and which extends along the first wiring. The electronic device further comprises a semiconductor device which is mounted on the wiring board and electrically connected to each of the first wiring and the second wiring. The electronic device yet further comprises a capacitor which is mounted on the wiring board and electrically connected to the semiconductor device via each of the first wiring and the second wiring. The distance between the semiconductor device and the capacitor is shorter than that between the capacitor and each of the first and second external terminals.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an electronic device having a wiring board on which a semiconductor device and a capacitor are mounted, for example.

  For example, Japanese Patent Laying-Open No. 2013-236360 (Patent Document 1) describes that a crosstalk noise is suppressed by combining a power supply wiring for a phase synchronization circuit of a semiconductor device and a reference potential supply wiring. A capacitor is connected to the combined power supply line and reference potential supply line.

JP 2013-236360 A

  A semiconductor device is used in various applications. From the viewpoint of stably operating a semiconductor device, a technique for reducing noise that affects the operation of the semiconductor device is required. As a method of reducing noise that affects the operation of the semiconductor device, a method of mounting noise countermeasure parts such as capacitors on the wiring board on which the semiconductor device is mounted can be considered, but it is improved from the viewpoint of efficiently reducing noise. It turns out that there is room for.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An electronic device according to an embodiment includes a wiring board having a first wiring connected to a first external terminal and a second wiring connected to the second external terminal and extending along the first wiring. The electronic device includes a semiconductor device mounted on the wiring board and electrically connected to each of the first wiring and the second wiring. The electronic device includes a capacitor mounted on the wiring board and electrically connected to the semiconductor device via each of the first wiring and the second wiring. The distance between the semiconductor device and the capacitor is shorter than the distance between each of the first external terminal and the second external terminal and the capacitor.

  According to the one embodiment, the reliability of the electronic device on which the semiconductor device is mounted can be improved.

It is explanatory drawing which shows typically the structural example of the system which controls an electronic component with an electronic device. It is explanatory drawing which shows the structural example of the test apparatus which tests the noise tolerance of the electronic device shown in FIG. FIG. 3 is a plan view showing a structural example of the electronic device shown in FIG. 2. It is a top view of the surface on the opposite side of the electronic device shown in FIG. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view along the BB line of FIG. It is an expanded sectional view of the capacitor | condenser shown in FIG. FIG. 4 is an equivalent circuit diagram of the electronic device shown in FIG. 3. FIG. 4 is a plan view of the wiring board from which the semiconductor device and the capacitor shown in FIG. 3 are removed. FIG. 10 is an enlarged plan view showing the periphery of the capacitor connecting portion shown in FIG. 9 in an enlarged manner. It is explanatory drawing which shows the characteristic curve which concerns on the frequency and impedance of a ceramic capacitor and an aluminum electrolytic capacitor. In the electronic device shown in FIG. 3, it is explanatory drawing which compares the characteristic curve with the case where an electrolytic capacitor is used as a capacitor | condenser for noise suppression, and the case where a ceramic capacitor is used. It is a top view which shows the electronic device of the modification with respect to FIG. It is a top view which shows the electronic device of the other modification with respect to FIG. It is a top view which shows the modification of the electronic device shown in FIG. FIG. 16 is an enlarged cross-sectional view taken along a wiring shown as a wiring 12g3 in the reference potential wiring shown in FIG. 15; It is a top view which shows the other modification with respect to FIG. It is a top view which shows the other modification with respect to FIG. It is a top view which shows the other modification with respect to FIG. It is a top view which shows the modification with respect to FIG. It is explanatory drawing which shows typically the definition of the wiring path | route demonstrated using FIG. 9, and the definition of a different wiring path | route. FIG. 22 is an enlarged cross-sectional view schematically showing an example of a wiring path inside the external terminal shown in the external terminal shown in FIG. 21. It is a top view of the electronic device which is an example of examination with respect to FIG. It is a top view of the electronic device which is a modification with respect to FIG. In the electronic device shown in FIG. 23, it is explanatory drawing which compares the characteristic curve with the case where an electrolytic capacitor is used as a capacitor | condenser for noise countermeasures, and the case where a ceramic capacitor is used.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

(Embodiment)
<Examples of using electronic devices>
First, an example of the application of the electronic device of this embodiment will be described with reference to FIG. FIG. 1 is an explanatory diagram schematically illustrating a configuration example of a system that controls an electronic component by the electronic apparatus according to the present embodiment. FIG. 2 is an explanatory diagram illustrating a configuration example of a test apparatus that tests noise resistance of the electronic device illustrated in FIG. 1.

  Along with miniaturization and higher functionality of semiconductor devices, semiconductor devices are incorporated into various devices and used as control components. For example, when considering automobiles and motor-driven motorcycles as examples, drive control of power systems such as engines and motors, operation control of various parts that transmit power to tires, control of optical parts such as lighting and blinkers, or doors It is used to control various parts such as window control. By building a control system using a semiconductor device, the control system can be enhanced. Alternatively, the control system can be reduced in size by constructing the control system using a semiconductor device.

  When a control electronic device is incorporated into a large-sized device such as an automobile or a motor-driven two-wheeled vehicle, there are many cases where a distance between the electronic device and a component that is a control target is large. For example, it is preferable to arrange the drive circuit of each component to be controlled in the vicinity of each component. On the other hand, in consideration of the operability and maintainability of the operator, it is preferable to arrange controller parts such as a control circuit in a part of the equipment. As a result, the distance between the control circuit and each component is increased.

  As in the present embodiment, when the distance between the component that is the object of control and the electronic device is large, it is necessary to electrically connect the component and the electronic device by some method. For example, in the control system shown in FIG. 1, an electronic device EDV1 that is a control component and a component COM1 that is a controlled component are electrically connected via an electric wire HAR1. Further, the power supply PWS1 and the electronic device EDV1 which is a control component are electrically connected via the electric wire HAR2. The electric wire HAR1 and the electric wire HAR2 shown in FIG. 1 may be a collective wiring (harness) in which a plurality of wiring paths are bundled.

  In addition, the component COM1 that is the controlled component shown in FIG. 1 has various modifications as described above. In the present embodiment, as an example of the component COM1, a turn indicator attached to a motorcycle with a motor is used. Take up and explain. Further, the semiconductor device included in the electronic device EDV1 includes a control circuit that controls (relay control) the operation of the direction indicator (lighting operation, extinguishing operation, or blinking operation).

  In the example shown in FIG. 1, the power supply potential Vcc is transmitted from the power supply PWS1 to the electronic device EDV1 via the electric wire HAR2 (power supply line 11V). The output potential (or output signal) OUT from the electronic device EDV1 is transmitted from the electronic device EDV1 toward the component COM1 via the electric wire HAR1 (output line 11A). The reference potential GND is transmitted from the power supply PWS1 to the component COM1 via the electric wire HAR3. Thereby, in the control system shown in FIG. 1, the drive of the component COM1 is controlled by the control circuit included in the electronic device EDV1.

  As shown in FIG. 1, when the control component and the power supply PWS1 or between the control component and the controlled component are connected by the electric wire HAR1 or the electric wire HAR2, the operation characteristics of the control circuit are applied from the electric wire HAR1 or the electric wire HAR2. Noise may have an effect. When the lengths of the electric wires HAR1 and HAR2 are increased, the possibility that electromagnetic waves are applied to the electric wires HAR1 and HAR2 increases. Therefore, from the viewpoint of improving the reliability of the control system, it is preferable to improve the noise resistance of the electronic device EDV1 having the control circuit.

  The influence of the noise applied from the electric wire connected to the electronic device EDV1 on the operation characteristics of the control circuit can be evaluated using a test apparatus as shown in FIG. The test apparatus shown in FIG. 2 is a test apparatus that performs an immunity test of a test target product. Specifically, the test performed by the test apparatus shown in FIG. 2 is called a BCI (Bulk Current Injection) test, and is a test apparatus that performs an immunity test defined by the ISO standard (ISO 11452-4).

  In the test apparatus shown in FIG. 2, the electronic device EDV1 which is a test target product and the power supply PWS2 are electrically connected via a plurality of electric wires HAR4 and HAR5. In each of the electric wires HAR4 and HAR5, a pseudo power supply network LISN1 is connected between the power supply PWS2 and the electronic device EDV1. The electric wires HAR4 and HAR5 are bundled and inserted into a coil (injection probe) IJP1 arranged in the vicinity of the electronic device EDV1. In the BCI test, noise is artificially generated by passing a current through the coil IJP1, and the noise resistance of the electronic device EDV1, which is a test target product, is evaluated.

  When evaluating the noise tolerance of the electronic device EDV1, an output signal from the electronic device EDV1 may be detected and evaluated. In the present embodiment, as described above, the component COM1 shown in FIG. 1 is a direction indicator. Therefore, in the example shown in FIG. 2, the lamp LAM1 is arranged in the wiring path of the electric wire HAR4, and the noise resistance of the electronic device EDV1 is evaluated based on the lighting operation of the lamp LAM1. For example, when a current is passed through the coil IJP1, the electronic device EDV1 is affected by noise, so that the blinking speed of the lamp LAM1 changes. When the blinking speed of the lamp LAM1 exceeds a preset allowable range (threshold), it can be determined that the electronic device EDV1 has malfunctioned.

<Electronic device>
Next, a configuration example of the electronic device EDV1 illustrated in FIGS. 1 and 2 will be described. FIG. 3 is a plan view showing a structural example of the electronic device shown in FIG. FIG. 4 is a plan view of the opposite surface of the electronic device shown in FIG. 5 is an enlarged sectional view taken along line AA in FIG. 3, and FIG. 6 is an enlarged sectional view taken along line BB in FIG. FIG. 7 is an enlarged cross-sectional view of the capacitor shown in FIG. FIG. 8 is an equivalent circuit diagram of the electronic device shown in FIG.

  As shown in FIGS. 5 and 6, in the present embodiment, each of the plurality of wirings 12 is formed on the main surface 10t side and covered with the insulating film 10SR. However, in order to explicitly show the planar shape of the wiring 12, in FIG. 3 and FIG. 4, the outline of the wiring 12 is indicated by a dotted line. FIG. 8 shows an oscillation circuit including two bipolar transistors as an example of a circuit formed in the semiconductor chip 21. However, the circuit included in the semiconductor chip 21 has various modifications. For example, a circuit other than the oscillation circuit may be provided. Further, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used as the transistor.

  As shown in FIGS. 3 and 4, the electronic device EDV1 of the present embodiment has a structure in which a plurality of components are mounted on a wiring board 10 that is a base material, and each component is electrically connected via a wiring 12. Is the body. As shown in FIG. 3, the electronic device EDV <b> 1 has a semiconductor device 20 mounted on the main surface 10 t of the wiring substrate 10 and a capacitor 30. As shown in FIG. 4, the electronic device EDV <b> 1 includes a capacitor 40, a diode 50, and a plurality of external terminals (connectors) 60 that are mounted on the main surface 10 b of the wiring board 10.

  The wiring board 10 has a main surface (surface, surface, upper surface, semiconductor device mounting surface) 10t shown in FIG. 3 and a main surface (surface, back surface, lower surface, external terminal mounting surface) 10b opposite to the main surface 10t (FIG. 4). In the example of the present embodiment, as shown in FIG. 5, the wiring board 10 includes a base material 10B made of an insulating material, and the base material 10B includes a main surface 10t and a main surface 10b. Each of the main surface 10t and the main surface 10b of the base material 10B is covered with an insulating film (solder resist film).

  In addition, the wiring substrate 10 includes a plurality of wirings 12. As shown in FIG. 3, the plurality of wirings 12 include a wiring 12 v constituting a power supply line (wiring path) 11 </ b> V that supplies a power supply potential to the semiconductor device 20. The plurality of wirings 12 include a wiring 12a that constitutes an output line (wiring path) 11A through which a potential (signal) output from the semiconductor device 20 is transmitted. 3 includes a wiring 12e that electrically connects the semiconductor device 20 and the oscillation circuit capacitor 40 (see FIG. 4) in a wiring path 11E different from the power supply line 11V and the output line 11A. It is.

  In the following description, each of the wiring paths such as the power supply line 11V and the output line 11A is configured by one wiring 12v and 12a, and a part of the wiring 12v and 12a is connected to the connecting portion 13 and the connecting portion 14. Alternatively, the description will be made assuming that the connection portion 15 is provided. However, as another expression, the connection portion 13, the connection portion 14, the connection portion 15, and the wiring 12 that electrically connects these connection portions can be considered as separate components. In this case, each of the wiring paths such as the power supply line 11V and the output line 11A is expressed as having a connection part 13, a connection part 14, and a connection part 15 connected via a plurality of wirings 12v and 12a. it can.

  Further, in the present embodiment, each of the plurality of wirings 12 is formed on the main surface 10 t side of the wiring board 10. Each of the plurality of wirings 12 is a metal pattern formed of a metal material such as copper, for example. As shown in FIG. 5, each of the plurality of wirings 12 electrically connects a plurality of components (for example, the semiconductor device 20, the capacitor 30, the capacitor 40, the diode 50, and the external terminal 60) mounted on the wiring substrate 10. It is patterned to be elongated so as to be connected to. In other words, each of the plurality of wirings 12 has an extending direction extending so as to electrically connect a plurality of components mounted on the wiring board 10 and a width direction orthogonal to the extending direction, and the width direction Is shorter than the length in the extending direction.

  Further, as shown in FIGS. 5 and 6, most of the plurality of wirings 12 are covered with the insulating film 10SR. The insulating film 10SR is provided with an opening in part, and a part of the wiring 12 is exposed from the insulating film 10SR in the opening. Further, a portion of the wiring 12 exposed from the insulating film 10SR is electrically connected to the semiconductor device 20 shown in FIG. 5, the capacitor 30, and the electrode portion of the external terminal 60 shown in FIG.

  In other words, a portion of the wiring 12 exposed from the insulating film 10SR is a plurality of components (for example, the semiconductor device 20, the capacitor 30, the capacitor 40, the diode 50, and the external terminal 60) mounted on the wiring substrate 10. It functions as a connection part (device connection part, capacitor connection part, external connection part) for electrical connection. A plurality of connection parts (device connection parts) 13, a plurality of connection parts (capacitor connection parts) 14, a plurality of connection parts (external terminal connection parts) 15, and a plurality of connection parts (electronic component connection parts) 16 shown in FIG. Are formed integrally with the wiring 12.

  Specifically, the wiring 12a constituting the output line 11A includes a connection portion 13a to which the terminal 22a of the semiconductor device 20 is connected, a connection portion 14a to which the electrode 31a of the capacitor 30 is connected, and an external terminal 60 (see FIG. 6). It has the connection part 15a to which the electrode (pin) 61a (refer FIG. 4) is connected. In other words, each of the connection portion 13a, the connection portion 14a, and the connection portion 15a is electrically connected to each other via the wiring 12a. Further, the wiring 12v constituting the power supply line 11V includes a connection portion 13v (see FIG. 5) to which the terminal 22v (see FIG. 5) of the semiconductor device 20 is connected, a connection portion 14v to which the electrode 31v of the capacitor 30 is connected, and It has the connection part 15v to which the electrode (pin) 61v (refer FIG. 4) of the external terminal 60 (refer FIG. 6) is connected. In other words, each of the connection portion 13v, the connection portion 14v, and the connection portion 15v is electrically connected to each other via the wiring 12v.

  Further, as shown in FIG. 3, the semiconductor device 20 is mounted on the main surface 10 t of the wiring substrate 10. The semiconductor device 20 includes a control circuit that controls the component COM1 shown in FIG. As described above, in the example of the present embodiment, the component COM1 shown in FIG. 1 is a direction indicator attached to the two-wheeled motor vehicle, and the semiconductor device 20 operates as a direction indicator (lighting operation, extinguishing operation, Or a control circuit for controlling the blinking operation). The semiconductor device 20 includes a semiconductor chip 21 (see FIG. 5) on which the control circuit is formed, a plurality of terminals (device terminals and lead terminals) 22 electrically connected to the semiconductor chip 21, and the semiconductor chip 21. This is a semiconductor package having a sealing body (resin body) 23 for sealing.

  The semiconductor device 20 is electrically connected to the wiring 12v, the wiring 12a, and the wiring 12e of the wiring board 10 through a plurality of terminals 22. Specifically, as shown in FIG. 3, a terminal (lead terminal) 22a among the plurality of terminals 22 included in the semiconductor device 20 is electrically connected to the wiring 12a and constitutes a part of the output line 11A. The terminal 22a is electrically connected to a connection portion (device connection portion) 13a formed on the wiring substrate 10 via a solder material 26. In addition, a terminal 22v (see FIG. 5) among the plurality of terminals 22 included in the semiconductor device 20 is electrically connected to the wiring 12v and constitutes a part of the power supply line 11V. The terminal 22v is electrically connected to a connection portion (device connection portion) 13v formed on the wiring substrate 10 via a solder material 26. In addition, a terminal (lead terminal) 22e among the plurality of terminals 22 included in the semiconductor device 20 is electrically connected to the wiring 12e. The terminal 22e is electrically connected to a connection portion (device connection portion) 13e formed on the wiring board 10 via a solder material 26.

  In the example shown in FIG. 5, the semiconductor chip 21 is mounted on the die pad 24. The semiconductor chip 21 is fixed to the die pad 24 via a die bond material 25. The die bond material 25 is a conductive member such as a solder material or a conductive adhesive, and the semiconductor chip 21 is electrically connected to the die pad 24. The die pad 24 is electrically connected to the connection portion 13v formed on the main surface 10t of the wiring board 10 via the solder material 26. That is, the die pad 24 provided in the semiconductor device 20 of the present embodiment functions as a terminal 22v that electrically connects the semiconductor chip 21 and the connection portion 13v.

  As shown in FIG. 3, a capacitor 30 is mounted on the main surface 10 t of the wiring board 10. As shown in FIG. 8, the capacitor 30 has one electrode connected to the power supply line 11V and the other electrode connected to the output line 11A. When the capacitor 30 is connected between the power supply line 11V and the output line 11A, noise flowing in the power supply line 11V or the output line 11A can be filtered. A capacitor that is inserted in parallel between the power supply line 11V and the output line 11A like the capacitor 30 and filters noise flowing in the power supply line 11V or the output line 11A is called a bypass capacitor.

  In the example shown in FIG. 3, the connection portion 13a to which the electrode 31a of the capacitor 30 is connected is arranged in the middle of the direction DR1 in which the wiring 12a extends. Further, the connection portion 13v to which the electrode 31v of the capacitor 30 is connected is disposed in the middle of the direction DR1 in which the wiring 12v extends. The capacitor 30 is mounted across the wiring 12a and the wiring 12v so that the electrode 31a and the electrode 31v are aligned along the direction DR2 intersecting (orthogonal in FIG. 3) with respect to the direction DR1.

  As shown in FIG. 3, the capacitor (chip capacitor) 30 forms a quadrangle in plan view. Further, the capacitor 30 has two long sides (long side surfaces) and two short sides (short side surfaces). Capacitor 30 includes electrode 31a and electrode 31v provided at opposite ends. In the example of the present embodiment, the two electrodes 31 are located at opposite ends of the long side of the capacitor 30 in the extending direction. The capacitor 30 has a main body 32 sandwiched between the electrode 31a and the electrode 31v. For example, as shown in FIG. 7, the main body 32 includes a plurality of conductor plates 34 stacked via an insulating layer (dielectric layer) 33, and each of the plurality of conductor plates 34 includes an electrode 31 a and an electrode. It is connected to one of 31v. The electrode 31a and the electrode 31v function as an external electrode terminal for taking out a capacitance formed between a plurality of conductive plates arranged opposite to each other.

  The capacitor 30 having the structure shown in FIG. 7 often uses a ceramic insulating layer 33 and is called a ceramic capacitor. As shown in FIG. 7, the capacitor 30 is a surface-mount type electronic component that can be mounted on the surface of the wiring substrate 10. The surface-mount type electronic component is also called a chip component (a chip capacitor in the case of the capacitor 30).

  On the other hand, the capacitor 40 shown in FIGS. 4 and 5 forms an insulating film (or semiconductor film) such as an oxide film on the surface of the electrode by subjecting a conductor plate (not shown) to chemical treatment, and this insulating film is formed into a dielectric. It is a capacitor used as Capacitor 40 obtains a predetermined capacity by laminating a conductor plate that has been subjected to surface treatment, but is filled with an electrolyte so as to fill a gap between the laminated conductor plates. For this reason, the capacitor having the structure of the capacitor 40 is called an electrolytic capacitor. The electrolytic capacitor has a rod-shaped (pin type) electrode 41 (see FIG. 4). In the present embodiment, the electrode 41 of the capacitor 40 is inserted into the through hole of the wiring substrate 10 and the inserted portion is fixed with a solder material. A connection portion 16 (see FIG. 3) is provided at a portion where the electrode 41 is inserted, and the connection portion 16 and the electrode 41 are electrically connected via a solder material.

  The capacitor 30 that is a ceramic capacitor has a smaller volume and a smaller mounting area than the capacitor 40 that is an electrolytic capacitor. Further, the capacity of the capacitor 30 is smaller than the capacity of the capacitor 40. For example, the capacity of the capacitor 30 is about 0.1 μF to 10 μF. On the other hand, the capacity of the capacitor 40 is about 22 μF to 100 μF.

  Although an example of the structure of the capacitor 30 has been described above, there are various modifications to the structure and capacity of the capacitor 30.

  Further, as shown in FIG. 4, a plurality of external terminals 60 are mounted on the main surface 10 b of the wiring board 10. The external terminal 60 is a terminal for an external interface of the electronic device EDV1, and is a connector for electrically connecting a plurality of wires 12 of the electronic device and the electric wires HAR1 and HAR2 shown in FIG. The external terminal 60 is a component having a large size in consideration of the connectivity with the electric wires HAR1 and HAR2 shown in FIG. For example, in the present embodiment, the surface area of the external terminal 60 is larger than the surface area of the capacitor 30 and the surface area of the semiconductor device 20 shown in FIG. Although details will be described later, when the external terminal 60 having a large surface area is inserted in the middle of the power supply line 11V and the output line 11A shown in FIG. 1 as in the present embodiment, it is necessary to consider the noise effect of the external terminal 60 itself. There is.

  Further, as shown in FIG. 4, electronic components such as a capacitor 40 and a diode 50 are mounted on the main surface 10 b of the wiring substrate 10. In the example of the present embodiment, as shown in FIG. 8, one electrode of the capacitor 40 is connected to the output line 11A, and the other electrode is connected to the wiring path 11E different from the power supply line 11V and the output line 11A. Has been. In the example illustrated in FIG. 8, the wiring path 11 </ b> E is connected to an input terminal (base terminal or gate terminal) of a transistor included in the semiconductor chip 21. The circuit illustrated in FIG. 8 operates as an oscillation circuit in which an output potential is supplied from the output line 11A (on state) and a state in which no output potential is supplied (off state) are alternately repeated. As shown in FIG. 1, the output line 11A is connected to a component COM1 on the load side, and the potential supplied to the component COM1 is turned on and off. As described above, in the example of the present embodiment, since the component COM1 is a direction indicator, the direction indicator blinks when the output potential is turned on / off. The interval of the blinking operation is determined by the capacitance value of the capacitor 40 shown in FIG. 8 and the resistance value included in the oscillation circuit.

  In the example of the present embodiment, the anode electrode of the diode 50 is connected to the output line 11A and the cathode electrode is connected to the power supply line 11V as shown in FIG. The diode 50 has a rod-shaped (pin type) electrode 51 (see FIG. 4). In the present embodiment, the electrode 51 of the diode 50 is inserted into the through hole of the wiring board 10 and the inserted portion is fixed with a solder material. A connection portion 16 (see FIG. 3) is provided at a portion where the electrode 51 is inserted, and the connection portion 16 and the electrode 51 are electrically connected via a solder material. The electronic components such as the capacitor 40 and the diode 50 are components that are mounted according to the specifications of the electronic device EDV1, and may not be mounted depending on the circuit of the electronic device EDV1.

<Relationship between noise and layout>
Next, the relationship between the noise effect on the semiconductor device included in the electronic device and the layout on the wiring board will be described in detail with reference to an example of study on the electronic device of the present embodiment. FIG. 23 is a plan view of an electronic device that is a study example with respect to FIG. FIG. 24 is a plan view of an electronic device which is a modification example of FIG. FIG. 9 is a plan view of the wiring board from which the semiconductor device and the capacitor shown in FIG. 3 are removed. FIG. 10 is an enlarged plan view showing the periphery of the capacitor connecting portion shown in FIG. 9 in an enlarged manner.

  23 and 24, the outlines of the conductor patterns 12ha, 12hv, 12he and the external terminal 60 are indicated by dotted lines. 23 and 24 schematically show examples of the layout of the capacitors 40 and the diodes 50 arranged on the back surface of the wiring board 10 using circuit symbols. In FIG. 9, the wiring path distances 11a1, 11a2, 11v1, and the wiring path distance 11v2 are schematically shown with double arrows. Further, in FIG. 10, the illustration of the plurality of wirings 12 other than the wiring 12a and the wiring 12v among the plurality of wirings 12 illustrated in FIG. 9 is omitted.

  In order to improve the reliability of an electronic device in which a semiconductor device including a control circuit is mounted as in this embodiment, it is necessary to improve the operation reliability of the control circuit formed in the semiconductor device. For this reason, it is necessary to improve the noise tolerance of the semiconductor device so that the control circuit operates stably.

  Further, from the viewpoint of improving the versatility of the electronic device, it is preferable to take measures against noise that can suppress noise transmission in a relatively wide frequency band. In order to improve the noise immunity of a circuit, first of all, a bypass capacitor that reduces the impedance value of the circuit in the frequency band where the amount of noise propagation is increased among the frequency bands targeted for noise immunity improvement. It is effective to connect to the wiring route that is the target of countermeasures. By connecting a capacitor between two wiring paths that are subject to noise countermeasures, the impedance of the circuit can be reduced in a frequency band corresponding to the capacitance value of the capacitor.

For example, in the case of the example shown in FIG. 3, the semiconductor device 20 can be cited as a component that greatly affects circuit noise propagation. In a frequency band close to the anti-resonance frequency of the semiconductor device 20, the impedance value of the circuit increases rapidly, and noise is easily propagated (in other words, noise resistance is reduced). The anti-resonance frequency is a resonance frequency value f ₀ when a certain component (in the above example, the semiconductor device 20) is considered as a parallel resonance circuit of a resistance component R, a capacitance component C, and an inductor component L. , F ₀ = 1 / 2π (LC) ^1/2 . In the parallel resonance circuit, the flowing currents cancel each other out at the resonance frequency, and the current value is minimized when viewed from the outside of the resonance circuit, so that the apparent impedance is maximized.

  Therefore, if a bypass capacitor having an electrical characteristic for reducing the impedance in the vicinity of the anti-resonance frequency of the semiconductor device 20 is inserted between the power supply line 11V and the output line 11A shown in FIG. The amount of noise caused by the semiconductor device 20 propagating through 11A can be reduced. However, according to the study by the present inventor, it has been found that the impedance reduction effect in a predetermined frequency band cannot be obtained depending on the layout of the wiring and the bypass capacitor. The result of this examination will be described in detail later.

  Further, as shown in FIG. 1, when connecting an electric wire to the electronic device EDV1, it is necessary to consider the influence that noise from the electric wire side (in other words, the external terminal 60 side shown in FIG. 4) is propagated to the semiconductor device 20. There is. Further, as shown in FIG. 6, when the external terminal 60 having a large surface area (see FIG. 6) is mounted, it is necessary to consider the noise effect of the external terminal 60 itself. Therefore, in order to improve the noise immunity of the circuit of the present embodiment, the frequency band close to the anti-resonance frequency of the semiconductor device 20 and the external terminal 60 (considering the influence of the wire when a wire is connected). It is necessary to reduce the impedance in a frequency band close to the antiresonance frequency.

  Therefore, the inventor of the present application, as a noise countermeasure method when there are a plurality of main noise sources, connects a plurality of bypass capacitors having different frequency characteristics to the circuit, and a frequency band close to each of the anti-resonance frequencies of the plurality of noise sources. The method of improving the noise resistance in the slab was investigated. In this case, if the difference between the anti-resonance frequencies of the plurality of noise sources is large, a bypass capacitor corresponding to each of the plurality of types of anti-resonance frequencies can be connected. In addition, when performing noise filtering at a low frequency, an inductor for noise filtering may be inserted into the circuit.

  Note that, when a plurality of wirings run parallel to each other as in this embodiment, capacitive coupling occurs between adjacent wirings. In view of this, a technology for using the capacitance generated between parallel wirings as a bypass capacitor was studied. However, for example, assuming that the wiring width is 0.2 mm and the distance between the wirings is 0.1 mm and ignoring the effects other than the two wirings that run in parallel, the parallel running distance (the two wirings extend along each other). Even when the distance is 30 mm, the capacitance value is about 0.8 pF (picofarad). With such a capacitance value, it is difficult to obtain an effect as a noise filtering bypass capacitor. Therefore, when providing a noise filtering bypass capacitor, it is preferable to use a capacitor capable of obtaining a capacity of 0.001 μF or more, such as a ceramic capacitor or an electrolytic capacitor.

  Further, when the number of electronic parts for noise suppression increases, a space for mounting the electronic parts on the wiring board is required. Therefore, the inventor of the present application examined the reduction of the number of noise countermeasure parts. As a result of this examination, the impedance of the capacitor 30 is devised by devising the layout of the bypass capacitor (capacitor 30) and the wirings 12v and 12a in the wiring board 10 as in the electronic device EDV1 of the present embodiment shown in FIG. It has been found that the reduction effect can reduce the propagation of noise caused by the semiconductor device 20 and the propagation of noise caused by the external terminal 60 (see FIG. 4).

  Hereinafter, description will be made with reference to the electronic device Eh1 of the examination example shown in FIG. 23 and the electronic device EDV1 of the present embodiment shown in FIG. In the following description, the electronic device Eh1 will be described focusing on differences from the electronic device EDV1 shown in FIG. Accordingly, with respect to the electronic device Eh1, the portions other than the portions described below are the same as those described above for the electronic device EDV1.

  In the electronic device Eh1 shown in FIG. 23, the pattern of the power supply line 11V, the output line 11A and the wiring path 11E formed on the wiring board 10h, and the positional relationship between the electronic components mounted on the wiring board 10h are shown in FIG. Different from the electronic device EDV1.

  In the electronic device Eh1, each of the conductor pattern 12hv constituting the power supply line 11V and the conductor pattern 12ha constituting the output line 11A is a large-area conductor pattern. Most of the main surface 10t of the wiring substrate 10h (at least half or more and 2/3 or more in the example shown in FIG. 23) is covered with the conductor pattern 12hv or the conductor pattern 12ha.

  In the electronic device EDV1 shown in FIG. 3, the external terminal 60 (see FIG. 4), the capacitor 30, and the semiconductor device 20 are connected in order along the extending direction of the wiring 12v and the wiring 12a. On the other hand, in the case of the electronic device Eh1 shown in FIG. 23, the connection order is not as clear as the electronic device EDV1, but the semiconductor device 20 is arranged between the capacitor 30 and the external terminal 60 as an arrangement of components. In the case of the electronic device Eh1, the circuit connection relationship can be expressed in the same manner as the circuit diagram of the electronic device EDV1 shown in FIG.

  In the case of the electronic device Eh1, the resistance values of the power supply line 11V and the output line 11A can be reduced by increasing the areas of the conductor pattern 12hv and the conductor pattern 12ha. However, as a result of the noise tolerance test shown in FIG. 2 for the electronic device Eh1, it was found that a malfunction of the control circuit occurred in some frequency bands.

  In the above test, the following reasons can be considered as the reason why the control circuit malfunctioned. That is, when the capacitor 30 is not provided between the semiconductor device 20 and the external terminal 60 as in the electronic device Eh1, noise is propagated without passing through the capacitor 30, so that the effect of noise reduction by the capacitor 30 is achieved. It is thought that was not obtained.

  Next, as shown in FIG. 24, the noise propagation amount reduction effect was evaluated for the electronic device Eh <b> 2 in which the capacitor 30 is disposed between the semiconductor device 20 and the external terminal 60. The electronic device Eh2 shown in FIG. 24 is different from the electronic device Eh1 shown in FIG. 23 in that the arrangement of the capacitor 30 is different and the external terminal 60 is mounted on the wiring. Except for the above differences, the electronic device is the same as the electronic device Eh1 shown in FIG.

  The effect of reducing the amount of noise propagation can be evaluated using a correlation diagram of frequency and circuit impedance in addition to the test method described with reference to FIG. That is, if there is a frequency where the impedance is locally high, it means that noise is easily propagated in that frequency band. In addition, in the correlation diagram between the frequency and the impedance, it can be considered that the noise resistance is improved if the peak value of the impedance in the vicinity of the anti-resonance frequency becomes small.

  In the case of the electronic device Eh2 shown in FIG. 24, it was found that the peak value of the impedance can be slightly reduced in the correlation diagram between the frequency and the impedance, as compared with the electronic device Eh1 shown in FIG. This is considered because the amount of noise propagated without passing through the capacitor can be reduced by disposing the capacitor 30 between the semiconductor device 20 and the external terminal 60. Therefore, if the path for electrically connecting the external terminal 60 and the semiconductor device 20 is reduced by bypassing the capacitor 30, the effect of reducing impedance by the capacitor 30 can be increased.

  Moreover, according to examination of this inventor, it turned out that there exists room to improve noise tolerance further with respect to the electronic device Eh2 shown in FIG. The inventor of the present application paid attention to the phase difference between two wiring paths in which bypass capacitors are inserted. For example, in the case of the electronic device Eh2 shown in FIG. 24, the path from the connection portion 15 connected to the external terminal 60 to the connection portion 14 connected to the capacitor 30 is the wiring route distance of each of the power supply line 11V and the output line 11A. Therefore, the occurrence of a phase difference between the external terminal 60 and the capacitor 30 can be suppressed. However, between the capacitor 30 and the semiconductor device 20, the pattern widths of the conductor patterns 12hv and 12ha are large and the transmission path is not stable, so that a phase difference is likely to occur between the power supply line 11V and the output line 11A. As a result, noise due to the phase difference between the power supply line 11V and the output line 11A is easily propagated to the semiconductor device 20, which causes a reduction in noise resistance as a whole of the electronic device Eh2.

  On the other hand, as shown in FIG. 3, in the electronic device EDV1 of the present embodiment, the wiring 12v constituting the power supply line 11V and the wiring 12a constituting the output line 11A are arranged so as to extend along each other. As shown in FIG. 3, the wiring 12 v and the wiring 12 a extend in different directions in a portion overlapping the connection portion 15 connected to the external terminal 60 (see FIG. 4). However, between the connection portion 14 and the connection portion 13 that connect the capacitor 30 and the semiconductor device 20, the wiring 12v and the wiring 12a extend along each other. Further, the wiring 12v and the wiring 12a extend along each other in the most part between the connecting portion 14 and the connecting portion 15 that connect the external terminal 60 and the capacitor 30. Specifically, in the region between the connecting portion 14 and the connecting portion 15 (the connecting portion 15 having the shortest wiring path distance to the connecting portion 14), the wiring 12v and the wiring 12v are more than half of the wiring paths of the wiring 12v and the wiring 12a. The wiring 12a extends along each other.

  Thus, if the wiring 12v and the wiring 12a are arranged so as to extend along each other, it is possible to suppress a phase difference between the power supply line 11V and the output line 11A. As a result, the electronic device EDV1 can improve noise resistance.

  Further, from the viewpoint of suppressing the propagation of noise to the semiconductor device 20, it is particularly important to suppress the occurrence of a phase difference between the capacitor 30 and the semiconductor device 20. Therefore, it is preferable to make the wiring path distance between the capacitor 30 and the semiconductor device 20 as short as possible. On the other hand, when the wiring path distance between the capacitor 30 and the external terminal 60 (see FIG. 4) becomes long, a phase difference may occur between the capacitor 30 and the external terminal 60. However, even if a phase difference occurs between the capacitor 30 and the external terminal 60, the noise component is filtered by the capacitor 30 unless the noise due to the phase difference is extremely large. Therefore, it is possible to suppress the noise caused by the phase difference from being propagated to the semiconductor device 20. That is, shortening the wiring path distance between the capacitor 30 and the external terminal 60 has a lower priority than shortening the wiring path distance between the capacitor 30 and the semiconductor device 20.

  Although details will be described later, in the electronic device EDV1 of the present embodiment, the value of the anti-resonance frequency on the semiconductor device 20 side and the external terminal are adjusted by adjusting the wiring path distance between the capacitor 30 and the external terminal 60. The impedance in the vicinity of both anti-resonance frequencies is reduced by one capacitor 30 so that the value of the anti-resonance frequency on the 60 side is close.

  Therefore, in the present embodiment, the wiring path distance of the wiring path connecting the capacitor 30 and the semiconductor device 20 shown in FIG. 3 is shorter than the wiring path distance connecting the capacitor 30 and the external terminal 60. . Specifically, in the wiring 12a shown in FIG. 9, the wiring path distance 11a1 between the connection part 13a and the connection part 14a is the connection of the wiring path distance 11a2 between the connection part 15a and the connection part 14a and the wiring 12v. Each of the wiring path distances 11v2 between the portion 15v and the connection portion 14v is shorter than each. Further, in the wiring 12a shown in FIG. 9, the wiring path distance 11v1 between the connection part 13v and the connection part 14v is the wiring path distance 11v2 between the connection part 15v and the connection part 14v, and the connection part of the wiring 12a. Each of the wiring path distances 11a2 between 15a and the connecting portion 14a is shorter than each.

  In addition, as shown in FIG. 9, the wiring route distance between each connection part is defined as a route distance which connects the center of each connection part. Also, as shown in FIG. 9, when there are a plurality of connection portions 15a, the route distance from the connection portion 15a to the connection portion 14a having the shortest wiring route distance to the connection portion 14a among the plurality of connection portions 15a is as follows. , Defined as a wiring path distance 11a2. Similarly, when there are a plurality of connection portions 15v, the route distance from the connection portion 15v to the connection portion 14v having the shortest wiring route distance to the connection portion 14v among the plurality of connection portions 15v is the wiring route distance 11v2. Is defined as

  If the wiring path distance of the wiring 12 connecting the capacitor 30 and the semiconductor device 20 shown in FIG. 3 is shortened as in the present embodiment, the wiring 12a and the wiring 12v are connected between the capacitor 30 and the semiconductor device 20. It can suppress that a phase difference arises between them. For example, from the viewpoint of making the phase difference difficult to occur, it is preferable to make the impedances of the respective wiring paths uniform, and therefore it is particularly preferable that the wiring path distance 11a1 and the wiring path distance 11v1 shown in FIG. However, the positions and shapes of the connecting portions 13a and 13v are determined in accordance with the structure of the terminal 22 (see FIGS. 3 and 5) of the semiconductor device 20 (see FIG. 3). For this reason, as shown in FIG. 9, the wiring path distance 11a1 and the wiring path distance 11v1 may not be equal. However, according to this embodiment, since the wiring path distance 11a1 and the wiring path distance 11v1 are short, a large phase difference is unlikely to occur. Therefore, according to the present embodiment, it is possible to suppress a reduction in noise resistance due to a phase difference generated in a wiring path connecting capacitor 30 and semiconductor device 20 shown in FIG.

  Further, according to the study of the present inventor, by fixing the wiring path distances 11a1 and 11v1 shown in FIG. 9 and adjusting the lengths of the wiring path distances 11a2 and 11v2, the semiconductor device 20 side shown in FIG. It has been found that the number of noise countermeasure capacitors 30 can be reduced by bringing the anti-resonance frequency on the external terminal 60 side shown in FIG. 4 closer.

As described above, when there are components with a large noise influence on both the semiconductor device 20 side and the external terminal 60 side, it is necessary to take noise countermeasures for each of the plurality of anti-resonance frequencies. Further, when the values of the plurality of anti-resonance frequencies are close to each other, the impedance value of the circuit is further increased in the vicinity of the anti-resonance frequency due to mutual influences. For this reason, in order to improve the noise resistance of a circuit having a plurality of anti-resonance frequencies, the impedance corresponding to each of the plurality of anti-resonance frequencies is set such that the values of the plurality of anti-resonance frequencies are separated from each other. A method of connecting a bypass capacitor having a reduction characteristic (in other words, a capacitance value) is conceivable.

  However, according to the study by the present inventor, a plurality of anti-resonances can be obtained by bypassing the capacitor 30 and reducing the number of paths for electrically connecting the external terminal 60 and the semiconductor device 20 as in the present embodiment. It has been found that the impedance can be reduced by the capacitor 30 even when the frequency values are close. That is, in the electronic device EDV1 of the present embodiment, an increase in impedance related to the anti-resonance frequency on the semiconductor device 20 side and an increase in impedance related to the anti-resonance frequency on the external terminal 60 side are suppressed by one capacitor 30. . For example, in the case of the present embodiment, the antiresonance frequency on the semiconductor device 20 side shown in FIG. 3 is about 265 MHz (megahertz). At this time, when the lengths of the wiring path distance 11a2 and the wiring path distance 11v2 shown in FIG. 9 are adjusted, the inductances of the wirings 12a and 12v change, so that the anti-resonance frequency value on the external terminal 60 side can be adjusted. .

  Thus, if the number of electronic components (capacitors 30) for noise reduction can be reduced, the mounting area of the electronic components can be reduced, and the planar size of the wiring board 10 can be reduced. Or since the freedom degree of the layout of the some wiring 12 with which the wiring board 10 is provided increases, it becomes easy to adjust the relationship of wiring route distance 11a1, 11a2, 11v1, and wiring route distance 11v2. In other words, it becomes easy to adjust the values of a plurality of anti-resonance frequencies. Further, since the number of electronic components is reduced, the electronic device EDV1 can be easily assembled, so that the manufacturing efficiency is improved. Further, since the number of electronic components is reduced, it is possible to prevent a reduction in circuit reliability due to a failure of some components.

  In the present embodiment, the width of the connecting portion 14 connected to the electrode 31 of the capacitor 30 in the wiring 12 shown in FIG. 3 is narrower than the width of the extending portion of the wiring 12. Specifically, it can be expressed as follows.

  As shown in FIG. 10, the wiring 12a constituting the output line 11A is disposed between the connecting portion 14a and the connecting portion 15a (see FIG. 9), and has an extending portion 17a1 extending along the direction DR1. . Further, the wiring 12v constituting the power supply line 11V is disposed between the connecting portion 14v and the connecting portion 15v (see FIG. 9), and has an extending portion 17v1 extending along the direction DR1. Here, the width 14wa in the direction DR2 orthogonal to the direction DR1 of the connecting portion 14a is narrower than the width 17wa1 in the direction DR2 of the extending portion 17a1. Further, the width 14wv in the direction DR1 of the connecting portion 14v is narrower than the width 17wv1 in the direction DR2 of the extending portion 17v1.

  From the viewpoint of reducing the impedance of the power supply line 11V and the output line 11A, the width of the wiring 12v and the wiring 12a should be somewhat thick. Further, even if the processing accuracy of the wiring pattern is taken into consideration, a pattern that is somewhat thick is easier to pattern. On the other hand, from the viewpoint of reducing the amount of noise that propagates without passing through the capacitor 30 shown in FIG. 3 (in other words, without being filtered by the capacitor 30), a path that bypasses the connection portion between the capacitor 30 and the wiring 12 is provided. It is preferable to reduce as much as possible.

  Therefore, in this embodiment, as shown in FIG. 10, the capacitor 14 (see FIG. 3), the wiring 12, and the width 14 wa of the connection portion 14 a and the width 14 wv of the connection portion 14 v are locally narrowed. The route that bypasses the connection part is reduced. Moreover, the impedance of the output line 11A can be reduced by increasing the width 17wa1 of the extended portion 17a1 having a long wiring path distance in the wiring 12a. Similarly, the impedance of the power supply line 11V can be reduced by increasing the width 17wv1 of the extended portion 17v1 having a long wiring path distance in the wiring 12v.

  In the example shown in FIG. 10, the width of the connection portion 14 is narrower than the width of the extending portion between the connection portion 14 and the connection portion 13. Specifically, as shown in FIG. 10, the wiring 12a constituting the output line 11A is disposed between the connecting portion 14a and the connecting portion 13a and has an extending portion 17a2 extending along the direction DR1. The wiring 12v constituting the power supply line 11V has an extending portion 17v2 that is disposed between the connecting portion 14v and the connecting portion 13v and extends along the direction DR1. Here, the width 14wa in the direction DR2 of the connecting portion 14a is narrower than the width 17wa2 in the direction DR2 of the extending portion 17a2. Further, the width 14wv in the direction DR1 of the connecting portion 14v is narrower than the width 17wv2 in the direction DR2 of the extending portion 17v2.

  As described above, the width 17wa2 of the extending portion 17a2 is made thicker than the width 14wa of the connecting portion 14a, and the width 17wv2 of the extending portion 17v2 is made thicker than the width 14wv of the connecting portion 14v, whereby the semiconductor device shown in FIG. The impedance of the wiring path connecting 20 and the capacitor 30 can be reduced.

  In the present embodiment, the width 14wa of the connecting portion 14a of the wiring 12a is narrower than the width 17wv1 of the extending portion 17v1 of the wiring 12v and the width 17wv2 of the extending portion 17v2. Further, the width 14wv of the connecting portion 14v of the wiring 12v is narrower than the width 17wa1 of the extending portion 17a1 and the width 17wa2 of the extending portion 17a2.

  As shown in FIG. 10, the width 14wa of the connection portion 14a of the wiring 12a is greater than the width 13wa in the direction DR2 of the connection portion 13a connected to the terminal 22a (see FIG. 3) of the semiconductor device 20 (see FIG. 3). Is also narrow. If the width 14wa of the connection portion 14a is sufficiently narrow, even if the width 13wa of the connection portion 13a is increased, a wiring path in which the noise component bypasses the capacitor 30 (see FIG. 3) does not occur. Further, by increasing the width 13wa of the connecting portion 13a, the mounting reliability of the terminal 22a shown in FIG. 3 can be improved.

  Similarly, the width 14wv of the connection portion 14v of the wiring 12v is larger than the width 13wv (see FIG. 9) in the direction DR2 of the connection portion 13v connected to the terminal 22v (see FIG. 5) of the semiconductor device 20 (see FIG. 5). narrow. The connecting portion 13v functions as a path for supplying a power supply potential to the semiconductor device 20 shown in FIG. 5, and also functions as a fixing portion for fixing the semiconductor device. Therefore, by increasing the width 13wv of the connection portion 13v, the area of the connection portion 13v increases, so that the mounting reliability of the semiconductor device 20 is improved.

  Although illustration is omitted, as a modification to the present embodiment, the width 14wa shown in FIG. 10 may be the same as the width 17wa1 or the width 17wa2, or may be wider than the width 17wa1 or the width 17wa2. Further, the width 14wv shown in FIG. 10 may be the same as the width 17wv1 and the width 17wv2, or may be wider than the width 17wv1 and the width 17wv2. For example, depending on the size of the mounting surface of the electrode 31 of the capacitor 30 shown in FIG. 3, even if the widths 14wa and 14wv are made as small as possible, the widths 17wa1, 17wa2, 17wv1, and 17wv2 may be comparable.

  Next, the effect of improving noise resistance will be described using a correlation diagram of frequency and impedance. FIG. 11 is an explanatory diagram showing characteristic curves related to the frequency and impedance of a ceramic capacitor and an aluminum electrolytic capacitor. FIG. 12 is an explanatory diagram for comparing the characteristic curves when an electrolytic capacitor is used as a noise countermeasure capacitor and when a ceramic capacitor is used in the electronic device shown in FIG. FIG. 25 is an explanatory diagram for comparing the characteristic curves between the case where an electrolytic capacitor is used as a noise countermeasure capacitor and the case where a ceramic capacitor is used in the electronic device shown in FIG.

  Each of FIGS. 11, 12, and 25 is a log-log graph in which the horizontal axis represents frequency and the vertical axis represents impedance on a logarithmic scale. In FIG. 11, as an example, a characteristic curve 30C of a 33 μF (microfarad) ceramic capacitor is shown by a solid line, and a characteristic curve 30E of a 33 μF aluminum electrolytic capacitor is shown by a dotted line. Similarly, in FIGS. 12 and 25, a characteristic curve using a ceramic capacitor as a bypass capacitor is indicated by a solid line, and a characteristic curve using an electrolytic capacitor is indicated by a dotted line.

  In the present embodiment, as shown in FIG. 3, a ceramic capacitor is used as a noise reduction bypass capacitor. In the case of a ceramic capacitor, for example, the equivalent series resistance (ESR) and the parasitic inductance (ESL) can be reduced as compared with an electrolytic capacitor having the same capacity. For this reason, especially in the region where the frequency is high, the ceramic capacitor has a higher impedance reduction effect. For example, in the example shown in FIG. 11, in the frequency band of about 10 kHz (kilohertz) or more, the characteristic curve 30C has a smaller impedance than the characteristic curve 30E. That is, it can be seen that in a frequency band higher than 10 kHz, the noise resistance of the ceramic capacitor is easier to reduce than the electrolytic capacitor.

  In the example shown in FIG. 11, a characteristic curve of a 33 μF capacitor is shown as an example. However, if the capacitance values are equal, the relationship between the characteristic curves of the ceramic capacitor and the electrolytic capacitor is not limited even if other capacitance values are used. This is the same as the example shown in FIG. That is, in a frequency band exceeding 10 kHz, the ceramic capacitor is easier to reduce noise resistance than the electrolytic capacitor.

  Further, as shown in FIG. 25, when a noise countermeasure bypass capacitor is connected to the position of the capacitor 30 of the electronic device Eh1 shown in FIG. 23, there is a large difference in the impedance reduction effect between the ceramic capacitor and the electrolytic capacitor. Does not occur. On the other hand, as shown in FIG. 12, when a bypass capacitor for noise suppression is connected to the position of the capacitor 30 of the electronic device EDV1 shown in FIG. 3, the impedance of the ceramic capacitor can be greatly reduced compared to the electrolytic capacitor. . For example, in the example shown in FIG. 12, the impedance value peak 30CP in the characteristic curve 30C is less than half of the impedance value peak 30EP in the characteristic curve 30E. Further, the characteristic curve 30C has a reduced impedance value in the frequency band other than the peak 30CP as compared with the characteristic curve 30EP.

  A comparison between FIG. 25 and FIG. 12 shows that when a capacitor 30 (see FIG. 3) is connected with a structure that easily filters noise as in the present embodiment, it is particularly effective to use a ceramic capacitor.

  Further, the impedance of the peak 30CP shown in FIG. 12 is 1/10 or less (for example, the peak 30CP is about 7% of the peak 30CPh) as compared with the peak 30CPh and the peak 30EPh shown in FIG. Further, the impedance of the peak 30EP shown in FIG. 12 is 1/5 or less (for example, the peak 30EP is about 17% of the peak 30CPh) compared to the peak 30CPh and the peak 30EPh shown in FIG. Thus, according to the present embodiment, the impedance value that peaks around the anti-resonance frequency can be reduced, so that the noise resistance of the electronic device can be improved.

(Modification)
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the electronic device EDV1 described in the above embodiment, as shown in FIG. 8, a capacitor 40 and a diode 50 constituting an oscillation circuit are connected to the output line 11A. However, the capacitor 40 and the diode 50 may not be connected depending on the circuit. FIG. 13 is a plan view showing an electronic device according to a modification to FIG.

  The electronic device EDV2 shown in FIG. 13 is between the connection portion 15 for the external terminal 60 and the connection portion 14 for the capacitor 30, and between the connection portion 14 of the capacitor 30 and the connection portion 13 for the semiconductor device 20. It differs from the electronic device EDV1 shown in FIGS. 3 to 8 in that other electronic components are not connected.

  Specifically, in the wiring 12a constituting the output line 11A included in the electronic device EDV2, other electronic components (electronic components other than the external terminal 60 and the capacitor 30) are not connected between the connection portion 15a and the connection portion 14a. . In addition, in the wiring 12v constituting the power supply line 11V included in the electronic device EDV2, other electronic components (electronic components other than the external terminal 60 and the capacitor 30) are not connected between the connection portion 15v and the connection portion 14v. Thereby, in the wiring path between the external terminal 60 and the capacitor 30 which is a bypass capacitor, it is possible to suppress the occurrence of a phase difference caused by another electronic component between the output line 11A and the power supply line 11V.

  In addition, in the wiring 12a constituting the output line 11A included in the electronic device EDV2, other electronic components (electronic components other than the semiconductor device 20 and the capacitor 30) are not connected between the connecting portion 13a and the connecting portion 14a. Further, in the wiring 12v constituting the power supply line 11V provided in the electronic device EDV2, other electronic components (electronic components other than the semiconductor device 20 and the capacitor 30) are not connected between the connecting portion 13v and the connecting portion 14v. Thereby, in the wiring path between the semiconductor device 20 and the capacitor 30 that is a bypass capacitor, it is possible to suppress the occurrence of a phase difference caused by another electronic component between the output line 11A and the power supply line 11V.

  In the example of the electronic device EDV1 shown in FIG. 3, the embodiment in which the capacitor 30 is mounted so as to straddle the output line 11A and the power supply line 11V has been described. However, there are various modified examples of the two wiring paths on which the bypass capacitor is mounted. FIG. 14 is a plan view showing another modified example of the electronic device shown in FIG. In FIG. 14, the power supply line 11V, the output line 11A, and the reference potential line (wiring path, input line) 11G are shown in a plan view for easy understanding, but each wiring path is hatched. Show.

  The semiconductor device 20A included in the electronic device EDV3 illustrated in FIG. 14 is different from the semiconductor device 20 included in the electronic device EDV1 illustrated in FIG. The semiconductor device 20A includes a plurality of terminals 22v for supplying a power supply potential. The semiconductor device 20A has a so-called SOP (Small Outline Package) structure in which a plurality of terminals 22v protrude from one side surface of the sealing body and another terminal 22 protrudes from the opposite side surface of the sealing body. It has become. 14 is provided with a reference potential line 11G for supplying a reference potential GND (see FIG. 1) to the semiconductor device 20A in addition to the power supply line 11V and the output line 11A. This is different from the electronic device EDV1 shown in FIG. In the electronic device EDV1, a capacitor 30 is connected between the output line 11A and the reference potential line 11G and between the power supply line 11V and the reference potential line 11G. Specifically, a capacitor 30ag is mounted across the wiring 12a and the wiring 12g1, and a capacitor 30vg is mounted across the wiring 12v and the wiring 12g2.

  In the example illustrated in FIG. 14, the reference potential line 11G includes a wiring 12g1 extending along the wiring 12a and a wiring 12g2 extending along the wiring 12v. The wiring 12g1 and the wiring 12g2 are electrically connected to the wiring 12g1 and the wiring 12 in the example illustrated in FIG. However, as a modification, the wiring 12g1 and the wiring 12g2 may be independently connected to the external terminal 60 and the semiconductor device 20, respectively. Each of the wiring 12g1 and the wiring 12g2 includes a connection portion 13g to which the terminal 22g of the semiconductor device 20 is connected, a connection portion 14g to which the electrode 31g of the capacitor 30 is connected, and a connection portion 15g to which the external terminal 60 is connected. Have. In other words, the connection portion 13g, the connection portion 14g, and the connection portion 15g are electrically connected to each other via the wiring 12g1 and the wiring 12g2.

  In the case of the electronic device EDV3, the wiring 12a constituting the output line 11A and the wiring 12g1 constituting the reference potential line 11G are arranged so as to extend along each other. Further, the wiring 12v constituting the power supply line 11V and the wiring 12g2 constituting the reference potential line 11G are arranged so as to extend along each other. A pair wiring path consisting of the output line 11A and the reference potential line 11G and a pair wiring path consisting of the power supply line 11V and the reference potential line 11G are respectively output lines 11A described using the electronic device EDV1 shown in FIG. Noise countermeasures similar to those of the paired wiring path consisting of the power line 11V are taken.

  That is, the wiring 12a includes a connection portion 14a to which the capacitor 30ag is connected between the connection portion 15a and the connection portion 13a. Further, the wiring 12g1 includes a connection portion 14g to which the capacitor 30ag is connected between the connection portion 15g and the connection portion 13g. Further, in the wiring 12a, the wiring path distance between the connecting part 13a and the connecting part 14a is shorter than the wiring path distance between the connecting part 14a and the connecting part 15a and the wiring path distance between the connecting part 14g and the connecting part 15g. Further, in the wiring 12g1, the wiring path distance between the connecting part 13g and the connecting part 14g is shorter than the wiring path distance between the connecting part 14a and the connecting part 15a and the wiring path distance between the connecting part 14g and the connecting part 15g.

  Therefore, in the paired wiring path composed of the output line 11A and the reference potential line 11G, noise resistance is improved as in the paired wiring path composed of the output line 11A and the power supply line 11V described in the electronic device EDV1 shown in FIG. Can be made.

  Further, as shown in FIG. 14, the wiring 12v includes a connection portion 14v to which a capacitor 30vg is connected between the connection portion 15v and the connection portion 13v. Further, the wiring 12g2 includes a connection portion 14g to which the capacitor 30vg is connected between the connection portion 15g and the connection portion 13g. Further, in the wiring 12v, the wiring path distance between the connecting part 13v and the connecting part 14v is shorter than the wiring path distance between the connecting part 14v and the connecting part 15v and the wiring path distance between the connecting part 14g and the connecting part 15g. Further, in the wiring 12g2, the wiring path distance between the connecting part 13g and the connecting part 14g is shorter than the wiring path distance between the connecting part 14v and the connecting part 15v and the wiring path distance between the connecting part 14g and the connecting part 15g.

  Therefore, in the paired wiring path composed of the power supply line 11V and the reference potential line 11G, the noise resistance is improved as in the paired wiring path composed of the output line 11A and the power supply line 11V described in the electronic device EDV1 shown in FIG. Can be made.

  As shown in FIG. 14, the semiconductor device 20 may have a plurality of terminals 22v for power supply potential. In the example illustrated in FIG. 14, the wiring 12 v has a plurality of connection portions 13 v at the tip portion that is connected to the semiconductor device 20. Further, in the example illustrated in FIG. 14, the wiring 12v includes a branch portion 12jc between a plurality of connection portions 13v and one connection portion 14v. When the wiring 12 is branched in the middle like the wiring 12v, it is preferable that the wiring path distance from the connecting portion 14v to the plurality of connecting portions 13v be as close as possible. Therefore, as shown in FIG. 14, when a plurality of connection portions 13v are arranged along the direction DR1, the branching portion may be arranged between the plurality of connection portions 13v in the direction DR1. preferable.

  However, in the electronic device EDV3, the wiring path distance between the connecting portion 14 to which the capacitor 30 is connected and the connecting portion 13 to which the semiconductor device 20 is connected is shortened as in the electronic device EDV1 shown in FIG. . For this reason, between the connection part 13 and the connection part 14, even if a difference of a wiring path | route arises between the wiring path | routes used as a pair, it has a structure which does not produce a phase difference easily.

  Further, in the electronic devices EDV1, EDV2, and electronic device EDV3 described above, each of a plurality of wirings that connect the external terminal 60 and the semiconductor device 20 is formed on one main surface 10t of the wiring substrate 10, and the main component on the opposite side is formed. The embodiment not formed on the surface 10b (see FIG. 4) has been described. However, like the electronic device EDV4 shown in FIG. 15, a part of the wiring 12 may be formed on a surface other than the main surface 10t. FIG. 15 is a plan view showing a modification of the electronic device shown in FIG. FIG. 16 is an enlarged cross-sectional view along the wiring shown as wiring 12g3 among the wirings for reference potential shown in FIG. In FIG. 15, the wiring 12g3 and the wiring 12g4 formed on the surface other than the main surface 10t of the wiring substrate 10 are schematically shown by two-dot chain lines for easy viewing. However, the widths of the wiring 12g3 and the wiring 12g4 are the same as the width of the wiring 12g shown in FIG.

  The electronic device EDV4 is different from the electronic device EDV3 shown in FIG. 14 in that a part of the plurality of wirings 12 is formed on the main surface 10b (see FIG. 16) of the wiring board 10. Specifically, the circuit of the electronic device EDV4 is the same as that of the electronic device EDV4 shown in FIG. However, the electronic device EDV4 is different from the electronic device EDV3 shown in FIG. 14 in the layout of the semiconductor device 20A. Accordingly, the layout of the plurality of wirings 12 is also different from that of the electronic device EDV3.

  In the example shown in FIG. 15, a part of the plurality of connection portions 13v is provided on the extended line of the wiring 12g extending along the wiring 12v supplying the power supply potential. For this reason, it is necessary to bypass the wiring 12g so that the wiring 12g and the connecting portion 13v do not contact each other. Here, as shown in FIG. 15, in the case of the wiring 12g3 arranged so as to bypass the semiconductor device 20A in a plan view, the wiring path from the connection portion 14g to the capacitor 30vg to the connection portion 13g to the semiconductor device 20A The distance becomes longer than the wiring path distance from the connecting portion 14v to the connecting portion 13v. Therefore, in the electronic device EDV4, a part of the reference potential line 11G is formed on a surface other than the main surface 10t (main surface 10b shown in FIG. 16) to reduce the difference in wiring path distance. That is, the connection portion 14g with the capacitor 30vg to the connection portion 13g with the semiconductor device 20 is electrically connected via the wiring 12g4. Thereby, in the pair of wiring paths composed of the power supply line 11V and the reference potential line 11G, the wiring path distance between the capacitor 30vg and the semiconductor device 20A can be shortened, so that the phase difference between the wiring paths can be reduced.

  In the example shown in FIG. 15, a part of the plurality of connection portions 13v is provided on an extension of the wiring 12a that transmits the output potential. For this reason, it is necessary to bypass the wiring 12a so that the wiring 12a and the connection part 13v do not contact. Here, as described above, in the output line 11A, if the wiring path distance between the connection part 13a and the connection part 14a is sufficiently short, the wiring path distance between the connection part 14a and the connection part 15a may be long. However, in this case, in order to reduce a phase difference generated between the wiring paths constituting the pair, it is preferable to arrange the wirings 12 constituting the pair so as to extend along each other.

  Therefore, as shown in FIG. 15, the wiring 12a of the electronic device EDV1 is formed to bypass the periphery of the semiconductor device 20A in plan view. Further, a part of the reference potential line 11G (wiring 12g3) forming a pair with the output line 11A overlaps with the wiring 12a in the thickness direction as shown in FIGS. In other words, the wiring 12a and the wiring 12g3 run in parallel via the base material 10B of the wiring board 10 as shown in FIG. For this reason, the wiring path distance between the connecting portion 14a and the connecting portion 15a is increased, but the phase difference generated between the output line 11A and the reference potential line 11G constituting the pair is reduced.

  As shown in FIG. 16, the wiring 12g formed on the main surface 10b and the wiring 12g3 formed on the main surface 10t are through-holes penetrating from one side to the other of the main surface 10t and the main surface 10b. Are electrically connected through a through-hole wiring 12TH, which is a conductor pattern embedded in the wiring. The wiring 12g4 shown in FIG. 15 is not shown in a sectional view, but is electrically connected to the wiring 12g on the main surface 10t side through the through-hole wiring 12TH similarly to the wiring 12g3 shown in FIG.

  Although not shown, as a further modification to the electronic device EDV4, a part of the output line 11A is formed on a surface other than the main surface 10t (for example, the main surface 10b shown in FIG. 16), and the wiring 12g4 shown in FIG. A wiring for the output line 11A may be provided along the line. However, since the structure of the through-hole wiring 12TH is different from that of the other wiring 12, the through-hole wiring 12TH easily becomes an impedance discontinuity point where the impedance changes in the middle of the wiring path. Therefore, it is particularly preferable that the output line 11A and the power supply line 11V are routed only on the main surface 10t side on which the semiconductor device 20A and the capacitor 30 are mounted. In other words, it is preferable that the main surface 10b shown in FIG. 16 does not have the wiring 12a constituting the output line 11A and the wiring 12v constituting the power supply line 11V.

  Further, as in the electronic device EDV5 shown in FIG. 17, a plurality of noise countermeasure capacitors 30 may be arranged adjacent to each other. FIG. 17 is a plan view showing another modification of FIG. The electronic device EDV5 is mounted across a capacitor 30ag mounted across a pair of wiring paths composed of an output line 11A and a reference potential line 11G, and a pair of wiring paths composed of a power supply line 11V and a reference potential line 11G. The capacitors 30vg are arranged adjacent to each other.

  In this case, as shown in FIG. 17, in the wiring 12g, the connection part 14g connected to the capacitor 30ag and the connection part 14g connected to the capacitor 30vg are shared. In other words, the capacitor 30ag is mounted on a part of the connection part 14g included in the wiring 12g, and the capacitor 30vg is mounted on the other part of the connection part 14g. In this case, depending on the planar size of the capacitors 30ag and 30vg, it is necessary to increase the area of the connection portion 14g. For this reason, in the example shown in FIG. 17, the width of the connecting portion 14g connected to the electrode of the capacitor 30 (the length of the connecting portion 14g in the direction DR2 shown in FIG. 17) is the width of the extending portion of the wiring 12g (direction). This is wider than the length of the extended portion of the wiring 12g in DR2. As described above, when a plurality of capacitors 30 are arranged adjacent to each other, even if the width of the connecting portion 14g is wider than the width of the extending portion, it is difficult to cause noise to propagate without passing through the capacitor 30. . For this reason, in the electronic device EDV5, the mounting reliability of the plurality of capacitors 30 can be improved by making the width of the connecting portion 14g wider than the width of the extending portion.

  In the electronic device EDV5, the widths of the extending portions of the plurality of wirings 12 are the same, but the widths of the extending portions of some of the plurality of wirings 12 (for example, the wiring 12g) are set to other widths. The width of the extended portion of the wiring 12 may be wider. In this case, even if it arrange | positions so that the several capacitor | condenser 30 may adjoin, you may make the embodiment into which the width | variety of the connection part 14g becomes narrower than the width | variety of the extension part of the wiring 12g.

  However, when the width of the extending portion of the wiring 12 is wider than the width of the extending portion of the other wiring 12, the impedance of the wide wiring 12 is smaller than the impedance of the other wiring 12. If the impedance difference between the wiring paths forming a pair becomes large, a phase difference is caused. Therefore, when the width of the extended portion of a part of the plurality of wirings 12 is wide, a measure for increasing the impedance of the relatively wide wiring 12 (for example, increasing the wiring path distance). It is preferable to take measures such as increasing the wiring inductance to bring the impedance value closer.

  In addition, the semiconductor device 20B included in the electronic device EDV5 illustrated in FIG. 17 includes a plurality of output terminals 22a arranged adjacent to each other. Thus, when the plurality of terminals 22 are arranged adjacent to each other, the area of the connection portion 13 of the wiring 12a is increased so that the plurality of terminals 22a are connected to one connection portion 13a. good. In the example shown in FIG. 17, since the wiring path distance from the connection part 13g of the wiring 12g to the connection part 14g is short, the difference with the wiring path distance from the connection part 13a to the connection part 14a becomes large. As described above, if the wiring path distance from the connection part 13a to the connection part 14a is sufficiently short, the phase difference between the wiring paths forming a pair is unlikely to increase. However, as in the electronic device EDV5, the area of the connection part 13g constituting the output line 11A having a relatively long wiring path distance is smaller than that of the connection part 13g of the reference potential line 11G having a relatively short wiring path distance. By configuring so as to increase, the impedance of the output line 11A can be reduced. As a result, the phase difference generated between the output line 11A and the reference potential line 11G can be reduced. Similarly, in the case of the electronic device EDV5, the area of the connection portion 13v constituting the power supply line 11V is larger than the area of the connection portion 13g. Therefore, the phase difference generated between the power supply line 11V and the reference potential line 11G can be reduced.

  Further, like the semiconductor device 20C included in the electronic device EDV6 shown in FIG. 18 and the electronic device EDV7 shown in FIG. 19, the semiconductor device 20C has a plurality of terminals 22a for output potential, and the same potential is output from each of the plurality of terminals 22a. In this case, the output line 11A may be branched. 18 and 19 are plan views showing an electronic device which is another modified example with respect to FIG.

  In the example illustrated in FIGS. 18 and 19, the output line 11 </ b> A is branched between the connection portion 14 a and the plurality of connection portions 13 a. In the electronic device EDV6 shown in FIG. 18, the wiring 12g also serves as a wiring path that forms a pair with the power supply line 11V and a wiring path that forms a pair with the output line 11A. For this reason, since the exclusive area of the wiring 12 is small compared with the electronic device EDV7 shown in FIG. 19, the electronic device EDV6 can be reduced in size.

  On the other hand, the electronic device EDV6 shown in FIG. 19 includes a wiring 12g1 that forms a pair with the output line 11A and a wiring 12g2 that forms a pair with the power supply line 11V. Thus, by forming the wiring 12g1 and the wiring 12g2, respectively, the degree of freedom of the wiring layout is improved. Further, the wiring 12g1 and the wiring 12g2 are electrically connected to each other at a position overlapping the semiconductor device 20C. Therefore, in the output wiring 12a, a reference potential wiring 12g is provided along a portion between the connection portion 14a and the connection portion 13a. Therefore, the electronic device EDV7 can reduce the phase difference between the wiring paths between the connecting portion 13a and the connecting portion 14a, as compared with the electronic device EDV6.

  Further, as shown in FIG. 19, the wiring 12g1 and the wiring 12g2 of the electronic device EDV7 are connected to each other through a wiring 12g5 formed on a surface other than the main surface 10t (for example, a main surface opposite to the main surface 10t). ing. As described above, if the wiring 12g1 and the wiring 12g2 are electrically connected, the external terminal 60 for the reference potential can be shared.

  Further, when different potentials are output from each of the plurality of terminals 22a as in the semiconductor device 20D included in the electronic device EDV8 illustrated in FIG. 20, the output line 11A1 and the output line 11A2 that are electrically separated from each other. You may have. FIG. 20 is a plan view showing a modification to FIG.

  The semiconductor device 20D included in the electronic device EDV8 outputs different potentials from the plurality of terminals 22a. In this case, it is necessary to provide the output line 11A1 and the output line 11A2 that are electrically separated from each other. Further, when the paired wirings 12 are formed on each of the output line 11A1 and the output line 11A2, the wiring density is increased, and the layout restrictions are increased. Therefore, the reference potential line 11G is disposed between the output line 11A1 and the output line 11A2 included in the electronic device EDV8. Also, each of the wiring 12a1 of the output line 11A1 and the wiring 12a2 of the output line 11A2 extends along the wiring 12g1 of the reference potential line 11G.

  In addition, the electronic device EDV8 is mounted across a pair of wiring paths composed of the output line 11A1 and the reference potential line 11G and the pair of wiring paths composed of the power supply line 11V and the reference potential line 11G. The capacitors 30ag2 are arranged so as to be adjacent to each other.

  In the case of an electronic device including a plurality of output lines 11A1 and 11A2 such as the electronic device EDV8, the increase in the wiring density is suppressed by sharing the wiring 12g1 that forms a pair with each of the plurality of output lines 11A1 and 11A2. it can. In the example shown in FIG. 20, the wiring 12g2 and the wiring 12g1 are electrically connected through the wiring 12g5. For this reason, the electronic device EDV1 can suppress an increase in the number of external terminals 60.

  In the above-described embodiment and each modification, the embodiment in which the capacitor 30 is mounted across the Japanese wiring 12 extending along each other has been described. However, as a modification, a lead wire (not shown) may be connected to the two wires, and the connection portion 14 may be provided in a part of the lead wire. In this case, the distance between the two wires can be set regardless of the outer size of the capacitor 30. However, as described in the above embodiment, from the viewpoint of reducing noise transmitted without passing through the capacitor 30, the connection portion 14 is preferably provided in the middle of the extending direction of the wiring 12. In other words, the capacitor 30 is preferably mounted across the two wires.

  In the above-described embodiment, as an example that the wiring path distance of the wiring path connecting the capacitor 30 and the semiconductor device 20 is shorter than the wiring path distance connecting the capacitor 30 and the external terminal 60. For example, as described with reference to FIG. 9, the lengths of the wirings 12 included in the wiring board 10 were compared. Specifically, the wiring path distance 11a1 between the connection part 13a and the connection part 14a of the wiring 12a shown in FIG. 9, the wiring path distance 11a2 between the connection part 15a and the connection part 14a, and the connection part 13v of the wiring 12v are connected. The wiring path distance 11v1 between the part 14v and the wiring path distance 11v2 between the connection part 15v and the connection part 14v were compared.

  However, the wiring path distance described above can be considered including the wiring path inside the semiconductor device 20 and the wiring path inside the external terminal 60 as shown in FIG. FIG. 21 is an explanatory diagram schematically showing the definition of the wiring route described with reference to FIG. 9 and the definition of a wiring route different from this. FIG. 22 is an enlarged cross-sectional view schematically showing an example of the wiring path inside the external terminal shown in the external terminal shown in FIG. 21 corresponds to the circuit diagram shown in FIG. 8, but the capacitor 40, the diode 50, and the paths connected to these shown in FIG. 8 are omitted for the sake of clarity. . Also, in FIG. 22, the external connection portion 62 to which external wiring (the electric wire shown in FIG. 1 and the contact conductor portion of the socket attached to the tip of the electric wire) of the external terminal 60 is connected and other portions are shown. A boundary line to be distinguished is indicated by a two-dot chain line.

  In the example shown in FIG. 21, the wiring path distance 11a3 and the wiring path distance 11v3 of the wiring path that electrically connects the capacitor 30 and the electrode 27 of the semiconductor chip 21 of the semiconductor device 20 are the same as those of the capacitor 30 and the external terminal 60, respectively. It is shorter than each of the wiring path distance 11a4 and the wiring path distance 11v4 that electrically connect the external connection portion 62.

  The wiring path distance 11a3 illustrated in FIG. 21 includes the wiring path distance 11a5 inside the semiconductor device 20 in addition to the wiring path distance 11a1 described with reference to FIG. The wiring path distance 11a5 includes a terminal (lead terminal) 22a shown in FIG. 3 and a conductive member (not shown) that connects the terminal 22a and the electrode 27a of the semiconductor chip 21 (see FIG. 21).

  Similarly, the wiring path distance 11v3 illustrated in FIG. 21 includes the wiring path distance 11v5 inside the semiconductor device 20 in addition to the wiring path distance 11v1 described with reference to FIG. In the example shown in FIG. 5, since the electrode 27v shown in FIG. 21 is formed on the back surface of the semiconductor chip 21, the wiring path distance 11v5 has a conductive material such as the solder material 26, the die pad 24, and the die bond material 25 shown in FIG. Sex members are included.

  21 includes the wiring route distance 11a6 inside the external terminal 60 in addition to the wiring route distance 11a2 described with reference to FIG. Similarly, the wiring path distance 11v4 shown in FIG. 21 includes the wiring path distance 11v6 inside the external terminal 60 in addition to the wiring path distance 11v2 described with reference to FIG. Further, as shown in FIG. 22, the wiring path distance 11a6 is defined by the distance from the connection portion with the connection portion 15a of the electrode 61a to the portion reaching the external connection portion 62. Further, the wiring path distance 11v6 is defined by the distance from the connection portion with the connection portion 15v of the electrode 61a to the portion reaching the external connection portion 62.

  When the through hole 63 is provided in a part of the external terminal 60 as in the example shown in FIG. 22, a part of the external wiring (attached to the wire shown in FIG. The contact conductor of the socket. For example, when a contact conductor (not shown) of a socket (not shown) attached to the tip of the electric wire shown in FIG. 1 is brought into contact with the external terminal 60, the socket is attached so as to cover the periphery of the through hole 63, and the through hole 63. A projection (not shown) is inserted into the socket and the socket and the external terminal 60 are fixed. At this time, a contact conductor portion (for example, a metal plate or a metal film) connected to the electric wire is formed inside the socket. In the external connection portion 62 around the through hole 63, the contact conductor portion and the external terminal 60 are formed. And contact. For example, when the electric wire is directly wound around the external terminal 60, a part of the electric wire is inserted into the through hole 63 and the electric wire is wound around the external connection portion 62 around the through hole 63. Therefore, in the external terminal 60 shown in FIG. 22, the portion from the external connection portion 62 to the connection portion 15 is a part of the wiring path that electrically connects the external electric wire of the electronic device EDV1 and the semiconductor device 20. Can be considered.

  In addition, modifications can be applied in combination within a range that does not depart from the gist of the technical idea described in the above embodiment.

  In addition, a part of the contents described in the above embodiment will be described below.

10, 10h Wiring board 10b Main surface (surface, back surface, bottom surface, external terminal mounting surface)
10B Base material 10SR Insulating film 10t Main surface (surface, surface, upper surface, semiconductor device mounting surface)
11A, 11A1, 11A2 Output line (wiring route)
11a1, 11a2, 11a3, 11a4, 11a5, 11a6, 11v1, 11v2, 11v3, 11v4, 11v5, 11v6 Wiring path distance 11E Wiring path 11G Reference potential line (wiring path, input line)
11V power line (wiring route)
12, wiring 12a wiring 12A wiring 12a, 12a1, 12e, 12g, 12g1, 12g2, 12g3, 12g4, 12g5, 12v wiring 12ha, 12hv, 12he conductor pattern 12hv conductor pattern 12jc branch part 12TH through-hole wiring 13, 13a, 13e, 13g, 13v connection part (device connection part)
13wa, 13wv, 14wa, 14wa, 14wv, 17wa1, 17wa2, 17wv1, 17wv2 Width 14, 14a, 14g, 14v Connection (capacitor connection)
15, 15a, 15g, 15v connection part (external terminal connection part)
16 connection part (electronic parts connection part)
17a1, 17a2, 17v1, 17v2 Extension part 20, 20A, 20B, 20C, 20D Semiconductor device 21 Semiconductor chip 22, 22a, 22e22g, 22v terminal (device terminal, lead terminal)
23 Sealing body (resin body)
24 Die Pad 25 Die Bond Material 26 Solder Material 27a, 27v Electrode 30, 30ag, 30ag1, 30ag2, 30vg Capacitor (Chip Capacitor)
30C, 30E Characteristic curve 30CP, 30CPh, 30EP, 30EPh Peak 31, 31a, 31g, 31v Electrode 32 Body 33 Insulating layer (dielectric layer)
34 Conductor plate 40 Capacitor 41 Electrode 50 Diode 60 External terminal (connector)
61a, 61v electrode (pin)
62 External connection part COM1 Parts DR1, DR2 Direction EDV1, EDV2, EDV3, EDV4, EDV5, EDV6, EDV7, EDV8, Eh1, Eh2 Electronic device GND Reference potential HAR1, HAR2, HAR3, HAR4, HAR5 Electric wire IJP1 Coil (injection probe)
LAM1 Lamp LISN1 Pseudo power supply network OUT Output potential (or output signal)
PWS1, PWS2 Power supply Vcc Power supply potential

Claims (10)

A first main surface; a first wiring formed on the first main surface; a second wiring formed on the first main surface; and a second main surface opposite to the first main surface. A wiring board;
A semiconductor device including a semiconductor chip, a first terminal electrically connected to the semiconductor chip, and a second terminal electrically connected to the semiconductor chip, the semiconductor device being mounted on the first main surface of the wiring board When,
A first capacitor comprising a first electrode and a second electrode, and mounted on the first main surface of the wiring board;
Have
The first wiring is
A first device connecting portion to which the first terminal of the semiconductor device is electrically connected;
A first capacitor connecting portion to which the first electrode of the first capacitor is electrically connected;
A first external terminal connection located farther from the first device connection than the first capacitor connection;
A first extension part connecting the first device connection part and the first capacitor connection part to each other;
A second extending part for connecting the first capacitor connecting part and the first external terminal connecting part to each other;
With
The second wiring is
A second device connection part in which the second terminal of the semiconductor device is electrically connected;
A second capacitor connecting portion to which the second electrode of the first capacitor is electrically connected;
A second external terminal connection located farther from the second device connection than the second capacitor connection;
A third extending part for connecting the second device connection part and the second capacitor connection part to each other;
A fourth extending part for connecting the second capacitor connecting part and the second external terminal connecting part to each other;
With
The first capacitor connection part is located on a path from one of the first device connection part and the first external terminal connection part to the other,
The second capacitor connecting portion is located on a path from one of the second device connecting portion and the second external terminal connecting portion to the other;
The length of the first extending portion serving as a first wiring path between the first device connection portion and the first capacitor connection portion is determined between the first capacitor connection portion and the first external terminal connection portion. Shorter than the length of the second extending portion which becomes the second wiring path between,
The length of the third extending portion serving as a third wiring path between the second device connection portion and the second capacitor connection portion is determined between the second capacitor connection portion and the second external terminal connection portion. Shorter than the length of the fourth extending portion which becomes the fourth wiring path between,
The length of the first extension portion and the length of the third extension portion are different from each other,
The first wiring and the second wiring are arranged to extend along each other,
The width of the first capacitor connecting portion is narrower than the width of each of the first extending portion and the second extending portion,
The width of the second capacitor connecting portion is narrower than the width of each of the third extending portion and the fourth extending portion,
The width of the first extension part, the width of the second extension part, the width of the third extension part, and the width of the fourth extension part are substantially the same as each other. The width of the first capacitor connection portion is narrower than the width of each of the first device connection portion, the first extension portion, the second extension portion, and the first external terminal connection portion.
The width of the second capacitor connection portion is narrower than the width of each of the second device connection portion, the third extension portion, the fourth extension portion, and the second external terminal connection portion. The electronic device described.   The electronic device according to claim 2, wherein an oscillation circuit including two bipolar transistors or a MOSFET is formed on the semiconductor chip. A second capacitor having a third electrode and a fourth electrode is mounted on the wiring board,
The wiring board further includes a third wiring formed on the first main surface,
The first wiring further includes a third capacitor connecting portion to which the third electrode of the second capacitor is electrically connected,
The third wiring is
A third device connecting portion to which a third terminal of the semiconductor device is electrically connected;
A fourth capacitor connecting portion to which the fourth electrode of the second capacitor is electrically connected;
With
The third capacitor connection part is located on the path from one of the first device connection part and the first external terminal connection part to the other, and the first capacitor connection part and the first external connection part The electronic device according to claim 3, wherein the electronic device is located between the terminal connection portion. The second capacitor is mounted on the second main surface of the wiring board;
The first capacitor is a ceramic capacitor;
The electronic device according to claim 4, wherein the second capacitor is an electrolytic capacitor. The second capacitor is mounted on the second main surface of the wiring board;
The electronic device according to claim 4, wherein a volume and a mounting area of the first capacitor are smaller than a volume and a mounting area of the second capacitor. The second capacitor is mounted on the second main surface of the wiring board;
The electronic device according to claim 4, wherein a capacity of the first capacitor is smaller than a capacity of the second capacitor. The capacity of the first capacitor is 0.1 μF to 10 μF,
The electronic device according to claim 7, wherein a capacity of the second capacitor is 22 μF to 100 μF. A diode having a fifth electrode and a sixth electrode is mounted on the second main surface of the wiring board,
The first wiring includes a first diode connection portion to which the fifth electrode of the diode is electrically connected,
The electronic device according to claim 3, wherein the second wiring includes a second diode connection portion to which the sixth electrode of the diode is electrically connected. On the second main surface of the wiring board,
A first connector including a seventh electrode electrically connected to the first external terminal connection portion of the first wiring;
A second connector including an eighth electrode electrically connected to the second external terminal connection portion of the second wiring;
The electronic device according to claim 3, wherein each is mounted.

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