JP2019186281A5 - - Google Patents
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- JP2019186281A5 JP2019186281A5 JP2018071779A JP2018071779A JP2019186281A5 JP 2019186281 A5 JP2019186281 A5 JP 2019186281A5 JP 2018071779 A JP2018071779 A JP 2018071779A JP 2018071779 A JP2018071779 A JP 2018071779A JP 2019186281 A5 JP2019186281 A5 JP 2019186281A5
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- JP
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- high frequency
- connection portion
- connection
- underfill
- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 8
- 230000002093 peripheral Effects 0.000 claims 1
Description
上記目的を達成するため、請求項１に記載の半導体装置は、一面（１ａ）を有し、複数の接続部（１５）を一面側に備える半導体チップ（１）と、接続部を介して半導体チップが搭載される基板（３）と、半導体チップと基板との隙間に配置されるアンダーフィル（２）と、を備える。このような構成において、接続部の一部は、高周波を伝送する高周波用接続部（１５１）であり、一面に対する法線方向から見て、高周波用接続部と他の接続部との間には壁部（１６）が配置され、壁部は、該法線方向から見て、該高周波用接続部と他の接続部とを区画しており、高周波用接続部は、アンダーフィルから露出しており、複数の接続部のうち高周波用接続部と異なる接続部は、アンダーフィルにより覆われており、高周波用接続部は、法線方向から見て半導体チップのうち最も外周側に配置されている。 In order to achieve the above object, the semiconductor device according to claim 1 has a semiconductor chip (1) having one surface (1a) and having a plurality of connection portions (15) on one surface side, and a semiconductor via the connection portion. A substrate (3) on which the chip is mounted and an underfill (2) arranged in a gap between the semiconductor chip and the substrate are provided. In such a configuration, a part of the connection part is a high frequency connection part (151) for transmitting a high frequency, and when viewed from the normal direction with respect to one surface, the high frequency connection part and the other connection part are separated from each other. A wall portion (16) is arranged, and the wall portion separates the high frequency connection portion from another connection portion when viewed from the normal direction, and the high frequency connection portion is exposed from the underfill. Of the plurality of connection portions, the connection portion different from the high frequency connection portion is covered with an underfill, and the high frequency connection portion is arranged on the outermost side of the semiconductor chip when viewed from the normal direction. ..
Claims (7)
前記接続部を介して前記半導体チップが搭載される基板（３）と、
前記半導体チップと前記基板との隙間に配置されるアンダーフィル（２）と、を備え、
前記接続部の一部は、高周波を伝送する高周波用接続部（１５１）であり、
前記一面に対する法線方向から見て、前記高周波用接続部と他の前記接続部との間には壁部（１６）が配置され、
前記壁部は、前記法線方向から見て、該高周波用接続部と他の前記接続部とを区画しており、
前記高周波用接続部は、前記アンダーフィルから露出しており、
複数の前記接続部のうち前記高周波用接続部と異なる前記接続部は、前記アンダーフィルにより覆われており、
前記高周波用接続部は、前記法線方向から見て前記半導体チップのうち最も外周側に配置されている半導体装置。 A semiconductor chip (1) having one surface (1a) and having a plurality of connecting portions (15) on the one surface side.
A substrate (3) on which the semiconductor chip is mounted via the connection portion,
An underfill (2) arranged in a gap between the semiconductor chip and the substrate is provided.
A part of the connection part is a high frequency connection part (151) for transmitting high frequency.
A wall portion (16) is arranged between the high frequency connection portion and the other connection portion when viewed from the normal direction with respect to the one surface.
The wall portion divides the high frequency connection portion and the other connection portion when viewed from the normal direction.
The high frequency connection portion is exposed from the underfill.
Of the plurality of connection portions, the connection portion different from the high frequency connection portion is covered with the underfill .
The high-frequency connection portion is a semiconductor device arranged on the outermost peripheral side of the semiconductor chip when viewed from the normal direction .
前記高周波用配線は、前記アンダーフィルから露出している請求項１に記載の半導体装置。 The substrate further comprises a high frequency wiring (33) electrically connected to the high frequency connection.
The semiconductor device according to claim 1, wherein the high-frequency wiring is exposed from the underfill.
前記接続部を介して前記半導体チップが搭載される基板（３）と、A substrate (3) on which the semiconductor chip is mounted via the connection portion,
前記半導体チップと前記基板との隙間に配置されるアンダーフィル（２）と、を備え、An underfill (2) arranged in a gap between the semiconductor chip and the substrate is provided.
前記接続部の一部は、高周波を伝送する高周波用接続部（１５１）であり、A part of the connection part is a high frequency connection part (151) for transmitting high frequency.
前記一面に対する法線方向から見て、前記高周波用接続部と他の前記接続部との間には壁部（１６）が配置され、A wall portion (16) is arranged between the high frequency connection portion and the other connection portion when viewed from the normal direction with respect to the one surface.
前記壁部は、前記法線方向から見て、該高周波用接続部と他の前記接続部とを区画しており、The wall portion divides the high frequency connection portion and the other connection portion when viewed from the normal direction.
前記高周波用接続部は、前記アンダーフィルから露出しており、The high frequency connection portion is exposed from the underfill.
複数の前記接続部のうち前記高周波用接続部と異なる前記接続部は、前記アンダーフィルにより覆われており、Of the plurality of connection portions, the connection portion different from the high frequency connection portion is covered with the underfill.
前記基板は、前記高周波用接続部と電気的に接続された高周波用配線（３３）をさらに有し、The substrate further comprises a high frequency wiring (33) electrically connected to the high frequency connection.
前記高周波用配線は、前記アンダーフィルから露出している半導体装置。The high frequency wiring is a semiconductor device exposed from the underfill.
前記素子部は、前記法線方向から見て、前記壁部を第１壁部（１６１）として、第２壁部（１６２）に囲まれていると共に、前記アンダーフィルから露出しており、
前記第２壁部は、前記半導体チップの前記一面側に形成されている請求項１ないし４のいずれか１つに記載の半導体装置。 An element portion (17) is further formed on the one surface side of the semiconductor chip.
When viewed from the normal direction, the element portion is surrounded by the second wall portion (162) with the wall portion as the first wall portion (161), and is exposed from the underfill.
The semiconductor device according to any one of claims 1 to 4 , wherein the second wall portion is formed on one surface side of the semiconductor chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018071779A JP7010116B2 (en) | 2018-04-03 | 2018-04-03 | Semiconductor device |
| PCT/JP2019/011947 WO2019193986A1 (en) | 2018-04-03 | 2019-03-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2018071779A JP7010116B2 (en) | 2018-04-03 | 2018-04-03 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019186281A JP2019186281A (en) | 2019-10-24 |
| JP2019186281A5 true JP2019186281A5 (en) | 2020-12-24 |
| JP7010116B2 JP7010116B2 (en) | 2022-01-26 |
Family
ID=68100712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018071779A Active JP7010116B2 (en) | 2018-04-03 | 2018-04-03 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP7010116B2 (en) |
| WO (1) | WO2019193986A1 (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3207222B2 (en) * | 1991-08-29 | 2001-09-10 | 株式会社東芝 | Electronic component equipment |
| JPH06204293A (en) * | 1992-12-28 | 1994-07-22 | Rohm Co Ltd | Semiconductor device |
| JP2000269384A (en) * | 1999-03-12 | 2000-09-29 | Nec Corp | Micro-wave and milli-wave circuit device and manufacture therefor |
| US7298235B2 (en) * | 2004-01-13 | 2007-11-20 | Raytheon Company | Circuit board assembly and method of attaching a chip to a circuit board with a fillet bond not covering RF traces |
| JP2006344672A (en) * | 2005-06-07 | 2006-12-21 | Fujitsu Ltd | Semiconductor chip and semiconductor device using the same |
| JP2006287962A (en) * | 2006-05-19 | 2006-10-19 | Mitsubishi Electric Corp | High frequency transmitting/receiving module |
| JP6183811B2 (en) * | 2014-06-30 | 2017-08-23 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Junction structure and wireless communication device |
| JP6204293B2 (en) | 2014-07-30 | 2017-09-27 | 富士通フロンテック株式会社 | Voting service device, data processing method, program, recording medium, and voting service system |
| JP6566846B2 (en) * | 2015-11-20 | 2019-08-28 | 新日本無線株式会社 | Hollow package and manufacturing method thereof |
-
2018
- 2018-04-03 JP JP2018071779A patent/JP7010116B2/en active Active
-
2019
- 2019-03-21 WO PCT/JP2019/011947 patent/WO2019193986A1/en active Application Filing
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