JP2019186281A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which an underfill 2 is selectively arranged and which achieves both relaxation of stress concentration on a connection portion 15 due to the underfill 2 and reduction of high-frequency signal loss at a high-frequency connection portion 151.SOLUTION: Between a high frequency connection portion 151 and the other connection portion 152 of a semiconductor chip 1, a wall portion 16 that partitions the connection portions is disposed, and a liquid underfill material is blocked by the wall portion 16 not to reach the high frequency connection portion 151. As a result, a predetermined region including the high frequency connection portion 151 between the semiconductor chip 1 and a substrate 3 is exposed from an underfill 2, and the other region is covered with the underfill 2 to achieve both relaxation of stress concentration to the connection portion 15 and reduction of high-frequency signal loss.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a substrate via a connection portion and an underfill.

  Conventionally, as this type of semiconductor device, for example, the one described in Patent Document 1 can be cited. In the semiconductor device described in Patent Document 1, a BGA (Ball Grid Array) type semiconductor chip having a plurality of terminals and solder bumps electrically connected thereto is mounted on a substrate. The formed wiring is connected via solder bumps. The semiconductor device further includes an underfill, and the underfill is disposed so as to fill a gap between the substrate and the semiconductor chip.

  In this semiconductor device, the underfill is disposed in a gap between the substrate and the semiconductor chip, so that stress caused by a difference in linear expansion coefficient between the substrate and the semiconductor chip electrically connects the substrate and the semiconductor chip. Plays a role in mitigating concentration on solder bumps.

JP 2005-203488 A

  By the way, in this type of semiconductor device, when a part of a plurality of terminals included in a semiconductor chip is used for transmission of a high-frequency signal, loss of the high-frequency signal may occur when the underfill is disposed at a predetermined location. .

  Specifically, the underfill is a terminal used for transmitting a high-frequency signal in a semiconductor chip or a member electrically connected to the terminal, or a wiring electrically connected to the terminal among wirings on a substrate, If it is in contact with the signal, a high-frequency signal is lost. This is because an underfill made of a material having a dielectric constant different from that of the material constituting the semiconductor chip and the substrate used for high-frequency signal transmission contacts the characteristic impedance in the high-frequency signal transmission path. It is caused by change.

  In addition, when the semiconductor chip is provided with an element part that functions as a switch or a sensor that outputs a signal corresponding to a physical quantity, for example, when the underfill covers this element part, the element part does not operate normally. Can occur.

  As described above, in this type of semiconductor device, in order to alleviate stress concentration between the solder bump and the substrate, and to suppress deterioration in characteristics such as loss of high-frequency signals and malfunction of the element portion, Must be in a selective arrangement that does not contact a given member. However, in the semiconductor device described in Patent Document 1, the underfill is merely filled in the gap between the semiconductor chip and the substrate, and the above characteristic deterioration cannot be effectively suppressed.

  The present invention has been made in view of the above points, and underfill is selectively disposed. Stress relaxation at the joint between the semiconductor chip and the substrate due to underfill, and suppression of characteristic deterioration due to underfill can be achieved. An object is to provide a semiconductor device having a compatible structure.

  In order to achieve the above object, a semiconductor device according to claim 1 includes a semiconductor chip (1) having one surface (1a) and having a plurality of connection portions (15) on one surface side, and a semiconductor via the connection portions. A substrate (3) on which the chip is mounted; and an underfill (2) disposed in a gap between the semiconductor chip and the substrate. In such a configuration, a part of the connection part is a high-frequency connection part (151) that transmits a high frequency, and when viewed from the normal direction with respect to one surface, the connection part for a high frequency and another connection part are between A wall portion (16) is disposed, the wall portion divides the high frequency connection portion and the other connection portion when viewed from the normal direction, and the high frequency connection portion is exposed from the underfill. And the connection part different from the connection part for high frequencies among the several connection parts is covered with the underfill.

  As a result, the semiconductor device has a configuration in which a connection portion for transmitting a high-frequency signal is exposed from the underfill while the underfill is disposed between the semiconductor chip and the substrate. As a result, a semiconductor device in which alleviation of stress concentration on the connecting portion due to underfill and reduction in loss of high-frequency signals are achieved.

  Reference numerals in parentheses attached to each component and the like indicate an example of a correspondence relationship between the component and the like and specific components described in the embodiments described later.

1 is a schematic plan view showing a semiconductor device according to a first embodiment. It is a schematic sectional drawing which shows the cross section between II-II shown with a dashed-dotted line in FIG. It is a schematic sectional drawing which expands and shows the cross-sectional structure of the area | region shown with a dashed-two dotted line in FIG. It is a schematic plan view which shows an example of the planar shape of the wall part in the semiconductor device of 1st Embodiment, and arrangement | positioning of a soldering resist layer. It is a schematic sectional drawing which shows the preparation process of a bare chip among the manufacturing processes of the semiconductor device of 1st Embodiment. FIG. 5B is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 5A and a process of forming part of the insulating layer. FIG. 5B is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 5B and a process of forming a resist film having a predetermined pattern. FIG. 5C is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 5C and a process of forming a rewiring layer and removing a resist film. FIG. 5D is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 5D and a process of forming the remaining portion of the insulating layer. FIG. 5E is a schematic cross-sectional view showing the manufacturing process subsequent to FIG. 5E and forming a resist film having a predetermined pattern. It is a manufacturing process following Drawing 6A, and is a schematic sectional view showing a process of forming a part of connection part and a wall part. FIG. 6B is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 6B and showing a step of forming the remaining portion of the connecting portion. FIG. 6D is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 6C and a resist film removal and reflow process. FIG. 6D is a schematic cross-sectional view illustrating a manufacturing process subsequent to FIG. 6D and a process of preparing a substrate and aligning a semiconductor chip. It is a manufacturing process following Drawing 7A, and is a schematic sectional view showing a process of junction of a substrate and formation of an underfill. It is a schematic plan view which shows the semiconductor device of 2nd Embodiment. It is a schematic sectional drawing which shows the cross section between IX-IX shown with a dashed-dotted line in FIG. It is a schematic sectional drawing which shows the modification of the semiconductor device of 2nd Embodiment. It is a schematic plan view which shows the semiconductor device of 3rd Embodiment. It is a schematic sectional drawing which shows the cross section between XII-XII shown with a dashed-dotted line in FIG. It is a schematic plan view which shows the semiconductor device of 4th Embodiment. It is a schematic plan view which shows the filling process of an underfill among the manufacturing processes of the semiconductor device of 4th Embodiment. It is a schematic plan view which shows the semiconductor device of 5th Embodiment. It is a schematic plan view which shows the semiconductor device of 6th Embodiment. It is a schematic sectional drawing which shows the cross section between XVII-XVII shown with a dashed-dotted line in FIG. It is a schematic plan view which shows the semiconductor device of 7th Embodiment. It is a schematic sectional drawing which shows an example of the cross-sectional structure between the wall part and board | substrate in the semiconductor device of other embodiment. It is a schematic sectional drawing which shows an example of the cross-sectional structure between the wall part and board | substrate in the semiconductor device of other embodiment. It is a schematic sectional drawing which shows an example of the cross-sectional structure in the semiconductor device of other embodiment. It is a schematic plan view which shows the planar shape of the wall part in the semiconductor device of other embodiment. It is a schematic sectional drawing which shows the structural example of the semiconductor chip in the semiconductor device of other embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to FIGS. The semiconductor device of this embodiment can be applied to a semiconductor device (for example, a millimeter wave radar) mounted on a vehicle such as an automobile.

  In FIG. 1, in order to make the configuration easy to understand, constituent elements of a semiconductor chip 1 and a substrate 3 which will be described later and which cannot be seen in a top view are indicated by broken lines or two-dot chain lines. In FIG. 1 to FIG. 7B, in order to make the configuration easy to understand, the dimensions and thicknesses of the constituent elements are deformed and exaggerated. In FIG. 2, a terminal 12, an insulating layer 13, and a rewiring layer 14 to be described later are omitted from the semiconductor chip 1 for easy understanding.

  As shown in FIG. 1 or FIG. 2, the semiconductor device of this embodiment includes a semiconductor chip 1, an underfill 2, and a substrate 3, and the semiconductor chip 1 is disposed on the upper surface 30 a of the base material 30 in the substrate 3. While being mounted, the underfill 2 is selectively disposed in these gaps.

  The semiconductor chip 1 is, for example, WLCSP (abbreviation of Wafer level Chip Size Package), and is formed by a normal semiconductor process. For example, as shown in FIG. 3, the semiconductor chip 1 has a substantially plate shape having one surface 1 a and includes a bare chip 11, a terminal 12, an insulating layer 13, a rewiring layer 14, a connection portion 15, and a wall portion 16. As shown in FIG. 3, the terminal 12, the insulating layer 13, the rewiring layer 14, the connection portion 15, and the wall portion 16 are disposed on the one surface 1 a side of the semiconductor chip 1.

  The bare chip 11 is mainly made of a semiconductor material such as silicon, for example, and includes an unillustrated integrated circuit (IC) and has a rectangular plate shape having a surface 11a as shown in FIG. 3, and terminals 12 are provided on the surface 11a side. Is formed.

  The terminals 12 are made of, for example, a metal material such as Al (aluminum), and a plurality of terminals 12 are arranged in an array as viewed from the normal direction to the surface 11a. As shown in FIG. 3, the terminal 12 is connected to the rewiring layer 14 and covered with an insulating layer 13. The number and arrangement of the plurality of terminals 12 are appropriately changed according to the application.

  The insulating layer 13 is made of, for example, an insulating material used in a normal rewiring process, for example, a resin material such as polyimide.

  The rewiring layer 14 is made of a conductive material used in a normal rewiring process, for example, a metal material such as Cu (copper), Al, Ag (silver), or Au (gold). The rewiring layer 14 is formed by, for example, electrolytic plating or electroless plating, and electrically connects the plurality of terminals 12 and the connection portions 15 corresponding to them as shown in FIG.

  The connection portion 15 is a member that is used when the semiconductor chip 1 is mounted on the substrate 3 and electrically connects the terminal 12 of the semiconductor chip 1 and the wiring formed on the substrate 3. As shown, a plurality are formed and arranged in an array. For example, as shown in FIG. 2, the connecting portion 15 has a structure in which a base layer 15a made of a metal material such as Cu or Ag and a bump 15b made of solder are laminated, and is formed by electrolytic plating or electroless plating. Is done. The underlying layer 15a and the bumps 15b are arbitrary in height (hereinafter simply referred to as “height”) in a normal direction (hereinafter referred to as “one surface normal direction”) with respect to the one surface 1a of the semiconductor chip 1.

  In the present embodiment, a part of the plurality of connection parts 15 is a high-frequency connection part 151 used for transmission of a high-frequency signal such as a millimeter wave band (frequency 30 GHz to 300 GHz), and the remaining part is used for other purposes. It is set as the other connection part 152 used.

  In the present embodiment, as shown in FIG. 1, two high-frequency connection portions 151 are disposed at positions adjacent to the outer periphery of the semiconductor chip 1 among the plurality of connection portions 15, that is, at the outermost periphery, as viewed from above. Yes. The high-frequency connection portion 151 does not necessarily have to be disposed on the outermost periphery, but is preferably disposed on the outermost periphery from the viewpoint of reducing loss in transmission of a high-frequency signal.

  In the present embodiment, for example, as shown in FIG. 1 or FIG. 2, the high-frequency connection portion 151 is connected to a high-frequency wiring 33 described later, and is partially surrounded by a wall portion 16 described later. Exposed from fill 2. For example, one of the two high-frequency connection portions 151 is an output connection portion that transmits a high-frequency signal from the semiconductor chip 1 to the substrate 3, and the other is an input connection that transmits a high-frequency signal from the substrate 3 to the semiconductor chip 1. The connection part. Thereby, the loss of the high frequency signal by the underfill 2 comprised with the material from which a dielectric constant differs contacts the high frequency connection part 151 which transmits a high frequency signal is suppressed.

  The wall portion 16 is a member that serves as a wall that prevents the underfill 2 from contacting the high-frequency connection portion 151 in the underfill 2 formation step in the manufacturing process of the semiconductor device of the present embodiment described later. is there. In this embodiment, the wall portion 16 is made of the same material as that of the base layer 15a in the connection portion 15, and is formed by electrolytic plating, electroless plating, or the like together with the connection portion 15 in the connection portion 15 formation process.

  As shown in FIG. 1, the wall portion 16 is disposed between the high frequency connection portion 151 and the other connection portion 152 at a position apart from the high frequency connection portion 151 in a top view. These are partitioned. Specifically, for example, as shown in FIG. 1, the wall portion 16 is substantially U-shaped when viewed from above, and the extending direction of the high-frequency wiring 33 to which the high-frequency connection portion 151 is connected. In a different direction, the high-frequency connection portion 151 is partially surrounded.

  In this embodiment, as shown in FIG. 2 or FIG. 3, the wall portion 16 is disposed with a gap from the substrate 3, and the height in the one surface normal direction is smaller than the height of the connection portion 15. In other words, in this embodiment, the wall portion 16 does not come into contact with the substrate 3 when the semiconductor chip 1 is mounted on the substrate 3, and is a material constituting the underfill 2 in the underfill 2 forming step described later. Is high enough to remain in the gap between the wall portion 16 and the substrate 3. Details of the height and shape of the wall 16 will be described later.

  The underfill 2 serves to reinforce the joint portion between the semiconductor chip 1 and the substrate 3, to relieve stress concentration on the joint portion, and to protect by sealing, and is made of a resin material such as an epoxy resin. . The underfill 2 is a material (hereinafter referred to as “underfill material”) that is made liquid by, for example, mixing a resin material with a solvent after the semiconductor chip 1 is mounted on the substrate 3, from the end face side of the semiconductor chip 1. It is arranged by being injected directly under the semiconductor chip 1 and cured by heating.

  The underfill 2 is selectively filled with a region different from a predetermined region including the high-frequency connection portion 151 in the gap between the semiconductor chip 1 and the substrate 3 as shown in FIG. It is considered as an arrangement. As shown in FIG. 1, the underfill 2 is electrically connected to the high-frequency connection portion 151 in the substrate 3 from the viewpoint of reducing the loss of the high-frequency signal in a region outside the outer periphery of the semiconductor chip 1 in a top view. It is preferable that the arrangement is such that it does not come into contact with the high-frequency wiring 33 connected to.

  For example, as shown in FIG. 2, the substrate 3 includes a base material 30, a plurality of lands 31, a solder resist layer 32, and a high-frequency wiring 33. The substrate 3 may be mounted with other wiring and electronic components (not shown).

  The base material 30 is mainly composed of a synthetic resin such as a polyimide resin, for example, and is formed in a rectangular plate shape having an upper surface 30a as shown in FIG. 1 or 2, and a land 31 and a solder resist layer on the upper surface 30a side. 32 and a high-frequency wiring 33 are arranged.

  The land 31 is made of, for example, a metal material such as Cu, and the connecting portion 15 of the semiconductor chip 1 is joined as shown in FIG. The land 31 is connected to a high-frequency wiring 33 for transmitting a high-frequency signal, other wiring (not shown), and the like. In the present embodiment, for example, as shown in FIG. 2, the land 31 is a first land 311 disposed immediately below the connecting portion 15 and a second land disposed directly below the wall portion 16 in a cross-sectional view. And a land 312.

  In the present embodiment, the second land 312 is used as a dummy for adjusting the dimension in the height direction of a gap between a wall portion 16 and a substrate 3 to be described later, and is connected to the first land 311 and this. It is electrically separated from the wiring to be done.

  The solder resist layer 32 is made of, for example, an insulating material such as polyimide resin, and is formed on the upper surface 30a side as shown in FIG. 2, and a part of the first land 311, the second land 312 and the wiring (not shown). Covers a part of

  In this embodiment, the solder resist layer 32 is made of an arbitrary insulating material with good wettability of the liquid underfill material, and this underfill material reaches the high frequency connection portion 151 beyond the wall portion 16. This is a predetermined arrangement for suppressing this. Details of this will be described later. The solder resist layer 32 has a thickness in the normal direction with respect to the upper surface 30a of about 50 μm, for example, but may be adjusted as appropriate.

  The high-frequency wiring 33 is made of a metal material such as Cu, and is connected to the first land 311 to which the high-frequency connection portion 151 is connected. In the present embodiment, the high-frequency wiring 33 is connected to, for example, an antenna (not shown) and exposed from the underfill 2 as shown in FIG.

  The above is the configuration of the semiconductor device of this embodiment.

  Next, the clearance gap between the wall part 16 and the board | substrate 3 is demonstrated with reference to FIG.

  In the present embodiment, for example, as shown in FIG. 3, between the wall portion 16 and a portion of the substrate 3 that is located immediately below the wall portion 16 in a sectional view (hereinafter referred to as “below the wall”), for example, There is a gap.

As shown in FIG. 3, the gap between the one surface 1a and the upper surface 30a of the substrate 3 of the semiconductor chip 1 and the gap G _0, the gap between the wall portion 16 and the wall immediately below the as the gap G _1, gap G ₁ is a gap it is preferably less than 10% of G _0. Specifically, when the gap _{G 0} is, for example, 100μm~150μm, the gap _{G 1} is 15 [mu] m or less, preferably so that the are 5 m to 10 m. Thereby, in the formation process of the underfill 2, a capillary phenomenon will arise between the wall part 16 and a wall directly lower part.

  Next, the shape and the effect of the wall 16 and the substrate 3 immediately below the wall and the effects thereof will be described with reference to FIG.

  As shown in FIG. 3, the underfill 2 is filled in the gap between the wall 16 and the portion immediately below the wall as a result of the capillary action in the process of pouring the underfill material in the manufacturing process described later. At this time, in order to prevent the underfill material from reaching the high-frequency connection portion 151 beyond the wall portion 16, the wall portion 16 is formed at the tip of the wall portion 16 on the substrate 3 side as shown in FIG. 3. The cross-sectional shape is a shape having corners, preferably a right-angled shape.

  On the other hand, in the present embodiment, the portion immediately below the wall of the substrate 3 is constituted by the second land 312 and a part of the solder resist layer 32 covering the second land 312 as shown in FIG. As shown in FIG. 3, the portion directly below the wall is formed in a region of the upper surface 30 a of the substrate 3 projected in the normal direction of the surface of the upper surface 30 a of the substrate 3. The tip of the wall portion 16 side and the high-frequency connection portion 151 side of the portion directly below the wall has a cross-sectional shape with a corner, preferably a right-angle shape, like the wall portion 16.

  In addition, as shown in FIG. 3, it is preferable that the end surface by the side of the connection part 151 for high frequency is arrange | equalized in the wall part 16 and the wall directly lower part by sectional view.

  Thereby, in the edge part by the side of the high frequency connection part 151 among the surface of the front-end | tip part of the wall part 16, and the surface of the front-end | tip part of a wall lower part, an underfill material is along the high frequency connection part 151 side along these surfaces. It becomes a shape that does not stick out. Therefore, the contact between the underfill 2 and the high frequency connection portion 151 is prevented, and the high frequency connection portion 151 is exposed from the underfill 2.

  Next, the shape of the wall portion 16 and the arrangement of the solder resist layer 32 on the substrate 30 will be described with reference to FIG.

  In FIG. 4, in order to easily understand the shape of the wall 16 and the solder resist layer 32, the wall 16, the high frequency connection portion 151, a part of the first land 311, the solder resist layer 32, A part of the high frequency wiring 33 is indicated by a solid line. In FIG. 4, for the purpose described above, the outline of the semiconductor chip 1 is indicated by a one-dot chain line, and the outline of the first land 311 that is covered with the solder resist layer 32 and is not visible is indicated by a broken line.

  In the following, for simplification of description, as shown in FIG. 4, the wall surface on the high frequency connection portion 151 side of the wall portion 16 is referred to as “inner wall surface 16 a” in the top view, and the wall surface on the opposite side thereof. Is referred to as "outer wall surface 16b". Also, as shown in FIG. 4, for the sake of convenience, the left-right direction in the plane of FIG. 4 is referred to as the “X direction”, and the direction perpendicular to the X direction in the plane of FIG.

  As shown in FIG. 4, the inner wall surface 16 a of the wall portion 16 is preferably curved at the intersection between the portion along the X direction and the portion along the Y direction when viewed from above. This is because when the underfill material is injected, the underfill material that has reached the gap between the crossing portion and the substrate 3 smoothly flows along the shape of the crossing portion and does not protrude to the high-frequency connection portion 151 side. It is to be done.

  In addition, the said intersection part should just be made into the shape without an angle | corner, and may be suitably changed not only R shape as shown in FIG.

  On the other hand, in the present embodiment, as shown in FIG. 4, the upper surface 30 a of the base material 30 is connected to the region directly below the semiconductor chip 1 and the region directly below the wall 16 and the high-frequency connection 151 in the top view. A part of the area between the first land 311 and the first land 311 is exposed from the solder resist layer 32. Specifically, as shown in FIG. 4, a region including at least a portion adjacent to a region immediately below the wall portion 16 of the upper surface 30 a of the base material 30 is exposed from the solder resist layer 32. In other words, a groove penetrating the solder resist layer 32 is formed between the region immediately below the wall portion 16 of the solder resist layer 32 and the first land 311, and the first land 311 is partially formed in the groove. It can be said that it is surrounded.

  Further, a region exposed from the solder resist layer 32 (hereinafter referred to as “exposed region”) on the upper surface 30 a of the base material 30 is in a state in which the wettability of the underfill material is worse than that of the solder resist layer 32. Specifically, for example, the base material 30 is mainly composed of an insulating material whose wettability of the underfill material is worse than that of the solder resist layer 32, or an arbitrary liquid repellent treatment so that the wettability of the underfill material is deteriorated. And the like.

  As a result, even if the underfill material that has entered the gap between the wall portion 16 and the substrate 3 tries to protrude to the high frequency connection portion 151 side, the progress is caused by the surface tension in the exposed region where the underfill material has poor wettability. Will be blocked.

  Therefore, due to the influence of the shape of the inner wall surface 16 a of the wall portion 16 on the flow of the underfill material and the influence of the underfill material wetting spread by the exposed region of the base material 30, the underfill material becomes the high frequency connection portion 151. Contact is prevented.

  Next, an example of a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 5A to 7B.

  In the semiconductor device of the present embodiment, any semiconductor process can be adopted except that the wall portion 16 is formed in the manufacture of the semiconductor chip 1, and the other steps will be briefly described. 5A to 6D, for easy understanding of the process, a part of the semiconductor chip 1 including the high-frequency connection portion 151 and the wall portion 16 is shown, and the other regions are omitted.

  First, as shown in FIG. 5A, a bare chip 11 having a plurality of terminals 12 formed on the surface 11a side by a normal semiconductor process is prepared. Then, as shown in FIG. 5B, a first insulating film 131 made of a photosensitive insulating material such as polyimide is formed on the surface 11a of the bare chip 11 and is a part of the insulating layer 13, and then photolithography etching is performed. Patterning is performed by the method, and a part of the terminal 12 is exposed.

  Subsequently, for example, Ti (titanium) and Cu are laminated, and a seed layer (not shown) covering the first insulating film 131 and a part of the terminal 12 is formed by sputtering or the like. Thereafter, as shown in FIG. 5C, a resist film 4 made of a photosensitive insulating material is formed on the seed layer by a coating method, and is patterned by a photolithography etching method. Expose the surrounding area.

  Next, as shown in FIG. 5D, for example, after forming the rewiring layer 14 with Cu or the like by electrolytic plating or the like, the resist film 4 is peeled off with a resist stripping solution or the like, and a seed layer (not shown) is removed with an etching solution or the like. . Thereafter, for example, the second insulating film 132 that covers the rewiring layer 14 and the first insulating film 131 is formed and patterned by the same procedure as described in FIG. 5B, and the surface 11 a of the bare chip 11 and the rewiring layer 14 are then formed. An insulating layer 13 is formed to cover a part of the film.

  Then, for example, Ti (titanium) and Cu are laminated, and a portion of the rewiring layer 14 exposed from the second insulating film 132 (hereinafter referred to as an “exposed portion”) and the second insulating film 132 are not illustrated. A seed layer is formed by sputtering or the like. Thereafter, for example, the resist film 4 is formed and patterned on the seed layer by the same procedure as described with reference to FIG. 5C. At this time, as shown in FIG. 6A, an opening 4a that exposes the exposed portion of the redistribution layer 14 in the seed layer (not shown) and a portion covering the periphery thereof, and a portion of the seed layer (not shown) separated from the exposed portion. The resist film 4 is provided with an opening 4b that exposes a portion covering the film.

  5D, for example, after forming the base layer 15a and the wall portion 16 made of Cu or the like as shown in FIG. 6B, Ni (not shown) is formed on the base layer 15a and the wall portion 16, as shown in FIG. 6B. A (nickel) thin film is formed by electrolytic plating or the like. Then, as shown in FIG. 6C, the resist film 4 on the insulating layer 13 is used as the first resist film 41, for example, a second resist film 42 covering the wall portion 16 is formed by dispenser application or the like, and soldering is performed by electrolytic plating or the like. Bumps 15b made of are formed on the base layer 15a.

  Subsequently, for example, after removing the resist films 41 and 42 and the seed layer (not shown) by the same procedure as described with reference to FIG. 5D, the bumps 15b made of solder are heated and melted, and then allowed to cool and solidify again. As a result, as shown in FIG. 6D, the semiconductor chip 1 including the wall portion 16 that partially surrounds the plurality of connection portions 15 and the high-frequency connection portions 151 can be manufactured.

  Next, as shown in FIG. 7A, the first land 311 to which the connecting portion 15 is connected, the second land 312 at a position corresponding to the wall portion 16, the solder resist layer 32 covering these, and the high frequency wiring A substrate 3 including 33 is prepared and aligned with the semiconductor chip 1. Then, for example, the bump 15b is heated and melted by a reflow method and then solidified again by being allowed to cool, thereby connecting the semiconductor chip 1 and the substrate 3.

  Then, as shown in FIG. 7B, a liquid underfill material in which an epoxy resin or the like is dissolved with a solvent or the like is poured from the end face of the semiconductor chip 1 directly under the semiconductor chip 1 and is heated and cured to form the underfill 2. Specifically, a surface between one surface 1a and the opposite surface 1b of the semiconductor chip 1 is an end surface 1c, and a portion of the end surface 1c on the high frequency connection portion 151 side in a top view is a first end surface 1ca. The opposite part is set as the second end face 1cb, and the coating liquid is poured from the second end face 1cb. At this time, since the wall portion 16 partially surrounds the high frequency connection portion 151, the liquid underfill material is prevented from coming into contact with the high frequency connection portion 151. In this state, the underfill material is heated and cured to form the underfill 2, whereby the semiconductor device of this embodiment in which the underfill 2 is selectively disposed can be manufactured.

  According to this embodiment, the semiconductor chip 1 is mounted on the substrate 3, and the high-frequency connection portion 151 that transmits a high-frequency signal is exposed from the underfill 2 in the semiconductor chip 1, and the other connection portions 152 are underfilled. Thus, a semiconductor device having a structure covered with 2 is obtained. Therefore, the underfill 2 is selectively disposed due to the presence of the wall portion 16, and both relaxation of stress concentration on the other connection portion 152 and reduction in loss in transmission of a high-frequency signal through the high-frequency connection portion 151 are achieved. A semiconductor device having the above structure is obtained.

(Second Embodiment)
A second embodiment will be described with reference to FIGS.

  In FIG. 8, as in FIG. 1, the constituent elements of the semiconductor chip 1 and the substrate 3 that are not visible in the top view are shown by broken lines or two-dot chain lines, and the sizes of the constituent elements are deformed and exaggerated. Shows what you did. 8 and 9, as in FIG. 1, the thickness and the like of the components are deformed and exaggerated, and a part of the semiconductor chip 1 is omitted.

  As shown in FIG. 8, in the semiconductor device of this embodiment, the wall portion 16 is constituted by the other connection portion 152 adjacent to the high frequency connection portion 151, and is partially exposed from the solder resist layer 32. The land 312 is electrically connected. The semiconductor device of this embodiment is different from the first embodiment in the above points. In the present embodiment, this difference will be mainly described.

  In the present embodiment, for example, as shown in FIG. 8, the wall portion 16 is adjacent to the high-frequency connection portion 151 among the other connection portions 152, and has a wall shape. It is composed of a ground connection portion 152a connected to a portion having a ground potential. For example, as shown in FIG. 8, the wall portion 16 is substantially U-shaped in a top view, and has a high frequency in a direction different from the extending direction of the high frequency wiring 33 to which the high frequency connection portion 151 is connected. The connection portion 151 is partially surrounded.

  In the present embodiment, as shown in FIG. 9, the wall portion 16 is formed by laminating a base layer 16 c made of a metal material such as Cu or Ag and a bump 16 d made of solder, like the other connection portions 152. It has been configured. The wall portion 16 is formed simultaneously with the connection portion 15 by, for example, electrolytic plating or electroless plating. In the present embodiment, for example, as shown in FIG. 9, the wall portion 16 is connected to the second land 312 that is set to the ground potential in the substrate 3, so that no gap is generated between the wall portion 16 and the substrate 3. It is said that.

  In the present embodiment, since the wall portion 16 and the second land 312 are connected, a region between the high-frequency connection portion 151 and the wall portion 16 in the upper surface 30a of the substrate 3 is a solder resist. It may be covered with the layer 32.

  According to the present embodiment, the effects of the first embodiment can be obtained, and a gap is not generated between the wall portion 16 and the substrate 3, so that the underfill 2 is for higher frequencies than the first embodiment. A semiconductor device in which contact with the connection portion 151 is suppressed is obtained. Further, in the present embodiment, the wall 16 and the connecting portion 15 have the same configuration and can be formed at the same time, so that an effect of becoming a semiconductor device with reduced manufacturing cost is also expected.

(Modification of the second embodiment)
A modification of the second embodiment will be described with reference to FIG. In FIG. 10, as in FIG. 2, the components are exaggerated by deforming the thickness and the like, and a part of the semiconductor chip 1 is omitted.

  The semiconductor device of this modification is different from the second embodiment in that the high-frequency connection portion 151, the wall portion 16, and the other connection portion 152 are formed of solder bumps as shown in FIG. To do.

  The semiconductor device of this modification is the same as the semiconductor device of the first embodiment except that the high-frequency connection portion 151, the wall portion 16, and the other connection portion 152 of the semiconductor chip 1 are configured only by bumps made of solder. It can be manufactured by the same manufacturing method. For example, instead of forming the base layer 15a and the wall portion 16 described with reference to FIG. 6B, a bump made of solder is formed by electrolytic plating, and then the resist film 4 and a seed layer (not shown) are removed and reflowed. The semiconductor chip 1 used in the example can be prepared.

  According to this modification, the semiconductor device can obtain the same effects as those of the second embodiment.

(Third embodiment)
A third embodiment will be described with reference to FIGS. In FIG. 11, as in FIG. 1, the constituent elements of the semiconductor chip 1 and the substrate 3 that cannot be seen in the top view are indicated by broken lines or two-dot chain lines, and the sizes of the constituent elements are deformed and exaggerated. Shows what you did. 11 and 12, as in FIG. 1, the components are exaggerated by deforming the thickness and the like, and a part of the semiconductor chip 1 is omitted.

  For example, as shown in FIG. 11, the semiconductor device according to the present embodiment includes, as a top view, a wall portion 16 that partially surrounds the high-frequency connection portion 151 as a first wall portion 161, and the element portion 17 and the element portion. The second embodiment is different from the first embodiment in that it further includes a second wall 162 that surrounds the second wall 162. In the present embodiment, this difference will be mainly described.

  As shown in FIG. 11, the second wall portion 162 is disposed so as to surround the element portion 17 in a top view, and has the same configuration as the first wall portion 161 as shown in FIG. 12. Similar to the first wall portion 161, the second wall portion 162 serves as a wall that blocks the underfill material from flowing into a predetermined position. The second wall portion 162 only needs to surround the element portion 17 and prevent the element portion 17 from being covered with the underfill 2, and the position, shape, and the like thereof are changed as appropriate.

  As shown in FIG. 12, the element unit 17 is formed on the semiconductor chip 1 and is configured by, for example, MEMS (abbreviation of Micro Electro Mechanical Systems) or the like and functions as a switch, a sensor, or the like. The element unit 17 has, for example, an arbitrary configuration that functions as an actuator, an acceleration sensor, a pressure sensor, and the like, and is formed by an arbitrary semiconductor process. The element portion 17 is exposed from the underfill 2 by being surrounded by the second wall portion 162 as shown in FIG. 11 or FIG.

  In the present embodiment, as shown in FIG. 12, the substrate 3 is a predetermined region including the element portion 17 of the semiconductor chip 1, that is, a region (hereinafter simply referred to as “element”) projected from the region surrounded by the second wall portion 162. The through-hole 34 is formed in the “partial projection area”.

  As shown in FIG. 12, the through-hole 34 is a through-hole that connects the upper surface 30a of the base material 30 and the surface on the opposite side, and transmits a signal output from the element unit 17 to an external electronic component (not shown). An electrode layer (not shown) is formed on the wall surface as necessary. When the element portion 17 is configured to function as a pressure sensor, a through hole (not shown) is formed in the element portion projection region of the substrate 3 in addition to the through hole 34.

  For a predetermined region including the outline of the element portion projection area of the substrate 3, the upper surface 30 a has a solder resist as shown in FIG. 12 for the purpose of suppressing the underfill material from flowing into the element portion projection area. Preferably it is exposed from layer 32. As a result, for the same reason as described in the first embodiment, the wettability of the underfill material is deteriorated at the portion where the upper surface 30a of the base material 30 is exposed in the element portion projection region, and the action of the surface tension at the portion. This suppresses the flow of the underfill material.

  According to this embodiment, in addition to the effects of the first embodiment, the second wall portion 162 suppresses the contact between the underfill 2 and the element portion 17 and the associated malfunction due to the element portion 17 being provided. The resulting semiconductor device is obtained.

(Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. In FIG. 13 and FIG. 14, in order to make it easy to understand the arrangement of the solder resist layer 32 and the underfill 2 described later, the cross section is not shown, but the underfill 2 or the underfill material 2a is hatched. In FIGS. 13 and 14, for the sake of clarity, the outline and components of the semiconductor chip 1 are indicated by broken lines, the portions hidden by the semiconductor chip 1 in a top view are indicated by solid lines, the sizes of the components, and the like. It shows what was exaggerated by deforming.

  Conventionally, this type of semiconductor device generally has a configuration in which the underfill 2 protrudes outside the outline of the semiconductor chip 1 in a top view. At this time, from the viewpoint of reducing the loss of the high frequency signal, the underfill 2 not only does not contact the high frequency connection portion 151 but also does not contact or contact the high frequency wiring 33 in the substrate 3. Is preferably arranged as little as possible.

  However, conventionally, it is difficult to control the amount of the underfill 2 protruding from the semiconductor chip 1, and the underfill 2 comes into contact with the high-frequency wiring 33 over a wide range, resulting in loss of high-frequency signals and variations in high-frequency characteristics of the semiconductor device. Has occurred.

  Therefore, as a result of intensive studies, the inventors adjusted the width of the portion of the solder resist layer 32 that protrudes from the semiconductor chip 1 in a top view, and the amount that the underfill 2 protrudes from the semiconductor chip 1 (hereinafter referred to as “the amount of protrusion”). To the semiconductor device of this embodiment.

  As shown in FIG. 13, the semiconductor device of the present embodiment is different from the first embodiment in that the amount of protrusion of the underfill 2 is controlled by the solder resist layer 32 in a top view. To do. In the present embodiment, this difference will be mainly described.

  In the following description, for simplification of description, as shown in FIG. 13, the end face 1 c of the semiconductor chip 1 adjacent to the high frequency connection portion 151 is referred to as a “first end face 1 ca”, and the first end face 1 ca The opposite side is referred to as "second end face 1cb". Further, as shown in FIG. 13, a region outside the outer periphery of the semiconductor chip 1 in a top view of the solder resist layer 32 is referred to as a “protrusion region 32 a”, and a region where the underfill material is dropped in the protrusion region 32 a. This will be referred to as “dropping region 32aa”.

  In the semiconductor device of this embodiment, the solder resist layer 32 is made of a material with good wettability of the liquid underfill material, that is, a lyophilic material. In the present embodiment, as shown in FIG. 14, the solder resist layer 32 has an underfill in the region on the opposite side of the semiconductor chip 1 from the straight line formed by the outline of the second end face 1 cb in the top view in the protruding region 32 a. It is set as the dripping area | region 32aa where a material is dripped.

  For example, as shown in FIG. 14, the solder resist layer 32 has a constant width L <b> 1 in a portion of the protruding region 32 a that is different from the dropping region 32 aa. The width L1 is arbitrary, but is, for example, about 0.2 mm to 1 mm.

  Here, the “width of the protruding region 32a” means a width in a direction perpendicular to the outline of the semiconductor chip 1 with which the protruding region 32a is in contact with the protruding region 32a. In other words, the width of the protruding region 32a is a width in a region between one side of the outline of the semiconductor chip 1 and a portion outside the one side of the outline of the protruding region 32a.

  By making the width L1 of the protruding region 32a constant in this way, as shown in FIG. 14, the underfill material 2a is dropped and the underfill material 2a is disposed immediately below the semiconductor chip 1 as shown in FIG. Excessive protrusion of 2a can be suppressed.

  Specifically, the underfill material 2a dropped on the dropping region 32aa is wetted by capillary action in the direction from the second end face 1cb side to the first end face 1ca side as shown by the white arrow in FIG. It spreads. After the underfill material 2a is first filled in the gap between the semiconductor chip 1 and the substrate 3 except for the portion surrounded by the wall portion 16, the underfill material 2a starts to protrude into the protruding area 32a, and dripping occurs at the start of protruding. Canceled.

  At this time, since the width L1 of the region different from the dropping region 32aa in the protruding region 32a is constant, the underfill material 2a is suppressed from causing unevenness in the protruding region. And in the said different area | region, while the underfill material 2a stays by the effect | action of surface tension, it is suppressed that it protrudes beyond the protrusion area | region 32a to the exterior. By heating and curing the underfill material 2a in this state, the semiconductor device of this embodiment having a configuration in which the amount of the underfill 2 protruding outside the outline of the semiconductor chip 1 is controlled is obtained.

  According to the present embodiment, in addition to the effects of the first embodiment, the amount of protrusion of the underfill 2 from the semiconductor chip 1 is controlled, so that a semiconductor device in which variations in high frequency characteristics are suppressed is obtained.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIG. In FIG. 15, for easy understanding of the arrangement of the solder resist layer 32, the semiconductor chip 1 is indicated by a broken line, and a portion hidden behind the semiconductor chip 1 in a top view is indicated by a solid line.

  In the present embodiment, the solder resist layer 32 is different from the first embodiment in that blank regions 321 and 322 are formed in portions of the protruding region 32a different from the dropping region 32aa.

  The blank areas 321 and 322 indicate that an unfilled area of the underfill 2 unintentionally, that is, a void is generated in an area immediately below the semiconductor chip 1 when an underfill material is injected directly from the dropping area 32aa to the semiconductor chip 1. Play a role to suppress.

  Here, when the underfill material is injected, the underfill material may also wrap around the protruding region 32 a, and the wrapping underfill material may spread out more quickly than the region immediately below the semiconductor chip 1. In this case, as viewed from above, the underfill material wetted and spread in the protruding region 32a surrounds the semiconductor chip 1 in the vicinity of the outer region of the semiconductor chip 1, and air is trapped in the region immediately below the semiconductor chip 1. A void occurs. When such a void occurs, the void becomes a starting point for cracking in the underfill 2 or the connection portion 15 due to a temperature change or the like, and may cause a problem.

  However, even when the underfill material wraps around the protruding region 32a, the presence of the blank regions 321 and 322 where the wrapped underfill material spreads out excessively causes the relative speed of the underfill material to spread out. Can be late. As a result, the underfill material wetting and spreading in the region immediately below the semiconductor chip 1 is completed before the underfill material wetting and spreading in the protruding region 32a, and the generation of voids is suppressed.

  In the present embodiment, the blank area 321 has, for example, one rectangular shape as shown in FIG. For example, as shown in FIG. 15, the blank area 322 has a comb-tooth shape including a plurality of rectangular protrusions. However, the margin areas 321 and 322 only have to be able to slow down the wetting and spreading speed of the underfill material that wraps around when the underfill material wraps around the protruding area 32a, and the number, arrangement, and shape are arbitrary. . In this method, if another semiconductor chip having no wall portion 16 is used, the space between the other semiconductor chip and the substrate on which the semiconductor chip is mounted is filled with an underfill material to suppress voids. It is effective for.

  According to the present embodiment, in addition to the effects of the first embodiment, a semiconductor device in which unintended voids are prevented from being generated in the gap between the semiconductor chip 1 and the substrate 3 is obtained.

(Sixth embodiment)
The sixth embodiment will be described with reference to FIGS. In FIG. 16, in order to make the arrangement and configuration of the solder resist layer 32 easier to understand, the cross section is not shown, but the solder resist layer 32 is hatched. In FIG. 16, for the sake of clarity, the semiconductor chip 1 is indicated by a broken line, a portion hidden by the semiconductor chip 1 in a top view is indicated by a solid line, and a region outside the solder resist layer 32 is omitted. .

  As shown in FIG. 16, the semiconductor device of the present embodiment has a configuration in which the amount of protrusion of the underfill 2 is controlled by a region exposed from the solder resist layer 32 in the upper surface 30 a of the substrate 3. This is different from the first embodiment. In the present embodiment, this difference will be mainly described.

  In the present embodiment, for example, as shown in FIG. 16, the solder resist layer 32 has a substantially rectangular frame shape surrounding the semiconductor chip 1 in a top view, and is surrounded by the solder resist layer 32 in the base material 30. It is said that the wettability of the underfill material is inferior to that of the part. This is to prevent the underfill material protruding from the outline of the semiconductor chip 1 from getting over the solder resist layer 32 and spreading further outward when the underfill material is injected.

  If necessary, any part of the upper surface 30a of the base material 30 surrounded by the solder resist layer 32 may be subjected to an arbitrary lyophilic treatment for improving the wettability of the underfill material, or the solder resist layer 32. Any liquid repellent treatment may be applied. In addition, the relative quality of the underfill material may be adjusted by selecting materials constituting the base material 30 and the solder resist layer 32.

  In the present embodiment, for example, as shown in FIG. 16, the underfill 2 covers a region 30b surrounded by the outline of the solder resist layer 32 in the substrate 3 (hereinafter referred to as “resist outline region 30b”). Is arranged. As shown in FIG. 16 or FIG. 17, the underfill 2 is disposed in the resist inner region 30 b exposed from the solder resist layer 32, and includes a predetermined high frequency connection portion 151 in the gap between the semiconductor chip 1 and the substrate 3. It covers an area different from the area.

  Hereinafter, for simplification of description, as illustrated in FIG. 16, a region of the resist inner region 30 b that is covered with the underfill 2 and that protrudes from the outer surface of the semiconductor chip 1 is referred to as an “excess region 30 ba”. Further, a region where the underfill material is dropped in the protruding region 30ba is referred to as a “dropping region 30bb”.

  Here, as shown in FIG. 16, the width in the region different from the dropping region 30bb in the protruding region 30ba is L2, and the width L2 is constant as in the fourth embodiment. This is for controlling the amount of the underfill 2 protruding outside the outer outline of the semiconductor chip 1 as in the fourth embodiment.

  Here, the “width of the protruding region 30ba” means a width in a direction perpendicular to the outline of the semiconductor chip 1 with which the protruding region 30ba is in contact with the protruding region 30ba.

  According to the present embodiment, in addition to the first embodiment, the amount of protrusion of the underfill 2 from the semiconductor chip 1 is controlled, so that a semiconductor device in which variations in high frequency characteristics are suppressed is obtained.

(Seventh embodiment)
A seventh embodiment will be described with reference to FIG. In FIG. 18, for the same purpose as in FIG. 17, the semiconductor chip 1 is indicated by a broken line, a portion hidden by the semiconductor chip 1 in a top view is indicated by a solid line, and a region outside the solder resist layer 32 is omitted. Yes.

  In the semiconductor device of this embodiment, as shown in FIG. 18, the protrusion amount of the underfill 2 is surrounded by the solder resist layer 32 in the upper surface 30 a of the substrate 3 and the resist inner region 30 b exposed from the solder resist layer 32. It is set as the structure controlled by. In the semiconductor device of this embodiment, the resist inner region 30b includes blank regions 30bc and 30bd. The semiconductor device of this embodiment is different from the first embodiment in these points. In the present embodiment, this difference will be mainly described.

  Similar to the sixth embodiment, the resist inner region 30b is a region where the wettability of the underfill material is better than that of the solder resist layer 32. In this embodiment, as shown in FIG. 18, the blank region 30bc , 30bd.

  The blank areas 30bc and 30bd play a role of suppressing the occurrence of unintended voids in the area immediately below the semiconductor chip 1 when the underfill material is injected, like the blank areas 321 and 322 in the fifth embodiment.

  In the present embodiment, the blank area 30bc has a rectangular shape as shown in FIG. 18, for example. For example, as shown in FIG. 18, the blank area 30bd has a comb-teeth shape with a plurality of rectangular protrusions. However, the margin areas 30bc and 30bd need only be able to slow down the wetting and spreading speed of the underfill material when the underfill material wraps around the protruding area 30ba, and the number, arrangement, and shape are arbitrary. .

  According to the present embodiment, in addition to the effects of the first embodiment, a semiconductor device in which unintended voids are prevented from being generated in the gap between the semiconductor chip 1 and the substrate 3 is obtained.

(Other embodiments)
The semiconductor device described in each of the above embodiments is an example of the semiconductor device of the present invention, and is not limited to each of the above embodiments, but within the scope described in the claims. Can be changed as appropriate.

(1) For example, in each of the above-described embodiments, the example in which the lower portion of the substrate 3 immediately below the wall portion 16 is configured by the second land 312 and part of the solder resist layer 32 has been described. However, it is only necessary that the gap G ₁ with the wall portion 16 is 10% or less of the gap G ₀ , and the lower portion of the wall may be composed of only the second land 312 as shown in FIG. Further, the second land 312 may be not only a land form but also a wiring form. Furthermore, as shown in FIG. 20, the portion directly below the wall may be configured with only a part of the solder resist layer 32.

(2) In the first embodiment described above, an example in which the underfill 2 is composed of only a resin material has been described. However, the underfill 2 includes a filler 21 made of an insulating material such as SiO ₂ as shown in FIG. It may be configured to include. In this case, as shown in FIG. 21, it is preferable that the filler 21 has a particle size larger than the gap G ₁ between the wall portion 16 and the substrate 3.

  As a result, as shown in FIG. 21, the filler 21 is clogged outside the gap between the wall portion 16 and the substrate 3, and the amount of the underfill material entering the gap between the wall portion 16 and the substrate 3 is suppressed. Further, the effect of preventing the underfill 2 from coming into contact with the high-frequency connection 151 is further enhanced. Therefore, the semiconductor device can further reduce the loss of high-frequency signals.

  The particle size of the filler 21 refers to, for example, the arithmetic average diameter in the average particle size distribution. The filler 21 may have a particle size larger than the gap between the wall portion 16 and the substrate 3 in a predetermined amount or more, and may have a particle size smaller than the gap between the wall portion 16 and the substrate 3. May be included.

  (3) In each of the above-described embodiments, the example in which the wall portion 16 has a shape that partially and continuously surrounds the high-frequency connection portion 151 has been described. However, as illustrated in FIG. The shape may be intermittently surrounded. In this case, the gap between the adjacent wall portions 16 in a top view may be set to such an extent that a capillary phenomenon occurs and the underfill material cannot easily pass therethrough.

  (4) In each of the above embodiments, the example in which the high-frequency wiring 33 is exposed from the underfill 2 has been described. However, the structure in which the underfill material is prevented from entering the high-frequency wiring 33 is also possible. The semiconductor device may be provided. For example, a convex portion or a concave portion that blocks the progress of the liquid underfill material may be formed in a region around the high-frequency wiring 33 in the substrate 3.

  (5) In each of the above embodiments, the structure example of the semiconductor device in which the semiconductor chip 1 is WLCSP has been described. However, as shown in FIG. 23, the semiconductor chip 1 has the interposer substrate 19 and the other surface 19b. The wall portion 16 may be formed on the wall.

  For example, in this case, as shown in FIG. 23, the semiconductor chip 1 includes a silicon chip 18 and an interposer substrate 19 having one surface 19a and another surface 19b.

  Similar to the first embodiment, the silicon chip 18 is a WLCSP, and includes a bare chip, a terminal, an insulating layer, a rewiring layer, and a connection portion 181 (not shown), and is manufactured by a normal semiconductor process. The silicon chip 18 is connected to the one surface 19a side of the interposer substrate 19 via a connection portion 181 made of an arbitrary conductive material such as solder or Cu.

  The interposer substrate 19 includes a base material mainly made of an insulating material such as an epoxy resin, for example, and as shown in FIG. 23, a connection portion 191 and a wall portion 16 are formed on the other surface 19b side. Is done. The interposer substrate 19 has wirings and through holes (not shown) formed therein, and wirings (not shown) formed on the one surface 19a side are electrically connected to the connection portion 191.

  That is, in this case, the connection unit 191 corresponds to the connection unit 15 in each of the above embodiments, and a part of the connection unit 191 is used for transmitting a high-frequency signal. The arrangement relationship between the connection portion 191 and the wall portion 16 is the same as the arrangement relationship between the connection portion 15 and the wall portion 16 in the above embodiments. That is, the connection portion 191 that is used for transmitting a high-frequency signal is exposed from the underfill 2 by being partially surrounded by the wall portion 16.

  Note that a filler (not shown) that is the same as or different from the underfill 2 may be disposed between the silicon chip 18 and the interposer substrate 19. In each of the above embodiments, even when the semiconductor chip 1 has the above structure, the same effects as those of the above embodiments can be obtained.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 151 High frequency connection part 16 Wall part 2 Underfill 3 Substrate 31 Land 32 Solder resist layer 33 High frequency wiring

Claims (7)

A semiconductor chip (1) having one surface (1a) and having a plurality of connecting portions (15) on the one surface side;
A substrate (3) on which the semiconductor chip is mounted via the connecting portion;
An underfill (2) disposed in a gap between the semiconductor chip and the substrate,
A part of the connection part is a high frequency connection part (151) for transmitting a high frequency,
A wall portion (16) is disposed between the high frequency connection portion and the other connection portion when viewed from the normal direction to the one surface,
The wall portion defines the high frequency connection portion and the other connection portion as seen from the normal direction,
The high frequency connection portion is exposed from the underfill,
The said connection part different from the said high frequency connection part among the said several connection parts is a semiconductor device covered with the said underfill.   The semiconductor device according to claim 1, wherein the wall portion is formed on the one surface side of the semiconductor chip.   The semiconductor device according to claim 1, wherein the high-frequency connection portion is disposed on the outermost peripheral side of the semiconductor chip as viewed from the normal direction. An element portion (17) is further formed on the one surface side of the semiconductor chip,
The element portion is surrounded by the second wall portion (162) as the first wall portion (161) when viewed from the normal direction, and is exposed from the underfill,
The semiconductor device according to claim 1, wherein the second wall portion is formed on the one surface side of the semiconductor chip.   5. The semiconductor device according to claim 1, wherein the wall portion includes a wall-like ground connection portion (152 a) connected to a ground potential among the plurality of connection portions. 6.   The semiconductor device according to claim 1, wherein the wall portion is different from the plurality of connection portions. The substrate further includes a high frequency wiring (33) electrically connected to the high frequency connection portion,
The semiconductor device according to claim 1, wherein the high-frequency wiring is exposed from the underfill.

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