JP2019176523A - Voltage supply circuit - Google Patents

Abstract

To provide a voltage supply circuit that can supply gradient voltage with low noise to a unit pixel cell.SOLUTION: A voltage supply circuit includes: a gradient voltage generation circuit; a first amplifier; a first capacitive element which is connected to the gradient voltage generation circuit and the first amplifier therebetween; and a first feedback circuit for performing negative feedback of output from the first amplifier. The first feedback circuit includes a switch which selectively forms a feedback loop.SELECTED DRAWING: Figure 1

Description

  The present application relates to an imaging apparatus, and more particularly, to an imaging apparatus having a photoelectric conversion unit stacked on a semiconductor substrate.

  Conventionally, digital cameras (digital video cameras or digital still cameras) are used in various fields. In these digital cameras, a CCD (Charge Coupled Device) type solid-state imaging device and a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device are used. As is well known, these solid-state imaging devices have a photodiode formed on a semiconductor substrate as a light receiving portion.

  A multilayer imaging device having a photoelectric conversion film stacked on the outermost surface of a semiconductor substrate is also known as a light receiving unit (for example, Patent Document 1). In a stacked imaging device, charges generated by photoelectric conversion in a photoelectric conversion film are stored in a charge storage region (referred to as “floating diffusion”). The accumulated charge is read out in the semiconductor substrate via a CCD circuit or a CMOS circuit. The stacked imaging device has an advantage that a larger number of pixels can be realized because it is relatively easy to secure the area of the light receiving portion even if the pixel size is reduced. For reference purposes, the entire disclosure of WO 2012/137445 is incorporated herein by reference.

International Publication No. 2012/137445

  In the field of imaging devices, noise reduction is desired.

  According to certain non-limiting exemplary embodiments of the present application, the following is provided.

  A ramp voltage generation circuit, a first amplifier, a first capacitive element connected between the ramp voltage generation circuit and the first amplifier, and a first that negatively feeds back the output of the first amplifier. And a feedback circuit, wherein the first feedback circuit includes a switch that selectively forms a feedback loop.

  According to one aspect of the present disclosure, it is possible to supply a low-noise gradient voltage to a unit pixel cell, and an imaging apparatus that can further reduce the influence of noise is provided.

FIG. 1 is a schematic diagram of an exemplary configuration of an imaging apparatus according to the first embodiment of the present disclosure. FIG. 2 is a diagram illustrating an exemplary circuit configuration of the unit pixel cell 10A. FIG. 3 is a diagram showing a typical example of the connection relationship between the unit pixel cell 10A and the peripheral circuit. FIG. 4 is an exemplary timing chart for explaining the operation in the voltage supply circuit 50A. FIG. 5 is another exemplary timing chart for explaining the operation of the voltage supply circuit 50A. FIG. 6 is an exemplary timing chart for explaining the operation of the imaging apparatus 100 during signal readout. FIG. 7 is a diagram illustrating a circuit configuration of the unit pixel cell 10B. FIG. 8 is a schematic diagram of an exemplary configuration of an imaging apparatus according to the second embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of a circuit configuration applicable as the control circuit 64. FIG. 10 is a diagram illustrating an exemplary circuit configuration of a unit pixel cell 10C according to the third embodiment of the present disclosure. FIG. 11 is an exemplary timing chart for explaining a signal reading operation using the unit pixel cell 10C. FIG. 12 is a diagram illustrating another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 13 is a diagram illustrating still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 14 is a diagram illustrating still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 15 is a diagram illustrating still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. FIG. 16 is a diagram showing an example of circuit configurations of inverting amplifier 62 and amplifier 80 in voltage supply circuit 50E shown in FIG. FIG. 17 is a schematic diagram of another exemplary configuration of the imaging apparatus according to the embodiment of the present disclosure. FIG. 18 is a block diagram illustrating an exemplary configuration of a ramp voltage generation circuit applicable to the voltage supply circuit of the present disclosure. FIG. 19 is a diagram illustrating an example of a circuit configuration of the ramp voltage generation circuit 52. FIG. 20 is a timing chart showing an example of the relationship between the input clocks CK and CKD and each control signal. FIG. 21 is a diagram illustrating an example of a clock generation circuit that generates the control signals Φ1, Φ2, Φ1d, and Φ2d illustrated in FIG. FIG. 22 is a diagram illustrating another example of the circuit configuration of the ramp voltage generation circuit. FIG. 23 is a diagram illustrating an exemplary connection relationship between a unit pixel cell and a peripheral circuit in an imaging device according to the fourth embodiment of the present disclosure. FIG. 24 is a diagram illustrating an exemplary circuit configuration of the unit pixel cell 10D. FIG. 25 is a diagram illustrating a modification of the unit pixel cell according to the fourth embodiment. FIG. 26 is a diagram schematically illustrating a configuration example of a camera system according to the fifth embodiment of the present disclosure.

  Prior to describing embodiments of the present disclosure, the knowledge of the present inventors will be described.

  Patent Document 1 described above discloses a circuit configuration in which a feedback amplifier and a control circuit that controls an input level (gate voltage) for a reset transistor are provided for each column in a pixel array. In this circuit configuration, the reset is executed with the output fed back through the feedback amplifier. Noise appearing at the output is canceled by being fed back to the input.

  Patent Document 1 further proposes that the gate voltage of the reset transistor is linearly reduced at the end of reset in such a circuit configuration. Patent Document 1 describes that by reducing the gate voltage of the reset transistor linearly, a high noise reduction effect can be obtained by limiting the band in the feedback loop.

  However, if noise is included in the input to the reset transistor (here, the linearly decreasing gate voltage) itself, the influence of the noise may affect the pixels and the image quality may deteriorate. Therefore, it is beneficial if the input to the transistor that limits the bandwidth in the feedback loop is low noise.

  The inventor has focused on the above points and has come up with an imaging apparatus according to the present disclosure.

  Hereinafter, an outline of one embodiment of the present disclosure will be described. In the present specification, a voltage having a waveform that generally increases or decreases with the passage of time may be referred to as a “ramp voltage”. The “gradient voltage” in this specification is not limited to a voltage that increases or decreases linearly, but widely includes a voltage having a stepped waveform, a voltage having a waveform that increases or decreases with vibration, and the like. Further, the “waveform” in the present specification is not limited to a shape showing a periodic or quasi-periodic change.

[Item 1]
A unit pixel cell including a photoelectric conversion unit that photoelectrically converts incident light; a signal detection circuit that detects a signal generated by the photoelectric conversion unit; and a voltage supply circuit that supplies a ramp voltage to the unit pixel cell. The supply circuit includes a ramp voltage generation circuit, a first amplifier, a capacitive element connected between the ramp voltage generation circuit and the first amplifier, and a first feedback circuit that negatively feeds back the output of the first amplifier. And the first feedback circuit includes a switch that selectively forms a feedback loop.

  According to the configuration of item 1, it is possible to supply the unit pixel cell with the ramp voltage from which the influence of the input / output offset due to the variation of the threshold voltage in the first amplifier is removed. Therefore, it is possible to reduce the influence of noise due to the variation in threshold voltage in the first amplifier.

[Item 2]
The imaging apparatus according to item 1, further comprising a reset circuit that initializes a signal of the photoelectric conversion unit.

  According to the configuration of item 2, the signal of the photoelectric conversion unit can be initialized.

[Item 3]
Item 3. The imaging device according to Item 2, further comprising a second feedback circuit that negatively feeds back an output of the signal detection circuit, wherein the reset circuit forms part of a feedback loop of the second feedback circuit.

  According to the configuration of item 3, thermal noise can be suppressed.

[Item 4]
4. The imaging device according to item 3, wherein the reset circuit includes a first transistor whose source or drain is connected to the photoelectric conversion unit, and a ramp voltage is applied to a gate of the first transistor.

  According to the configuration of item 4, the noise in the transistor in the unit pixel cell can be suppressed using the ramp voltage. In addition, the number of transistors in the unit pixel cell can be reduced.

[Item 5]
A second feedback circuit that negatively feeds back the output of the signal detection circuit is further provided. The second feedback circuit is a first transistor that forms part of the feedback loop of the second feedback circuit, and a ramp voltage is applied to the gate of the first transistor. The imaging device according to item 2, wherein the reset circuit includes a second transistor whose source or drain is connected to the photoelectric conversion unit.

  According to the configuration of item 5, the noise in the transistor in the unit pixel cell can be suppressed using the ramp voltage. It is also possible to apply an arbitrary voltage as a reference voltage for resetting to the charge storage node.

[Item 6]
6. The imaging according to item 4 or 5, further comprising a control circuit that detects a change in threshold voltage of the first transistor and applies a reference voltage corresponding to the threshold voltage to the non-inverting input terminal of the second amplifier. apparatus.

  According to the configuration of item 6, the initial voltage at the start of application of the ramp voltage can be flexibly changed according to the fluctuation of the threshold voltage of the first transistor. Therefore, it is possible to shorten the time required for noise reduction.

[Item 7]
The imaging device according to any one of items 1 to 6, wherein the first amplifier has a source follower, and an output voltage of the ramp voltage generation circuit is input to the source follower via the capacitive element.

  According to the configuration of item 7, when the switch in the first feedback circuit is turned off, a potential that makes the output voltage of the voltage supply circuit equal to a predetermined voltage can be held in the capacitor element.

[Item 8]
8. The imaging device according to any one of items 1 to 7, wherein the first feedback circuit includes a second amplifier that is an inverting amplifier, and an output of the first amplifier is input to an inverting input terminal of the second amplifier.

  According to the configuration of item 8, the initial voltage at the start of application of the ramp voltage can be set to an arbitrary voltage.

  Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that each of the embodiments described below shows a comprehensive or specific example. Numerical values, shapes, materials, components, arrangement and connection forms of components, steps, order of steps, and the like shown in the following embodiments are merely examples, and are not intended to limit the present disclosure. The various aspects described herein can be combined with each other as long as no contradiction arises. In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements. In the following description, components having substantially the same function are denoted by common reference numerals, and description thereof may be omitted.

(First embodiment)
FIG. 1 schematically illustrates an exemplary configuration of an imaging apparatus according to the first embodiment of the present disclosure. An imaging apparatus 100 illustrated in FIG. 1 includes a pixel array PA and a peripheral circuit. The pixel array PA includes a plurality of unit pixel cells 10A. As will be described later, each of the unit pixel cells 10A includes a photoelectric conversion unit that photoelectrically converts incident light and a signal detection circuit that detects a signal generated by the photoelectric conversion unit. In the illustrated example, the unit pixel cells 10A are arranged in the row direction and the column direction. When the unit pixel cell 10A has a two-dimensional array, a photosensitive region (pixel region) is formed. In this specification, the row direction and the column direction mean directions in which the row and the column extend, respectively, the vertical direction is the column direction, and the horizontal direction is the row direction. The plurality of unit pixel cells 10A may be arranged one-dimensionally. In other words, the imaging device 100 may be a line sensor.

  The imaging apparatus 100 includes a voltage supply circuit 50A and a vertical scanning circuit (also referred to as “row scanning circuit”) 16 connected to the voltage supply circuit 50A. As schematically shown in FIG. 1, the vertical scanning circuit 16 is connected to each of the unit pixel cells 10 </ b> A via a feedback control line 28. The voltage supply circuit 50A and the vertical scanning circuit 16 constitute a part of the peripheral circuit.

  The voltage supply circuit 50A generates a ramp voltage to be supplied to each unit pixel cell 10A. As will be described later, the supply of the ramp voltage to the unit pixel cell 10A is selectively executed through the vertical scanning circuit 16 here. Details of the structure and operation of the voltage supply circuit 50A will be described later.

  In the configuration illustrated in FIG. 1, the voltage supply circuit 50 </ b> A includes a ramp voltage generation circuit 52, a capacitive element 56, and an amplifier 54. The capacitive element 56 is connected between the ramp voltage generation circuit 52 and the amplifier 54. In this specification, “capacitor” means a structure in which a dielectric such as an insulating film is sandwiched between electrodes. The “electrode” in the present specification is not limited to an electrode formed from a metal, and is interpreted to include a polysilicon layer and the like. An “electrode” herein may be a part of a semiconductor substrate.

  The ramp voltage generation circuit 52 converts, for example, an input voltage into a ramp voltage and outputs it. The configuration of the ramp voltage generation circuit 52 is not limited to a specific circuit configuration as long as the ramp voltage can be output. A specific example of the configuration of the ramp voltage generation circuit 52 will be described later. The output voltage (ramp voltage) Vgen of the ramp voltage generation circuit 52 is input to the amplifier 54 via the capacitive element 56. The amplifier 54 is disposed between the ramp voltage generation circuit 52 and the pixel array PA, and buffers the output voltage Vgen of the ramp voltage generation circuit 52. Amplifier 54 typically includes a source follower.

  From the viewpoint of applying a low-noise gradient voltage to each unit pixel cell 10A, it is beneficial that the amplifier 54 as a buffer has low noise. In order to reduce the noise of the buffer, it is effective to reduce the number of transistors that are noise sources and to increase the size of the transistors. When the buffer is arranged in a certain area, the size of the transistor in the buffer can be increased if the number of transistors necessary for the buffer configuration is small. The source follower can be composed of a relatively small number of transistors, and adopting a circuit having the source follower as a buffer is advantageous in terms of reducing noise.

  However, the output voltage of the source follower is shifted from the input voltage by the threshold voltage of the transistor of the source follower. In general, transistor characteristics are not constant due to manufacturing variations. Further, the threshold voltage of the source follower transistor fluctuates under the influence of temperature. If the variation in threshold voltage for each transistor and the influence of fluctuations in threshold voltage can be reduced, it is beneficial because a desired voltage (gradient voltage) can be applied to the unit pixel cell 10A.

  As shown in FIG. 1, the voltage supply circuit 50 </ b> A in the embodiment of the present disclosure includes a feedback circuit 58 that negatively feeds back the output of the amplifier 54. By negatively feeding back the output of the amplifier 54 using the feedback circuit 58, it is possible to reduce the variation in threshold voltage for each transistor of the source follower and the influence of fluctuations in the threshold voltage. In the configuration illustrated in FIG. 1, the feedback circuit 58 includes a switch 60. By switching on / off of the switch 60, a feedback loop can be selectively formed. A typical example of the “switch” in this specification is a switching element such as a field effect transistor (FET).

  In the illustrated example, the feedback circuit 58 includes an inverting amplifier 62. The output of the amplifier 54 is applied to the inverting input terminal of the inverting amplifier 62. On the other hand, a predetermined reference voltage Vsrt is applied to the non-inverting input terminal of the inverting amplifier 62. This reference voltage Vsrt need not be a fixed single voltage. Here, the above-described switch 60 is connected between the output terminal of the inverting amplifier 62 and the input terminal of the amplifier 54. The switch 60 switches whether to input the output Vamp of the inverting amplifier 62 to the amplifier 54. The operation of the inverting amplifier 62 will be described later.

  FIG. 2 shows an exemplary circuit configuration of the unit pixel cell 10A. As illustrated in FIG. 2, the unit pixel cell 10 </ b> A includes a photoelectric conversion unit 15 and a signal detection circuit SC including an amplification transistor 34.

  The photoelectric conversion unit 15 typically includes a photoelectric conversion film 15b stacked on a semiconductor substrate on which the unit pixel cell 10A is formed, a first electrode 15a, and a second electrode (pixel electrode) 15c. The photoelectric conversion film 15b is formed from an organic material or an inorganic material such as amorphous silicon. Note that the “semiconductor substrate” in this specification is not limited to a substrate which is a semiconductor as a whole, and may be an insulating substrate provided with a semiconductor layer on the surface on which a photosensitive region is formed.

  As schematically shown in FIG. 2, the photoelectric conversion film 15b is sandwiched between the first electrode 15a and the second electrode (pixel electrode) 15c. The first electrode 15a is provided on the light receiving surface side of the photoelectric conversion film 15b. The first electrode 15a is formed from a transparent conductive material such as ITO. The second electrode 15c is provided on the side facing the first electrode 15a through the photoelectric conversion film 15b. The second electrode 15c collects charges generated by photoelectric conversion in the photoelectric conversion film 15b. The second electrode 15c is formed of a metal such as aluminum or copper, or polysilicon provided with conductivity by being doped with impurities.

  The first electrode 15 a is connected to the storage control line 17, and the second electrode 15 c is connected to a charge storage node (also referred to as “floating diffusion node”) 44. By controlling the potential of the first electrode 15a via the accumulation control line 17, it is possible to collect either the hole or the electron among the hole-electron pairs generated by the photoelectric conversion by the second electrode 15c. it can. When holes are used as signal charges, the potential of the first electrode 15a may be higher than that of the second electrode 15c. Below, the case where a hole is utilized as a signal charge is illustrated. For example, a voltage of about 10 V is applied to the first electrode 15 a via the accumulation control line 17. As a result, the signal charge is stored in the charge storage node 44. Of course, electrons may be used as signal charges.

  The signal generated by the photoelectric conversion unit 15 is amplified by the amplification transistor 34. The gate of the amplification transistor 34 of the signal detection circuit SC is connected to the charge storage node 44. In other words, the gate of the amplification transistor 34 has an electrical connection with the second electrode 15c. One of the source and the drain of the amplifying transistor 34 (the drain in the case of an N-channel MOS) is connected to the voltage switching circuit 7 via the power supply wiring 22. The voltage switching circuit 7 includes a first switch SW1 and a second switch SW2, and a first voltage source VS1 and a second voltage source VS2. One of the source and the drain of the amplification transistor 34 and the first voltage source VS1 are connected in series via the first switch SW1. One of the source and drain of the amplification transistor 34 and the second voltage source VS2 are connected in series via the second switch SW2. By controlling on / off of each of the first switch SW1 and the second switch SW2, either the first voltage V1 or the second voltage V2 is applied to one of the source and drain of the amplification transistor 34. Can be switched. The first voltage V1 is, for example, 0 V (ground), and the second voltage V2 is, for example, VDD (power supply voltage). The voltage switching circuit 7 may be shared between a plurality of pixels or may be provided for each pixel.

  The other of the source and the drain of the amplification transistor 34 (the source in the case of an N-channel MOS) is connected to the signal read line 18 and the constant current source 6 via the address transistor 40. The signal readout line 18 may be shared between two or more pixels. An address signal line 30 is connected to the gate of the address transistor 40. The state of the address transistor 40 is determined by the potential of the address signal line 30. When the potential of the address signal line 30 is at a high level, the address transistor 40 is turned on, and the source transistor is formed by the address transistor 40, the amplification transistor 34, and the constant current source 6. As a result, a signal corresponding to the charge accumulated in the charge accumulation node 44 is output to the signal readout line 18. When the potential of the address signal line 30 is at a low level, the address transistor 40 is turned off, and the amplification transistor 34 and the signal readout line 18 are electrically separated.

  In the configuration illustrated in FIG. 2, the amplification transistor 34 and the voltage switching circuit 7 constitute the amplifier 2. The address transistor 40 constitutes an output selection unit 5S. The signal of the photoelectric conversion unit 15 in each unit pixel cell 10A is amplified by the amplifier 2 and selectively read out via the output selection unit 5S and the signal readout line 18. The constant current source 6 may be shared between a plurality of pixels or may be provided for each pixel.

  In the configuration illustrated in FIG. 2, the unit pixel cell 10A includes a feedback circuit 48 that negatively feeds back the output of the signal detection circuit SC. A part of the signal amplified by the amplifier 2 is input to the band controller 3SA. The feedback circuit 48 shown in FIG. 2 includes a band control circuit 3 having a feedback transistor 38 and capacitive elements 41 and 42. The band control circuit 3 limits the band of the output signal of the amplifier 2 and outputs it to the charge storage node 44. That is, in the configuration illustrated in FIG. 2, the signal read from the charge storage node 44 is amplified by the amplifier 2, band-limited by the band control circuit 3, and then fed back to the charge storage node 44.

  In the illustrated example, one of the source and the drain of the feedback transistor 38 is connected to the photoelectric conversion unit 15 via the capacitive element 41. The other of the source and drain of the feedback transistor 38 is connected to the side of the source and drain of the amplification transistor 34 that is not connected to the voltage switching circuit 7 and the signal readout line 18 of the source and drain of the address transistor 40. Not connected to the side.

The gate of the feedback transistor 38 is connected to the feedback control line 28. The feedback control line 28 is connected to the voltage supply circuit 50A via the switch SW _i. The switch SW _i is typically provided corresponding to each row of the unit pixel cells 10A. Here, the subscript i is an index for designating the row of the unit pixel cell 10A in the pixel array PA, and the feedback control line 28 and the voltage supply circuit connected to the plurality of unit pixel cells 10A belonging to the i-th row. The switch disposed between the two terminals 50A is denoted as switch SW _i . The switch SW _i is a switching element provided in the vertical scanning circuit 16, for example. When the switch SW _i is turned on, an electrical connection is established between the unit pixel cell 10A in the i-th row and the voltage supply circuit 50A. By turning on the switch SW _i , the output voltage Vout of the voltage supply circuit 50A is applied to the feedback control line 28. That is, by switching on / off the switch SW _i , it is possible to selectively apply the ramp voltage as the band control signal Tpr to the gate of the feedback transistor 38 of the unit pixel cell 10A in the desired row.

The state of the feedback transistor 38 is determined by the potential of the feedback control line 28. Here, when the switch SW _i is on, the feedback control line 28 in the unit pixel cell 10A in the i-th row and the voltage supply circuit 50A are electrically connected. Therefore, it is possible to control the state of the feedback transistor 38 using the output voltage of the voltage supply circuit 50A. When the output voltage of the voltage supply circuit 50A is at a high level, the feedback transistor 38 is turned on. As a result, a feedback loop including the charge storage node 44, the amplification transistor 34, the feedback transistor 38, and the capacitive element 41 is formed. When the output voltage of the voltage supply circuit 50A decreases, the resistance of the feedback transistor 38 increases. When the resistance of the feedback transistor 38 is increased, the band of the feedback transistor 38 is narrowed, and the frequency region of the feedback signal is narrowed. When the feedback loop is formed (it may be said that the feedback transistor 38 is not off), the signal output from the feedback transistor 38 is an attenuation formed by the capacitive element 41 and the parasitic capacitance of the charge storage node 44. Attenuated in the circuit. When the capacitance value of the capacitive element 41 is C1 and the capacitance value of the parasitic capacitance of the charge storage node 44 is Cfd, the attenuation factor B is expressed as B = C1 / (C1 + Cfd). When the output voltage of the voltage supply circuit 50A decreases and reaches a low level, the feedback transistor 38 is turned off. That is, no feedback loop is formed.

  In the configuration illustrated in FIG. 2, one of the source and the drain of the feedback transistor 38 is connected to the charge storage node 44 via the capacitive element 41. The capacitive element 41 disposed between the feedback transistor 38 and the second electrode 15c of the photoelectric conversion unit 15 has a relatively small capacitance value. Hereinafter, a node including a connection point between the feedback transistor 38 and the capacitive element 41 may be referred to as a reset drain node 46. Here, a capacitive element 42 having a larger capacitance value than the capacitive element 41 is connected to the reset drain node 46. Of the electrodes of the capacitive element 42, the electrode not connected to the reset drain node 46 is connected to the sensitivity adjustment line 32 and supplied with a reference voltage VR1 (for example, 0 V). An RC filter circuit is formed from the capacitive element 42 and the feedback transistor 38. Note that the potential of the sensitivity adjustment line 32 does not need to be fixed when the imaging apparatus 100 is in operation. For example, a pulse voltage may be supplied to the sensitivity adjustment line 32. The sensitivity adjustment line 32 can be used for controlling the potential of the charge storage node 44.

  In the configuration illustrated in FIG. 2, the band control unit 3SA includes a reset circuit 4A that initializes the signal of the photoelectric conversion unit 15. The reset circuit 4 </ b> A includes a reset transistor 36 in which one of a source and a drain is connected to the charge storage node 44. The other of the source and the drain of the reset transistor 36 is connected to the reset voltage line 25, and a predetermined voltage VR <b> 2 is applied via the reset voltage line 25. The voltage VR2 is a reference voltage at the time of reset in the configuration illustrated in FIG. As shown in FIG. 2, the gate of the reset transistor 36 is connected to the reset control line 26. The state of the reset transistor 36 is determined by the potential of the reset control line 26. When the potential of the reset control line 26 is at a high level, the reset transistor 36 is turned on and the charge storage node 44 is reset.

  The reset circuit 4A may be provided in each of the unit pixel cells 10A, or may be shared between two or more unit pixel cells 10A. The “reset circuit” in this specification means a portion that includes a switching element that switches application / non-application of a reference voltage in reset to the charge storage node 44 and that has an output connected to the charge storage node 44. The “reset circuit” may include a circuit outside the unit pixel cell as a part thereof.

  Each of amplification transistor 34, reset transistor 36, feedback transistor 38, and address transistor 40 may be an N-channel MOS or a P-channel MOS. It is not necessary that all of these be unified with either the N-channel MOS or the P-channel MOS. In the following description, it is assumed that the transistor is an N-channel MOS unless otherwise specified.

  FIG. 3 shows a typical example of the connection relationship between the unit pixel cell 10A and peripheral circuits. In FIG. 3, four unit pixel cells 10A are shown. However, this is merely an example, and the number of unit pixel cells included in the pixel array PA is not limited to four.

  Each unit pixel cell 10 </ b> A is connected to a power supply line 22 and a reset voltage line 25. A predetermined power supply voltage (here, the first voltage V1 or the second voltage V2) is supplied to the unit pixel cell 10A via the power supply wiring 22. Further, the reference voltage VR2 for reset is supplied via the reset voltage line 25. The reset reference voltage VR2 may be supplied from the vertical scanning circuit 16 to the unit pixel cell 10A via the reset voltage line 25. Each unit pixel cell 10 </ b> A is connected to an accumulation control line 17 that applies a constant voltage to the first electrode 15 a (see FIG. 2) of the photoelectric conversion unit 15. In the illustrated example, a common voltage is applied to each of the unit pixel cells 10A. However, a common voltage need not be applied to all the unit pixel cells 10A. For example, a different voltage may be supplied for each pixel block including several unit pixel cells 10A. By supplying different voltages for each pixel block, the sensitivity of each pixel can be made variable.

  In the configuration illustrated in FIG. 3, each unit pixel cell 10 </ b> A is connected to a reset control line 26, a feedback control line 28, and an address signal line 30. The reset control line 26, the feedback control line 28, and the address signal line 30 are connected to the vertical scanning circuit 16. That is, in the illustrated example, the reset signal for controlling the reset operation, the band control signal (gradient voltage), and the address signal are supplied from the vertical scanning circuit 16 to the unit pixel cell 10A. For example, the vertical scanning circuit 16 applies a predetermined voltage to the address signal line 30 to select the unit pixel cells 10A in units of rows. Thereby, reading of the signal voltage of the selected unit pixel cell 10A and resetting can be executed. In the configuration illustrated in FIG. 3, one voltage supply circuit 50 </ b> A is connected to the vertical scanning circuit 16. However, this is merely an example, and two or more voltage supply circuits may be connected to the vertical scanning circuit 16.

  The unit pixel cell 10A is connected to the signal readout line 18 for each column. A constant current source 19 and a column signal processing circuit (also referred to as “row signal storage circuit”) 20 are connected to the signal readout line 18 corresponding to each column. The column signal processing circuit 20 performs noise suppression signal processing typified by correlated double sampling, analog-digital conversion (A / D conversion), and the like. A horizontal signal readout circuit (also referred to as “column scanning circuit”) 21 is connected to the column signal processing circuit 20 provided corresponding to the column of the unit pixel cells 10A. The horizontal signal reading circuit 21 sequentially reads signals from the column signal processing circuit 20 to the horizontal common signal line 23.

(Operation in voltage supply circuit)
Next, an example of the operation in the voltage supply circuit 50A will be described with reference to FIGS. 1, 2, 4, and 5. FIG. In the embodiment of the present disclosure, a ramp voltage is applied to the gate of the feedback transistor 38 of the unit pixel cell 10A. The voltage supply circuit 50 </ b> A supplies a ramp voltage to be applied to the gate of the feedback transistor 38. Here, a case where the amplifier 54 includes a source follower will be described as an example.

  FIG. 4 shows an exemplary timing chart for explaining the operation of the voltage supply circuit 50A. The graph in FIG. 4 shows, in order from the top, the on / off state of the switch 60, the output voltage Vout of the voltage supply circuit 50A, and the output voltage Vgen of the ramp voltage generation circuit 52. The horizontal axis of each graph indicates time T. As shown in FIG. 4, in this example, the ramp voltage generation circuit 52 generates a constant voltage during a period from time t0 to time t3. Further, the ramp voltage generation circuit 52 generates a voltage that monotonously decreases between time t3 and time t4.

  First, at time t1, the switch 60 is turned on. Thereby, a feedback loop (feedback circuit 58) for negatively feeding back the output of the amplifier 54 is formed.

  As already described, the output voltage of the source follower is shifted with respect to the input voltage by the threshold voltage of the transistor of the source follower. Therefore, when the switch 60 is off in the voltage supply circuit 50A, the output voltage VOUT of the source follower is VOUT = VIN if the input voltage of the source follower and the threshold voltage of the source follower transistor are VIN and VTs, respectively. -VTs. Since the threshold voltage VTs is affected by variations in manufacturing and temperature, the threshold voltage VTs is not constant among individual transistors and varies even in the same transistor. Therefore, in general, the output of the source follower is not uniquely determined.

  However, in the embodiment of the present disclosure, by turning on the switch 60, a feedback loop (feedback circuit 58) that negatively feeds back the output of the amplifier 54 is formed. Since the output of the amplifier 54 is negatively fed back, according to the embodiment of the present disclosure, the variation in the threshold voltage of the transistor of the amplifier 54 (here, the source follower) and the variation in the threshold voltage are canceled. Is possible.

Further, in the configuration illustrated in FIG. 1, the feedback circuit 58 includes an inverting amplifier 62 in the feedback loop. In the illustrated example, the output of the amplifier 54 is connected to the inverting input terminal of the inverting amplifier 62. A connection configuration may be employed in which the output of the switch SW _i (see FIG. 2) is input to the inverting input terminal of the inverting amplifier 62.

  On the other hand, a voltage source (not shown) is connected to the non-inverting input terminal of the inverting amplifier 62, and the voltage Vsrt is applied to the non-inverting input terminal of the inverting amplifier 62. This voltage Vsrt can be arbitrarily set. When the inverting amplifier 62 operates so that the voltage at the inverting input terminal is equal to the voltage at the non-inverting input terminal, after a while from the time t1, the output voltage Vout of the voltage supply circuit 50A is changed to the amplifier 54 (here, the source follower). ) Is equal to the voltage Vsrt regardless of the threshold voltage of the transistor (time t2). At time t2 when the output voltage Vout is sufficiently close to the voltage Vsrt, the switch 60 is turned off.

  Thereafter, at time t3, the ramp voltage generation circuit 52 starts decreasing the output voltage Vgen. At this time, the input voltage of the amplifier 54 changes via the capacitive element 56. As the voltage Vgen decreases, the input voltage Vin (see FIG. 1) of the amplifier 54 also decreases. As the input voltage Vin of the amplifier 54 decreases, the output voltage Vout of the voltage supply circuit 50A decreases.

  What should be noted here is that a capacitor 56 is connected between the ramp voltage generation circuit 52 and the amplifier 54 in the configuration illustrated in FIG. When the switch 60 is off, the capacitive element 56 holds a potential that makes the output voltage Vout of the voltage supply circuit 50A equal to the arbitrarily set voltage Vsrt. Therefore, the output voltage Vout of the voltage supply circuit 50A changes with the voltage Vsrt as a starting point, as shown in FIG. As described above, according to the embodiment of the present disclosure, a voltage at the start of a change that decreases (or increases) the output voltage Vout of the voltage supply circuit 50A (hereinafter, may be referred to as an “initial voltage”) is arbitrarily set. Voltage Vsrt. In other words, the initial voltage at the start of applying the ramp voltage can be determined using the voltage Vsrt.

  As will be described in detail later, in the embodiment of the present disclosure, the potential of the feedback control line 28 is changed so as to cross the threshold voltage of the feedback transistor 38. That is, assuming that the threshold voltage of the feedback transistor 38 and the voltage at the end of the ramp voltage change are VTf and Vend, respectively, the threshold voltage VTf is a voltage between the voltage Vsrt and the voltage Vend. The voltage Vsrt is set. Note that the change in the potential of the feedback control line 28 may be a change from the high level to the low level, or a change from the low level to the high level.

  The threshold voltage of the feedback transistor 38 is affected by variations during manufacturing, similar to the threshold voltage of the transistor of the amplifier 54 (here, the source follower). Therefore, an appropriate initial voltage value may be different for each unit pixel cell 10A. According to the embodiment of the present disclosure, by appropriately setting the voltage Vsrt input to the non-inverting input terminal of the inverting amplifier 62, the initial voltage of the ramp voltage is not added to the ramp voltage generation circuit 52 without adding a special function. Can be set to a voltage corresponding to the threshold voltage of the feedback transistor 38 of each unit pixel cell 10A.

  As described above, according to the embodiment of the present disclosure, it is possible to cancel the influence of the variation in the threshold value of the transistor of the source follower. Therefore, it is possible to supply a low noise gradient voltage to the unit pixel cell 10A. In addition, it is easy to cancel the threshold variation and simultaneously shift the output voltage Vout of the voltage supply circuit 50A to an arbitrary voltage range. Therefore, it is possible to supply a ramp voltage starting from an initial voltage suitable for each unit pixel cell 10A. The time required from time t3 to time t4 shown in FIG. 4 is shortened by setting the range of voltage fluctuation in the ramp voltage to an appropriate range corresponding to the variation in threshold voltage of the feedback transistor 38 in the unit pixel cell 10A. Is possible. Therefore, high-speed noise suppression can be realized.

  Note that the waveform of the ramp voltage is not limited to a waveform in which the voltage decreases. Depending on the application, a ramp voltage that increases the voltage as shown in FIG. 5 may be supplied to the unit pixel cell 10A.

  Next, an exemplary operation of the imaging apparatus 100 at the time of signal reading will be described.

(Operation in imaging device)
FIG. 6 is an exemplary timing chart for explaining the operation of the imaging apparatus 100 during signal readout. In FIG. 6, the horizontal axis of each graph indicates time T. The vertical axis of the graph shown in FIG. 6 indicates the voltage level Vr of the reset control line 26, the voltage level Vf of the feedback control line 28, the voltage level Va of the address signal line 30, and the drain and source of the amplification transistor 34 in order from the top. Of these, the voltage level Vs on the side (typically the drain) connected to the voltage switching circuit 7 is shown. A voltage VTf shown in the graph is a threshold voltage of the feedback transistor 38.

(reset)
First, at time t11, the potential of the address signal line 30 is set to a low level. As a result, the address transistor 40 is turned off, and the amplification transistor 34 and the signal readout line 18 are electrically separated. Further, the potential of the feedback control line 28 is set to the high level, and the feedback transistor 38 is turned on. Thereby, a feedback loop is formed in the unit pixel cell 10A (see FIG. 2). The amplification factor at this time is represented as (−A × B) when the amplification factor of the amplifier 2 is (−A) (“×” represents multiplication). The designer can design the amplification factor so as to be an optimum value for the circuit system. Usually, A is larger than 1 and can be set to a numerical value on the order of several tens to several hundreds. At this time, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned on and off, respectively, and the first voltage V1 (typically GND) is applied to the drain (or source) of the amplification transistor 34. Apply. Further, the potential of the reset control line 26 is set to a high level, and the reset transistor 36 is turned on. By turning on the reset transistor 36, the charge storage node 44 is reset. In other words, the potential of the charge storage node 44 becomes the reference potential VR2 at reset.

(First noise suppression period)
Next, at time t12, the potential of the reset control line 26 is set to low level, and the reset transistor 36 is turned off. As the reset transistor 36 is turned off, kTC noise is generated. However, when the reset transistor 36 is off, a feedback loop with an amplification factor of (−A × B) is formed in the unit pixel cell 10A. Therefore, during the period from time t12 to time t13, the kTC noise of the charge storage node 44 generated when the reset transistor 36 is turned off is suppressed to 1 / (1 + A × B) times. At this time, if the potential of the feedback control line 28 is set so that the operation band of the feedback transistor 38 becomes the first band which is a wide band, the noise can be suppressed at high speed. The first band means a band corresponding to a high level gate potential. Here, since the potential of the feedback control line 28 is set to a high level, noise suppression is fast.

(Second noise suppression period)
Next, during the period from time t13 to time t14, the potential of the feedback control line 28 is changed so that the feedback transistor 38 gradually changes from the on state to the off state. That is, the potential of the feedback control line 28 is gradually lowered from the high level to the low level so as to cross the threshold voltage VTf of the feedback transistor 38. At this time, the potential of the feedback control line 28 is controlled so that the operation band of the feedback transistor 38 becomes a second band narrower than the first band. The second band means a band corresponding to an intermediate level gate potential.

  Here, at time t13, the potential of the feedback control line 28 is lowered to the potential V3 between the high level and the low level. Further, the potential of the feedback control line 28 is continuously lowered to the potential V4 between time t13 and time t14. Here, after the potential of the feedback control line 28 is lowered to the potential V4, the potential of the feedback control line 28 is changed to a low level at time t15. The potential V4 is lower than the potential V3 and higher than the low level. Of course, the potential of the feedback control line 28 may be continuously changed from the high level to the low level.

  It is not necessary for the voltage supply circuit 50A to generate all of the voltage applied to the feedback control line 28 (voltage level Vf shown in FIG. 4). For example, a voltage having a rectangular waveform (for example, a voltage at time t11 to t13 and a voltage at time t14 to t15 shown in FIG. 6) is generated by the vertical scanning circuit 16, and a ramp voltage portion (time t13 to t14 shown in FIG. 6) is generated. May be generated by the voltage supply circuit 50A (see FIG. 1).

  Although the time for sufficiently suppressing noise (time from time t13 to time t14) becomes longer, noise suppression is achieved by setting the second band to a band sufficiently lower than the operating band of the amplification transistor 34. The effect can be improved. However, even if the second band is higher than the operating band of the amplifying transistor 34, the noise suppression effect can be obtained. Therefore, the designer can arbitrarily set the second band according to the allowable time period from time t13 to time t14. To design. In the following description, it is assumed that the second band is a band that is sufficiently lower than the operating band of the amplification transistor 34.

In a state where the second band is lower than the operating band of the amplification transistor 34, the thermal noise generated in the feedback transistor 38 is suppressed to 1 / (1 + A × B) ^1/2 times by the feedback circuit 48. In a state where the second band is lower than the operating band of the amplification transistor 34, the potential of the feedback control line 28 is set to low level at time t15, and the feedback transistor 38 is turned off. When the feedback transistor 38 is off, the kTC noise remaining at the charge storage node 44 is expressed by the square root of the square sum of the kTC noise caused by the reset transistor 36 and the kTC noise caused by the feedback transistor 38.

Further, when the capacitance value of the capacitive element 42 is C2, the kTC noise of the feedback transistor 38 generated in a state where there is no suppression due to feedback is the (Cfd / C2) of the kTC noise of the reset transistor 36 generated in the state where there is no suppression due to feedback. ) ^1/2 times. Considering this point, the kTC noise in the presence of feedback is (1+ (1 + A × B) × (Cfd / (C2 × B ² ))) ^1/2 / (1 + A × in comparison with the case without feedback. B) Doubled.

(Exposure / readout period)
Next, at time t16, the potential of the address signal line 30 is set to the high level, and the address transistor 40 is turned on. Further, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned off and on, respectively, and the second voltage V2 (typically VDD) is applied to the drain (or source) of the amplification transistor 34. . In this state, the amplification transistor 34 and the constant current source 6 form a source follower circuit. The potential of the signal readout line 18 becomes a potential corresponding to the signal charge stored in the charge storage node 44. The amplification factor of the source follower circuit is set to about 1, for example.

  The voltage of the charge storage node 44 at time t16 changes from the reference voltage (voltage VR2) at the reset by an amount corresponding to the electrical signal generated by the photoelectric conversion unit 15 during the period from time t15 to time t16. . The voltage of the charge storage node 44 is amplified by the amplifier 2 (in this example, the amplification factor is about 1) and output to the signal readout line 18 (time t17).

Random noise means fluctuation in output when the electrical signal generated by photoelectric conversion in the photoelectric conversion unit 15 is 0, that is, kTC noise. In the embodiment of the present disclosure, the kTC noise is suppressed to (1+ (1 + A × B) × (Cfd / (C2 × B ² ))) ^1/2 / (1 + A × B) times during the noise suppression period. Furthermore, the amplification factor in the exposure / readout period is about 1. Therefore, a signal in which random noise is suppressed can be read from the signal read line 18. As a result, good image data in which random noise is suppressed can be acquired.

  The circuit configuration of the unit pixel cell is not limited to the configuration shown in FIG. For example, a circuit configuration as shown in FIG. 7 is also applicable. In the unit pixel cell 10B shown in FIG. 7, among the source and drain of the reset transistor 36 in the reset circuit 4B in the band control unit 3SB, the side not connected to the charge storage node 44 is the source and drain of the feedback transistor 38. Are connected to the side not connected to the reset drain node 46.

  In the configuration illustrated in FIG. 7, the output of the amplification transistor 34 is used as a reference voltage at reset. Therefore, the reset voltage line 25 is omitted in the unit pixel cell 10B shown in FIG. According to such a configuration, the change in the voltage of the charge storage node 44 before and after the reset transistor 36 is turned off can be reduced. Therefore, faster noise suppression is possible. The operation timing of each transistor in the configuration illustrated in FIG. 7 can be the same as that of the unit pixel cell 10A.

(Second Embodiment)
FIG. 8 schematically illustrates an exemplary configuration of an imaging apparatus according to the second embodiment of the present disclosure. The difference between the above-described imaging device 100 and the imaging device 200 shown in FIG. 8 is that the imaging device 200 detects a change in threshold voltage of the feedback transistor 38 (see FIG. 2) of the unit pixel cell 10A. 64.

  The control circuit 64 has an electrical connection with a transistor that is a detection target of a variation in threshold voltage. The transistor that is the detection target of the threshold voltage fluctuation is typically a dummy pixel transistor provided on the substrate on which the pixel array PA is formed. When it is considered that the variation between the transistors on the same substrate is small, the threshold voltage of the dummy transistor can be regarded as the threshold voltage of the feedback transistor 38 of the unit pixel cell 10A included in the pixel array PA. it can.

  The control circuit 64 detects a change in the threshold voltage of the feedback transistor 38 and generates a voltage Vsrt corresponding to the change in the threshold voltage of the feedback transistor 38. As shown in FIG. 8, the control circuit 64 is connected to the non-inverting input terminal of the inverting amplifier 64. The control circuit 64 applies a reference voltage corresponding to the fluctuation of the threshold voltage of the feedback transistor 38 to the non-inverting input terminal of the inverting amplifier 64.

  FIG. 9 shows an example of a circuit configuration applicable as the control circuit 64. In the circuit shown in FIG. 9, a source follower is formed using the detection target transistor 68. A constant current source 66 is connected to the drain of the transistor 68, and the source potential is fixed. In the configuration illustrated in FIG. 9, a feedback amplifier 65 is connected to the source of the transistor 68. The output of this source follower is taken out through a buffer 67.

  The specific configuration of the control circuit 64 is not limited to the configuration shown in FIG. Various known circuits can be applied as the control circuit 64. A circuit configuration for monitoring a threshold voltage of a transistor and generating a voltage according to a detection result is well known. For example, Japanese Patent Application Laid-Open Nos. 2010-152959 and 2011-55459 disclose such circuits. For reference, the entire contents disclosed in Japanese Patent Application Laid-Open Nos. 2010-152959 and 2011-55459 are incorporated herein by reference.

  As already described with reference to FIG. 4 and the like, according to the circuit configuration illustrated in FIG. 1, the initial voltage in the ramp voltage output from the voltage supply circuit 50A is applied to the non-inverting input terminal of the inverting amplifier 64. It can be determined by the voltage. That is, by applying the voltage Vsrt corresponding to the fluctuation of the threshold voltage of the feedback transistor 38 to the non-inverting input terminal of the inverting amplifier 64, the initial voltage in the ramp voltage can be shifted to the voltage Vsrt. In the configuration illustrated in FIG. 8, the voltage Vsrt generated by the control circuit 64 configured to detect the fluctuation of the threshold voltage of the feedback transistor 38 is used as the voltage applied to the non-inverting input terminal of the inverting amplifier 64. Used. Therefore, the voltage variation in the ramp voltage can be shifted to an appropriate range according to the variation in the threshold voltage of the feedback transistor 38.

  In this example, the ramp voltage has a waveform starting from an initial voltage that reflects fluctuations in the threshold voltage of the feedback transistor 38. As a result, it is possible to more reliably supply a gradient voltage across the threshold voltage of the feedback transistor 38 to the unit pixel cell 10A. In addition, the voltage sweep time can be shortened. As described above, according to the embodiment of the present disclosure, it is possible to cancel the variation in threshold voltage of the amplifier 54 itself as a buffer and to shift the ramp voltage in accordance with the threshold voltage of the feedback transistor 38. It is.

(Third embodiment)
FIG. 10 illustrates an exemplary circuit configuration of a unit pixel cell 10C according to the third embodiment of the present disclosure. The feedback circuit 49 shown in FIG. 10 negatively feeds back the output of the signal detection circuit SC, similarly to the feedback circuit 48 described with reference to FIG. The feedback circuit 49 includes a band control circuit 3 </ b> C having a feedback transistor 38. The band control circuit 3C band-limits the output signal of the amplifier 2 and outputs it to the charge storage node 44. In the configuration illustrated in FIG. 10, the reset circuit 4 </ b> C in the band control unit 3 </ b> SC is provided in the feedback loop of the feedback circuit 49. The reset circuit 4C includes a feedback transistor 38. The feedback transistor 38 is connected between the output of the amplification transistor 34 and the charge storage node 44. In this example, one of the source and the drain of the feedback transistor 38 is connected to the photoelectric conversion unit 15 without passing through a capacitive element. The feedback transistor 38 forms part of a feedback loop.

  In the configuration illustrated in FIG. 10, the feedback transistor 38 forms a part of the reset circuit 4 </ b> C that initializes the signal of the photoelectric conversion unit 15, and application / non-application of the reference voltage at the reset to the charge storage node 44. Functions as a switching element for switching between. That is, in the configuration illustrated in FIG. 10, the feedback transistor 38 also has a function of the reset transistor 36 in the unit pixel cell 10A illustrated in FIG. 2 and the unit pixel cell 10B illustrated in FIG. According to the circuit configuration illustrated in FIG. 10, the number of transistors in the unit pixel cell can be reduced as compared with the unit pixel cell 10A illustrated in FIG. 2 and the unit pixel cell 10B illustrated in FIG.

  FIG. 11 is an exemplary timing chart for explaining a signal reading operation using the unit pixel cell 10C. In FIG. 11, the horizontal axis of each graph indicates time T. The vertical axis of the graph shown in FIG. 11 is connected to the voltage switching circuit 7 among the voltage level Vf of the feedback control line 28, the voltage level Va of the address signal line 30, and the drain and source of the amplification transistor 34 in order from the top. The voltage level Vs on the connected side (typically the drain) is shown respectively. A voltage VTf shown in the graph is a threshold voltage of the feedback transistor 38. Hereinafter, an outline of the signal reading operation will be described with reference to FIG.

(reset)
First, at time t11, the potential of the address signal line 30 is set to low level, and the address transistor 40 is turned off. Further, the potential of the feedback control line 28 is set to the high level, and the feedback transistor 38 is turned on. At this time, the first switch SW1 and the second switch SW2 of the voltage switching circuit 20 are turned on and off, respectively, and the first voltage V1 (typically GND) is applied to the drain (or source) of the amplification transistor 34. To do. With these operations, the charge storage node 44 is reset. The reference voltage at the reset is the output of the amplification transistor 34. The operation band of the feedback transistor 38 at this time is the first band.

(Noise suppression period)
Next, during the period from time t13 to time t14, the potential of the feedback control line 28 is changed so that the feedback transistor 38 gradually changes from the on state to the off state. That is, the potential of the feedback control line 28 is changed from the high level to the low level so as to cross the threshold voltage VTf of the feedback transistor 38. At this time, the potential of the feedback control line 28 is controlled so that the operation band of the feedback transistor 38 becomes a second band narrower than the first band. Here, at time t13, the potential of the feedback control line 28 is lowered to the potential V3 between the high level and the low level. Further, the potential of the feedback control line 28 is continuously lowered to the potential V4 between time t13 and time t14. Here, after the potential of the feedback control line 28 is lowered to the potential V4, the potential of the feedback control line 28 is changed to a low level at time t15. The potential V4 is lower than the potential V3 and higher than the low level. Of course, the potential of the feedback control line 28 may be continuously changed from the high level to the low level.

In a state where the second band is lower than the operating band of the amplification transistor 34, the thermal noise generated in the feedback transistor 38 is suppressed to 1 / (1 + A) ^1/2 times by the feedback circuit 49. When the potential of the feedback control line 28 is set to a low level at time t15 and the feedback transistor 38 is turned off in a state where the second band is lower than the operating band of the amplification transistor 34, the kTC noise remaining in the charge storage node 44 is also fed back. Compared with the case where there is no, 1 / (1 + A) ^1/2 times.

(Exposure / readout period)
Next, at time t16, the potential of the address signal line 30 is set to the high level, and the address transistor 40 is turned on. Further, the first switch SW1 and the second switch SW2 of the voltage switching circuit 7 are turned off and on, respectively, and the second voltage V2 (typically VDD) is applied to the drain (or source) of the amplification transistor 34. . In this state, the amplification transistor 34 and the constant current source 6 form a source follower circuit. The potential of the signal readout line 18 becomes a potential corresponding to the signal charge stored in the charge storage node 44. The amplification factor of the source follower circuit is set to about 1, for example. The voltage of the charge storage node 44 is amplified by the amplifier 2 (in this example, the amplification factor is about 1) and output to the signal readout line 18 (time t17).

(Other modifications)
Hereinafter, other modifications will be described with reference to the drawings.

  FIG. 12 illustrates another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. A voltage supply circuit 50B illustrated in FIG. 12 includes a capacitive element 70 connected to a node including a connection point between the capacitive element 56 and the input of the amplifier 54. Of the electrodes of the capacitive element 70, the potential of the electrode not connected to the input of the amplifier 54 is fixed.

  In such a circuit configuration, the potential (Vin) of the node including the connection point between the capacitive element 56 and the input of the amplifier 54 is inclined if the capacitance values of the capacitive element 56 and the capacitive element 70 are C3 and C4, respectively. This is (C3 / (C3 + C4)) times the potential at the output of the voltage generation circuit 52. Since C3 / (C3 + C4) <1, the noise included in the output of the ramp voltage generation circuit 52 can be reduced at a ratio of (C3 / (C3 + C4)). In this way, the noise included in the output of the ramp voltage generation circuit 52 is reduced by connecting the capacitive element 70 whose potential at one end is fixed to the node including the connection point between the capacitive element 56 and the input of the amplifier 54. It is possible.

  FIG. 13 illustrates still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. A voltage supply circuit 50C illustrated in FIG. 13 includes an amplifier 54S configured as a so-called super source follower.

  The amplifier 54S shown in FIG. 13 includes an input transistor 55, a PMOS current source 57P including a P channel MOS transistor, an NMOS current source 57N including an N channel MOS transistor, and a feedback transistor 59. The input voltage of the amplifier 54S is applied to the gate of the input transistor 55. The source (or drain) of the PMOS current source 57P is connected to the power supply, and the drain (or source) of the PMOS current source 57P is connected to the drain (or source) of the input transistor. The source (or drain) of the input transistor is connected to the drain (or source) of the NMOS current source 57N, and the source (or drain) of the NMOS current source 57N is grounded. The source (or drain) of the feedback transistor 59 is connected to the power supply, and the drain (or source) of the feedback transistor 59 is connected to the connection point between the input transistor 55 and the NMOS current source 57N. The gate of the feedback transistor 59 is connected to the connection point between the PMOS current source 57P and the input transistor 55.

  In such a configuration, the loop formed by the feedback transistor 59 acts to suppress output fluctuation. Therefore, the amount of output current is controlled according to the output voltage. Further, an output impedance reduction effect of the amplifier 54S can be obtained.

  FIG. 14 shows still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. A feedback circuit 58D in the voltage supply circuit 50D shown in FIG. 14 has a switch 61 connected between the output of the amplifier 54 and the inverting input of the inverting amplifier 62. Further, the feedback circuit 58D includes capacitive elements 71 and 72 whose potential at one end is fixed. Of the two electrodes of the capacitive element 71, the electrode that is not grounded is connected between the output of the amplifier 54 and the inverting input of the inverting amplifier 62. Of the two electrodes of the capacitive element 72, the electrode that is not grounded is connected between the output of the inverting amplifier 62 and the input of the amplifier 54.

  As can be understood from the operation described with reference to FIG. 4 and the like, in the embodiment of the present disclosure, the ramp voltage is sequentially supplied to the unit pixel cells. That is, every time the unit pixel cell to which the ramp voltage is supplied is switched, the switch 60 is turned on / off, and the formation / release of the feedback loop is repeated. As can be seen from the graph of the output voltage Vout in FIG. 4, the output voltage after supplying the ramp voltage to a certain unit pixel cell is the voltage Vend. Next, when a ramp voltage is supplied to some other unit pixel cell, the output voltage rises again from the voltage Vend to the voltage Vsrt by forming a feedback loop. That is, when the switch 60 returns from OFF to ON, the output voltage Vout varies greatly in the process of reconstructing the feedback loop.

  In the configuration illustrated in FIG. 14, the capacitive element 71 holds the voltage at the inverting input terminal of the inverting amplifier 62 before the switch 61 is turned off. The capacitive element 72 holds the voltage at the output terminal of the inverting amplifier 62 before the switch 61 is turned off. With this operation, even when the feedback loop is not formed, it is possible to hold the information on the potentials on the input side and the output side of the inverting amplifier 62 in the state where the feedback loop is formed. Therefore, the starting point of the voltage change when the feedback loop is formed can be a voltage close to the voltage Vsrt. As a result, it is possible to suppress large fluctuations in the output voltage when the feedback loop is formed again after the feedback loop is released. In addition, high-speed convergence can be realized.

  FIG. 15 illustrates still another exemplary circuit configuration of the voltage supply circuit according to the embodiment of the present disclosure. The feedback circuit 58E in the voltage supply circuit 50E shown in FIG. 15 has an amplifier 80 connected between the output of the inverting amplifier 62 and the input of the amplifier 54. The amplifier 80 is connected between the inverting amplifier 62 and the switch 60.

  FIG. 16 shows an example of the circuit configuration of the inverting amplifier 62 and the amplifier 80 in the voltage supply circuit 50E shown in FIG. In the configuration illustrated in FIG. 16, the inverting amplifier 62 includes a transistor 73, input transistors 74 and 75, transistors 76 and 77, and current source transistors 78 and 79. The gate of the input transistor 74 is connected to the inverting input terminal 62n. A transistor 76 is connected to the drain of the input transistor 74, and a current source transistor 78 is cascode-connected to the transistor 76. The gate of the input transistor 75 is connected to the non-inverting input terminal 62p. A transistor 77 is connected to the drain of the input transistor 75, and a current source transistor 79 is cascode-connected to the transistor 77. The transistor 73 forms a so-called tail current source and supplies a current used for the operation of the transistors 74 to 79. A mirror primary transistor 82, a current source transistor 83, and a diode connection transistor 84 are connected between the positive power supply terminal and the negative power supply terminal of the inverting amplifier 62.

  In the configuration illustrated in FIG. 16, the transistor 76 and the current source transistor 78 are cascode-connected, and the transistor 77 and the current source transistor 79 are cascode-connected. Therefore, compared with the case where such a cascade connection is not provided, even when the potential difference between the connection point of the input transistor 74 and the transistor 76 and the connection point of the input transistor 75 and the transistor 77 is large, the inverting input is performed. The current distributed to the non-inverting input side is kept from becoming unbalanced. That is, the occurrence of systematic offset in the inverting amplifier 62 can be suppressed.

  However, in such a circuit configuration, the transistor 76 and the current source transistor 78 are cascode-connected, and the transistor 77 and the current source transistor 79 are cascode-connected, so that the voltage range at the output (Vamp1) of the inverting amplifier 62 Is difficult to increase.

  In the configuration illustrated in FIGS. 15 and 16, an amplifier 80 is connected to the output side of the inverting amplifier 62. An amplifier 80 shown in FIG. 16 has an amplifier input transistor 85 and a current source transistor 86. The output Vamp1 of the inverting amplifier 62 is applied to the gate of the amplifier input transistor 85 via the connection line 89. A current source transistor 86 is connected to the amplifier input transistor 85. In this example, a resistor 87 and a capacitive element 88 (not shown in FIG. 15) are connected in series between the inverting amplifier 62 and the amplifier 80.

  Thus, by providing the amplifier 80 having gain on the output side of the inverting amplifier 62, the amplitude at the output Vamp2 of the amplifier 80 can be expanded even if the output of the inverting amplifier 62 is small. 15 and FIG. 16, the input offset of the inverting amplifier 62 can be suppressed to set the input of the amplifier 54 with high accuracy, and the voltage range at the input of the amplifier 54 can be expanded.

  FIG. 17 illustrates an outline of another exemplary configuration of the imaging apparatus according to the embodiment of the present disclosure. An imaging apparatus 300 illustrated in FIG. 17 includes two voltage supply circuits 50Fa and 50Fb. The voltage supply circuit 50Fa includes a ramp voltage generation circuit 52a, a capacitive element 56a, a switch 60a, an inverting amplification circuit 62a, an amplifier 54a, and a capacitive element 90a. The voltage supply circuit 50Fb has a configuration similar to that of the voltage supply circuit 50Fa. The voltage supply circuit 50Fb includes a ramp voltage generation circuit 52b, a capacitive element 56b, a switch 60b, an inverting amplification circuit 62b, an amplifier 54b, and a capacitive element 90b. Voltage supply circuits 50Fa and 50Fb are electrically connected to each other through capacitive elements 90a and 90b.

As illustrated in FIG. 17, two or more voltage supply circuits may be provided in the imaging apparatus. As described with reference to FIGS. 2 and 3, the ramp voltage generated by the voltage supply circuit passes through the switch SW _i in the vertical scanning circuit 16 and the gate of the feedback transistor 38 of the selected unit pixel cell. To be applied. The number of unit pixel cells included in the pixel array PA may be several thousand. In such a case, the voltage applied to the unit pixel cell far from the voltage supply circuit may be delayed compared to the unit pixel cell close to the voltage supply circuit due to the difference in wiring length. .

In the configuration illustrated in FIG. 17, the output voltage Vouta (here, the ramp voltage) of the voltage supply circuit 50Fa and the output voltage Voutb (here, the ramp voltage) of the voltage supply circuit 50Fb are both applied to the common signal line 24. The voltage applied to the common signal line 24 is supplied to the unit pixel cell 10A belonging to the row corresponding to each switch via the switch SW _i in the vertical scanning circuit 16. Thereby, the influence of the voltage drop resulting from the difference in the wiring length between the voltage supply circuit and the unit pixel cell can be suppressed.

  However, if a plurality of voltage supply circuits are simply provided, variations due to the difference in characteristics between the ramp voltage generation circuits occur between the ramp voltages. In the illustrated example, one of the electrodes of the capacitive element 90a is connected to a node where the capacitive element 56a of the voltage supply circuit 50Fa and the amplifier 54a are connected, and the other is connected to the ramp voltage generation circuit 52b of the voltage supply circuit 50Fb and the capacitance. The node is connected to the node to which the element 56b is connected. One of the electrodes of the capacitive element 90b is connected to a node to which the capacitive element 56b of the voltage supply circuit 50Fb and the amplifier 54b are connected, and the other is connected to the ramp voltage generation circuit 52a of the voltage supply circuit 50Fa and the capacitive element. 56a is connected to the connected node. Therefore, the variation between the ramp voltage (Vgena) generated by the ramp voltage generation circuit 52a and the ramp voltage (Vgenb) generated by the ramp voltage generation circuit 52b can be averaged. Furthermore, the noise included in the ramp voltage generated by the ramp voltage generation circuit 52a and the noise included in the ramp voltage generated by the ramp voltage generation circuit 52b are also averaged according to the capacitance ratio.

  With the configuration illustrated in FIG. 17, it is possible to supply a low-noise ramp voltage to each unit pixel cell while suppressing variations in the ramp voltage between the plurality of ramp voltage generation circuits.

  Next, the details of the configuration of the ramp voltage generation circuit applicable to the voltage supply circuit of the present disclosure will be described with reference to FIGS.

  As described with reference to FIGS. 4 and 5, in the embodiment of the present disclosure, a voltage having a waveform that monotonously decreases (or increases) is generated by the ramp voltage generation circuit 52 (see, for example, FIG. 1). (See the graph of the output voltage Vgen shown in FIGS. 4 and 5). When generating a voltage having a waveform that decreases monotonously (or increases), it is common to perform filtering after generating a voltage having a stepped waveform. In the generation of a voltage having a stepped waveform, it is beneficial that the number of bits in the digital / analog conversion circuit is large. However, it may be difficult to increase the number of bits due to the limitation of the area of the substrate (semiconductor substrate). When a digital / analog conversion circuit with a small number of bits is used, high-frequency noise (hereinafter referred to as “spike noise”) may occur near the point where switching is performed. It is difficult to remove spike noise by filtering.

  In the example described below, a plurality of sample / hold circuits are provided in the ramp voltage generation circuit, and spike noise is removed using these sample / hold circuits. The bit accuracy is improved by inputting the output from which the spike noise has been removed to the smoothing circuit.

  FIG. 18 schematically illustrates an exemplary configuration of a ramp voltage generation circuit applicable to the voltage supply circuit of the present disclosure. In the configuration illustrated in FIG. 18, the ramp voltage generation circuit 52 includes a digital / analog conversion circuit 92 (D / A conversion circuit 92) and sample / hold circuits 94a and 94b (first S / H circuit 94a and second S / H circuit 94b) and a smoothing circuit 96. In the configuration illustrated in FIG. 18, the output Dout of the D / A conversion circuit 92 is input to each of the two S / H circuits 94a and 94b. The outputs SHout of the two S / H circuits 94 a and 94 b are input to the smoothing circuit 96, and the output of the smoothing circuit 96 is output outside the ramp voltage generation circuit 52. The output of the smoothing circuit 96 (the voltage generated by the ramp voltage generation circuit 52) is input to the amplifier 54 in the feedback circuit 58 via the capacitive element 56 and output to the unit pixel cell 10A (see FIG. 1). ). Hereinafter, a circuit block provided between the ramp voltage generation circuit 52 and the vertical scanning circuit 16 may be referred to as a ramp voltage output unit.

  FIG. 19 shows an example of the circuit configuration of the ramp voltage generation circuit 52. In the configuration illustrated in FIG. 19, the ramp voltage generation circuit 52 includes a polarity switching circuit 91, a D / A conversion circuit 92, a first S / H circuit 94a and a second S / H circuit 94b, and smoothing. A circuit 96 and a ramp voltage output unit 98 are included. In the illustrated example, the ramp voltage output unit 98 includes a capacitive element 56, a feedback circuit including an amplifier 54, an inverting amplifier 62, and a switch 60, and a capacitive element 70 whose potential at one end is fixed. That is, here, the voltage supply circuit 50B shown in FIG. 12 will be described as an example.

  In the configuration illustrated in FIG. 19, the D / A conversion circuit 92 is a bilinear switched capacitor integrator. However, this is merely an example, and the D / A conversion circuit 92 is not limited to a bilinear switched capacitor integrator. The D / A conversion circuit 92 includes switches SW8 to SW17, capacitive elements C7 to C10, and an integrating amplifier 99. One of the top voltage VTOP and the bottom voltage VBTM is applied to the first node N1, and the other of the top voltage VTOP and the bottom voltage VBTM is applied to the second node N2. The top voltage VTOP and the bottom voltage VBTM are sampled into the capacitive element C7 and the capacitive element C8 by a so-called crawl type switched capacitor operation, and transferred to the integrating capacitive element C10.

  Switches SW8 and SW9 are used for the sampling operation to the capacitive element C7. Switches SW12 and SW13 are used for sampling to the capacitive element C8. Switches SW10 and SW11 are used for the transfer from the capacitive element C7 to the integrating capacitive element C10 and the reset operation. Switches SW14 and SW15 are used for the transfer from the capacitive element C8 to the integrating capacitive element C10 and the reset operation. Note that “Φ1” and “Φ2” in FIG. 19 indicate control signals of the switches SW8 to SW15. The integration capacitor element C10 is initialized by applying a control signal Φini1 to the switch SW17. The operating point of the integrating amplifier 99 is set by sampling the common voltage VCM into the capacitive element C9 via the switch SW16. When the ramp voltage is generated, the propagation of noise superimposed on the common voltage VCM can be cut off by turning off the switch SW16.

  In the configuration illustrated in FIG. 19, a polarity switching circuit 91 is provided between the input terminal for the top voltage VTOP and the input terminal for the bottom voltage VBTM, and the D / A conversion circuit 92. The polarity switching circuit 91 has four switches SW4 to SW7. The switches SW4 and SW5 are not turned on at the same time, and when one is on, the other is off. Similarly, the switches SW6 and SW7 are not turned on at the same time, and when one is on, the other is off. Therefore, the top voltage VTOP can be applied to one of the first node and the second node N2, and the bottom voltage VBTM can be applied to the other of the first node N1 and the second node N2. Both the top voltage VTOP and the bottom voltage VBTM are not simultaneously applied to the first node N1, and both the top voltage VTOP and the bottom voltage VBTM are not simultaneously applied to the second node N2.

  By switching on and off in each of the switches SW4 to SW7, it is possible to switch whether the top voltage VTOP and the bottom voltage VBTM are applied to the first node N1 or the second node N2. By providing the polarity switching circuit 91, the generation of the descending voltage Vgen as shown in FIG. 4 and the generation of the ascending voltage Vgen as shown in FIG. 5 can be realized with a simple configuration.

  In the configuration illustrated in FIG. 19, the first S / H circuit 94a includes switches SW18 and SW19, resistors R2 to R4, and a hold capacitive element C11. Second S / H circuit 94b includes switches SW20 and SW21, resistors R5 to R7, and a hold capacitive element C12. It is beneficial to perform the layout so that the characteristics are substantially the same between the first S / H circuit 94a and the second S / H circuit 94b. In the illustrated example, the first S / H circuit 94 a and the second S / H circuit 94 b are arranged symmetrically with respect to the smoothing circuit 96. The number of S / H circuits connected to the output side of the D / A conversion circuit 92 may be three or more.

  “Φ1d” and “Φ2d” in FIG. 19 indicate control signals of the switches SW18 to SW21. The sample / hold operation will be described focusing on the first S / H circuit 94a. By controlling the switch SW18 using the control signal Φ1d, the output of the D / A conversion circuit 92 is passed through the resistor R2 to the node SHA having a connection with the hold capacitive element C11 at a timing that avoids spike noise. And sample. Thereafter, using the control signal Φ2d, the output is transferred to the midpoint node VMID of the smoothing circuit 96 via the switch SW19 and the resistor R4.

  In the illustrated example, the smoothing circuit 96 includes capacitive elements C13 and C14 and resistors R8 and R9. The midpoint node VMID of the smoothing circuit 96 is initialized to the reference potential Vini in advance. The midpoint node VMID is initialized by applying the control signal Φini2 to the switch SW22. The reference potential Vini is held in the capacitive element C13 through the switch SW22. The potential at the midpoint node VMID changes depending on the charge held in the capacitor C13, the output of the first S / H circuit 94a, and the output of the second S / H circuit 94b. The ramp voltage generation circuit 52 outputs a voltage smoothed by the resistors R8 and R9 and the capacitive element C14. According to the configuration as shown in FIG. 19, smoothing can also be performed in the sampling period, so that output delay can be reduced.

  FIG. 20 is a timing chart showing an example of the relationship between the input clocks CK and CKD and each control signal. In FIG. 20, the horizontal axis of each graph indicates time T. In FIG. 20, in order from the top, input clock CK, input clock CKD, control signal Φ1, control signal Φ2, output Dout of D / A conversion circuit 92, control signal Φ1d, control signal Φ2d, first S / H circuit 94a The potential of the node SHA, the potential of the node SHB of the second S / H circuit 94b (see FIG. 19), and the output voltage Vgen of the ramp voltage generation circuit 52 are shown. In FIG. 20, the potential of the node SHA is indicated by a solid line LA, and the potential of the node SHB is indicated by a broken line LB.

  The input clock CKD is a signal shifted by, for example, several nanoseconds with respect to the input clock CK. The control signals Φ1, Φ2, Φ1d, and Φ2d are generated using the input clock CK and the input clock CKD.

  FIG. 21 shows an example of a clock generation circuit that generates the control signals Φ1, Φ2, Φ1d, and Φ2d shown in FIG. The clock generation circuit 160 illustrated in FIG. 21 includes a plurality of logic gates 135 to 152.

  The D / A conversion circuit 92 operates based on the control signals Φ1 and Φ2 generated from the input clocks CK and CKD, and outputs a staircase waveform (output Dout in FIG. 20). The output Dout includes spike noise in the vicinity of the step. The output Dout is sampled avoiding spike noise by using the control signals Φ1d and Φ2d. The first S / H circuit 94a and the second S / H circuit 94b output waveforms LA and LB as shown in FIG. These two waveforms are superimposed and smoothed at the midpoint node VMID in the smoothing circuit 96. In this way, the first S / H circuit 94a, the second S / H circuit 94b, and the smoothing circuit 96 generate a ramp voltage having a substantially smooth slope from the step-like output Dout. And output from the ramp voltage generation circuit 52. According to the configuration illustrated in FIG. 19, it is possible to achieve a reduction in noise of the ramp voltage generation circuit 52 and an accuracy higher than the bit accuracy of the D / A conversion circuit 92.

  FIG. 22 shows another example of the circuit configuration of the ramp voltage generation circuit. The difference between the ramp voltage generation circuit 52B shown in FIG. 22 and the ramp voltage generation circuit 52 shown in FIG. 19 is that the ramp voltage generation circuit 52B replaces the resistors R3, R4, R6 and R7 with transistors 154 to 157. It is to have. In the configuration illustrated in FIG. 19, a control circuit 153 is connected to the gates of the transistors 154 to 157. The control circuit 153 generates a gate voltage supplied to the transistors 154 to 157.

  In the configuration illustrated in FIG. 22, P-channel MOS transistors are used as the transistors 154 to 157. In this example, a P-channel MOS transistor is used as a resistor whose resistance is variable. That is, in this example, the source-drain voltage dependency in the linear region of the MOS transistor is used. According to the configuration illustrated in FIG. 22, the resistances of the transistors 154 to 157 can be changed by adjusting the gate voltage supplied from the control circuit 153. By changing the gate voltage supplied from the control circuit 153, the time constant in the first S / H circuit 94a and the time constant in the second S / H circuit 94b can be changed to active. is there.

  As shown in FIG. 20, the graph showing the potential of the node SHA and the graph showing the potential of the node SHB generally show a curve-like change at the rise and fall of the voltage. This is because the current flowing through the switch SW19 of the first S / H circuit 94a and the current flowing through the switch SW21 of the second S / H circuit 94b vary depending on the potential difference across the resistor in the averaging transient state. Due to

  In this example, the transistor 154 uses a voltage that adjusts the time constant according to the gradient of the ramp voltage as the gate voltage so that the current flowing through the switch SW19 and the current flowing through the switch SW21 are constant even in the transient state of averaging. Apply to ~ 157. Thereby, it is possible to obtain an appropriate time constant according to the gradient of the ramp voltage.

  An N channel MOS transistor may be used instead of the P channel MOS transistor. In the illustrated example, the voltages applied to the gates of the transistors 154 to 157 may be different from each other, or a common voltage is selectively applied to some of the transistors 154 to 157. May be. As the gate voltage, a ramp voltage generated using the output of the ramp voltage generation circuit or the like may be applied.

(Fourth embodiment)
FIG. 23 illustrates an exemplary connection relationship between unit pixel cells and peripheral circuits in an imaging apparatus according to the fourth embodiment of the present disclosure. An imaging apparatus 400 illustrated in FIG. 23 includes a voltage supply circuit 50A and a pixel array PA connected to the voltage supply circuit 50A via the vertical scanning circuit 16. In the configuration illustrated in FIG. 23, the pixel array PA includes four unit pixel cells 10D. Of course, the number of unit pixel cells 10D included in the pixel array PA is not limited to four. Instead of the voltage supply circuit 50A, any of the voltage supply circuits 50B to 50E described above or a set of the voltage supply circuits 50Fa and 50Fb may be used.

  The imaging apparatus 400 includes a vertical scanning circuit 16, a load circuit 27, a column signal processing circuit 20, a horizontal signal readout circuit 21, and an inverting amplifier 29 as peripheral circuits. The column signal processing circuit 20, the load circuit 27, and the inverting amplifier 29 are arranged for each column of the unit pixel cells 10D that are two-dimensionally arranged. The negative input terminal of the inverting amplifier 29 is connected to the corresponding signal readout line 18. A predetermined voltage (for example, 1 V or a positive voltage near 1 V) Vref is supplied to the positive input terminal of the inverting amplifier 29. This voltage Vref is used as a reference voltage for reset. An output terminal of the inverting amplifier 29 is connected to a plurality of unit pixel cells 10D having a connection with a negative input terminal of the inverting amplifier 29 via a feedback line 31 provided corresponding to each column. .

  In the configuration illustrated in FIG. 23, the feedback control line 28 is connected to the vertical scanning circuit 16. As will be described later, when the vertical scanning circuit 16 applies a predetermined voltage to the feedback control line 28, a feedback loop for negatively feeding back the output of the unit pixel cell 10D is formed. The inverting amplifier 29 constitutes a part of a feedback circuit that negatively feeds back the output from the unit pixel cell 10D. The inverting amplifier 29 may be called a feedback amplifier. The inverting amplifier 29 may have a gain adjustment terminal 29a for changing the inverting amplification gain. The gain of the inverting amplifier 29 changes according to the potential of the gain adjustment terminal 29a. Since the product of the gain G and the band B is constant in the inverting amplifier 29, for example, when the gain G is decreased, the band B becomes wider (the cut-off frequency is higher).

FIG. 24 shows an exemplary circuit configuration of the unit pixel cell 10D. In FIG. 24, illustration of the voltage supply circuit 50A and the switch SW _i in the vertical scanning circuit 16 is omitted.
In the configuration illustrated in FIG. 24, the gate of the amplification transistor 34 is connected to the charge storage node 44. One of the source and the drain of the amplifying transistor 34 (the drain in the case of an N channel MOS) is connected to the power supply wiring (source follower power supply) 22. The amplification transistor 34 amplifies the signal generated by the photoelectric conversion unit 15. In the configuration illustrated in FIG. 24, the voltage switching circuit 7 described with reference to FIG. 2 is not necessary.

  By applying a predetermined voltage to the feedback control line 28, a feedback circuit 47 that negatively feeds back the output of the signal detection circuit SC can be formed. The feedback circuit 47 is a negative feedback amplification circuit including the amplification transistor 34, the inverting amplifier 29, and the feedback transistor 38. If the gain of the feedback circuit 47 is A, the kTC noise is canceled to 1 / (1 + A) due to the formation of the feedback circuit 47.

  In this example, the formation of the feedback circuit 47 is performed for one of the plurality of unit pixel cells 10D sharing the feedback line 31. In this manner, the feedback circuit may be formed for each column of the pixel array PA.

  The voltage applied to the feedback control line 28 can be a ramp voltage. By using the ramp voltage as the gate voltage, abrupt on / off of the transistor can be avoided. Thereby, noise generated with the on / off of the transistor can be reduced. The ramp voltage may be applied to the gain adjustment terminal 29 a of the inverting amplifier 29.

  FIG. 25 shows a modification of the unit pixel cell in the fourth embodiment. In the unit pixel cell 10E shown in FIG. 25, one of the source and the drain of the reset transistor 36 is connected to the charge storage node 44, and the other is connected to the reset drain node 46. That is, in this example, the reset transistor 36 is connected in parallel with the capacitive element 41. Such a circuit configuration is also applicable. Also in the circuit configuration shown in FIG. 25, the feedback circuit 47 is formed on one of the plurality of unit pixel cells 10E sharing the feedback line 31, as in the circuit configuration shown in FIG.

(Fifth embodiment)
FIG. 26 schematically illustrates a configuration example of a camera system according to the fifth embodiment of the present disclosure. A camera system 600 illustrated in FIG. 26 includes a lens optical system 601, an imaging apparatus 100, a system controller 603, and a camera signal processing unit 604.

  The lens optical system 601 includes, for example, an autofocus lens, a zoom lens, and a diaphragm. The lens optical system 601 condenses light on the imaging surface of the imaging device 100.

  A system controller 603 controls the entire camera system 600. The system controller 603 can be realized by a microcomputer, for example.

  The camera signal processing unit 604 functions as a signal processing circuit that processes an output signal from the imaging device 100. The camera signal processing unit 604 performs processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance, for example. The camera signal processing unit 604 can be realized by, for example, a DSP (Digital Signal Processor).

  In the imaging device 100 in the camera system according to the embodiment of the present disclosure, the influence of noise is reduced. As a result, charges can be read out accurately and a good image can be acquired. Further, since the variation in the threshold voltage of the transistor in the amplifier 54 can be canceled, a low-noise gradient voltage can be supplied to the band transistor 38 of the unit pixel cell 10A. Furthermore, since the initial voltage of the ramp voltage can be arbitrarily set, an appropriate initial voltage corresponding to the variation in the threshold voltage of the band transistor 38 can be used, and efficient noise suppression can be executed. Instead of the imaging device 100, any of the imaging device 200 described with reference to FIG. 8, the imaging device 300 described with reference to FIG. 17, and the imaging device 400 described with reference to FIG. 23 may be used. Good.

  According to the embodiment of the present disclosure, the influence of noise can be reduced. The imaging apparatus according to the present disclosure can be applied to various camera systems and sensor systems such as a digital still camera, a medical camera, a monitoring camera, a vehicle-mounted camera, a digital single-lens reflex camera, and a digital mirrorless single-lens camera.

2 Amplifier 3, 3C Band control circuit 3SA, 3SB, 3SC Band control unit 4A, 4B, 4C Reset circuit 5S Output selection unit 6 Constant current source 7 Voltage switching circuit 10A-10E Unit pixel cell 15 Photoelectric conversion unit 15a First electrode 15b Photoelectric conversion film 15c Second electrode 16 Vertical scanning circuit 17 Storage control line 18 Signal readout line 19 Constant current source 20 Column signal processing circuit 21 Horizontal signal readout circuit 22 Power supply wiring 23 Horizontal common signal line 24 Common signal line 25 Reset voltage line 26 Reset control line 27 Load circuit 28 Feedback control line 29 Inverting amplifier 29a Gain adjustment terminal 30 Address signal line 31 Feedback line 32 Sensitivity adjustment line 34 Amplifying transistor 36 Reset transistor (second transistor)
38 Feedback transistor (first transistor)
40 Address transistor 41, 42 Capacitor element 44 Charge storage node 46 Reset drain node 47, 48, 49 Feedback circuit (second feedback circuit)
50A to 50E, 50Fa, 50Fb Voltage supply circuit 52, 52a, 52b, 52B Ramp voltage generation circuit 54, 54a, 54b, 54S Amplifier (first amplifier)
55 Input transistor 56, 56a, 56b Capacitor element 57N NMOS current source 57P PMOS current source 58, 58D, 58E Feedback circuit (first feedback circuit)
59 Feedback transistor 60, 60a, 60b, 61 Switch 62, 62a, 62b Inverting amplifier (second amplifier)
62n Inverting input terminal 62p Non-inverting input terminal 64 Control circuit 65 Feedback amplifier 66 Constant current source 67 Buffer 68 Threshold voltage detection target transistor 70, 71, 72 Capacitance element 73 Transistor 74, 75 Input transistor 76, 77 Transistor 78 79 Current source transistor 80 Amplifier 82 Mirror primary transistor 83 Current source transistor 84 Diode connection transistor 85 Amplifier input transistor 86 Current source transistor 87 Resistor 88 Capacitance element 89 Connection line 90a, 90b Capacitance element 92 Digital / analog conversion circuit 94a, 94b Sample / hold circuit 96 Smoothing circuit 100, 200, 300, 400 Imaging device 600 Camera system 601 Lens optical system 603 System controller 6 04 camera signal processing unit PA pixel array SW1, SW2, SW _i switch VS1 first voltage source VS2 second voltage source

Claims (9)

A ramp voltage generation circuit;
A first amplifier;
A first capacitive element connected between the ramp voltage generation circuit and the first amplifier;
A first feedback circuit for negatively feeding back the output of the first amplifier,
The first feedback circuit includes a switch that selectively forms a feedback loop.   The voltage supply circuit according to claim 1, wherein the first amplifier includes a source follower, and an output voltage of the ramp voltage generation circuit is input to the source follower via the first capacitive element. The first feedback circuit includes a second amplifier that is an inverting amplifier;
The voltage supply circuit according to claim 1, wherein an output of the first amplifier is input to an inverting input terminal of the second amplifier.   The voltage supply circuit according to claim 3, wherein the switch includes a first switch connected between an output terminal of the second amplifier and an input terminal of the first amplifier.   5. The voltage supply circuit according to claim 1, further comprising a second capacitor element having one end connected to an input terminal of the first amplifier. 6. A second capacitive element having one end connected to the inverting input terminal of the second amplifier;
A third capacitive element having one end connected to the output terminal of the second amplifier;
Further comprising
The voltage supply circuit according to claim 4, wherein the switch includes a second switch connected between an output terminal of the first amplifier and an inverting input terminal of the second amplifier.   5. The voltage supply circuit according to claim 3, further comprising a third amplifier connected between an output terminal of the second amplifier and an input terminal of the first amplifier. The ramp voltage generation circuit includes:
A D / A conversion circuit;
A smoothing circuit;
A first sample / hold circuit and a second sample / hold circuit connected in parallel with each other between the D / A conversion circuit and the smoothing circuit;
The voltage supply circuit according to claim 1, wherein an output of the smoothing circuit is input to the first amplifier via the first capacitive element. The D / A conversion circuit includes:
A first sample circuit including a fourth capacitive element;
A second sample circuit including a fifth capacitive element;
The signal sampled by the fourth capacitive element is input to the first sample / hold circuit,
The voltage supply circuit according to claim 8, wherein the signal sampled by the fifth capacitor element is input to the second sample / hold circuit.

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