JP2019165033A - Solar battery element - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 109
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 109
- 239000010703 silicon Substances 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 230000005684 electric field Effects 0.000 claims description 22
- 238000002161 passivation Methods 0.000 claims description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 14
- 239000013078 crystal Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000969 carrier Substances 0.000 description 5
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 238000009623 Bosch process Methods 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000002803 fossil fuel Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
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- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
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- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
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Abstract
Description
本発明は、太陽電池技術に関し、より詳細には、超薄型のシリコン太陽電池の技術に関する。 The present invention relates to solar cell technology, and more particularly to the technology of ultra-thin silicon solar cells.
近年の環境保全への社会的関心が高まるにつれ、化石燃料に代替するクリーンエネルギーの技術開発の重要性は益々高くなってきている。このような社会背景の下、太陽電池は、自然エネルギーを利用した電力用デバイスとして普及してきたが、太陽電池が主要なエネルギー供給源として利用されるようになるためには、更なるコスト低減と光電変換効率の向上が求められる。 As social interest in environmental conservation has increased in recent years, the importance of developing clean energy technologies that replace fossil fuels has become increasingly important. Under such a social background, solar cells have become widespread as power devices using natural energy. However, in order for solar cells to be used as a major energy supply source, further cost reduction is required. Improvement in photoelectric conversion efficiency is required.
結晶系シリコン太陽電池は、その変換効率の高さから、研究開発が盛んに進められてきており、種々の構造のものが提案されてきている。しかし、結晶系シリコン太陽電池には、モジュール化する際の製造コストに占めるシリコン基板の調達コストの割合が非常に高いという問題がある。このため、シリコン材料費の低減を目的として、シリコン基板の厚さを可能な限り薄くする検討が進められてきた（例えば、特開平８−１４８７０９号公報（特許文献１）や特開２０１３−４５５４号公報（特許文献２）を参照）。 Crystalline silicon solar cells have been actively researched and developed because of their high conversion efficiency, and various structures have been proposed. However, the crystalline silicon solar cell has a problem that the ratio of the procurement cost of the silicon substrate in the manufacturing cost for modularization is very high. Therefore, for the purpose of reducing the silicon material cost, studies have been made to reduce the thickness of the silicon substrate as much as possible (for example, JP-A-8-148709 (Patent Document 1) and JP-A-2013-4554). No. (Patent Document 2)).
また、太陽電池におけるシリコン結晶部分が薄くなると、有効に光閉じ込めが行われることとなり、光入射により発生したキャリアの収集が効率的に行われる。また、シリコン結晶部分が薄くなると、フォトキャリアのライフタイムが長くなり、開放電圧を上げることも可能となる。このため、太陽電池のシリコン結晶部分を薄くすることは、製造コスト低減という経済的メリットのみならず、高光変換効率化の観点からも有利である。 Further, when the silicon crystal portion in the solar cell is thinned, light confinement is effectively performed, and carriers generated by light incidence are efficiently collected. In addition, when the silicon crystal portion is thinned, the lifetime of the photo carrier is lengthened, and the open circuit voltage can be increased. For this reason, thinning the silicon crystal portion of the solar cell is advantageous not only from the economical merit of reducing the manufacturing cost but also from the viewpoint of high light conversion efficiency.
しかし、このようなシリコン結晶部分の薄膜化に伴い、機械的強度の低下という問題が生じてくる。厚みの薄いシリコン基板を用いて太陽電池を製造する場合、基板の元厚が１００μｍ以下になると、割れや反りが発生し易くなる。特に、基板の元厚が５０μｍ以下になると、支持基板への貼り付けにより機械的強度を確保することが必須になる。つまり、シリコン結晶部分の薄膜化のために薄いシリコン基板を用いることとすると、基板自体が割れやすくなることはもとより、熱的・機械的なストレスにも弱くなるために反りが生じ易くなる。このようなセルの反りは、モジュール化工程での歩留り低下をもたらしてしまう。 However, with such thinning of the silicon crystal portion, there arises a problem that the mechanical strength is lowered. When manufacturing a solar cell using a thin silicon substrate, if the original thickness of the substrate is 100 μm or less, cracks and warpage are likely to occur. In particular, when the original thickness of the substrate is 50 μm or less, it is essential to ensure mechanical strength by being attached to the support substrate. That is, if a thin silicon substrate is used to reduce the thickness of the silicon crystal portion, the substrate itself is easily broken, and warpage is likely to occur because it is weak against thermal and mechanical stress. Such warping of the cell results in a decrease in yield in the modularization process.
このような機械的強度の低下を抑制するために、いわゆる「貼り合せ技術」を利用して、支持基板側で機械的強度を担保しつつ、シリコン結晶部分の薄膜化を図ろうとする試みもある。 In order to suppress such a decrease in mechanical strength, there is an attempt to use a so-called “bonding technique” to reduce the thickness of the silicon crystal portion while ensuring the mechanical strength on the support substrate side. .
しかし、貼り合せ技術を採用することに伴い、シリコン基板以外に支持基板が必要となること、また、製造プロセス中に貼り合せ工程を組み込む必要が生じることなどから、製造コストを全体としてみると、必ずしもコスト低減にはつながらないという懸念もある。 However, with the adoption of bonding technology, a support substrate is required in addition to the silicon substrate, and it is necessary to incorporate a bonding process during the manufacturing process. There is also a concern that it will not necessarily lead to cost reduction.
本発明は、このような問題に鑑みてなされたものであって、その目的とするところは、シリコン太陽電池セル（素子）としての機械的強度を充分に担保しつつ、高光変換効率化の観点からも有利な構造の超薄型のシリコン太陽電池を提供することにある。 The present invention has been made in view of such problems, and the object of the present invention is to achieve high light conversion efficiency while sufficiently securing the mechanical strength as a silicon solar battery cell (element). It is another object of the present invention to provide an ultra-thin silicon solar cell having an advantageous structure.
上述の課題を解決するために、本発明に係る第１の態様の太陽電池素子は、第１の導電型を有するシリコン基板の裏面には全面に渡り複数の凹凸部が設けられており、前記凹部は前記凸部を側壁として互いに離間されており、前記シリコン基板の表面から前記シリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下であり、前記シリコン基板の表面側には、前記第１の導電型もしくは該第１の導電型と反対の第２の導電型を有する第１のコンタクト層が形成されており、前記複数の凹部の底部には、前記第１のコンタクト層とは反対の導電型を有する第２のコンタクト層が形成されており、前記第１のコンタクト層に接続する第１電極と、前記第２のコンタクト層に接続する第２電極とを備えている、ことを特徴とする。 In order to solve the above-described problem, the solar cell element according to the first aspect of the present invention is provided with a plurality of uneven portions over the entire back surface of the silicon substrate having the first conductivity type. The concave portions are spaced apart from each other with the convex portion as a side wall, and the depth from the surface of the silicon substrate to the bottom surface of the concave portion provided on the back surface of the silicon substrate is 100 μm or less, and on the surface side of the silicon substrate, A first contact layer having the first conductivity type or a second conductivity type opposite to the first conductivity type is formed, and the first contact layer is formed at the bottom of the plurality of recesses. A second contact layer having a conductivity type opposite to that of the first contact layer is formed, and includes a first electrode connected to the first contact layer and a second electrode connected to the second contact layer. It is characterized by that.
ある態様では、前記第１のコンタクト層と前記シリコン基板の表面との間に第１の非晶質層が設けられるとともに、前記複数の凹部の底部と前記シリコン基板の裏面との間に第２の非晶質層が設けられており、前記第１および第２の非晶質層は、非晶質シリコン層もしくは非晶質酸化シリコン層である。 In one embodiment, a first amorphous layer is provided between the first contact layer and the surface of the silicon substrate, and a second portion is provided between the bottoms of the plurality of recesses and the back surface of the silicon substrate. The amorphous layer is provided, and the first and second amorphous layers are an amorphous silicon layer or an amorphous silicon oxide layer.
また、本発明に係る第２の態様の太陽電池素子は、第１の導電型を有するシリコン基板の裏面には全面に渡り複数の凹凸部が設けられており、前記凹部は前記凸部を側壁として互いに離間されており、前記シリコン基板の表面から前記シリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下であり、前記シリコン基板の表面側には、前記第１の導電型と同じ導電型を有する表面電界層が形成されており、前記複数の凹部のうちの一部の底部には、前記表面電界層とは反対の導電型を有する第２のコンタクト層が形成されるとともに、残りの凹部の底部には前記表面電界層と同じ導電型を有する第３のコンタクト層が形成されており、前記第２のコンタクト層に接続する第２電極と、前記第３のコンタクト層に接続する第３電極とを備えている、ことを特徴とする。 In the solar cell element according to the second aspect of the present invention, a plurality of concave and convex portions are provided over the entire back surface of the silicon substrate having the first conductivity type, and the concave portion has the convex portion as a side wall. The depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is 100 μm or less, and the surface side of the silicon substrate has the first conductivity type And a second contact layer having a conductivity type opposite to that of the surface electric field layer is formed at a part of the bottom of the plurality of recesses. In addition, a third contact layer having the same conductivity type as that of the surface electric field layer is formed at the bottom of the remaining recess, and a second electrode connected to the second contact layer and the third contact layer 3rd power connected to And a bets, characterized in that.
ある態様では、前記表面電界層と前記シリコン基板の表面との間に第１の非晶質層が設けられ、前記複数の凹部のうちの一部の底部と前記シリコン基板の裏面との間に第２の非晶質層が設けられ、前記残りの凹部の底部と前記シリコン基板の裏面との間に第３の非晶質層が設けられており、前記第１、第２、および第３の非晶質層は、非晶質シリコン層もしくは非晶質酸化シリコン層である。 In one embodiment, a first amorphous layer is provided between the surface electric field layer and the surface of the silicon substrate, and between a part of the bottoms of the plurality of recesses and a back surface of the silicon substrate. A second amorphous layer is provided, and a third amorphous layer is provided between the bottom of the remaining recess and the back surface of the silicon substrate, and the first, second, and third layers are provided. The amorphous layer is an amorphous silicon layer or an amorphous silicon oxide layer.
また、ある態様では、前記第２の非晶質層と前記第３の非晶質層は単一の非晶質層である。 In one embodiment, the second amorphous layer and the third amorphous layer are a single amorphous layer.
これらの態様において、好ましくは、前記シリコン基板の表面側に反射防止構造物が設けられている。このような反射防止構造物は、例えば、反射防止膜もしくは光閉じ込めのための微細な凹凸を有するテクスチャー構造である。 In these aspects, preferably, an antireflection structure is provided on the surface side of the silicon substrate. Such an antireflection structure is, for example, an antireflection film or a texture structure having fine irregularities for light confinement.
また、好ましくは、前記太陽電池素子の裏面において、少なくとも露出面の全面がパッシベーション膜で被覆されている。 Preferably, on the back surface of the solar cell element, at least the entire exposed surface is covered with a passivation film.
例えば、前記パッシべーション膜はＳｉＯ2膜である。 For example, the passivation film is a SiO 2 film.
ある態様では、前記凹部に絶縁性物質が埋め込まれている。 In one embodiment, an insulating material is embedded in the recess.
また、ある態様では、前記シリコン基板は単結晶シリコン基板である。 In one embodiment, the silicon substrate is a single crystal silicon substrate.
例えば、前記反射防止膜は窒化シリコン膜である。 For example, the antireflection film is a silicon nitride film.
また、例えば、前記第１〜３電極の少なくとも何れかは、ＩＴＯ膜である。 For example, at least one of the first to third electrodes is an ITO film.
さらに、例えば、前記シリコン基板を裏面側から上面視したときに、前記複数の凹部の底部に設けられた前記第２電極もしくは前記第３電極の形状が、ストライプ状、三角形状、矩形状、円形状、若しくはハニカム状である。 Furthermore, for example, when the silicon substrate is viewed from the back side, the shape of the second electrode or the third electrode provided at the bottom of the plurality of recesses is a stripe shape, a triangular shape, a rectangular shape, a circular shape, or the like. Shape or honeycomb shape.
例えば、前記第２電極および前記第３電極の形状がストライプ状であり、櫛歯状電極として形成されている。 For example, the second electrode and the third electrode are striped and formed as comb-like electrodes.
上述の太陽電池素子は、これをボトムセルとして備えている太陽電池としての利用も可能である。 The above-described solar cell element can also be used as a solar cell provided with this as a bottom cell.
本発明に係る太陽電池素子では、シリコン基板の裏面には全面に渡り複数の凹凸部が設けられており、凹部は凸部を側壁として互いに離間されており、凹部の底部にはコンタクト層が形成されている。このような構造では、機械的強度は凸部で担保されつつ、凹部により高光変換効率化を図ることが可能となる。その結果、シリコン太陽電池セル（素子）としての機械的強度を充分に担保しつつ、高光変換効率化の観点からも有利な構造の超薄型のシリコン太陽電池を提供することが可能となる。 In the solar cell element according to the present invention, a plurality of concave and convex portions are provided on the entire back surface of the silicon substrate, the concave portions are separated from each other with the convex portions serving as side walls, and a contact layer is formed at the bottom of the concave portion. Has been. In such a structure, it is possible to achieve high light conversion efficiency by the concave portion while the mechanical strength is secured by the convex portion. As a result, it is possible to provide an ultra-thin silicon solar cell having an advantageous structure from the viewpoint of high light conversion efficiency while sufficiently ensuring the mechanical strength as a silicon solar cell (element).
以下に、図面を参照して、本発明に係る太陽電池素子の構造について説明する。なお、結晶性Ｓｉ層は、単結晶Ｓｉ層であっても多結晶Ｓｉ層であってもよいが、以降の説明では、単結晶シリコン基板のバルク部分（すなわち単結晶Ｓｉ層）であるものとして説明する。 Hereinafter, the structure of the solar cell element according to the present invention will be described with reference to the drawings. Note that the crystalline Si layer may be a single crystal Si layer or a polycrystalline Si layer, but in the following description, it is assumed that it is a bulk portion (ie, a single crystal Si layer) of a single crystal silicon substrate. explain.
［第１の基本構造の概略］
図１Ａは、本発明に係る太陽電池素子の第１の基本構造の概略を説明するための断面図である。この図に示した構造例の太陽電池素子１００では、ｐ型の導電型のシリコン基板１０の裏面に、全面に渡り複数の凹凸部２０が設けられており、凹部２０ａは凸部２０ｂを側壁として、互いに離間されている。なお、この図に示した例では、ｐ型のシリコン基板１０を用いているが、ｎ型のシリコン基板を用いることとしてもよい。
[Outline of the first basic structure]
FIG. 1A is a cross-sectional view for explaining an outline of a first basic structure of a solar cell element according to the present invention. In the solar cell element 100 of the structural example shown in this figure, a plurality of concave and convex portions 20 are provided over the entire back surface of the p-type conductive silicon substrate 10, and the concave portion 20a has the convex portion 20b as a side wall. Are spaced apart from each other. In the example shown in this figure, the p-type silicon substrate 10 is used, but an n-type silicon substrate may be used.
従来の構造における「結晶性Ｓｉ層」の厚みに相当することとなる、シリコン基板１０の表面からシリコン基板１０の裏面に設けられた凹部２０ａの底面までの深さｄは概ね１００μｍ以下に設計され、太陽電池素子における光閉じ込めを有効に行い、光入射により発生したキャリアの収集を効率的なものとしている。一方、シリコン基板１０の厚み（つまり、上記ｄと凸部２０ｂの高さｈの和ｔ）は、機械的強度が十分に担保できる値（例えば１５０μｍ以上）に設計される。このような構造では、機械的強度は凸部で担保されつつ、凹部により高光変換効率化を図ることが可能となる。 The depth d from the surface of the silicon substrate 10 to the bottom surface of the recess 20a provided on the back surface of the silicon substrate 10 corresponding to the thickness of the “crystalline Si layer” in the conventional structure is designed to be approximately 100 μm or less. Therefore, light confinement is effectively performed in the solar cell element, and collection of carriers generated by light incidence is made efficient. On the other hand, the thickness of the silicon substrate 10 (that is, the sum t of the above d and the height h of the protrusion 20b) is designed to a value (for example, 150 μm or more) that can sufficiently ensure the mechanical strength. In such a structure, it is possible to achieve high light conversion efficiency by the concave portion while the mechanical strength is secured by the convex portion.
シリコン基板１０の表面側には、ｎ型の導電型を有する第１のコンタクト層（この例ではｎ+シリコン層）３０が形成されており、凹部２０ａの底部のそれぞれには、上記第１のコンタクト層３０とは反対の導電型を有する第２のコンタクト層（この例ではｐ+シリコン層）４０が形成されている。なお、図示はしないが、凹部２０ａの底部と第２のコンタクト層４０との界面に、キャリアがトンネル可能な程度の厚みの非晶質層を設けるようにしてもよい。この場合の非晶質層としては、非晶質シリコン層や非晶質酸化シリコン層を例示することができる。 A first contact layer (in this example, an n + silicon layer) 30 having an n-type conductivity is formed on the surface side of the silicon substrate 10, and the first contact layer 30 is formed on each bottom of the recess 20 a. A second contact layer (in this example, a p + silicon layer) 40 having a conductivity type opposite to that of the contact layer 30 is formed. Although not shown, an amorphous layer having a thickness capable of tunneling carriers may be provided at the interface between the bottom of the recess 20a and the second contact layer 40. Examples of the amorphous layer in this case include an amorphous silicon layer and an amorphous silicon oxide layer.
なお、この図に示した例では、第１のコンタクト層３０の導電型を、シリコン基板１０の導電型と反対に設計しているが、シリコン基板１０の導電型と同じに設計してもよい。つまり、図１Ａに示したようにｐ型のシリコン基板１０を用いた場合には、第１のコンタクト層３０の導電型をｐ+に設計してもよい。その場合、凹部２０ａの底部のそれぞれに設けられる第２のコンタクト層４０の導電型は、ｎ+に設計することとなる。 In the example shown in this figure, the conductivity type of the first contact layer 30 is designed to be opposite to the conductivity type of the silicon substrate 10, but may be designed to be the same as the conductivity type of the silicon substrate 10. . That is, when the p-type silicon substrate 10 is used as shown in FIG. 1A, the conductivity type of the first contact layer 30 may be designed to be p + . In that case, the conductivity type of the second contact layer 40 provided at each bottom of the recess 20a is designed to be n + .
そして、第１のコンタクト層３０には第１電極５０が、第２のコンタクト層４０には第２電極６０が、電気的に接続するように設けられ、さらに、シリコン基板１０の表面側には、例えばＳｉＮxの反射防止膜（ＡＲＣ層）７０が設けられ、シリコン基板１０の裏面側に設けられた凸部２０ｂの側壁面は、例えばＳｉＯxのパッシべーション膜８０で被覆されている。なお、この図に示した例では、凹部２０ａには、例えばＳｉＯxなどの絶縁性物質９０が埋め込まれ、裏面電極である第２電極６０相互間の電気的短絡防止を確実なものとすると同時に、機械的強度を向上させている。 A first electrode 50 is provided on the first contact layer 30, a second electrode 60 is provided on the second contact layer 40 so as to be electrically connected, and further, on the surface side of the silicon substrate 10. For example, a SiN x antireflection film (ARC layer) 70 is provided, and the side wall surface of the convex portion 20 b provided on the back side of the silicon substrate 10 is covered with, for example, a SiO x passivation film 80. In the example shown in this figure, an insulating material 90 such as SiO x is embedded in the recess 20a to ensure prevention of an electrical short circuit between the second electrodes 60 that are back electrodes. , Improve the mechanical strength.
つまり、本発明に係る太陽電池素子の第１の基本構造とは、下記のものである。第１の導電型を有するシリコン基板の裏面に全面に渡り複数の凹凸部が設けられており、凹部は凸部を側壁として互いに離間されている。そして、シリコン基板の表面からシリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下に設計されている。シリコン基板の表面側には、第１の導電型もしくは該第１の導電型と反対の第２の導電型を有する第１のコンタクト層が形成されており、複数の凹部の底部には、第１のコンタクト層とは反対の導電型を有する第２のコンタクト層が形成されている。そして、第１のコンタクト層に接続する第１電極と、第２のコンタクト層に接続する第２電極とが設けられている。なお、第１および第２電極は、ＩＴＯ膜であってもよい。 That is, the first basic structure of the solar cell element according to the present invention is as follows. A plurality of concave and convex portions are provided on the entire back surface of the silicon substrate having the first conductivity type, and the concave portions are separated from each other with the convex portions serving as side walls. The depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is designed to be 100 μm or less. A first contact layer having a first conductivity type or a second conductivity type opposite to the first conductivity type is formed on the surface side of the silicon substrate. A second contact layer having a conductivity type opposite to that of the first contact layer is formed. A first electrode connected to the first contact layer and a second electrode connected to the second contact layer are provided. The first and second electrodes may be ITO films.
そして、上記基本構造に加え、図１Ａに示した態様では、シリコン基板１０の表面側に反射防止膜７０が設けられ、凸部２０ｂの側壁面はパッシべーション膜８０で被覆されている。つまり、シリコン基板１０の裏面において、少なくとも露出面の全面がパッシベーション膜８０で被覆されている。さらに、凹部２０ａには、絶縁性物質９０が埋め込まれている。 In addition to the above basic structure, in the embodiment shown in FIG. 1A, the antireflection film 70 is provided on the surface side of the silicon substrate 10, and the side wall surface of the convex portion 20 b is covered with the passivation film 80. That is, at least the entire exposed surface is covered with the passivation film 80 on the back surface of the silicon substrate 10. Further, an insulating material 90 is embedded in the recess 20a.
このような構造では、機械的強度は凸部で担保されつつ、凹部により高光変換効率化を図ることが可能となる。つまり、太陽電池素子の製造に際し、支持基板を必要とすることなく、シリコン太陽電池セル（素子）としての機械的強度を充分に担保しつつ、高光変換効率化の観点からも有利な構造の超薄型のシリコン太陽電池を提供することが可能となる。なお、図１Ａには反射防止のための構造物として反射防止膜７０を例示したが、図１Ｂに示したような、光閉じ込めのための微細な凹凸を有するテクスチャー構造７５を設けるようにしてもよい。つまり、本発明において、反射防止構造物は、反射防止膜や光閉じ込めのための微細な凹凸を有するテクスチャー構造などとすることができる。 In such a structure, it is possible to achieve high light conversion efficiency by the concave portion while the mechanical strength is secured by the convex portion. In other words, in the manufacture of solar cell elements, a super-structural structure that is advantageous from the viewpoint of high light conversion efficiency while sufficiently securing the mechanical strength as a silicon solar cell (element) without requiring a support substrate. A thin silicon solar cell can be provided. In FIG. 1A, the antireflection film 70 is illustrated as an antireflection structure. However, as shown in FIG. 1B, a texture structure 75 having fine irregularities for confining light may be provided. Good. That is, in the present invention, the antireflection structure can be an antireflection film or a texture structure having fine irregularities for light confinement.
［第２の基本構造の概略］
図２は、本発明に係る太陽電池素子の第２の基本構造の概略を説明するための断面図である。図１Ａに示した第１の基本構造とは、上述の第１のコンタクト層に相当する部分に表面電界層（フロントサーフェスフィールド層）３０が形成されており、複数の凹部２０ａのうちの一部の底部には、表面電界層３０とは反対の導電型（ｐ+型）を有する第２のコンタクト層４０ａが形成されるとともに、残りの凹部の底部には表面電界層３０と同じ導電型（ｎ+型）を有する第３のコンタクト層４０ｂが形成され、これらが交互に配置されている点、また、表面電界層には図１Ａに示した第１電極５０は必須のものとされていない点、において相違している。
[Outline of the second basic structure]
FIG. 2 is a cross-sectional view for explaining the outline of the second basic structure of the solar cell element according to the present invention. In the first basic structure shown in FIG. 1A, a surface electric field layer (front surface field layer) 30 is formed in a portion corresponding to the first contact layer described above, and a part of the plurality of recesses 20a. A second contact layer 40a having a conductivity type opposite to that of the surface electric field layer 30 (p + type) is formed at the bottom of the surface electric field layer 30 and the same conductivity type as that of the surface electric field layer 30 is formed at the bottom of the remaining recesses. n + -type) third contact layers 40b are formed and are alternately arranged, and the first electrode 50 shown in FIG. 1A is not essential in the surface electric field layer. The point is different.
この基本構造においても、用いるシリコン基板１０はｐ型でもｎ型でもよいが、図２においても、ｐ型のシリコン基板１０であるとして図示している。図１Ａに示した基本構造と同様に、シリコン基板１０の表面側には、ｎ型の導電型を有する表面電界層（この例ではｎ+シリコン層）３０が形成されており、複数の凹部２０ａのうちの一部のものの底部には、上記表面電界層３０とは反対の導電型を有する第２のコンタクト層（この例ではｐ+シリコン層）４０ａが形成され、残りの凹部の底部には表面電界層３０と同じ導電型（ｎ+型）を有する第３のコンタクト層４０ｂが形成されている。なお、この基本構造においても、図示はしないが、凹部２０ａの底部と第２のコンタクト層４０との界面に、キャリアがトンネル可能な程度の厚みの酸化膜等を設けるようにしてもよい。 Also in this basic structure, the silicon substrate 10 to be used may be p-type or n-type, but in FIG. 2, it is shown as being the p-type silicon substrate 10. Similar to the basic structure shown in FIG. 1A, a surface electric field layer (n + silicon layer in this example) 30 having n-type conductivity is formed on the surface side of the silicon substrate 10, and a plurality of recesses 20a are formed. A second contact layer (a p + silicon layer in this example) 40a having a conductivity type opposite to that of the surface electric field layer 30 is formed at the bottom of some of them, and at the bottom of the remaining recesses A third contact layer 40 b having the same conductivity type (n + type) as surface electric field layer 30 is formed. In this basic structure, though not shown, an oxide film or the like having a thickness that allows carriers to tunnel may be provided at the interface between the bottom of the recess 20a and the second contact layer 40.
この図に示した例においても、表面電界層３０の導電型を、シリコン基板１０の導電型と反対に設計しているが、シリコン基板１０の導電型と同じに設計してもよい。つまり、図２に示したようにｐ型のシリコン基板１０を用いた場合には、表面電界層３０の導電型をｐ+に設計してもよい。 Also in the example shown in this figure, the conductivity type of the surface electric field layer 30 is designed to be opposite to the conductivity type of the silicon substrate 10, but may be designed to be the same as the conductivity type of the silicon substrate 10. That is, as shown in FIG. 2, when the p-type silicon substrate 10 is used, the conductivity type of the surface electric field layer 30 may be designed to be p + .
この基本構造では、第２のコンタクト層４０ａには第２電極６０ａが、第３のコンタクト層４０ｂには第３電極６０ｂが、電気的に接続するように設けられ、さらに、シリコン基板１０の表面側には、例えばＳｉＮxの反射防止膜（ＡＲＣ層）７０が設けられ、シリコン基板１０の裏面側に設けられた凸部２０ｂの側壁面は、例えばＳｉＯxのパッシべーション膜８０で被覆されている。なお、この図に示した例においても、凹部２０ａには、例えばＳｉＯxなどの絶縁性物質９０が埋め込まれ、裏面電極である第２電極６０ａと第３電極６０ｂ相互間の電気的短絡防止を確実なものとすると同時に、機械的強度を向上させている。 In this basic structure, the second electrode 60a is provided on the second contact layer 40a, and the third electrode 60b is provided on the third contact layer 40b so as to be electrically connected. On the side, for example, a SiN x antireflection film (ARC layer) 70 is provided, and the side wall surface of the convex portion 20 b provided on the back side of the silicon substrate 10 is covered with, for example, a SiO x passivation film 80. ing. Also in the example shown in this figure, the recess 20a is filled with an insulating material 90 such as SiO x to prevent an electrical short circuit between the second electrode 60a and the third electrode 60b which are back electrodes. At the same time, the mechanical strength is improved.
つまり、本発明に係る太陽電池素子の第２の基本構造とは、下記のものである。第１の導電型を有するシリコン基板の裏面には全面に渡り複数の凹凸部が設けられており、凹部は凸部を側壁として互いに離間されている。そして、シリコン基板の表面からシリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下に設計されている。シリコン基板の表面側には、第１の導電型と同じ導電型を有する表面電界層（フロントサーフェスフィールド層）が形成されており、複数の凹部のうちの一部の底部には、前記表面電界層とは反対の導電型を有する第２のコンタクト層が形成されるとともに、残りの凹部の底部には前記表面電界層と同じ導電型を有する第３のコンタクト層が形成されている。そして、第２のコンタクト層に接続する第２電極と、第３のコンタクト層に接続する第３電極とが設けられている。なお、第２および第３電極は、ＩＴＯ膜であってもよい。 That is, the second basic structure of the solar cell element according to the present invention is as follows. The back surface of the silicon substrate having the first conductivity type is provided with a plurality of concave and convex portions over the entire surface, and the concave portions are separated from each other with the convex portion as a side wall. The depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is designed to be 100 μm or less. A surface electric field layer (front surface field layer) having the same conductivity type as the first conductivity type is formed on the surface side of the silicon substrate, and the surface electric field is formed at the bottom of some of the plurality of recesses. A second contact layer having a conductivity type opposite to the layer is formed, and a third contact layer having the same conductivity type as the surface electric field layer is formed at the bottom of the remaining recess. A second electrode connected to the second contact layer and a third electrode connected to the third contact layer are provided. The second and third electrodes may be ITO films.
そして、上記基本構造に加え、図２に示した態様では、シリコン基板１０の表面側に反射防止膜７０が設けられ、凸部２０ｂの側壁面はパッシべーション膜８０で被覆されている。さらに、凹部２０ａには、絶縁性物質９０が埋め込まれている。 In addition to the basic structure described above, in the embodiment shown in FIG. 2, the antireflection film 70 is provided on the surface side of the silicon substrate 10, and the side wall surface of the convex portion 20 b is covered with the passivation film 80. Further, an insulating material 90 is embedded in the recess 20a.
［その他の構造例］
上記第１および第２の基本構造において、凹部に形成される第２ないし第３のコンタクト層領域は、種々のレイアウト変更が可能である。
[Other structural examples]
In the first and second basic structures, various layout changes can be made to the second to third contact layer regions formed in the recesses.
例えば、第１の基本構造においては、図３に示したように、第２電極６０を、複数の凹部２０ａに形成された第２のコンタクト層に共通するものとしてもよい。 For example, in the first basic structure, as shown in FIG. 3, the second electrode 60 may be common to the second contact layers formed in the plurality of recesses 20a.
また、第１および第２の基本構造において、図４に示したように、複数の凹部２０ａの底部領域にもパッシベーション膜８０を形成し、当該パッシベーション膜８０を貫通するような態様で第２ないし第３のコンタクト層に電極形成するようにしてもよい。 Further, in the first and second basic structures, as shown in FIG. 4, the passivation film 80 is also formed in the bottom region of the plurality of recesses 20a, and the second or second structure is formed so as to penetrate the passivation film 80. An electrode may be formed on the third contact layer.
さらに、第１および第２の基本構造において、図５に示したように、コンタクト層もしくは表面電界層とシリコン基板の表面もしくは裏面との界面領域に、キャリアがトンネル効果で通過可能な程度の厚みの非晶質層５、５ａ、５ｂを設けるようにしてもよい。 Further, in the first and second basic structures, as shown in FIG. 5, the thickness is such that carriers can pass through the interface region between the contact layer or surface electric field layer and the front or back surface of the silicon substrate by the tunnel effect. Amorphous layers 5, 5 a, 5 b may be provided.
このような非晶質層は、結晶質シリコンの表面に対するパッシベーション膜として機能し、キャリアの再結合の抑制に効果がある。斯かる非晶質層としては非晶質シリコン層や非晶質酸化シリコン層を例示することができる。非晶質層が非晶質シリコン層である場合、その厚みは例えば２〜３ｎｍ程度が一般的である。 Such an amorphous layer functions as a passivation film for the surface of crystalline silicon, and is effective in suppressing carrier recombination. Examples of such an amorphous layer include an amorphous silicon layer and an amorphous silicon oxide layer. When the amorphous layer is an amorphous silicon layer, the thickness is generally about 2 to 3 nm, for example.
この場合も、第２の非晶質層５ａと第３の非晶質層５ｂを単一の非晶質層としても支障はない。 Also in this case, there is no problem even if the second amorphous layer 5a and the third amorphous layer 5b are formed as a single amorphous layer.
［裏面電極のレイアウト］
図６は、本発明に係る太陽電池素子の裏面電極のレイアウトを例示する図である。レイアウトには種々のものがあり得るが、例えば、シリコン基板を裏面側から上面視したときに、上述の複数の凹部の底部に設けられた第２電極もしくは第３電極の形状として、ストライプ状（Ａ〜Ｂ）、ストライプ櫛歯状（Ｃ）、矩形状（Ｄ）、円形状（Ｅ）、若しくはハニカム状（Ｆ）とすることができ、三角形状等の他の形状としてもよい。
[Back electrode layout]
FIG. 6 is a diagram illustrating the layout of the back electrode of the solar cell element according to the present invention. There are various layouts. For example, when the silicon substrate is viewed from the back side, the shape of the second electrode or the third electrode provided at the bottom of the plurality of recesses is a stripe shape ( A to B), a striped comb shape (C), a rectangular shape (D), a circular shape (E), or a honeycomb shape (F), and may have other shapes such as a triangular shape.
図７は、図６（Ｂ）に図示したようなストライプ状の裏面電極が設けられた太陽電池素子の斜視図である。なお、便宜上、この図では、パッシベーション膜８０および凹部２０に埋め込まれる絶縁性物質９０は不図示とした。 FIG. 7 is a perspective view of a solar cell element provided with a striped back electrode as illustrated in FIG. For convenience, in this figure, the passivation film 80 and the insulating material 90 embedded in the recess 20 are not shown.
［太陽電池素子の製造プロセス例］
図８は、本発明に係る太陽電池素子の製造プロセスを例示により説明する図である。
[Example of manufacturing process of solar cell element]
FIG. 8 is a diagram illustrating the manufacturing process of the solar cell element according to the present invention by way of example.
先ず、シリコン基板１０を用意する（Ａ）。このシリコン基板１０は、自立基板としての強度を担保できる程度の厚み（例えば１５０μｍ以上）のものである。このシリコン基板１０を熱酸化して、表面に酸化膜８５を形成し、その後、裏面にフォトレジストパターン１５を設ける（Ｂ）。 First, a silicon substrate 10 is prepared (A). The silicon substrate 10 has a thickness (for example, 150 μm or more) that can ensure the strength as a self-supporting substrate. The silicon substrate 10 is thermally oxidized to form an oxide film 85 on the front surface, and then a photoresist pattern 15 is provided on the back surface (B).
次に、ボッシュプロセスなどのドライエッチングプロセスやドライプロセスで酸化膜８５をパターニングし、更に、アルカリエッチングなどのウエットエッチングなどによりシリコン基板１０の裏面に、凹部２０ａを複数形成する（Ｃ）。 Next, the oxide film 85 is patterned by a dry etching process such as a Bosch process or a dry process, and a plurality of recesses 20a are formed on the back surface of the silicon substrate 10 by wet etching such as alkali etching (C).
続いて、熱酸化や酸化膜デポジション等により、凹部２０ａの側壁および底部にパッシベーション膜８０を形成した後、ＩＣＰ等の異方性ドライエッチングによりパッシベーション膜８０を部分的にエッチングする。これにより、凹部２０ａの底部に形成されたパッシベーション膜は除去され、シリコン結晶が露出する（Ｄ）。 Subsequently, after forming a passivation film 80 on the sidewall and bottom of the recess 20a by thermal oxidation, oxide film deposition, or the like, the passivation film 80 is partially etched by anisotropic dry etching such as ICP. Thereby, the passivation film formed on the bottom of the recess 20a is removed, and the silicon crystal is exposed (D).
このようにして露出させたシリコン結晶領域に、イオン注入法や熱拡散法により、ドナーやアクセプターのドーパントを注入して、ｎ+層もしくはｐ+層とする（Ｅ）。 A donor or acceptor dopant is implanted into the exposed silicon crystal region by ion implantation or thermal diffusion to form an n + layer or p + layer (E).
さらに、表面側の酸化膜（８０および８５）をエッチングにより除去し（Ｆ）、第１のコンタクト層３０および反射防止膜（ＡＲＣ層）７０を形成したのち（Ｇ）、印刷法やスパッタリング法などにより、表面電極５０および裏面電極６０を形成して、素子が完成する。 Further, the oxide films (80 and 85) on the surface side are removed by etching (F), and after forming the first contact layer 30 and the antireflection film (ARC layer) 70 (G), the printing method, the sputtering method, etc. Thus, the front surface electrode 50 and the back surface electrode 60 are formed to complete the device.
図９は、シリコン基板の表面からシリコン基板の裏面に設けられた凹部の底面までの深さｄと開放電圧との関係を調べた結果を示すグラフである。このグラフから、開放電圧は上記深さｄが小さくなるほど高い値を示すことが読み取れる。なお、上記深さｄは、エッチング時間を変えることで制御できる。この実施例では、ＫＯＨ溶液（３０ｗ％）をエッチャントとし、液温８０℃でエッチングを行っている。この条件の場合、エッチング時間と上記深さｄの関係は、図１０に示した関係を示す。 FIG. 9 is a graph showing the results of examining the relationship between the depth d from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate and the open circuit voltage. From this graph, it can be seen that the open circuit voltage increases as the depth d decreases. The depth d can be controlled by changing the etching time. In this embodiment, KOH solution (30 w%) is used as an etchant and etching is performed at a liquid temperature of 80 ° C. In the case of this condition, the relationship between the etching time and the depth d is the relationship shown in FIG.
この開放電圧の測定に際しては、擬定常状態光伝導度測定装置（ＱＳＳ−ＰＣ）を用いた。この測定装置では、図１１Ａ（上面視概略図）および図１１Ｂ（エッチング時間が３５分、５０分、７０分の各試料のＳＥＭ像）に示したようにセル化した時のセルの開放電圧を、照射光を減衰させながら電気伝導度の時間依存性を測り、ライフタイムの注入量依存性を求めることで得ている。よって、得られる開放電圧は、少数キャリアライフタイムの測定から理論的に推定される値である。なお、これらのセルの表面および裏面は、全面に渡り、ヨウ素によるパッシベーションが施されている。 In measuring the open circuit voltage, a quasi-steady state photoconductivity measurement device (QSS-PC) was used. In this measuring apparatus, as shown in FIG. 11A (schematic view in top view) and FIG. 11B (SEM image of each sample with an etching time of 35 minutes, 50 minutes, and 70 minutes), the open-circuit voltage of the cell is shown. It is obtained by measuring the time dependency of the electrical conductivity while attenuating the irradiation light and determining the dependency of the lifetime on the injection amount. Therefore, the open circuit voltage obtained is a value that is theoretically estimated from the measurement of minority carrier lifetime. Note that the front and back surfaces of these cells are subjected to passivation with iodine over the entire surface.
このように、開放電圧の観点から、シリコン基板の表面からシリコン基板の裏面に設けられた凹部の底面までの深さは１００μｍ以下であることが好ましい。本発明ではこの結果に基づき、上記深さを１００μｍ以下に設計している。 Thus, from the viewpoint of open circuit voltage, the depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is preferably 100 μm or less. In the present invention, based on this result, the depth is designed to be 100 μm or less.
なお、上述の太陽電池素子は、単独の素子としての使用はもとより、この太陽電池素子をボトムセルとして備えたタンデム型の太陽電池としての利用も可能である。 The solar cell element described above can be used not only as a single element but also as a tandem solar cell including the solar cell element as a bottom cell.
このように、本発明に係る太陽電池素子では、シリコン基板の裏面には全面に渡り複数の凹凸部が設けられており、凹部は凸部を側壁として互いに離間されており、凹部の底部にはコンタクト層が形成されている。このような構造では、機械的強度は凸部で担保されつつ、凹部により高光変換効率化を図ることが可能となる。その結果、シリコン太陽電池セル（素子）としての機械的強度を充分に担保しつつ、高光変換効率化の観点からも有利な構造の超薄型のシリコン太陽電池を提供することが可能となる。 Thus, in the solar cell element according to the present invention, the back surface of the silicon substrate is provided with a plurality of concave and convex portions over the entire surface, and the concave portions are separated from each other with the convex portions serving as side walls, and at the bottom of the concave portions. A contact layer is formed. In such a structure, it is possible to achieve high light conversion efficiency by the concave portion while the mechanical strength is secured by the convex portion. As a result, it is possible to provide an ultra-thin silicon solar cell having an advantageous structure from the viewpoint of high light conversion efficiency while sufficiently ensuring the mechanical strength as a silicon solar cell (element).
５、５ａ、５ｂ 非晶質層
１０ シリコン基板１０
１５ フォトレジスト
２０ 凹凸部
２０ａ 凹部
２０ｂ 凸部
３０ 第１のコンタクト層
４０ 第２のコンタクト層
５０ 第１電極
６０ 第２電極
７０ 反射防止膜（ＡＲＣ層）
７５ テクスチャー構造
８０ パッシべーション膜
８５ 酸化膜
９０ 絶縁性物質
１００ 太陽電池素子
5, 5a, 5b Amorphous layer 10 Silicon substrate 10
DESCRIPTION OF SYMBOLS 15 Photoresist 20 Uneven part 20a Recess 20b Convex part 30 1st contact layer 40 2nd contact layer 50 1st electrode 60 2nd electrode 70 Antireflection film (ARC layer)
75 Texture structure 80 Passivation film 85 Oxide film 90 Insulating material 100 Solar cell element
Claims (15)
前記凹部は前記凸部を側壁として互いに離間されており、
前記シリコン基板の表面から前記シリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下であり、
前記シリコン基板の表面側には、前記第１の導電型もしくは該第１の導電型と反対の第２の導電型を有する第１のコンタクト層が形成されており、
前記複数の凹部の底部には、前記第１のコンタクト層とは反対の導電型を有する第２のコンタクト層が形成されており、
前記第１のコンタクト層に接続する第１電極と、前記第２のコンタクト層に接続する第２電極とを備えている太陽電池素子。 The back surface of the silicon substrate having the first conductivity type is provided with a plurality of uneven portions over the entire surface,
The recesses are spaced apart from each other with the projections as side walls,
The depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is 100 μm or less,
A first contact layer having the first conductivity type or a second conductivity type opposite to the first conductivity type is formed on the surface side of the silicon substrate,
A second contact layer having a conductivity type opposite to that of the first contact layer is formed at the bottom of the plurality of recesses,
A solar cell element comprising: a first electrode connected to the first contact layer; and a second electrode connected to the second contact layer.
前記第１および第２の非晶質層は、非晶質シリコン層もしくは非晶質酸化シリコン層である、請求項１に記載の太陽電池素子。 A first amorphous layer is provided between the first contact layer and the surface of the silicon substrate, and a second amorphous layer is formed between the bottoms of the plurality of recesses and the back surface of the silicon substrate. Layers are provided,
The solar cell element according to claim 1, wherein the first and second amorphous layers are an amorphous silicon layer or an amorphous silicon oxide layer.
前記凹部は前記凸部を側壁として互いに離間されており、
前記シリコン基板の表面から前記シリコン基板の裏面に設けられた凹部の底面までの深さが１００μｍ以下であり、
前記シリコン基板の表面側には、前記第１の導電型と同じ導電型を有する表面電界層が形成されており、
前記複数の凹部のうちの一部の底部には、前記表面電界層とは反対の導電型を有する第２のコンタクト層が形成されるとともに、残りの凹部の底部には前記表面電界層と同じ導電型を有する第３のコンタクト層が形成されており、
前記第２のコンタクト層に接続する第２電極と、前記第３のコンタクト層に接続する第３電極とを備えている太陽電池素子。 The back surface of the silicon substrate having the first conductivity type is provided with a plurality of uneven portions over the entire surface,
The recesses are spaced apart from each other with the projections as side walls,
The depth from the surface of the silicon substrate to the bottom surface of the recess provided on the back surface of the silicon substrate is 100 μm or less,
A surface electric field layer having the same conductivity type as the first conductivity type is formed on the surface side of the silicon substrate,
A second contact layer having a conductivity type opposite to that of the surface electric field layer is formed at a part of the bottom of the plurality of concave portions, and the same as the surface electric field layer at the bottom of the remaining concave portions. A third contact layer having a conductivity type is formed;
A solar cell element comprising: a second electrode connected to the second contact layer; and a third electrode connected to the third contact layer.
前記第１、第２、および第３の非晶質層は、非晶質シリコン層もしくは非晶質酸化シリコン層である、請求項３に記載の太陽電池素子。 A first amorphous layer is provided between the surface electric field layer and the surface of the silicon substrate, and a second non-layer is provided between the bottom of some of the plurality of recesses and the back surface of the silicon substrate. A crystalline layer is provided, and a third amorphous layer is provided between the bottom of the remaining recess and the back surface of the silicon substrate,
4. The solar cell element according to claim 3, wherein the first, second, and third amorphous layers are amorphous silicon layers or amorphous silicon oxide layers.
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