JP2019153639A - Semiconductor device, receiver and manufacturing method of semiconductor device - Google Patents

Abstract

To improve electrical characteristics, in a semiconductor device using a semiconductor nanowire.SOLUTION: A semiconductor device has a semiconductor substrate formed of a compound semiconductor, a semiconductor nanowire formed on the semiconductor substrate and formed of a compound semiconductor extending upward from the surface of the semiconductor substrate, a lower electrode layer formed of a metal material around the semiconductor nanowire on the semiconductor substrate, and an insulator film formed on the lower electrode layer. The semiconductor nanowire has a first conductivity type first nanowire region on the semiconductor substrate side, and a second conductivity type second nanowire region on the opposite side to the semiconductor substrate and in contact with the first nanowire region. Around the semiconductor substrate side of the first nanowire region of the semiconductor nanowire is in contact with the lower electrode layer.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device, a receiver, and a method for manufacturing a semiconductor device.

  As a method for forming a minute vertical semiconductor device, there is a method of forming a semiconductor nanowire by bottom-up and forming a vertical semiconductor device using the semiconductor nanowire as a core. The semiconductor nanowire can be formed by forming a mask having an opening in a region where the semiconductor nanowire is formed on the surface of the semiconductor substrate and growing the crystal by a MOVPE (Metalorganic vapor phase epitaxy) method. (For example, patent document 1).

  As vertical semiconductor devices using semiconductor nanowires, vertical transistors using III-V compound semiconductor nanowires are disclosed (for example, Non-Patent Document 1).

JP2015-34115A

Tomas Bryllert, Lars-Erik Wernersson, Linus E. Froberg, and Lars Samuelson, “Vertical High-Mobility Wrap-Gated InAs Nanowire Transistor” IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 5, MAY 2006

  In such a semiconductor device using semiconductor nanowires, semiconductor nanowires are formed on a semiconductor layer having a conductivity doped with an impurity element at a high concentration on a semiconductor substrate. The semiconductor layer having conductivity is in contact with the lower electrode of the semiconductor device, and the semiconductor layer having conductivity is a contact layer.

  By the way, the semiconductor nanowire has an elongated shape with a small diameter, the contact area with the conductive semiconductor layer is extremely narrow, and the resistance at the contact portion between the semiconductor nanowire and the conductive semiconductor layer is high. For this reason, in a semiconductor device using semiconductor nanowires, there are cases where good electrical characteristics such as high-frequency characteristics cannot be obtained.

  Therefore, semiconductor devices using semiconductor nanowires are required to have good electrical characteristics.

  According to one aspect of the present embodiment, a semiconductor substrate formed of a compound semiconductor, a semiconductor nanowire formed of a compound semiconductor extending above the substrate surface of the semiconductor substrate formed on the semiconductor substrate, A lower electrode layer formed of a metal material around the semiconductor nanowire on the semiconductor substrate; and an insulating film formed on the lower electrode layer, the semiconductor nanowire on the semiconductor substrate side A first nanowire region of the first conductivity type, and a second nanowire region of the second conductivity type opposite to the semiconductor substrate in contact with the first nanowire region. The periphery of the first nanowire region of the semiconductor nanowire on the semiconductor substrate side is in contact with the lower electrode layer.

  According to the disclosed semiconductor device, electrical characteristics can be improved in a semiconductor device using semiconductor nanowires.

Illustration of semiconductor devices using semiconductor nanowires Explanatory drawing of the semiconductor device in 1st Embodiment Structure diagram of semiconductor device according to first embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 1st Embodiment Process drawing of the manufacturing method of the semiconductor device in 1st Embodiment (2) Process drawing (3) of the manufacturing method of the semiconductor device in the first embodiment Process drawing (4) of the manufacturing method of the semiconductor device in 1st Embodiment Structural diagram of Modification 1 of the semiconductor device according to the first embodiment Structural diagram of Modification 2 of the semiconductor device according to the first embodiment Structure diagram of semiconductor device according to second embodiment Explanatory drawing of the semiconductor device in 2nd Embodiment Process drawing (1) of the manufacturing method of the semiconductor device in 2nd Embodiment Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (2) Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (3) Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (4) Process drawing of the manufacturing method of the semiconductor device in 2nd Embodiment (5) Explanatory drawing of the radio wave receiver in 3rd Embodiment Explanatory drawing of the generator in 3rd Embodiment

  Modes for carrying out the invention will be described below. In addition, about the same member etc., the same code | symbol is attached | subjected and description is abbreviate | omitted.

[First Embodiment]
First, the reason why good electrical characteristics cannot be obtained in a semiconductor device using semiconductor nanowires will be described.

  FIG. 1 illustrates a diode using a semiconductor nanowire (nanowire diode) as a semiconductor device using the semiconductor nanowire. In this nanowire diode, a conductive semiconductor layer 911 having conductivity is formed on a semiconductor substrate 910, and the semiconductor nanowire 920 is substantially on the substrate surface of the semiconductor substrate 910 on the conductive semiconductor layer 911. It is formed to extend vertically.

The semiconductor substrate 910 is a semi-insulating semiconductor substrate, and a non-doped GaAs substrate not doped with an impurity element is used. A GaAs substrate which is not doped with an impurity element has a high resistance and is called a semi-insulating substrate. The conductive semiconductor layer 911 is an n-GaAs layer in which Si as an impurity element is doped at a concentration of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ , and thus conductive by doping Si at a high concentration in GaAs. Sex can be obtained.

  The semiconductor nanowire 920 is formed by a lower n-InAs region 921 and an upper p-GaAsSb region 922, and a pn junction is formed between the n-InAs region 921 and the p-GaAsSb region 922, and a vertical type A diode is formed.

  An n-side electrode 931 is formed on the conductive semiconductor layer 911, and a p-side electrode 932 is formed on the p-GaAsSb region 922 of the semiconductor nanowire 920. In addition, an insulating film 940 such as SiN is formed on the conductive semiconductor layer 911 in a region excluding the region where the semiconductor nanowire 920 and the n-side electrode 931 are formed. Note that the p-side electrode 932 may be a metal serving as a catalyst for growing the semiconductor nanowire 920, but is referred to as a p-side electrode 932 for convenience.

In the nanowire diode having the structure shown in FIG. 1, the resistance of the contact portion between the conductive semiconductor layer 911 surrounded by the one-dot chain line 1A and the n-InAs region 921 below the semiconductor nanowire 920 is increased. Specifically, the semiconductor nanowire 920 has an elongated shape with a diameter of about 100 nm. Accordingly, the contact area between the conductive semiconductor layer 911 and the n-InAs region 921 below the semiconductor nanowire 920 in this case, that is, the area of the bottom surface 921b of the semiconductor nanowire 920 is 50 ² × πnm ² and is extremely narrow. Therefore, the resistance increases at the contact portion.

  Thus, if the resistance of the contact portion between the conductive semiconductor layer 911 and the n-InAs region 921 below the semiconductor nanowire 920 is high, good high frequency characteristics cannot be obtained in the semiconductor device, and power consumption Becomes larger. Therefore, good electrical characteristics cannot be obtained with the nanowire diode having the structure shown in FIG.

  For this reason, semiconductor devices using nanowires are required to have good electrical characteristics.

(Semiconductor device)
Next, a nanowire diode that is a semiconductor device in the present embodiment will be described with reference to FIG. In the nanowire diode in the present embodiment, the semiconductor nanowire 20 is formed on the semiconductor substrate 10 so as to extend upward, for example, substantially perpendicular to the substrate surface of the semiconductor substrate 10.

  As the semiconductor substrate 10, a GaAs crystal substrate which is a semi-insulating semiconductor substrate and is not doped with an impurity element is used.

  The semiconductor nanowire 20 is formed by a lower n-InAs region 21 and an upper p-GaAsSb region 22, and a pn junction is formed between the n-InAs region 21 and the p-GaAsSb region 22. A diode is formed. The diameter of the semiconductor nanowire 20 is not less than 40 nm and not more than 500 nm, more preferably not less than 50 nm and not more than 300 nm. In the present embodiment, the diameter is about 100 nm. A p-side electrode 51 is formed on the upper end of the p-GaAsSb region 22 of the semiconductor nanowire 20. In the present application, the n-InAs region 21 may be described as a first nanowire region, and the p-GaAsSb region 22 may be described as a second nanowire region. The p-side electrode 51 may be a metal serving as a catalyst for growing the semiconductor nanowire 20, but is referred to as the p-side electrode 51 for convenience.

The semiconductor nanowire 20 is formed so that the total height is 1 μm to 2 μm, the height of the n-InAs region 21 is 0.5 to 1 μm, and the height of the p-GaAsSb region 22 is 0.5 to 1 μm. ing. The semiconductor nanowire 20 is formed directly on the semiconductor substrate 10. On the surface of the semiconductor substrate 10 where the semiconductor nanowire 20 is formed, the semiconductor nanowire 20 becomes the lower electrode layer 30 except for the region where the semiconductor nanowire 20 is formed. It is covered with a metal film. An insulating film 40 is formed on the lower electrode layer 30 with SiN or the like. The metal film to be the lower electrode layer 30 is an Au film having a thickness of 100 nm to 300 nm and is in contact with the side surface 21 c of the n-InAs region 21 of the semiconductor nanowire 20. In the n-InAs region 21 of the semiconductor nanowire 20, a portion in contact with the lower electrode layer 30 is a high concentration region 21 a formed by n ⁺ -InAs having a higher impurity concentration than the other portions of the n-InAs region 21. It has become.

In the present embodiment, the side surface 21c of the n-InAs region 21 of the semiconductor nanowire 20 is in contact with the lower electrode layer 30. The height of the contacted portion of the side surface 21c is h, and the semiconductor nanowire 20 When the radius of r is r, the area of the contact portion is 2πrh. Here, when r is 50 nm and h is 100 nm, 100 ² × πnm ² is obtained. On the other hand, in the semiconductor device of the structure shown in FIG. 1, the area of the contact portion of the bottom surface 921b of the lower end of the semiconductor nanowire 920 is pi] r ^2, 50 nm and r, when the 100nm to h, the 50 ² × πnm ^2. Therefore, the semiconductor device in the present embodiment can make the contact area about four times wider than the semiconductor device having the structure shown in FIG. 1, and the resistance in this portion can be reduced to about 1/4. The area of the contact portion between the bottom surface 21b of the semiconductor nanowire 20 and the semiconductor substrate 10 is πr ² , where r is 50 nm and h is 100 nm, 50 ² × πnm ² .

  In addition, the semiconductor nanowire has a submicron diameter, specifically, 500 nm or less, and since the semiconductor nanowire is not a semiconductor nanowire when the diameter increases, there is an upper limit on the thickness of the semiconductor nanowire. There is also an upper limit to the area of the bottom surface of. Furthermore, since the diameter of the semiconductor nanowire is reduced as the diameter of the semiconductor nanowire is reduced, the resistance of this portion is high and the tendency becomes remarkable.

  However, in the present embodiment, since the lower electrode layer 30 is in contact with the side surface 21c of the semiconductor nanowire 20, if the thickness of the lower electrode layer 30 is increased, the contact area can be increased and the resistance is reduced. can do. Thereby, in the semiconductor device in the present embodiment, it is possible to improve high frequency characteristics, reduce power consumption, and the like, and improve electrical characteristics.

In the present embodiment, in the n-InAs region 21 excluding the high concentration region 21a, Sn as an n-type impurity element has a concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. Doped. In the high concentration region 21a, Sn is doped as an n-type impurity element at a concentration of 3 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less. In the p-GaAsSb region 22, Zn is doped as a p-type impurity element at a concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  Therefore, the concentration of the impurity element in the high concentration region 21a is higher than the concentration of the impurity element in the n-InAs region 21 excluding the high concentration region 21a. Moreover, since the lower electrode layer 30 is in contact with the side surface 21c of the high concentration region 21a of the n-InAs region 21, the resistance is lowered by increasing the impurity concentration of the contacted portion to make ohmic contact. can do. In this way, the resistance can be lowered by forming an alloy of both materials in the portion where the high concentration region 21a of the n-InAs region 21 and the lower electrode layer 30 are in contact with each other.

  FIG. 3 shows a structure of a nanowire diode which is a semiconductor device in the present embodiment. This nanowire diode is a nanowire backward diode, and a resin layer 41 is formed on the insulating film 40 by BCB (benzocyclobutene) or the like. The resin layer 41 is an insulator and is formed to be substantially the same height as the upper end of the semiconductor nanowire 20. A through-hole penetrating the insulating film 40 and the resin layer 41 is formed in the insulating film 40 and the resin layer 41, and the n-side electrode 31 that contacts the lower electrode layer 30 is formed by embedding this portion. A p-side electrode 32 is formed on the upper end of the p-GaAsSb region 22 of the semiconductor nanowire 20. Since the resin layer 41 has insulating properties, a thick insulating layer is formed by the insulating film 40 and the resin layer 41.

  The nanowire backward diode having the structure shown in FIG. 3 is formed by one semiconductor nanowire 20, but is not limited thereto. The semiconductor device in the present embodiment may be a nanowire backward diode formed by a plurality of semiconductor nanowires 20, for example. In addition, the material forming the semiconductor nanowire in the nanowire backward diode is not limited to the heterojunction of n-InAs and p-GaAsSb, but has a structure such as p-GaSb / GaAs / n-InGaAs. It may be.

(Semiconductor device manufacturing method)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.

  First, as shown in FIG. 4A, the lower electrode layer 30 and the insulating film 40 are formed on the semiconductor substrate 10.

  The semiconductor substrate 10 is a semi-insulating (SI) -GaAs (111) B substrate not doped with an impurity element.

  The lower electrode layer 30 is formed by depositing an Au film having a thickness of 100 nm to 300 nm by EB (electron beam) vapor deposition or the like.

  The insulating film 40 is a layer serving as a growth mask, and is formed by forming a SiN film having a thickness of about 50 nm by plasma CVD (Chemical Vapor Deposition).

  Next, as shown in FIG. 4B, an opening is formed in the lower electrode layer 30 and the insulating film 40 in the region where the semiconductor nanowire 20 is formed, and the surface of the semiconductor substrate 10 exposed in the opening. A catalyst layer 50 is formed of AuSn. Specifically, an EB resist is applied to the surface of the insulating film 40, and EB drawing and development are performed by an EB drawing apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the semiconductor nanowire 20 is formed. . Thereafter, the insulating film 40 and the lower electrode layer 30 in the region where the resist pattern is not formed are removed by dry etching, thereby forming openings in the insulating film 40 and the lower electrode layer 30. The SiN forming the insulating film 40 is removed by RIE (Reactive Ion Etching) or the like, and the Au film forming the lower electrode layer 30 is removed by ion etching such as Ar. Thereby, the surface of the semiconductor substrate 10 is exposed in a region where the resist pattern is not formed. Thereafter, an AuSn film is formed by EB vapor deposition, and then immersed in an organic solvent, thereby removing the AuSn film formed on the resist pattern together with the resist pattern. Thereby, the catalyst layer 50 is formed of AuSn on the surface of the semiconductor substrate 10 in the opening. The catalyst layer 50 thus formed serves as a growth catalyst for semiconductor nanowires and has a diameter of 20 nm to 100 nm.

  Next, as shown in FIG. 5A, the semiconductor nanowire 20 is formed by, for example, MOCVD (metal organic chemical vapor deposition). The growth temperature when the semiconductor nanowire 20 is grown is 280 ° C. to 300 ° C., which exceeds the melting point of AuSn. Therefore, the semiconductor nanowire 20 is formed by droplet formation and VLS (Vapor-Liquid-Solid) mode growth. Is done. The melting point of Au is 1064 ° C., which is lower than the growth temperature of the semiconductor nanowire 20, so that the lower electrode layer 30 does not change due to the growth of the semiconductor nanowire 20. That is, in the present embodiment, the growth temperature of the semiconductor nanowire 20 is a temperature that exceeds the melting point of AuSn forming the catalyst layer 50 and is lower than the melting point of the lower electrode layer 30.

When the semiconductor nanowire 20 grows and extends upward, the side surface of the semiconductor nanowire 20 comes into contact with the lower electrode layer 30 and is electrically connected. When AuSn is used as a catalyst, the solid solubility of Sn contained in AuSn in InAs is high, and the solubility of Au in InAs is extremely low and can be neglected. It is captured. Therefore, even if the impurity element is not intentionally doped, an n ⁺ -InAs nanowire doped with Sn as an impurity element at a high concentration is formed at the initial stage of the growth of the semiconductor nanowire 20. In the present embodiment, this portion becomes the high concentration region 21 a of the n-InAs region 21 that is in contact with the lower electrode layer 30.

  The diameter of the opening is smaller than the diameter of the catalyst layer 50 so that the catalyst layer 50 formed of AuSn is not entrained to the lower electrode layer 30 formed of Au when the catalyst layer 50 is formed into droplets. It is also preferable that the film is formed slightly wider. Even if there is a gap between the catalyst layer 50 and the lower electrode layer 30 in the opening, when the semiconductor nanowire 20 grows upward due to growth, the semiconductor nanowire 20 grows slowly in the lateral direction, so the diameter of the semiconductor nanowire 20 is large. Become. For this reason, the semiconductor nanowire 20 contacts the lower electrode layer 30 by growth, and the semiconductor nanowire 20 and the lower electrode layer 30 are electrically connected.

In the present embodiment, the n-InAs region 21 is grown until the height, that is, the nanowire length becomes 1 μm. As a raw material for forming the n-InAs region 21, for example, trimethyindium (TMIn) or arsine (AsH ₃ ) is used. In addition, the n-type impurity element is doped with Sn contained in AuSn, which is the catalyst layer 50, but tetramethyltin (TMSn) may be supplied as a raw material, and silane (SiH ₄ ) is supplied. By doing so, Si which becomes n-type may be doped.

Thereafter, the substrate is heated to 500 ° C. to 550 ° C., which is the growth temperature of p-GaAsSb, with AsH ₃ supplied (AsH ₃ atmosphere). By this heating, an alloy region is formed at the contact interface between Au forming the lower electrode layer 30 and the n-InAs region 21.

Thereafter, at this temperature, the p-GaAsSb region 22 is crystal-grown until the height, that is, the nanowire length becomes 1 μm. For example, triethylgallium (TEGa), arsine (AsH ₃ ), or trimethylantimony (TMSb) is used as a raw material for forming the p-GaAsSb region 22. When the p-GaAsSb region 22 is grown, diethyl zinc (DEZn) is supplied at the same time. As a result, the p-GaAsSb region 22 is doped with Zn as an impurity element to be p-type. The concentration of Zn in the p-GaAsSb region 22 is, for example, a concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  In this embodiment mode, a tunnel junction is formed and a backward diode can be formed by appropriately controlling the concentration of impurity elements to be doped and the band gap.

  Next, as shown in FIG. 5B, the passivation film and the passivation film are formed by, for example, forming an aluminum oxide (AlO) film having a film thickness of 5 nm to 10 nm by an atomic layer deposition (ALD) method. An insulating film 60 is formed. As a result, the catalyst layer 50, the side surfaces of the semiconductor nanowire 20, and the insulating film 40 are covered by the formed insulating film 60.

  Next, as illustrated in FIG. 6A, a resin layer 41 is formed on the entire surface of the insulating film 60. Specifically, after applying BCB or the like by a spin coater, the resin layer 41 is formed by heating and thermosetting. Thereby, the resin layer 41 covers the insulating film 60 including the region where the semiconductor nanowire 20 is formed.

  Next, as shown in FIG. 6B, the resin layer 41, a part of the insulating film 60 and the catalyst layer 50 are removed by etching back to expose the upper end of the p-GaAsSb region 22, and the p-GaAsSb region 22. A p-side electrode 32 is formed thereon. Specifically, the resin layer 41, a part of the insulating film 60, and the catalyst layer 50 are removed by etch back, and the upper end of the p-GaAsSb region 22 of the semiconductor nanowire 20 is exposed. This etch back is performed by dry etching. Thereafter, a photoresist is applied to the surfaces of the etched back resin layer 41 and p-GaAsSb region 22, and exposure and development are performed by an exposure apparatus, thereby providing an opening in a region where the p-side electrode 32 is formed. A resist pattern (not shown) is formed. Thereafter, an AuZn film is formed by vacuum vapor deposition and immersed in an organic solvent or the like, whereby the AuZn film formed on the resist pattern is removed together with the resist pattern by lift-off. Thereby, the p-side electrode 32 is formed by the remaining AuZn film.

  Next, as shown in FIG. 7A, an opening 41a penetrating the resin layer 41, the insulating film 60, and the insulating film 40 is formed, and the surface of the lower electrode layer 30 is exposed in the opening 41a. Specifically, a photoresist is applied on the resin layer 41 and the p-side electrode 32, and exposure and development are performed by an exposure apparatus, whereby a resist (not shown) having an opening in a region where the opening 41a is formed. Form a pattern. Thereafter, the resin layer 41, the insulating film 60, and the insulating film 40 in a region where the resist pattern is not formed are removed by dry etching, thereby exposing the surface of the lower electrode layer 30 to form an opening 41a. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 7B, the n-side electrode 31 is formed by embedding the opening 41a with an Au film. Specifically, a resist pattern (not shown) having an opening in the region where the n-side electrode 31 is formed is formed, and an Au film is formed on the lower electrode layer 30 exposed in the opening 41a by Au plating. By depositing, the n-side electrode 31 is formed. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Through the above steps, the semiconductor device in the present embodiment can be manufactured.

(Modification 1)
The semiconductor device in the present embodiment may have a structure in which the high concentration region 21a is not provided in the n-InAs region 21, as shown in FIG. Even in the semiconductor device having such a structure, since the contact area between the n-InAs region 21 of the semiconductor nanowire 20 and the lower electrode layer 30 is large, the resistance of this portion can be reduced. Further, the n-InAs region 21 may have a structure in which the concentration of an impurity element that becomes n-type is increased.

(Modification 2)
Further, as shown in FIG. 9, the semiconductor device in the present embodiment has a structure in which an insulating film 42 is formed on a semiconductor substrate 10 and a lower electrode layer 30 is formed on the insulating film 42. It may be. By forming the insulating film 42 between the semiconductor substrate 10 and the lower electrode layer 30, direct contact between the semiconductor substrate 10 and the lower electrode layer 30 can be avoided, and the semiconductor substrate 10 and the lower electrode layer 30 can be avoided. Insulating property with 30 can be increased. For this reason, even if it is a case where it heats, the alloying of GaAs contained in the semiconductor substrate 10 and Au contained in the lower electrode layer 30 can be prevented.

[Second Embodiment]
(Semiconductor device)
Next, a nanowire transistor that is a semiconductor device in the second embodiment will be described with reference to FIGS. FIG. 10 is a cross-sectional view of the nanowire transistor in the present embodiment, and FIG. 11 is a perspective view through the insulating film 40 and the resin layer 140. In FIG. 11, the insulating film 60 is omitted for convenience. In the nanowire transistor in the present embodiment, the semiconductor nanowire 20 is formed on the semiconductor substrate 10 so as to extend substantially perpendicular to the substrate surface of the semiconductor substrate 10. The resin layer 140 has an insulating property, and a thick insulating layer is formed by the insulating film 40, a part of the insulating film 60, and the resin layer 140.

  The semiconductor nanowire 20 is formed by a lower n-InAs region 21 and an upper p-GaAsSb region 22, and the side surfaces of the semiconductor nanowire 20 are covered with an insulating film 60. A gate electrode layer 130 is formed through an insulating film 60 at substantially the same height as the junction between the n-InAs region 21 and the p-GaAsSb region 22, and the gate electrode 131 is connected to the gate electrode layer 130. Has been. A source electrode 132 is formed on the upper end of the p-GaAsSb region 22 of the semiconductor nanowire 20, and the side surface near the lower end of the n-InAs region 21 of the semiconductor nanowire 20 is in contact with the lower electrode layer 30. The electrode layer 30 is connected to the drain electrode 133.

(Semiconductor device manufacturing method)
Next, a method for manufacturing a semiconductor device in the present embodiment will be described.

  First, as shown in FIG. 12A, the lower electrode layer 30 and the insulating film 40 are formed on the semiconductor substrate 10.

  Next, as shown in FIG. 12B, in the region where the semiconductor nanowire 20 is formed, an opening is formed in the lower electrode layer 30 and the insulating film 40, and the surface of the semiconductor substrate 10 exposed in the opening is formed. A catalyst layer 50 is formed of AuSn.

  Next, as shown in FIG. 13A, the semiconductor nanowire 20 is formed by MOCVD using the catalyst layer 50, for example.

  Next, as shown in FIG. 13B, an insulating film 60 to be a passivation film is formed by depositing, for example, an aluminum oxide (AlO) film having a thickness of 5 nm to 10 nm by an atomic layer deposition method. .

  Next, as illustrated in FIG. 14A, a resin layer 141 is formed on the insulating film 60. The resin layer 141 is formed of BCB or the like, and is formed to have a height slightly below the junction between the n-InAs region 21 and the p-GaAsSb region 22.

  Next, as shown in FIG. 14B, a metal film 130 a is formed of Au or the like on the insulating film 60 covering the semiconductor nanowire 20 and on the resin layer 141 around the semiconductor nanowire 20. Specifically, a photoresist is applied on the resin layer 141, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the metal film 130a is formed. Thereafter, a metal film is formed by vacuum deposition and immersed in an organic solvent or the like, thereby removing the metal film on the resist pattern together with the resist pattern. As a result, the metal film 130 a is formed on the insulating film 60 covering the semiconductor nanowire 20 and on the resin layer 141 around the semiconductor nanowire 20.

  Next, as shown in FIG. 15A, a part of the metal film 130a is removed except for a portion in contact with the insulating film 60 in the vicinity of the junction portion between the n-InAs region 21 and the p-GaAsSb region 22. Then, the gate electrode layer 130 is formed. Specifically, a resist pattern (not shown) having an opening in a region where the semiconductor nanowire 20 is formed is formed by applying a photoresist, exposing and developing. Thereafter, the metal film 130a exposed in the region where the photoresist is not formed is removed by ion etching of Ar or the like, and the insulating film 60 in this portion is exposed. Thereby, the gate electrode layer 130 is formed by the remaining metal film 130a. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as illustrated in FIG. 15B, the resin layer 142 is formed on the resin layer 141 and the gate electrode layer 130. The resin layer 142 is formed of BCB or the like, and the insulating layer 60 is covered with the resin layer 142 including the region where the semiconductor nanowire 20 is formed. The resin layer 140 is formed by the resin layer 141 and the resin layer 142 thus formed.

  Next, as shown in FIG. 16, a gate electrode 131, a source electrode 132, and a drain electrode 133 are formed. Specifically, the resin layer 141 and the catalyst layer 50 are removed by etching back, the upper end of the p-GaAsSb region 22 is exposed, and the source electrode 132 is formed on the p-GaAsSb region 22. Thereafter, an opening is formed in the resin layer 140 in a region where the gate electrode 131 and the drain electrode 133 are formed. In the opening formed at this time, the surface of the gate electrode layer 130 is exposed at the bottom of the opening in the region where the gate electrode 131 is formed, and the bottom of the opening in the region where the drain electrode 133 is formed. The surface of the lower electrode layer 30 is exposed. Then, the gate electrode 131 and the drain electrode 133 are formed by embedding each opening by plating.

  Through the above steps, the semiconductor device in the present embodiment can be manufactured.

[Third Embodiment]
Next, a third embodiment will be described. The present embodiment is a radio wave receiver and a generator using the nanowire diode in the first embodiment.

  As shown in FIG. 17, the radio wave receiver 210 in the present embodiment is a radio wave receiver of a large-capacity radio communication system having the nanowire diode in the first embodiment. The radio wave receiver 210 includes a reception antenna 211, a low noise amplifier 212, a nanowire diode 200, an inductor 213, and an output terminal. As the nanowire diode 200, the nanowire diode in the first embodiment is used.

  In this radio wave receiver 210, the receiving antenna 211 is connected to the input of the low noise amplifier 212, and the output of the low noise amplifier 212 is connected to the anode of the nanowire diode 200 and one terminal of the inductor 213. The cathode of the nanowire diode 200 is grounded, and the output terminal is connected to the other terminal of the inductor 213.

  The radio wave received by the receiving antenna 211 is amplified by the low noise amplifier 212, half-wave rectified by the nanowire diode 200, impedance-matched by the inductor 213, and output from the output terminal.

  The nanowire diode 200 has a smaller junction capacitance than a conventional diode, and can receive radio waves up to the terahertz wave band region. Due to the excellent high-frequency characteristics of the nanowire diode 200, a highly reliable large-capacity wireless communication network system can be realized. It is also possible to obtain sufficient mechanical strength by bundling and using a plurality of nanowires.

  As shown in FIG. 18, the generator 220 in the present embodiment is an IoT (Internet of Things) sensor generator using the nanowire diode in the first embodiment. The generator 220 includes a receiving antenna 221, nanowire diodes 201 and 202, a smoothing capacitor 222, a voltage stabilizing circuit 223, an output terminal, and the like. In the generator 220, the receiving antenna 221 is connected to the cathode of the nanowire diode 201 and the anode of the nanowire diode 202, and the anode of the nanowire diode 201 is grounded. The cathode of the nanowire diode 202 is connected to one terminal of the smoothing capacitor 222 and the input of the voltage stabilization circuit 223, and the output of the voltage stabilization circuit 223 is connected to the output terminal. The other terminal of the smoothing capacitor 222 is grounded.

  The reception antenna 221 is an antenna that receives, for example, microwaves as energy. The nanowire diodes 201 and 202 are alternately conducted, and full-wave rectification of the microwave incident from the receiving antenna 221 is performed. The smoothing capacitor 222 provides a stable DC (direct current) output. The voltage stabilizing circuit 223 sets the DC output to a constant value. The output terminal is connected to the power source of the IoT sensor, and the DC output that has been rectified and has a constant value is supplied to the power source of the IoT sensor.

  In the generator 220 in the present embodiment, the nanowire diodes 201 and 202 are the nanowire diodes in the first embodiment. For this reason, due to the excellent high frequency characteristics of the nanowire diodes 201 and 202, it is possible to harvest minute electric power such as microwaves with high energy conversion efficiency. Thereby, the IoT sensor which can be operated with low power can be driven without using a battery or the like.

  Although the embodiment has been described in detail above, it is not limited to the specific embodiment, and various modifications and changes can be made within the scope described in the claims.

In addition to the above description, the following additional notes are disclosed.
(Appendix 1)
A semiconductor substrate formed of a compound semiconductor;
A semiconductor nanowire formed of a compound semiconductor extending above a substrate surface of the semiconductor substrate formed on the semiconductor substrate;
A lower electrode layer formed of a metal material around the semiconductor nanowire on the semiconductor substrate;
An insulating film formed on the lower electrode layer;
Have
The semiconductor nanowire includes a first conductivity type first nanowire region on the semiconductor substrate side, and a second conductivity type second on the opposite side of the semiconductor substrate in contact with the first nanowire region. A nanowire region,
The semiconductor device according to claim 1, wherein a periphery of the first nanowire region of the semiconductor nanowire on the semiconductor substrate side is in contact with the lower electrode layer.
(Appendix 2)
On the semiconductor substrate side of the first nanowire region, a high concentration region having a higher impurity element concentration than other portions of the first nanowire region is formed,
The semiconductor device according to appendix 1, wherein the semiconductor device is in contact with the lower electrode layer around the high concentration region.
(Appendix 3)
The semiconductor nanowire is made of a III-V compound semiconductor,
The semiconductor device according to appendix 2, wherein the high concentration region is doped with Sn.
(Appendix 4)
The first conductivity type is n-type;
4. The semiconductor device according to any one of appendices 1 to 3, wherein the second conductivity type is p-type.
(Appendix 5)
The first nanowire region is formed of a material containing InAs,
The semiconductor device according to any one of appendices 1 to 4, wherein the second nanowire region is formed of a material containing GaAsSb.
(Appendix 6)
The semiconductor substrate is a semi-insulating GaAs substrate,
6. The semiconductor device according to any one of appendices 1 to 5, wherein the lower electrode layer is made of a material containing Au.
(Appendix 7)
An antenna,
A semiconductor device according to any one of appendices 1 to 6 connected to the antenna;
A receiver comprising:
(Appendix 8)
On the semiconductor substrate formed of a compound semiconductor, a step of sequentially laminating a lower electrode layer with a metal material and an insulating film with an insulating material;
Forming an opening in the lower electrode layer and the insulating film, and forming a catalyst layer on the semiconductor substrate in the opening;
By supplying a gas containing one element of the compound semiconductor contained in the semiconductor nanowire and a gas containing the other element, the compound semiconductor is grown in a region where the catalyst layer is formed, and the semiconductor Forming a nanowire;
Have
The method for manufacturing a semiconductor device, wherein a melting point of a material forming the catalyst layer is lower than a melting point of a material forming the lower electrode layer.
(Appendix 9)
In the step of forming the semiconductor nanowire, the growth temperature of the semiconductor nanowire is higher than the melting point of the material forming the catalyst layer and lower than the melting point of the material forming the lower electrode layer. 9. A method for manufacturing a semiconductor device according to appendix 8.
(Appendix 10)
The semiconductor nanowire is formed of a III-V group compound semiconductor,
The method for manufacturing a semiconductor device according to appendix 8 or 9, wherein the catalyst layer is a material containing Au and Sn.
(Appendix 11)
The first conductivity type is n-type;
11. The method for manufacturing a semiconductor device according to any one of appendices 8 to 10, wherein the second conductivity type is p-type.
(Appendix 12)
The first nanowire region is formed of a material containing InAs,
12. The method of manufacturing a semiconductor device according to any one of appendices 8 to 11, wherein the second nanowire region is formed of a material containing GaAsSb.
(Appendix 13)
The semiconductor substrate is a semi-insulating substrate formed of GaAs,
13. The method for manufacturing a semiconductor device according to any one of appendices 8 to 12, wherein the lower electrode layer is made of a material containing Au.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 20 Semiconductor nanowire 21 n-InAs area | region 21a High concentration area | region 22 p-GaAsSb area | region 30 Lower electrode layer 31 n side electrode 32 p side electrode 40 Insulating film 41 Resin layer 50 Catalyst layer 60 Insulating film

Claims (10)

A semiconductor substrate formed of a compound semiconductor;
A semiconductor nanowire formed of a compound semiconductor extending above a substrate surface of the semiconductor substrate formed on the semiconductor substrate;
A lower electrode layer formed of a metal material around the semiconductor nanowire on the semiconductor substrate;
An insulating film formed on the lower electrode layer;
Have
The semiconductor nanowire includes a first conductivity type first nanowire region on the semiconductor substrate side, and a second conductivity type second on the opposite side of the semiconductor substrate in contact with the first nanowire region. A nanowire region,
The semiconductor device according to claim 1, wherein a periphery of the first nanowire region of the semiconductor nanowire on the semiconductor substrate side is in contact with the lower electrode layer. On the semiconductor substrate side of the first nanowire region, a high concentration region having a higher impurity element concentration than other portions of the first nanowire region is formed,
The semiconductor device according to claim 1, wherein the semiconductor device is in contact with the lower electrode layer around the high concentration region. The semiconductor nanowire is formed of a III-V group compound semiconductor,
The semiconductor device according to claim 2, wherein the high concentration region is doped with Sn. The first conductivity type is n-type;
The semiconductor device according to claim 1, wherein the second conductivity type is p-type. The first nanowire region is formed of a material containing InAs,
The semiconductor device according to claim 1, wherein the second nanowire region is formed of a material containing GaAsSb. The semiconductor substrate is a semi-insulating GaAs substrate,
6. The semiconductor device according to claim 1, wherein the lower electrode layer is made of a material containing Au. An antenna,
The semiconductor device according to any one of claims 1 to 6, connected to the antenna;
A receiver comprising: On the semiconductor substrate formed of a compound semiconductor, a step of sequentially laminating a lower electrode layer with a metal material and an insulating film with an insulating material;
Forming an opening in the lower electrode layer and the insulating film, and forming a catalyst layer on the semiconductor substrate in the opening;
Forming a semiconductor nanowire by growing a compound semiconductor in a region where the catalyst layer is formed by supplying a gas containing one element forming a compound semiconductor and a gas containing the other element; ,
Have
The method for manufacturing a semiconductor device, wherein a melting point of a material forming the catalyst layer is lower than a melting point of a material forming the lower electrode layer.   In the step of forming the semiconductor nanowire, the growth temperature of the semiconductor nanowire is higher than the melting point of the material forming the catalyst layer and lower than the melting point of the material forming the lower electrode layer. A method for manufacturing a semiconductor device according to claim 8. The semiconductor nanowire is formed of a III-V group compound semiconductor,
The method for manufacturing a semiconductor device according to claim 8, wherein the catalyst layer is a material containing Au and Sn.

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