JP2019145715A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of suppressing a warpage of a semiconductor wafer after sandblasting, and the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device according to an embodiment comprises the steps of: preparing a semiconductor wafer 10 of a first conductivity type; forming a diffusion region 14 of a second conductivity type on a principal surface 10a of the semiconductor wafer 10; forming a diffusion region 16 of the second conductivity type on a principal surface 10b of the semiconductor wafer 10; forming a diffusion region 17 of the first conductivity type in the diffusion region 14; forming a wafer protection part 19 for protecting the principal surface 10b of the semiconductor wafer 10 from sandblasting on the principal surface 10b (wafer protection part forming step); and subjecting the principal surface 10b of the semiconductor wafer 10 to sandblasting after the wafer protection part forming step (sandblasting step).SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  As vertical semiconductor devices, thyristors and bidirectional thyristors (triacs) are known. In manufacturing the thyristor, a diffusion region (base, second emitter) is formed on the front surface of the semiconductor wafer, and a diffusion region (first emitter) is formed on the back surface. Thereafter, a contact window is formed in the oxide film on the front surface, and a cathode electrode and a gate electrode are formed in the contact window. Thereafter, an anode electrode is formed on the back surface. Then, the semiconductor wafer is diced to obtain a plurality of thyristors.

  In the above manufacturing process, a sandblast process is performed on the semiconductor wafer before the anode electrode is formed on the back surface. As a result of this sandblasting, irregularities are formed on the back surface of the semiconductor wafer, and the surface area of the back surface is increased. As a result, the on voltage (VT) of the thyristor can be reduced.

  In Patent Document 1, when a conductive film is formed on the back surface of a semiconductor wafer by sputtering, warpage of the semiconductor wafer is reduced by forming the conductive film on the semiconductor wafer separately for each island-shaped chip formation region. Is described.

JP 2001-93863 A

  Conventionally, an oxide film and a passivation film are formed on the front surface of the semiconductor wafer so as to cover the front surface, and the back surface is covered with the back surface before the sandblasting process is performed. Thus, an oxide film is formed. Since the oxide film has a denser crystal structure than the semiconductor wafer, tensile stress is generated on both the front surface side and the back surface side.

  In a state where these stresses are balanced, the occurrence of warpage of the semiconductor wafer is suppressed. However, in the above manufacturing method, when the contact window is formed on the front surface oxide film, the back surface oxide film is removed by an etching process, and thereafter, the exposed back surface is subjected to a sandblasting process. Thereby, the tensile stress on the back surface side is released, and the tensile stress on the front surface side becomes dominant. As a result, the semiconductor wafer warps so that the back surface is convex.

  When the warp occurs in the semiconductor wafer in this way, the transfer device may not be able to suck the semiconductor wafer and a transfer error may occur. In addition, a storage error may occur when the semiconductor wafer is stored in the wafer carrier.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of suppressing warpage of a semiconductor wafer after sandblasting.

A method for manufacturing a semiconductor device according to the present invention includes:
Providing a first conductivity type semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;
Forming a second diffusion type first diffusion region on the first main surface;
Forming a second conductivity type second diffusion region on the second main surface of the semiconductor wafer;
Forming a first conductivity type third diffusion region in the first diffusion region;
A wafer protection part forming step for forming a wafer protection part for protecting the second main surface from sandblasting on the second main surface of the semiconductor wafer;
After the wafer protection part forming step, a sand blasting step for performing a sand blasting process on the second main surface of the semiconductor wafer;
It is characterized by providing.

In the method for manufacturing the semiconductor device,
In the wafer protection part forming step, the wafer protection part may be formed in a mesh shape so as to cover the second main surface.

In the method for manufacturing the semiconductor device,
In the wafer protection portion forming step, the wafer protection portion may be formed in a dicing area including a cutting line for partitioning the semiconductor wafer into a plurality of semiconductor device formation areas.

In the method for manufacturing the semiconductor device,
In the wafer protection part forming step, the wafer protection part may be formed in a lattice shape so as to surround each semiconductor device formation region.

In the method for manufacturing the semiconductor device,
After the sandblasting process,
Forming a protective film so as to cover the first main surface side of the semiconductor wafer;
Forming a contact window in the protective film;
Forming a conductive layer on the second main surface of the semiconductor wafer;
A dicing step of dicing the semiconductor wafer on which the conductive layer is formed along the semiconductor device formation region;
May be further provided.

In the method for manufacturing the semiconductor device,
The wafer protection part forming step includes:
Forming an etching mask on the oxide film on the second main surface;
An etching step of forming the wafer protection unit by etching the oxide film using the etching mask;
You may have.

In the method for manufacturing the semiconductor device,
After the etching step, the etching mask may be removed, and then the sandblasting step may be performed.

In the method for manufacturing the semiconductor device,
The oxide film constituting the wafer protection part may be a thermal oxide film of the semiconductor wafer formed on the second main surface when forming the third diffusion region.

In the method for manufacturing the semiconductor device,
The oxide film may have a thickness of 0.5 to 3.0 μm.

In the method for manufacturing the semiconductor device,
The wafer protection part forming step includes:
Removing the oxide film on the second main surface of the semiconductor wafer;
Forming a resist film having a predetermined pattern shape on the second main surface as the wafer protection portion;
You may have.

In the method for manufacturing the semiconductor device,
The second diffusion region may be of a second conductivity type.

In the method for manufacturing the semiconductor device,
The first conductivity type may be an N type, and the second conductivity type may be a P type.

A semiconductor device according to the present invention includes:
A first conductivity type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
A first diffusion region of a second conductivity type formed on the first main surface;
A second diffusion region formed on the second main surface;
A third diffusion region of the first conductivity type formed in the first diffusion region;
A first main electrode formed on the first main surface and in ohmic contact with the third diffusion region;
A control electrode formed on the first main surface and in ohmic contact with the first diffusion region;
A second main electrode formed on the second main surface and in ohmic contact with the second diffusion region;
An insulating portion provided at a peripheral portion of the second main surface and embedded in the second main electrode;
It is characterized by providing.

In the semiconductor device,
The second diffusion region may be a second conductivity type, and the semiconductor device may be a thyristor.

  In the present invention, the wafer protection part is formed on the second main surface of the semiconductor wafer before the sandblasting process. In the region where the wafer protection part is formed, the second main surface is covered and protected by the wafer protection part, so that damage caused by the sandblasting process is reduced. Thereby, release of the internal stress on the second main surface side is suppressed. As a result, according to the present invention, warpage of the semiconductor wafer after sandblasting can be suppressed.

5 is a flowchart for explaining a method for manufacturing a semiconductor device according to the embodiment. 1B is a flowchart for explaining the semiconductor device manufacturing method according to the embodiment, following FIG. 1A; 1B is a flowchart for explaining the semiconductor device manufacturing method according to the embodiment, following FIG. 1B. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment after FIG. 2A. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment following FIG. 2B. FIG. 2D is a process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment, which is subsequent to FIG. 2C; It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment after FIG. 2D. It is process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment after FIG. 2E. FIG. 2F is a process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment, following FIG. 2F; It is a top view which shows the back surface of the semiconductor wafer after a sandblast process. It is sectional drawing of the semiconductor device which concerns on embodiment. It is a bottom view of the semiconductor device concerning an embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, the component which has an equivalent function is attached | subjected the same code | symbol, and detailed description of the component of the same code | symbol is not repeated.

<Method for Manufacturing Semiconductor Device>
A method for manufacturing a semiconductor device according to this embodiment will be described with reference to the flowcharts of FIGS. 1A to 1C. Here, a manufacturing method in the case where the semiconductor device is a thyristor will be described. In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type, but may be reversed.

  First, as shown in FIG. 2A (1), a first conductivity type semiconductor wafer 10 is prepared (step S11). The semiconductor wafer 10 has a main surface 10a (first main surface) and a main surface 10b (second main surface) opposite to the main surface 10a. In the present embodiment, the semiconductor wafer 10 is a silicon wafer (for example, 5 inches in diameter and 200 μm in thickness) containing a first conductivity type impurity. The semiconductor wafer 10 may be made of a semiconductor other than silicon, for example, a compound semiconductor (SiC or the like).

  Next, an isolation region 13 that partitions the semiconductor wafer 10 into a plurality of semiconductor device formation regions R is formed (step S12).

Here, a method for forming the isolation region 13 will be described in detail. First, as shown in FIG. 2A (2), an oxide film 11A is formed on the main surface 10a of the semiconductor wafer 10, and an oxide film 12A is formed on the opposite main surface 10b. The oxide films 11A and 12A are, for example, thermal oxide films (SiO ₂ ), and are formed by heating the semiconductor wafer 10 in an oxidizing atmosphere. Thereafter, as shown in FIG. 2A (3), a resist film 21 and a resist film 22 are formed on the oxide film 11A and the oxide film 12A, respectively. Thereafter, as shown in FIG. 2B (1), the resist films 21 and 22 are exposed and developed to form openings 21h and 22h. More specifically, the opening 21 h is formed in the resist film 21, and the opening 22 h is formed in the resist film 22. Thereafter, as shown in FIG. 2B (2), the oxide films 11A and 12A exposed to the openings 21h and 22h are removed using the resist films 21 and 22 as etching masks. Thereafter, the resist films 21 and 22 are removed. Thereafter, as shown in FIG. 2B (3), the second conductivity type (P-type in this embodiment) is formed in the semiconductor wafer 10 from the region of the main surface 10a not covered with the oxide film 11A by the deposition method. Impurities are introduced and diffused. Similarly, impurities of the second conductivity type are introduced and diffused into the semiconductor wafer 10 from the region of the main surface 10b not covered with the oxide film 12A. Impurities to be introduced are, for example, aluminum and boron. Thereby, the isolation region 13 is formed. As shown in FIG. 2B (3), the openings of the oxide films 11A and 12A are closed by the heating in the diffusion process after the deposition process, and the oxide films 11B and 12B are formed. In FIG. 2B (3), reference numeral RD indicates a dicing area in the present embodiment. Generally speaking, the dicing region is a region including a cutting line for partitioning the semiconductor wafer 10 into a plurality of semiconductor device formation regions R. Note that a part of the dicing region may remain after the semiconductor wafer 10 is diced. That is, the dicing area may not be completely removed by dicing.

  After the isolation region 13 is formed, as shown in FIGS. 2C (1) to 2C (3), the second conductivity type diffusion region 14 (first diffusion region) is formed on the main surface 10a in each semiconductor device formation region R. ) Is formed (step S13). This diffusion region 14 is also called a base. In step S <b> 13, the guard ring 15 may be formed so as to surround the diffusion region 14 together with the diffusion region 14. A second conductivity type diffusion region 16 (second diffusion region) is formed on the main surface 10b of the semiconductor wafer 10 (step S14).

  In the present embodiment, the diffusion region 14, the guard ring 15, and the diffusion region 16 are formed by the same deposition process. That is, as shown in FIG. 2C (1), a resist film 23 is formed on the oxide film 11B, and then the resist film 23 is exposed and developed to form openings 23h1 and 23h2. Thereafter, as shown in FIG. 2C (2), the oxide film 11B exposed in the openings 23h1 and 23h2 is removed using the resist film 23 as an etching mask. Thereafter, the resist film 23 is removed. Further, the oxide film 12B on the back surface of the semiconductor wafer 10 is also removed. Thereafter, as shown in FIG. 2C (3), the second conductivity type impurity is introduced into the semiconductor wafer 10 from the region of the main surface 10a not covered with the oxide film 11B and the main surface 10b by the deposition method. . Impurities to be introduced are, for example, aluminum and boron. Thereby, the diffusion region 14, the guard ring 15, and the diffusion region 16 are formed. As shown in FIG. 2C (3), the heating in the diffusion process after the deposition process closes the opening of the oxide film 11B to form the oxide film 11C, and the main surface 10b of the semiconductor wafer 10 is formed. An oxide film 12C is formed.

  After forming the second conductivity type diffusion region 14, the first conductivity type diffusion region 17 (third diffusion region) is formed in the diffusion region 14 (step S15). The diffusion region 17 is also called an emitter. Here, a method for forming the diffusion region 17 will be described in detail. First, as shown in FIG. 2D (1), a resist film 24 is formed on the oxide film 11C, and then the resist film 24 is exposed and developed to form openings 24h1 and 24h2. The oxide film 12C is covered with a resist film so that the oxide film 12C is not removed by etching. Thereafter, as shown in FIG. 2D (2), the oxide film 11C exposed to the openings 24h1 and 24h2 is removed using the resist film 24 as an etching mask. Thereafter, the resist films 24 and 27 are removed. Thereafter, as shown in FIG. 2D (3), a first conductivity type (N-type) impurity is introduced into the region of the main surface 10a not covered with the oxide film 11C by a deposition method. Impurities to be introduced are, for example, phosphorus and arsenic. Thereby, the diffusion region 17 and the channel stopper 18 are formed. As shown in FIG. 2D (3), the heating in the diffusion process after the deposition process closes the opening of the oxide film 11C to form the oxide film 11D and the oxide film 12C on the main surface 10b. It becomes thicker and becomes an oxide film 12D.

  Next, a passivation film 31 is formed on the main surface 10a side of the semiconductor wafer 10 (step S16). In the present embodiment, as shown in FIG. 2E (1), the passivation film 31 is formed on the oxide film 11D. The passivation film 31 is, for example, PSG (Phosphor-Silicate Glass).

  Next, as shown in FIG. 2E (2), an etching mask 25 (first etching mask) for forming a contact window is formed on the passivation film 31 (step S17). The etching mask 25 is provided with an opening 25h1 and an opening 25h2.

  Next, as shown in FIG. 2E (2), an etching mask 26 (second etching mask) for forming a protective part is formed on the oxide film 12D on the main surface 10b (step S18). For example, the etching mask 26 is formed in a lattice shape along the dicing region.

  In addition, you may implement step S17 and S18 collectively as one process using a double-sided exposure method.

  Next, as shown in FIG. 2E (3), the passivation windows 31 and the oxide film 11D are etched using the etching mask 25, so that the contact windows 31h1 and 31h2 in which the main surface 10a of the semiconductor wafer 10 is exposed on the bottom surface are formed. Form (step S19). The diffusion region 17 is exposed on the bottom surface of the contact window 31h1, and the diffusion region 14 is exposed on the bottom surface of the contact window 31h2.

  Next, as shown in FIG. 2E (3), the oxide film 12D is etched using the etching mask 26 to form the wafer protection part 19 on the main surface 10b of the semiconductor wafer 10 (step S20, wafer protection part). Forming step). The wafer protection unit 19 is a protective film for protecting the main surface 10b from the subsequent sandblasting process. As shown in FIG. 3, the wafer protection unit 19 is formed in a lattice shape so as to surround each semiconductor device formation region R.

  Note that step S19 and step S20 may be performed simultaneously. That is, the main surface 10a side and the main surface 10b side may be etched simultaneously by immersing the semiconductor wafer 10 in an etching solution.

  The oxide film constituting the wafer protection unit 19 is a thermal oxide film of the semiconductor wafer 10 formed on the main surface 10b when the diffusion region 17 is formed. The thickness of the thermal oxide film is, for example, 0.5 to 3.0 μm. By securing such a thickness, the main surface 10b can be sufficiently protected from the sandblast treatment.

  The wafer protection unit 19 is an oxide film patterned in the present embodiment as described above, but may be another insulating film (for example, a nitride film or a resist film), or a metal film (Al , Ni, Ti, etc.). In addition, when the wafer protection part 19 is comprised with a resist film, the thickness of a resist film is 1.0-5.0 micrometers, for example. By securing such a thickness, the main surface 10b can be sufficiently protected from the sandblast treatment.

  After etching the oxide film 12D, the etching mask 26 is removed. By removing the etching mask 26, dust on the etching mask 26 can be prevented from being generated during the subsequent sandblasting process. Note that the etching mask 26 on the wafer protection unit 19 may be left as it is.

  Next, as shown in FIG. 2F (1), the main electrode 3 (first main electrode) and the control electrode 4 are formed (step S21). In the present embodiment, the main electrode 3 is a cathode electrode, and the control electrode 4 is a gate electrode. The main electrode 3 and the control electrode 4 are formed by filling the contact windows 31h1 and 31h2 with a conductive material by vapor deposition or the like. In addition, this step may be after the sandblasting process.

  After the wafer protection portion forming step, as shown in FIG. 2F (2), the main surface 10b of the semiconductor wafer 10 is subjected to sandblasting (step S22, sandblasting step). By irradiating the main surface 10b with the blast particles, as shown in FIG. 2F (3), irregularities are formed on the main surface 10b which is not covered with the wafer protection part 19. In the present embodiment, the area surrounded by the wafer protection unit 19 is roughened. On the other hand, the main surface 10b covered with the wafer protection part 19 is less affected by the sandblasting process.

  After the sandblasting process, as shown in FIG. 2G (1), a protective film 32 is formed so as to cover the main surface 10a side of the semiconductor wafer 10 (step S23). The protective film 32 is, for example, a polyimide film. Thereafter, as shown in FIG. 2G (2), contact windows 32h1 and 32h2 are formed in the protective film 32 (step S24). The main electrode 3 is exposed on the bottom surface of the contact window 32h1, and the control electrode 4 is exposed on the bottom surface of the contact window 32h2.

  Next, as shown in FIG. 2G (3), the conductive layer 20 is formed on the main surface 10b of the semiconductor wafer 10 (step S25). The conductive layer 20 is formed so as to embed the wafer protection unit 19. Note that it is not essential to leave the wafer protection part 19, and the wafer protection part 19 may be removed before the conductive layer 20 is formed.

  Next, the semiconductor wafer 10 on which the conductive layer 20 is formed is diced along the semiconductor device formation region R (step S26, dicing process). By this step, the semiconductor wafer 10 is divided into pieces, and a plurality of semiconductor devices are obtained (see FIG. 4). The conductive layer 20 is separated for each semiconductor device by this step and becomes a main electrode (in this embodiment, an anode electrode). In this step, the semiconductor wafer 10 is separated into pieces using a blade, but the present invention is not limited to this, and dicing may be performed by scribing or etching (chemical dicing).

  According to the semiconductor device manufacturing method described above, the sand blasting process is performed after the wafer protection portion 19 is formed on the main surface 10 b of the semiconductor wafer 10. Since the main surface 10b of the semiconductor wafer 10 in the region where the wafer protection unit 19 is formed is covered and protected by the wafer protection unit 19, damage due to sandblasting is reduced. Thereby, release of the internal stress on the main surface 10b side is suppressed. As a result, warpage of the semiconductor wafer 10 after the sandblasting process can be suppressed.

  In the wafer protection part forming step, the wafer protection part 19 is preferably formed in a mesh shape so as to cover the main surface 10b. The mesh shape includes shapes such as a lattice shape and a honeycomb shape. By forming the wafer protection part 19 in a mesh shape, a region in which damage is suppressed by the sand blasting process is formed in a mesh shape on the main surface 10b, so that the warpage of the semiconductor wafer 10 after the sand blasting process is more effectively suppressed. can do.

  Moreover, it is preferable to form the wafer protection part 19 in the dicing area RD in the wafer protection part formation step. In this case, the wafer protection unit 19 may be formed linearly along the dicing region RD, or a plurality of wafer protection units 19 may be formed in an island shape. By forming the wafer protection part 19 in the dicing region RD in this way, the effect of the sand blasting process for reducing the on-voltage of the semiconductor device and preventing the peeling of the electrode formed on the main surface 10b is effective. Can be avoided.

  In the wafer protection portion forming step, as shown in FIG. 3, it is preferable that the wafer protection portion 19 is formed in a lattice shape so as to surround each semiconductor device formation region R in the dicing region RD. Thereby, the curvature of the semiconductor wafer 10 after the sandblasting process can be more effectively suppressed while maintaining the effect of the sandblasting process.

  Further, in the manufacturing method described above, the thermal oxide film of the semiconductor wafer 10 is patterned to form the wafer protection part 19, but the present invention is not limited to this. For example, the wafer protection unit may be constituted by an etching mask. In this case, after the diffusion region 17 is formed, the oxide film 12D of the semiconductor wafer 10 formed on the main surface 10b when the diffusion region 17 is formed is removed. Then, a resist film having a predetermined pattern shape is formed on the main surface of the semiconductor wafer 10 as a wafer protection part. Further, the main surface 10 b may be protected by superposing a hard mask (for example, metal) having a predetermined shape such as a lattice shape on the main surface 10 b of the semiconductor wafer 10 before performing the sandblasting process. That is, you may comprise a wafer protection part with a hard mask.

  In the above manufacturing method, the isolation region 13 is formed, but the isolation region 13 may not be formed.

  Further, the manufacturing method according to the present embodiment is not limited to a thyristor, and can be applied to other vertical semiconductor devices such as a bidirectional thyristor (triac) and a power MOSFET.

<Semiconductor device>
A vertical semiconductor device 1 according to the embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 shows a cross-sectional view of the semiconductor device 1 obtained through the dicing process. FIG. 5 shows a bottom view of the semiconductor device 1.

  The semiconductor device 1 is a thyristor, and includes a first conductivity type semiconductor substrate 2, a second conductivity type diffusion region 14 (base), a second conductivity type guard ring 15, and a second conductivity type diffusion region 16. (First emitter), first conductivity type diffusion region 17 (second emitter), first conductivity type channel stopper 18, main electrode 3 (cathode electrode), control electrode 4 (gate electrode), A main electrode 5 (anode electrode) and an insulating portion 6 are provided.

  The semiconductor substrate 2 is obtained by dividing the semiconductor wafer 10 in a dicing process, and has a main surface 2a and a main surface 2b opposite to the main surface 2a. The diffusion region 14 is formed on the main surface 2 a, the diffusion region 16 is formed on the main surface 2 b, and the diffusion region 17 is formed in the diffusion region 14. The main electrode 3 is formed on the main surface 2 a and is in ohmic contact with the diffusion region 17. The control electrode 4 is formed on the main surface 2 a and is in ohmic contact with the diffusion region 14. The main electrode 5 is formed on the main surface 2 b and is in ohmic contact with the diffusion region 16.

  The insulating part 6 is a part of the wafer protection part 19 cut in the dicing process. As shown in FIGS. 4 and 5, the insulating portion 6 is provided on the peripheral portion of the main surface 2 b and is embedded in the main electrode 5.

  According to the semiconductor device of this embodiment, since the stress due to the insulating portion 6 acts on the peripheral portion of the semiconductor substrate 2 when the temperature changes due to a temperature cycle test or thermal fatigue test (intermittent energization) of the semiconductor device 1, It can prevent that a crack generate | occur | produces in the peripheral part of 2. FIG. Therefore, the reliability of the vertical semiconductor device can be improved.

  Based on the above description, those skilled in the art may be able to conceive additional effects and various modifications of the present invention, but the aspects of the present invention are not limited to the individual embodiments described above. . You may combine suitably the component covering different embodiment. Various additions, modifications, and partial deletions can be made without departing from the concept and spirit of the present invention derived from the contents defined in the claims and equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Main electrode 4 Control electrode 5 Main electrode 6 Insulation part 10 Semiconductor wafer 10a, 10b Main surface 11A, 12A Oxide film 13 Isolation area | region 14 Diffusion area | region (base)
15 Guard ring 16 Diffusion region (first emitter)
17 Diffusion region (second emitter)
18 Channel stopper 19 Wafer protection part 20 Conductive layers 21, 22, 23, 24, 27 Resist films 25, 26 Etching mask 31 Passivation film 32 Protection film R Semiconductor device formation area RD Dicing area

Claims (14)

Providing a first conductivity type semiconductor wafer having a first main surface and a second main surface opposite to the first main surface;
Forming a second diffusion type first diffusion region on the first main surface;
Forming a second conductivity type second diffusion region on the second main surface of the semiconductor wafer;
Forming a first conductivity type third diffusion region in the first diffusion region;
A wafer protection part forming step for forming a wafer protection part for protecting the second main surface from sandblasting on the second main surface of the semiconductor wafer;
After the wafer protection part forming step, a sand blasting step for performing a sand blasting process on the second main surface of the semiconductor wafer;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the wafer protection portion forming step, the wafer protection portion is formed in a mesh shape so as to cover the second main surface.   The said wafer protection part is formed in the dicing area | region containing the cutting line for dividing the said semiconductor wafer into a several semiconductor device formation area in the said wafer protection part formation process, The Claim 1 or 2 characterized by the above-mentioned. A method for manufacturing a semiconductor device.   4. The method of manufacturing a semiconductor device according to claim 3, wherein, in the wafer protection portion forming step, the wafer protection portion is formed in a lattice shape so as to surround each of the semiconductor device formation regions. After the sandblasting process,
Forming a protective film so as to cover the first main surface side of the semiconductor wafer;
Forming a contact window in the protective film;
Forming a conductive layer on the second main surface of the semiconductor wafer;
A dicing step of dicing the semiconductor wafer on which the conductive layer is formed along the semiconductor device formation region;
The method of manufacturing a semiconductor device according to claim 3, further comprising: The wafer protection part forming step includes:
Forming an etching mask on the oxide film on the second main surface;
An etching step of forming the wafer protection unit by etching the oxide film using the etching mask;
The method for manufacturing a semiconductor device according to claim 1, wherein:   The method of manufacturing a semiconductor device according to claim 6, wherein the etching mask is removed after the etching step, and then the sandblasting step is performed.   7. The oxide film constituting the wafer protection part is a thermal oxide film of the semiconductor wafer formed on the second main surface when the third diffusion region is formed. Or a method of manufacturing a semiconductor device according to 7;   The method of manufacturing a semiconductor device according to claim 8, wherein the oxide film has a thickness of 0.5 to 3.0 μm. The wafer protection part forming step includes:
Removing the oxide film on the second main surface of the semiconductor wafer;
Forming a resist film having a predetermined pattern shape on the second main surface as the wafer protection portion;
The method for manufacturing a semiconductor device according to claim 1, wherein:   The method of manufacturing a semiconductor device according to claim 1, wherein the second diffusion region is of a second conductivity type.   12. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. A first conductivity type semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
A first diffusion region of a second conductivity type formed on the first main surface;
A second diffusion region formed on the second main surface;
A third diffusion region of the first conductivity type formed in the first diffusion region;
A first main electrode formed on the first main surface and in ohmic contact with the third diffusion region;
A control electrode formed on the first main surface and in ohmic contact with the first diffusion region;
A second main electrode formed on the second main surface and in ohmic contact with the second diffusion region;
An insulating portion provided at a peripheral portion of the second main surface and embedded in the second main electrode;
A semiconductor device comprising:   The semiconductor device according to claim 13, wherein the second diffusion region is of a second conductivity type, and the semiconductor device is a thyristor.

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