JP2019140150A5

JP2019140150A5 -

Info

Publication number: JP2019140150A5
Application number: JP2018019434A
Authority: JP
Filing date: 2018-02-06
Publication date: 2019-11-28
Anticipated expiration: 2038-02-06

Description

本発明の半導体装置の製造方法は、主面側に剥離層が形成された支持基板を用意すること、前記支持基板上の前記剥離層よりも上に、部分的に配線層および層間絶縁膜を形成すること、半導体チップのパッドの少なくとも一部が、前記配線層の少なくとも一部に電気的に接続するように、前記半導体チップを前記支持基板上に配置すること、前記配線層の少なくとも一部、前記層間絶縁膜の少なくとも一部、および前記半導体チップを包含するとともに、前記支持基板上の前記剥離層またはそれよりも上の層と接触する封止層を形成し、前記支持基板上に、前記半導体チップおよび前記配線層、前記封止層を含む中間積層体を形成すること、前記中間積層体を形成した後に、前記支持基板の周辺部であって前記封止層が形成されている部分を切断すること、および、前記周辺部を切断した前記支持基板から、前記剥離層を境界として、前記中間積層体を機械的に剥離すること、とを含む。 According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: preparing a support substrate having a release layer formed on a main surface side; and partially forming a wiring layer and an interlayer insulating film on the support substrate above the release layer. Forming the semiconductor chip on the support substrate such that at least a part of the pad of the semiconductor chip is electrically connected to at least a part of the wiring layer, and at least a part of the wiring layer. Forming a sealing layer that includes at least a part of the interlayer insulating film and the semiconductor chip , and is in contact with the release layer on the support substrate or a layer above it, on the support substrate, Forming the intermediate laminated body including the semiconductor chip, the wiring layer, and the sealing layer, and a portion where the sealing layer is formed around the support substrate after the intermediate laminated body is formed The It is cross, and, from the supporting substrate obtained by cutting the peripheral portion, the peeling layer as a boundary, mechanically peeled to be the intermediate laminate, including capital.

Claims

Preparing a support substrate having a release layer formed on the main surface side;
Forming a wiring layer and an interlayer insulating film partially above the release layer on the support substrate;
Disposing the semiconductor chip on the support substrate such that at least a part of the pad of the semiconductor chip is electrically connected to at least a part of the wiring layer;
Forming at least part of the wiring layer, at least part of the interlayer insulating film, and the semiconductor chip , and forming a sealing layer in contact with the release layer on the support substrate or a layer above it; Forming an intermediate laminate including the semiconductor chip, the wiring layer, and the sealing layer on the support substrate;
After forming the intermediate laminate, cutting a portion around the support substrate, where the sealing layer is formed ,
The intermediate laminated body is mechanically peeled from the support substrate cut at the peripheral portion with the release layer as a boundary.

In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the cutting, a portion of the periphery of the support substrate where the sealing layer and the interlayer insulating film are formed is cut.

In the manufacturing method of the semiconductor device according to claim 1 or 2 ,
The cutting of the peripheral portion of the support substrate is
Forming a cutting line on the periphery of the support substrate;
Cutting the release layer and the sealing layer formed on the support substrate from the main surface side of the support substrate at a position corresponding to the planned cutting line;
Cleaving a peripheral portion of the support substrate along the planned cutting line.

In the manufacturing method of the semiconductor device according to claim 3 ,
The method of manufacturing the semiconductor device is performed by forming a cut line on the back surface of the support substrate.

In the manufacturing method of the semiconductor device according to claim 4 ,
The cut line is formed after the intermediate laminate is formed on the support substrate.

In the manufacturing method of the semiconductor device according to claim 4 ,
The cut line is formed before the wiring layer is formed on the support substrate.

In the manufacturing method of the semiconductor device according to claim 3 ,
The method of manufacturing the semiconductor device is performed by forming a cut line on a main surface of the support substrate before forming the release layer.

In the manufacturing method of the semiconductor device according to claim 3 ,
The method of manufacturing a semiconductor device is performed by forming a parting line that is weaker than other parts inside the support substrate.

In the manufacturing method of the semiconductor device as described in any one of Claim 1- Claim 8,
A method for manufacturing a semiconductor device, wherein a glass substrate is used as the support substrate.

In the manufacturing method of the semiconductor device as described in any one of Claim 1- Claim 9 ,
A manufacturing method of a semiconductor device using a supporting substrate in which a metal layer, a peeling layer, and a thin copper layer are formed in order from the substrate side on the main surface as the supporting substrate.

In the manufacturing method of the semiconductor device according to any one of claims 1 to 10 ,
A method of manufacturing a semiconductor device, wherein the wiring layer is formed a plurality of times to form a multilayer wiring type wiring layer.

In the manufacturing method of the semiconductor device as described in any one of Claim 1- Claim 11 ,
A plurality of the intermediate laminates are formed in parallel on the support substrate, and the intermediate laminates formed in parallel are peeled from the support substrate integrally, and the intermediate laminate is formed after the peeling. A method of manufacturing a semiconductor device in which a body is cut individually.

In the manufacturing method of the semiconductor device according to any one of claims 1 to 12 ,
A method of manufacturing a semiconductor device, wherein a plurality of the semiconductor chips are arranged in the intermediate laminate.

In the manufacturing method of the semiconductor device according to any one of claims 1 to 13 ,
A method of manufacturing a semiconductor device, wherein passive components are arranged together with the semiconductor chip in the intermediate laminate.