JP2019129172A - Circuit board, manufacturing method of circuit board, electronic apparatus and manufacturing method of electronic apparatus - Google Patents

Abstract

To realize a circuit board that has high performance and reliability.SOLUTION: A circuit board 10A comprises: a resin layer 1; a wiring structure 11 that is provided above the resin layer 1; and a resin layer 2 that is provided above the resin layer 1 and that covers the wiring structure 11. A material layer 7 including siloxane linkages is provided between the resin layer 1 and the resin layer 2. Remaining or adhesion of an unnecessary conductive material around the wiring structure 11 is suppressed by the material layer 7 provided between the resin layer 1 and the resin layer 2, and occurrence of electric leak or ionic migration, and occurrence of an electrical failure such as a short circuit caused thereby are suppressed.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a circuit board, a method of manufacturing a circuit board, an electronic device, and a method of manufacturing an electronic device.

  A semi-additive method is known as one of the wiring layer forming techniques for circuit boards. In the semi-additive method, the adhesion layer and the seed layer are formed on the insulating resin layer, and the wiring layer is formed in the opening of the resist formed thereon by electrolytic plating using the seed layer for feeding. Thereafter, the resist is removed, and the exposed portions of the seed layer and the adhesion layer are removed by etching. Besides this, there is also known a technique in which the exposed portion of the adhesion layer is oxidized by oxidation after the resist is removed and the seed layer is removed. By such a method, a wiring layer electrically isolated from other conductors on the resin layer is formed.

  In addition, a technique is known in which a barrier layer is further formed on the surface of the wiring layer by electroless plating in order to prevent the components of the formed wiring layer from diffusing to the outside.

Japanese Patent Application Laid-Open No. 10-233579 JP, 2014-135385, A

  In the semi-additive method as described above, a portion of the seed layer and the adhesion layer which are not removed by etching remain on the surface exposed around the formed wiring layer, or the wiring layer exposed to the etching Ingredients may be attached.

  The conductive substance remaining or attached to the surface around the wiring layer in this way causes electrical leakage and ion migration in the circuit board, and may cause an electrical failure such as a short circuit. In addition, when a barrier layer is formed on the surface of the wiring layer by electroless plating, such a conductive substance becomes a nucleus, abnormal deposition occurs on the surface around the wiring layer, and a short circuit in a circuit board, etc. Electrical failure may be more likely to occur.

  According to one aspect, a first resin layer, a wiring structure provided above the first resin layer, a second resin layer provided above the first resin layer and covering the wiring structure, A circuit board is provided which is provided between a first resin layer and the second resin layer and has a material layer containing a siloxane bond.

  In addition, according to one aspect, a method for manufacturing the circuit board as described above, an electronic device using the circuit board as described above, and a method for manufacturing the same are provided.

  A circuit board with high performance and reliability, which can suppress electrical defects, is realized. In addition, an electronic device with high performance and reliability using such a circuit board is realized.

It is a figure showing an example of the circuit board concerning a 1st embodiment. FIG. 7 is a first view showing an example of a method of forming a circuit board according to the first embodiment; FIG. 7 is a second diagram showing an example of a method of forming a circuit board according to the first embodiment; It is FIG. (1) which shows an example of the formation method of the circuit board which concerns on another form. It is FIG. (2) which shows an example of the formation method of the circuit board which concerns on another form. It is a figure which shows an example of the circuit board which concerns on 2nd Embodiment. It is a figure (the 1) showing an example of the formation method of the circuit board concerning a 2nd embodiment. It is a figure (the 2) showing an example of the formation method of the circuit board concerning a 2nd embodiment. It is a figure which shows an example of the circuit board which concerns on 3rd Embodiment. It is a figure (the 1) showing an example of the formation method of the circuit board concerning a 3rd embodiment. It is FIG. (2) which shows an example of the formation method of the circuit board which concerns on 3rd Embodiment. It is a figure which shows an example of the circuit board which concerns on 4th Embodiment. It is a figure (the 1) showing an example of the formation method of the circuit board concerning a 4th embodiment. It is FIG. (2) which shows an example of the formation method of the circuit board which concerns on 4th Embodiment. It is a figure showing the example of the 1st composition of the circuit board concerning a 5th embodiment. It is a figure showing the example of the 2nd composition of the circuit board concerning a 5th embodiment. It is a figure showing the example of the 3rd composition of the circuit board concerning a 5th embodiment. It is a figure showing the example of the 4th composition of the circuit board concerning a 5th embodiment. It is a figure (the 1) showing an example of the formation method of the circuit board concerning a 5th embodiment. It is FIG. (2) which shows an example of the formation method of the circuit board which concerns on 5th Embodiment. FIG. 31 is a third diagram illustrating an example of a method of forming a circuit board according to a fifth embodiment; It is a figure which shows the circuit board of a comparative example. It is a figure which shows the 1st structural example of the electronic device which concerns on 6th Embodiment. It is a figure showing the 2nd example of composition of the electronic device concerning a 6th embodiment. It is explanatory drawing of the electronic device which concerns on 7th Embodiment.

First, the first embodiment will be described.
FIG. 1 is a diagram illustrating an example of a circuit board according to the first embodiment. FIG. 1 schematically shows a cross section of an essential part of an example of a circuit board.

  A circuit board 10A shown in FIG. 1 includes a resin layer 1, a resin layer 2, a resin layer 3, an adhesion layer 4, a seed layer 5a, a wiring layer 5, a barrier layer 6, and a material layer 7. In the circuit board 10 </ b> A, the adhesion layer 4 is provided on the resin layer 1 via the resin layer 3, and the seed layer 5 a and the wiring layer 5 are provided on the adhesion layer 4. A barrier layer 6 is provided on the surface of the wiring layer 5 and the seed layer 5a. A resin layer 2 is provided on the resin layer 1 so as to cover the resin layer 3, the adhesion layer 4, the seed layer 5 a, the wiring layer 5, and the barrier layer 6. A material layer 7 is provided between the resin layer 1 and the resin layer 2.

  Although one wiring structure 11 including the adhesion layer 4, the seed layer 5a, and the wiring layer 5 provided on the resin layer 3 is illustrated in FIG. 1, such a wiring structure is provided for the circuit board 10A. A plurality of eleven may be included. In that case, a barrier layer 6 may be provided on the surfaces of the wiring layer 5 and the seed layer 5a of each wiring structure 11.

  In the circuit board 10 </ b> A shown in FIG. 1, various resin materials functioning as a permanent interlayer film are used for the resin layer 1, the resin layer 2, and the resin layer 3. For example, for the resin layer 1, the resin layer 2, and the resin layer 3, a resin material containing one or more of phenol resin, acrylic resin, epoxy resin, imide resin, and amide resin is used. The resin material used for the resin layer 1, the resin layer 2, and the resin layer 3 contains an insulating filler such as glass, silica, and alumina in order to suppress deformation such as curing shrinkage when applied and cured. May be The resin material used for the resin layer 1, the resin layer 2 and the resin layer 3 may be photosensitive or non-photosensitive. The resin materials used for the resin layer 1, the resin layer 2 and the resin layer 3 may be the same as or different from each other.

  For the adhesion layer 4, various materials having a function of improving adhesion between the seed layer 5 a and the wiring layer 5 provided thereon and the underlying layer (resin layer 3 in this example) are used. . For example, various metal materials such as titanium (Ti), aluminum (Al), and zirconium (Zr) are used for the adhesion layer 4. The adhesion layer 4 may be made of one or more materials. The adhesion layer 4 may have a single layer structure or a laminated structure.

  Various conductor materials are used for the wiring layer 5. For example, a metal material such as copper (Cu) or Al is used for the wiring layer 5. The wiring layer 5 is formed by electrolytic plating as described later. A seed layer 5 a is formed on the adhesion layer 4, and the seed layer 5 a is used for power feeding at the time of electrolytic plating to form a wiring layer 5. For the seed layer 5a, various conductor materials capable of forming the wiring layer 5 by electrolytic plating are used. For example, when Cu is used for the wiring layer 5, Cu or nickel (Ni) or a material containing Cu and Ni is used for the seed layer 5a.

  For the barrier layer 6, various materials having a function of suppressing the diffusion of the conductor material component such as Cu contained in the wiring layer 5 and the seed layer 5a to the outside of the wiring layer 5 and the seed layer 5a are used. For example, for the barrier layer 6, a conductor material having a higher resistance than the conductor material used for the wiring layer 5 and the seed layer 5a is used. For example, when Cu is used for the wiring layer 5, the barrier layer 6 may be made of one of Ni, phosphorus (P), cobalt (Co), boron (B), tungsten (W) and palladium (Pd). Two or more conductor materials are used. The barrier layer 6 is formed by electroless plating as described later.

  A material different from that of the resin layer 1, the resin layer 2, and the resin layer 3 is used for the material layer 7. For the material layer 7, for example, a material containing a siloxane bond is used. Here, the material containing a siloxane bond includes various compounds having a siloxane bond as a skeleton, such as siloxane, polysiloxane, and silicone. The material containing a siloxane bond may be a mixture of various compounds having a siloxane bond in the skeleton and other compounds (resin, additives, etc.). For example, the material layer 7 is made of an organic siloxane having an organic group, an inorganic siloxane having no organic group, or a material mainly composed of an organic siloxane or an inorganic siloxane. The material layer 7 may include both an organic siloxane or a material mainly composed thereof and an inorganic siloxane or a material mainly composed thereof.

Next, a method for forming the circuit board 10A having the above configuration will be described.
2 and 3 are diagrams illustrating an example of a method of forming a circuit board according to the first embodiment. FIGS. 2A to 2C and FIGS. 3A to 3C schematically show the cross-sections of the main parts of each process of circuit board formation.

First, a structure as shown in FIG. 2A, that is, a structure in which the material layer 7, the resin layer 3, the adhesion layer 4, and the seed layer 5a are sequentially laminated on the resin layer 1 is prepared.
Here, for the material layer 7, various materials that can be formed on the resin layer 1 and in which a siloxane bond is included in the layer after formation are used. However, in the case of an SOG (Spin On Glass) material, it is necessary to select a material whose baking temperature does not exceed the heat resistance temperature of the resin material used for the circuit board 10A.

For the material layer 7, for example, a silicon-containing material represented by the following formula (1), formula (2) or formula (3) is used.
(R ² R ^{2 ′} -SiO _2/2 ) _e (O _1/2 R ¹ ) _f (1)
(R ³ —SiO _3/2 ) _c (O _1/2 R ¹ ) _d (2)
(SiO _4/2 ) _a (O _1/2 R ⁴ ) _b (3)
In these formulas (1) to (3), R ¹ , R ² , R ^{2 ′} , R ³ and R ⁴ are each independently hydrogen, an alkyl group or a triorganosilyl group, or an alkyl group or a triorgano group It is a derivative of silyl group. a to f represent composition ratios, and a, c and e are integers of 1 or more, and b, d and f are integers of 0 or more. Terms whose composition ratios are a, c, and e represent the skeleton structure of the silicon-containing material. Formula (1) represents a difunctional siloxane, formula (2) represents a trifunctional siloxane, and formula (3) represents a tetrafunctional siloxane.

Silicon-containing materials represented by the formulas (1) to (3) (wherein R ¹ , R ² , R ^{2 ′} , R ³ , R ⁴ ) or silicon-containing materials represented by the formulas (1) to (3) The additive added to the material may contain a functional group (photosensitive group) that is reactive to light such as ultraviolet light. The silicon-containing material represented by Formulas (1) to (3) can be obtained by including such a photosensitive group in the silicon-containing material represented by Formulas (1) to (3) or the additive thereof. It is cured by light irradiation.

Silicon-containing materials represented by the formulas (1) to (3) (wherein R ¹ , R ² , R ^{2 ′} , R ³ , R ⁴ ) or silicon-containing materials represented by the formulas (1) to (3) The additive added to the material may contain a functional group that is reactive to heat. The silicon-containing material represented by Formula (1)-(3) is heated by such a functional group being contained in the silicon-containing material represented by Formula (1)-(3), or its additive. Hardened by

  The thickness of the material layer 7 formed on the resin layer 1 is, for example, 10 nm to 500 nm. If the thickness of the material layer 7 is thinner than 10 nm, good film formability may not be obtained, and if the thickness of the material layer 7 is thicker than 500 nm, the resin layer 1 is formed thereon In some cases, cracks and peeling may easily occur at the interface with the resin layer 3 or the resin layer 2.

  As a method for forming the material layer 7, when a photocurable material as described above is used, the material applied on the resin layer 1 by spin coating or spray coating or the like is irradiated with light. Curing is performed to form the material layer 7. When the thermosetting material as described above is used, the material applied on the resin layer 1 by spin coating or spray coating is cured by heating, so that the material layer 7 is formed. It is formed. Besides, the material layer 7 may be formed on the resin layer 1 by using a CVD (Chemical Vapor Deposition) method.

  A resin layer 3 is formed on the material layer 7 formed on the resin layer 1, an adhesion layer 4 is formed on the resin layer 3, and a seed layer 5 a is further formed on the adhesion layer 4. For example, Ti with a thickness of 20 nm is formed as the adhesion layer 4 by sputtering, and Cu with a thickness of 50 nm is formed as the seed layer 5a by sputtering.

  Next, as shown in FIG. 2B, a resist 8 having an opening 8a in the region where the wiring layer 5 is to be formed is formed on the seed layer 5a. Then, the wiring layer 5 is formed in the opening 8a of the resist 8 by electroplating using the seed layer 5a for power supply. After the wiring layer 5 is formed, the resist 8 is removed. Thereby, a state as shown in FIG. 2 (C) is obtained.

  Next, as shown in FIG. 3A, the seed layer 5a exposed after the removal of the resist 8 and the adhesion layer 4 thereunder are removed, and the resin layer 3 exposed after the removal of the adhesion layer 4 is removed . For example, the seed layer 5a formed using Cu is removed by wet etching, and the adhesion layer 4 using Ti is removed by dry etching. Further, the resin layer 3 is dug down by dry etching until the material layer 7 is exposed. Thereby, the state where the material layer 7 is exposed on the surface of the wiring structure 11 including the adhesion layer 4 and the seed layer 5a and the wiring layer 5 provided thereon as shown in FIG. can get.

After the state where the material layer 7 is exposed on the surface around the wiring structure 11 is obtained in this manner, the cleaning process using the cleaning material may be performed.
Next, as shown in FIG. 3B, the barrier layer 6 is formed on the surfaces of the wiring layer 5 and the seed layer 5a. The barrier layer 6 is formed by electroless plating. For example, nickel phosphorus (NiP) with a thickness of 70 nm is formed as the barrier layer 6. Thereafter, as shown in FIG. 3C, the resin layer 2 is formed so as to cover the resin layer 3, the adhesion layer 4, the seed layer 5 a and the wiring layer 5.

As described above, the circuit board 10A is formed by the steps shown in FIGS. 2 (A) to 2 (C) and 3 (A) to 3 (C).
As described above, in the formation of the circuit board 10A, the seed layer 5a, the adhesion layer 4 and the resin layer 3 are partially removed by etching after the step of FIG. 2C, as shown in FIG. 3A. A state in which the material layer 7 is exposed is obtained. As a result, generation of unnecessary conductive material in the process of forming the circuit board 10A and abnormal deposition of unnecessary conductive material at the time of formation of the barrier layer 6 resulting therefrom can be effectively suppressed. Hereinafter, this point will be further described.

  First, for comparison, an example of a method of forming a circuit board according to another embodiment will be described with reference to FIGS. 4 and 5. FIGS. 4A to 4C and FIGS. 5A to 5C schematically show a cross section of a main part of each step in an example of a method for forming a circuit board.

  In this example, a structure as shown in FIG. 4A, that is, a structure in which the adhesion layer 4 and the seed layer 5a are sequentially laminated on the resin layer 1 is prepared. The adhesion layer 4 and the seed layer 5a are formed by sputtering. Next, as shown in FIG. 4B, a resist 8 having an opening 8a in a region where the wiring layer 5 is to be formed is formed on the seed layer 5a. Then, the wiring layer 5 is formed in the opening 8a of the resist 8 by electroplating using the seed layer 5a for power supply. After the wiring layer 5 is formed, the resist 8 is removed. Thereby, a state as shown in FIG. 4C is obtained.

  Next, as shown in FIG. 5A, the seed layer 5a exposed after the removal of the resist 8 and the adhesion layer 4 therebelow are removed by etching. In the case of this etching, unnecessary conductive substance 9 may be generated on the surface of resin layer 1 exposed by the etching of adhesion layer 4. The conductive substance 9 is a part of the seed layer 5 a and the adhesion layer 4 which are not removed by the etching, or a part of the wiring layer 5 exposed to the etching.

  After the etching of the seed layer 5 a and the adhesion layer 4, as shown in FIG. 5B, the barrier layer 6 is formed on the surface of the wiring layer 5 by electroless plating. During the electroless plating, when the conductive substance 9 is generated on the surface of the resin layer 1 as described above, the conductive substance 9 becomes a nucleus, and the electroless plating is abnormally deposited on the surface of the resin layer 1 The conductive substance 9 may be generated.

  From such a state, as shown in FIG. 5C, the adhesion layer 4, the seed layer 5a, the wiring layer 5 and the barrier layer 6 are covered with the resin layer 2 to obtain the circuit board 10a. However, in the circuit board 10a obtained in this manner, the conductive substance 9 generated around the wiring layer 5 or the like may cause an electrical leak or ion migration, which may cause an electrical failure such as a short.

  In order to remove the conductive substance 9 (FIG. 5 (A)) generated on the surface of the resin layer 1, before the electroless plating (FIG. 5 (B)) for forming the barrier layer 6, a strong acid, a strong base, etc. When the cleaning process using this cleaning material is performed, the wiring layer 5 and the resin layer 1 may be damaged. The damage generated in the wiring layer 5 and the resin layer 1 may lead to a decrease in performance and reliability of the circuit board 10 a to be obtained. In particular, when the design dimensions (line and space L / S and height) of the wiring layer 5 are as small as 5 μm or less, the wiring layer 5 and the resin layer 1 are easily damaged by such cleaning, The influence of the damage on the performance and reliability of the circuit board 10a tends to increase.

  As a method of suppressing the influence of the conductive substance 9 generated on the surface of the resin layer 1 regardless of the cleaning as described above, the method of digging the resin layer 1 to a position below the adhesion layer 4 by etching A method has been proposed in which the basic substance 9 is oxidized and removed by etching. However, all of these methods attempt to remove the conductive substance 9 once generated (remaining or adhered) on the surface of the resin layer 1 by using etching. On the other hand, the amount and state of generation of the conductive substance 9 may greatly vary when the wiring structure, for example, the height and width of the wiring, the wiring layout, the material of the resin layer 1 and the like are changed. Therefore, the conductive material 9 may not be sufficiently removed, and the circuit board 10a having high performance and reliability may not be obtained. Moreover, the component from the wiring layer 5 etc. exposed to the etching performed in order to remove the electroconductive substance 9 adheres to the surface of the resin layer 1 as a new electroconductive substance 9, and causes electrical leak and ion migration. It could be

  On the other hand, in the method of forming the circuit board 10A (FIGS. 2 and 3), the material layer 7 is provided on the resin layer 1, the seed layer 5a, the adhesion layer 4 and the resin layer 3 are etched to form the surface. , And expose the material layer 7 containing a siloxane bond.

  According to the method of forming the circuit board 10A, even if the unnecessary conductive substance 9 is generated on the surface of the resin layer 3 by the etching of the seed layer 5a and the adhesion layer 4, the resin layer 3 is dug by etching. The conductive substance 9 can be removed. Further, the material layer 7 containing a siloxane bond, which is exposed to the surface by digging the resin layer 3 by etching, is unnecessary conductive substance 9 (seed layer as described above, as compared with the resin layer 3 and the resin layer 1. It is difficult for the residue 5a or the residue of the adhesion layer 4 or the component from the wiring layer 5 to adhere. Further, the material layer 7 containing a siloxane bond is less damaged by cleaning than the resin layer 3 and the resin layer 1 even when cleaning is performed using a cleaning material capable of removing unnecessary conductive substances 9. It is hard to receive. As described above, in the method of forming the circuit board 10A, the remaining and adhesion of the unnecessary conductive substance 9 can be suppressed. Therefore, abnormal deposition of the electroless plating can be suppressed when the barrier layer 6 is formed by the electroless plating. According to the method of forming the circuit board 10A, it is possible to effectively suppress the occurrence of electrical defects such as electrical leaks, ion migration, and shorts thereby, and realize the circuit board 10A with high performance and reliability. It will be possible to

  In this example, the barrier layer 6 is provided on the surface of the seed layer 5a and the wiring layer 5. However, the resin layer 2 covering the seed layer 5a and the wiring layer 5 may be provided without providing the barrier layer 6. In this case, the same effect as described above can be obtained. That is, it is possible to suppress the occurrence of electrical defects such as electrical leakage and ion migration due to unnecessary conductive substances 9 (residues of the seed layer 5a or the adhesion layer 4 and components from the wiring layer 5) and shorts caused thereby. it can.

  Although the wiring structure 11 including the adhesion layer 4 and the seed layer 5a and the wiring layer 5 provided thereon is taken as an example here, a configuration in which the adhesion layer 4 is not provided may be adopted as the wiring structure 11. it can. In this case as well, the occurrence of electrical leakage and ion migration due to unnecessary conductive material 9 (residue of seed layer 5a and components from wiring layer 5) can be suppressed as described above.

  Further, although the wiring structure 11 formed using the semi-additive method is taken as an example here, the wiring structure formed using the subtractive method (wiring structure not including the adhesion layer and the seed layer as described above) The same effect as described above can be obtained by adopting the above-described method of providing the material layer 7. That is, when the wiring structure is formed using the subtractive method, the components from the wiring structure exposed to the etching can be prevented from adhering to the periphery, and the occurrence of electrical leakage and ion migration due to the adhesion can be suppressed.

  In addition, the material layer 7 containing a siloxane bond has higher moisture resistance than the resin layer 1, the resin layer 2 and the resin layer 3. For example, in a circuit board in which the material layer 7 is not provided, when moisture enters from the outside, the dielectric constant of the resin layer changes and the transmission characteristics deteriorate, or the wiring layer is caused by an organic acid generated by hydrolysis of the resin layer. May corrode or ion migration may increase under applied voltage. As a result, in the circuit board in which the material layer 7 is not provided, the performance and the reliability may be reduced. On the other hand, in the circuit board 10A, by providing the material layer 7 having moisture resistance, it is possible to effectively suppress the intrusion and diffusion of moisture from the outside to the inner layer of the circuit board 10A. A highly reliable circuit board 10A can be realized.

Next, a second embodiment will be described.
FIG. 6 is a diagram illustrating an example of a circuit board according to the second embodiment. FIG. 6 schematically shows a cross-section of the main part of an example of the circuit board.

  The circuit board 10B shown in FIG. 6 is characterized in that the opening 7a is provided at a position corresponding to the adhesion layer 4 (as well as the seed layer 5a and the wiring layer 5 thereon) of the material layer 7. This is different from the circuit board 10A described in the above embodiment. In the circuit board 10B shown in FIG. 6, the resin layer 3 is provided in the opening 7a of the material layer 7 in contact with the resin layer 1 below the material layer 7, and the adhesion layer 4 and the seed layer 5a are formed on the resin layer 3. And the wiring layer 5 is stacked to form a wiring structure 12.

The circuit board 10B having such a configuration is formed as follows, for example.
7 and 8 are diagrams illustrating an example of a circuit board forming method according to the second embodiment. FIGS. 7A to 7C and FIGS. 8A to 8C schematically show cross sections of relevant parts of each process of circuit board formation.

First, a structure as shown in FIG. 7A, that is, a structure in which the material layer 7, the resin layer 3, the adhesion layer 4, and the seed layer 5a are sequentially laminated on the resin layer 1 is prepared.
Here, the material layer 7 is obtained, for example, by applying and curing a silicon-containing material such as the formulas (1) to (3) described in the first embodiment on the resin layer 1. It is done. If the silicon-containing material is photosensitive, the opening portion 7a of the material layer 7 is irradiated with light using a predetermined mask after application, is cured by applying a photolithography technique, and is irradiated (uncured). It is formed by removing the site. If the silicon-containing material is non-photosensitive, it is formed by applying and curing using an etching technique, and then removing a portion where the opening 7a is to be formed by etching using a predetermined mask. The resin layer 3 is formed on the resin layer 1 on which the material layer 7 having the opening 7a is formed, and the adhesion layer 4 and the seed layer 5a are formed thereon by sputtering, as shown in FIG. Such a structure is obtained. The resin layer 1 and the resin layer 3 are in contact with each other through the opening 7 a of the material layer 7.

  Thereafter, as shown in FIG. 7B, a resist 8 having an opening 8a is formed in a region where the wiring layer 5 is to be formed. Then, after the formation of the wiring layer 5 by electrolytic plating using the seed layer 5a for power feeding, the resist 8 is removed. Thereby, a state as shown in FIG. 7C is obtained.

  Next, as shown in FIG. 8A, the seed layer 5a exposed after the removal of the resist 8 and the adhesion layer 4 therebelow are removed by etching, and further, the resin layer 3 exposed after the removal of the adhesion layer 4 is etched. Removed by As a result, a state in which the material layer 7 is exposed on the peripheral surface of the wiring structure 12 including the seed layer 5a and the wiring layer 5 provided on the adhesion layer 4 as shown in FIG. 8A is obtained. .

  Next, as shown in FIG. 8B, the barrier layer 6 is formed on the surfaces of the wiring layer 5 and the seed layer 5a by electroless plating. Thereafter, as shown in FIG. 8C, the resin layer 2 is formed to cover the resin layer 3, the adhesion layer 4, the seed layer 5 a, the wiring layer 5 and the barrier layer 6.

As described above, the circuit board 10B is formed by the steps shown in FIGS. 7A to 7C and FIGS. 8A to 8C.
As described above, also in the method of forming the circuit board 10B, the seed layer 5a, the adhesion layer 4 and the resin layer 3 are etched to expose the material layer 7 including a siloxane bond on the surface (FIG. 8A and FIG. 8). (B)). By digging the resin layer 3 by etching, unnecessary conductive substances that may be generated on the surface can be removed, and further, by exposing the material layer 7 including the siloxane bond by digging, unnecessary conductive The adhesion of substances can be suppressed. Since the remaining and adhesion of the unnecessary conductive substance can be suppressed, abnormal deposition of the electroless plating can be suppressed when the barrier layer 6 is formed by the electroless plating. According to the method for forming the circuit board 10B, it is possible to effectively suppress the occurrence of electrical defects such as electrical leaks, ion migration, and shorts thereby, and realize the circuit board 10B with high performance and reliability. It will be possible to

  Here, the case where the barrier layer 6 is provided on the surface of the seed layer 5 a and the wiring layer 5 is taken as an example, but the resin layer 2 covering the seed layer 5 a and the wiring layer 5 may be provided without providing the barrier layer 6. In this case, the same effect as described above can be obtained.

  Although the wiring structure 12 including the adhesion layer 4 and the seed layer 5 a and the wiring layer 5 provided thereon is taken as an example here, it is also possible to adopt a configuration without the adhesion layer 4 as the wiring structure 12. it can. Also in this case, it is possible to obtain the same effect as described above.

  Furthermore, although the wiring structure 12 formed using the semi-additive method is taken as an example here, the wiring structure formed using the subtractive method (wiring structure not including the adhesion layer and the seed layer as described above) For the above, the same effect as described above can be obtained by adopting the above-described method of providing the material layer 7.

Further, in the circuit board 10B, by providing the material layer 7 having moisture resistance, it is possible to effectively suppress the penetration and diffusion of moisture from the outside into the inner layer of the circuit board 10B.
Further, in the circuit board 10 B, the resin layer 3 on which the adhesion layer 4, the seed layer 5 a and the wiring layer 5 are formed penetrates the material layer 7 different from that and is in contact with the resin layer 1. Therefore, when the resin layer 3 is provided on the material layer 7, it is possible to effectively suppress cracks and peeling that may occur at the interface between them.

Next, a third embodiment will be described.
FIG. 9 is a diagram showing an example of a circuit board according to the third embodiment. FIG. 9 schematically shows a cross-section of the main part of an example of the circuit board.

  The circuit board 10C shown in FIG. 9 has a point that the adhesion layer 4 is directly laminated on the material layer 7, and the seed layer 5a and the wiring layer 5 are laminated on the adhesion layer 4 to form the wiring structure 13. This is different from the circuit board 10A described in the first embodiment. Thus, in the circuit board 10C shown in FIG. 9, the resin layer 3 as described above is not provided on the material layer 7, and the material layer 7 and the adhesion layer 4 are in contact with each other.

The circuit board 10C having such a configuration is formed as follows, for example.
10 and 11 are diagrams showing an example of a circuit board forming method according to the third embodiment. FIGS. 10A to 10C and FIGS. 11A to 11C schematically show cross sections of relevant parts of each process of circuit board formation.

First, a structure as shown in FIG. 10A, that is, a structure in which the material layer 7, the adhesion layer 4 and the seed layer 5a are sequentially stacked on the resin layer 1 is prepared.
The material layer 7 is formed, for example, by applying and curing a silicon-containing material such as the formulas (1) to (3) described in the first embodiment on the resin layer 1. The adhesion layer 4 and the seed layer 5a are formed on the material layer 7 by sputtering to obtain a structure as shown in FIG.

  Thereafter, as shown in FIG. 10B, a resist 8 having an opening 8a in the region where the wiring layer 5 is to be formed is formed. Then, after the formation of the wiring layer 5 by electrolytic plating using the seed layer 5a for power feeding, the resist 8 is removed. Thereby, a state as shown in FIG. 10C is obtained.

  Next, as shown in FIG. 11A, the seed layer 5a exposed after the removal of the resist 8 and the adhesion layer 4 therebelow are removed by etching. Thereby, the state where the material layer 7 is exposed on the surface of the wiring structure 13 including the seed layer 5 a and the wiring layer 5 provided on the adhesion layer 4 as shown in FIG. 11A is obtained. .

  Next, as shown in FIG. 11B, the barrier layer 6 is formed on the surfaces of the wiring layer 5 and the seed layer 5a by electroless plating. Thereafter, as shown in FIG. 11C, the resin layer 2 is formed so as to cover the adhesion layer 4, the seed layer 5a, the wiring layer 5, and the barrier layer 6.

As described above, the circuit board 10C is formed by the steps as shown in FIGS. 10 (A) to 10 (C) and FIGS. 11 (A) to 11 (C).
As described above, also in the method of forming the circuit board 10C, the seed layer 5a and the adhesion layer 4 are etched to expose the material layer 7 including a siloxane bond on the surface (FIGS. 11A and 11B). . By exposing the material layer 7 containing a siloxane bond, it is possible to suppress the remaining and attachment of unnecessary conductive substances. Since the remaining and adhesion of the unnecessary conductive substance can be suppressed, abnormal deposition of the electroless plating can be suppressed when the barrier layer 6 is formed by the electroless plating. According to the method of forming the circuit board 10C, it is possible to effectively suppress the occurrence of electrical defects such as electrical leaks, ion migration, and shorts thereby, and realize the circuit board 10C with high performance and reliability. It will be possible to

  Here, the case where the barrier layer 6 is provided on the surface of the seed layer 5 a and the wiring layer 5 is taken as an example, but the resin layer 2 covering the seed layer 5 a and the wiring layer 5 may be provided without providing the barrier layer 6. Also in this case, it is possible to obtain the same effect as described above.

  In addition, here, the adhesion layer 4 and the wiring structure 13 including the seed layer 5a and the wiring layer 5 provided thereon are taken as an example. However, as the wiring structure 13, a configuration in which the adhesion layer 4 is not provided may be adopted. it can. In this case, the same effect as described above can be obtained.

  Furthermore, although the wiring structure 13 formed using the semi-additive method is taken as an example here, the wiring structure formed using the subtractive method (wiring structure not including the adhesion layer and the seed layer as described above) For the above, the same effect as described above can be obtained by adopting the above-described method of providing the material layer 7.

  Further, in the circuit board 10C, by providing the material layer 7 having moisture resistance, it is possible to effectively suppress the penetration and diffusion of moisture from the outside, and the circuit board 10C having high performance and reliability is realized. It will be possible to

Next, a fourth embodiment will be described.
FIG. 12 is a diagram illustrating an example of a circuit board according to the fourth embodiment. FIG. 12 schematically shows a cross section of an essential part of an example of a circuit board.

  In the circuit board 10D shown in FIG. 12, an opening 7a is provided at a position corresponding to the adhesion layer 4 (as well as the seed layer 5a and the wiring layer 5 thereon) of the material layer 7, and the adhesion layer is formed by the opening 7a. 4 differs from the circuit board 10C described in the third embodiment in that it is in contact with the resin layer 1. The seed layer 5 a and the wiring layer 5 are stacked on the adhesion layer 4 in contact with the resin layer 1 to form a wiring structure 14.

The circuit board 10D having such a configuration is formed as follows, for example.
13 and 14 are views showing an example of a circuit board forming method according to the fourth embodiment. FIGS. 13A to 13C and FIGS. 14A to 14C schematically show cross sections of relevant parts of each process of circuit board formation.

First, a structure as shown in FIG. 13A, that is, a structure in which the material layer 7 having the opening 7a, the adhesion layer 4 and the seed layer 5a are sequentially stacked on the resin layer 1 is prepared.
For example, after the material layer 7 having the opening 7a is applied and cured on the resin layer 1 with a silicon-containing material such as the formulas (1) to (3) described in the first embodiment, It can be obtained by forming the opening 7a using a photolithography technique or an etching technique. The adhesion layer 4 and the seed layer 5a are formed by sputtering on the material layer 7 in which the opening 7a is formed, and a structure as shown in FIG. 13A is obtained. The resin layer 1 and the adhesion layer 4 are in contact with each other through the opening 7 a of the material layer 7.

  Thereafter, as shown in FIG. 13B, a resist 8 having an opening 8a is formed in a region where the wiring layer 5 is to be formed. Then, after the formation of the wiring layer 5 by electrolytic plating using the seed layer 5a for power feeding, the resist 8 is removed. Thereby, a state as shown in FIG. 13C is obtained.

  Next, as shown in FIG. 14A, the seed layer 5a exposed after the removal of the resist 8 and the adhesion layer 4 therebelow are removed by etching. Thereby, the state where the material layer 7 is exposed on the surface of the wiring structure 14 including the seed layer 5 a and the wiring layer 5 provided on the adhesion layer 4 as shown in FIG. 14A is obtained. .

  Next, as shown in FIG. 14B, the barrier layer 6 is formed on the surfaces of the wiring layer 5 and the seed layer 5a by electroless plating. Thereafter, as shown in FIG. 14C, the resin layer 2 is formed so as to cover the adhesion layer 4, the seed layer 5 a, the wiring layer 5, and the barrier layer 6.

As described above, the circuit board 10D is formed by the steps shown in FIGS. 13 (A) to 13 (C) and 14 (A) to 14 (C).
As described above, also in the method of forming the circuit board 10D, the seed layer 5a and the adhesion layer 4 are etched to expose the material layer 7 including the siloxane bond on the surface (FIGS. 14A and 14B). . By exposing the material layer 7 including a siloxane bond, it is possible to suppress the remaining and adhesion of the unnecessary conductive substance. Since the remaining and adhesion of the unnecessary conductive substance can be suppressed, abnormal deposition of the electroless plating can be suppressed when the barrier layer 6 is formed by the electroless plating. According to the method of forming the circuit board 10D, it is possible to effectively suppress the occurrence of electrical defects such as electrical leaks, ion migration, and shorts thereby, and realize the circuit board 10D with high performance and reliability. It will be possible to

  In this example, the barrier layer 6 is provided on the surface of the seed layer 5a and the wiring layer 5. However, the resin layer 2 covering the seed layer 5a and the wiring layer 5 may be provided without providing the barrier layer 6. Also in this case, it is possible to obtain the same effect as described above.

  Further, here, the adhesion layer 4 and the wiring structure 14 including the seed layer 5a and the wiring layer 5 provided thereon are taken as an example. However, as the wiring structure 14, a configuration in which the adhesion layer 4 is not provided may be adopted. it can. In this case, the same effect as described above can be obtained.

  Furthermore, although the wiring structure 12 formed using the semi-additive method is taken as an example here, the wiring structure formed using the subtractive method (wiring structure not including the adhesion layer and the seed layer as described above) The same effect as described above can be obtained by adopting the above-described method of providing the material layer 7.

Further, in the circuit board 10D, by providing the material layer 7 having moisture resistance, it is possible to effectively suppress the penetration and diffusion of moisture from the outside.
Further, in the circuit board 10 </ b> D, the adhesion layer 4 penetrates the material layer 7 and is in contact with the resin layer 1. Therefore, the material of the adhesion layer 4 can be selected in consideration of only the adhesion to the resin layer 1 among the material layer 7 and the resin layer 1.

Next, a fifth embodiment will be described.
Here, a more specific configuration example of the circuit board will be described as a fifth embodiment.
FIG. 15 is a view showing a first configuration example of the circuit board according to the fifth embodiment. FIG. 15 schematically illustrates a cross-section of an essential part of an example of a circuit board.

  A circuit board 20 </ b> A illustrated in FIG. 15 includes a substrate 21 and a resin layer 22 provided on the substrate 21. In the resin layer 22, a material layer 23, a first wiring structure 24 (six are shown as an example), and a second wiring structure 25 (one is shown as an example) are provided. The first wiring structure 24 includes a seed layer 24b and a wiring layer 24c on the adhesion layer 24a, and has a structure in which these are covered with a barrier layer 24d. The second-layer wiring structure 25 has a structure including the seed layer 25b on the adhesion layer 25a, the wiring layer 25c, and the via 25d. The resin layer 22 is provided with an opening 27 leading to the second-layer wiring structure 25, and the portion of the wiring structure 25 exposed from the opening 27 is used as a pad for external connection of the circuit board 20A.

  As the substrate 21, for example, various substrates such as a resin substrate, a glass substrate, a semiconductor substrate, a metal substrate, and a ceramic substrate are used. Besides, a buildup layer or buildup substrate in which a wiring layer having a predetermined pattern is provided on a surface layer or an inner layer of a resin layer, or a wafer level package in which electronic parts such as semiconductor elements are embedded in resin. (Wafer Level Package, WLP) may be used. In the case of WLP, the substrate 21 may be one before separation (in the wafer state) or one after separation.

  For the resin layer 22, a resin material containing one or more of phenol resin, acrylic resin, epoxy resin, imide resin, and amide resin is used. The resin material may contain an insulating filler. Also, the resin material may be photosensitive or non-photosensitive.

  For the material layer 23, a material different from the resin layer 22, for example, a material containing a siloxane bond is used. In this case, the material layer 23 is made of an organic siloxane or an inorganic siloxane, or a material mainly composed of an organic siloxane or an inorganic siloxane. The material layer 23 may include both organic siloxane or a material mainly composed thereof and inorganic siloxane or a material mainly composed thereof. The material layer 23 is formed, for example, by applying and curing a silicon-containing material such as the formulas (1) to (3) described in the first embodiment.

  In the circuit board 20 </ b> A, the material layer 23 does not have a continuous layer including a portion immediately below each wiring structure 24 below the first wiring structure group 24, in other words, does not have an opening directly below each wiring structure 24. It is considered to be a layer.

  Various materials, for example, metal materials such as Ti, are used for the adhesion layer 24a and the adhesion layer 25a. One or more materials may be used for the adhesion layer 24a and the adhesion layer 25a. Further, each of the adhesion layer 24a and the adhesion layer 25a may have a single layer structure or a laminated structure.

  Various conductor materials are used for the seed layer 24 b and the wiring layer 24 c, and the seed layer 25 b, the wiring layer 25 c, and the via 25 d. For example, a metal material such as Cu is used for the wiring layer 24c, the wiring layer 25c, and the via 25d, and a metal material such as Cu and Ni is used for the seed layer 24b and the seed layer 25b. The wiring layer 24c is formed by electrolytic plating using the seed layer 24b for power supply, and the wiring layer 25c is formed by electrolytic plating using the seed layer 25b for power supply.

  For the barrier layer 24d, various materials having a function of suppressing the diffusion of a conductor material component such as Cu contained in the wiring layer 24c and the seed layer 24b to the outside thereof are used for the wiring layer 24c and the seed layer 24b, for example. Conductor materials of higher resistance than the conductor materials used are used. For example, one or more conductor materials of Ni, P, Co, B, W, and Pd are used for the barrier layer 24d. The barrier layer 24d is formed by electroless plating.

In the circuit board 20A, the second-layer wiring structure 25 is electrically connected to the first-layer wiring structure 24 provided in the resin layer 22 via the via 25d.
The material layer 23 is not only between the substrate 21 and the first-layer wiring structure 24 group, but also between the first-layer wiring structure 24 group and the second-layer wiring structure 25 group (excluding the via 25d). May be provided. In this case, the moisture resistance of the two material layers 23 makes it possible to effectively suppress the penetration and diffusion of moisture from the outside.

FIG. 16 is a view showing a second configuration example of the circuit board according to the fifth embodiment. FIG. 16 schematically illustrates a cross-section of an essential part of an example of a circuit board.
The circuit board 20B shown in FIG. 16 is different from the circuit board 20A (FIG. 15) described in the first configuration example in that the material layer 23 has an opening 23a immediately below each wiring structure 24 of the first layer. Do.

  When the material layer 23 is also provided between the first wiring structure group 24 and the second wiring structure group 25 (excluding the via 25d), the second layer of the material layer 23 is provided. The openings 23 a may be provided immediately below the wiring structures 25 of FIG.

FIG. 17 is a view showing a third configuration example of the circuit board according to the fifth embodiment. FIG. 17 schematically illustrates a cross-section of an essential part of an example of a circuit board.
A circuit board 20C shown in FIG. 17 includes a first-layer wiring structure 24 (six are shown as an example) and a second-layer wiring structure 25 (four as an example) in a resin layer 22 provided on the substrate 21. And a third layer wiring structure 26 (one is shown as an example).

  In the circuit board 20C, the first-layer wiring structure 24 group and the second-layer wiring structure 25 group have the same structure as described in the first configuration example. The third-layer wiring structure 26 has a structure including the seed layer 26 b on the adhesion layer 26 a, the wiring layer 26 c, and the via 26 d. The second layer wiring structure 25 including the via 25 d is electrically connected to the first layer wiring structure 24 provided in the resin layer 22 via the via 25 d, and the second layer wiring structure 25 is provided. The third layer wiring structure 26 is electrically connected through the via 26d. The resin layer 22 is provided with an opening 27 leading to the third-layer wiring structure 26, and the portion of the wiring structure 26 exposed from the opening 27 is used as an external connection pad of the circuit board 20C.

  In the resin layer 22 of the circuit board 20C, between the substrate 21 and the first layer wiring structure 24 group, the first layer wiring structure 24 group and the second layer wiring structure 25 group (except for the via 25d) And a material layer 23 is provided between the second wiring structure 25 group and the third wiring structure 26 (excluding the via 26d). The three material layers 23 are respectively directly below the first wiring structure 24, immediately below the second wiring structure 25 (except for the via 25 d), and at the third wiring structure 26 (via 26 d). The layer does not have an opening directly under (except).

FIG. 18 is a view showing a fourth configuration example of the circuit board according to the fifth embodiment. FIG. 18 schematically illustrates a cross section of an essential part of an example of a circuit board.
In the circuit board 20D shown in FIG. 18, the three material layers 23 are respectively directly below the first wiring structure 24, immediately below the second wiring structure 25 and immediately below the third wiring structure 26. And the circuit board 20C (FIG. 17) described in the third configuration example in that it has an opening 23a.

Subsequently, a method of forming a circuit board according to the fifth embodiment will be described.
19 to 21 are diagrams showing an example of a circuit board forming method according to the fifth embodiment. 19 (A) to 19 (D), 20 (A) to 20 (D), and FIGS. 21 (A) to 21 (C) are cross-sectional views of main parts of each process of circuit board formation. It has illustrated typically.

Here, an example of the formation method will be described by taking the circuit board 20C described in the third configuration example as an example.
First, as shown in FIG. 19A, a resin layer 22a (a part of the resin layer 22) is formed on a substrate 21, and a first material layer 23 is formed on the resin layer 22a. Ru. For example, a resin material mainly composed of a phenol resin is formed with a thickness of 5 μm on the substrate 21 to form the resin layer 22a. On the resin layer 22a, a UV curable resin material mainly composed of trifunctional siloxane is applied with a thickness of 50 nm by a spin coating method, cured by irradiation with UV light, and a material layer 23 including a siloxane bond is formed. Ru.

  Next, as shown in FIG. 19B, the resin layer 22 b (a part of the resin layer 22) is formed on the material layer 23. For example, on the material layer 23, a resin material mainly composed of a phenol resin is formed with a thickness of 0.4 μm to form the resin layer 22b.

  Next, as shown in FIG. 19C, an adhesion layer 24a and a seed layer 24b are formed on the resin layer 22b by sputtering. For example, Ti is formed as the adhesion layer 24a with a thickness of 20 nm, and Cu is formed thereon as the seed layer 24b with a thickness of 50 nm.

  Next, as shown in FIG. 19D, on the seed layer 24b, a resist 28 having an opening 28a in the region where the wiring layer 24c is to be formed is formed. For example, a resist 28 having an opening 28a having an L / S of 1 μm and a height of 2 μm is formed.

  Next, as shown in FIG. 20A, the wiring layer 24c is formed in the opening 28a of the resist 28 by electrolytic plating using the seed layer 24b for feeding. For example, Cu electroplating layer 24c having a maximum height of 1.1 μm is formed in opening 28a of resist 28 by electrolytic plating of Cu.

Next, as shown in FIG. 20B, the resist 28 is stripped and removed under wet conditions.
Next, as shown in FIG. 20C, the seed layer 24b exposed after the removal of the resist 28 is removed, the adhesion layer 24a exposed after the removal of the seed layer 24b is removed, and the exposure is performed after the removal of the adhesion layer 24a. The resin layer 22b to be removed is removed. For example, after the removal of the resist 28, first, the Cu seed layer 24b is removed by wet etching. Thereafter, the adhesion layer 24a of Ti is removed by dry etching. Furthermore, the resin layer 22b is dug down by dry etching until the material layer 23 is exposed.

As a result, a first-layer wiring structure 24 group is formed in which the adhesion layer 24a, the seed layer 24b and the wiring layer 24c are stacked on the resin layer 22b.
Next, as shown in FIG. 20D, a barrier layer 24d is formed to cover the seed layer 24b and the wiring layer 24c. For example, a barrier layer 24d having a thickness of 70 nm is formed on the surfaces of the seed layer 24b and the wiring layer 24c by electroless plating.

  Next, as shown in FIG. 21A, a resin layer 22c (a part of the resin layer 22) is formed so as to cover the first layer of the wiring structure 24 group, and two layers are formed on the resin layer 22c. The eye material layer 23 is formed, and the resin layer 22 d (a part of the resin layer 22) is formed on the material layer 23. For example, a resin material mainly composed of phenol resin is formed with a thickness of 5 μm to form the resin layer 22c. On the resin layer 22c, a UV curable resin material mainly composed of trifunctional siloxane is applied with a thickness of 50 nm by a spin coating method, and cured by UV irradiation using a mask of a via hole to be formed. A material layer 23 having an opening 23a at the formation position is formed. Further, on the material layer 23, a resin material mainly composed of a phenol resin is formed with a thickness of 0.4 μm to form a resin layer 22d.

  Next, as shown in FIG. 21B, a second-layer wiring structure 25 group is formed, which includes the adhesion layer 25a, the seed layer 25b and the wiring layer 25c, and further includes the via 25d. The resin layer 22e (a part of the resin layer 22) is formed so as to cover the After the formation of the via hole communicating with the first layer wiring structure 24 to which the via 25d included in a part is connected, the second layer wiring structure 25 group is formed as shown in FIGS. 19C to 20C. It is formed according to the example of the process. Thereafter, for example, a resin material mainly composed of a phenol resin is formed to a thickness of 5 μm to form a resin layer 22e.

  Thereafter, as shown in FIG. 21C, a third material layer 23 is formed on the resin layer 22e in accordance with the example of the process of FIG. A layer 22f (a part of the resin layer 22) is formed. Then, after forming the via holes communicating with the second layer wiring structure 25 in the same manner as described with reference to FIG. 21 (B), adhesion is performed according to the example of the steps of FIGS. 19 (C) to 20 (C). A third-layer wiring structure 26 including the layer 26a, the seed layer 26b, the wiring layer 26c, and the via 26d is formed.

  Finally, a resin layer 22g (a part of the resin layer 22) is formed to cover the third layer wiring structure 26, and an opening 27 communicating with the third layer wiring structure 26 is formed in the resin layer 22g. As a result, pads for external connection of circuit board 20C are formed.

As described above, the circuit board 20C is formed by the steps shown in FIGS. 19A to 19D, 20A to 20D, and 21A to 21C. Be done.
The first to third layer wiring structures 24 to 26 are formed at the time of formation of the first to third material layers 23 (FIGS. 19A, 21A, and 21C). When the opening 23a is formed in a portion directly below the circuit board 20, the circuit board 20D described in the fourth configuration example is obtained.

  Further, in the process of FIG. 21B, when the opening 27 communicating with the second layer wiring structure 25 is formed in the resin layer 22e, it has the same configuration as the circuit board 20A described in the first configuration example. A circuit board is obtained. In this case, when the first material layer 23 is formed (FIGS. 19A and 21A), the opening 23a is formed at a position directly below each of the first wiring structures 24 and 25 to be formed. Is formed, a circuit board having the same configuration as the circuit board 20B described in the second configuration example is obtained.

  Further, an example in which the adhesion layers 24a, 25a, 26a are formed on the first to third material layers 23 via the resin layers 22b, 22d, 22f, respectively, is shown here. Besides, in accordance with the example of the third embodiment (FIGS. 9 to 11), the adhesion layers 24a, 25a, 26a are formed so as to be in contact with the material layer 23 without the resin layers 22b, 22d, 22f. May be Furthermore, according to the example of the fourth embodiment (FIGS. 12 to 14), openings 23a are formed in the first to third material layers 23, respectively, and the resin layers 22a and 22c under each material layer 23 are formed. , 22e may be formed in contact with the contact layers 24a, 25a, 26a.

  Further, the barrier layer in the first wiring structure 24 is formed on the surfaces of the seed layer 25b and the wiring layer 25c in the second wiring structure 25 and the surface of the seed layer 26b and the wiring layer 26c in the third wiring structure 26. Similar to 24d, the barrier layer may be formed by electroless plating.

  Further, when the diffusion of the conductor material component from the seed layer 24b and the wiring layer 24c in the first wiring structure 24 poses no problem, the step of providing the barrier layer 24d on the surface (FIG. 20D) is omitted. The first layer wiring structure 24 may be covered with the resin layer 22c.

  As described above, according to the method described in the fifth embodiment, before the barrier layer 24 d of the first-layer wiring structure 24 is formed by electroless plating, and the first-layer wiring structure 24 is covered with the resin layer 22 c. Previously, the material layer 23 containing a siloxane bond on the surface is exposed (FIG. 20C). As a result, it is possible to effectively suppress the generation of the conductive substance, the abnormal deposition of the electroless plating, the electric leak and the ion migration resulting therefrom, and the generation of the electrical failure such as the short circuit. In addition, when providing a barrier layer also in the wiring structure 25 of the 2nd layer and the wiring structure 26 of the 3rd layer, the same effect can be acquired when forming those barrier layers by electroless plating.

  Here, an example in which the material layer 23 is provided below the first to third wiring structures 24 to 26 is shown. In addition, the material layer 23 is provided in the lower layer between the relatively narrow first layer wiring structures 24, and between the lower layer or the third layer wiring structures 26 between the relatively large second layer wiring structures 25. Alternatively, the material layer 23 may not be provided in the lower layer. This is because electrical defects such as shorts caused by the generation of a conductive substance or abnormal deposition of electroless plating are more likely to occur as the distance between the wiring structures becomes narrower. However, if the material layers 23 are respectively provided in the lower layers of the first to third wiring structures 24 to 26, the moisture resistance of the material layers 23 can effectively suppress the intrusion and diffusion of moisture from the outside. Performance and reliability can be improved.

Then, the result of having evaluated the circuit board which concerns on 5th Embodiment is described.
[Observation of abnormal deposition]
After forming the barrier layer 24d of the first wiring structure 24 on the circuit board 20C (FIGS. 17 and 21C) of the third configuration example (FIG. 20D), a scanning electron microscope When the surface of the material layer 23 exposed between the wiring structures 24 was observed using the above, no abnormal deposition was observed. For the circuit board 20D (FIG. 18) of the fourth configuration example, after forming the barrier layer 24d of the first wiring structure 24, the material layer 23 exposed between the wiring structures 24 using a scanning electron microscope. When the surface of was observed, abnormal deposition was not observed.

Here, the circuit board of the comparative example is shown in FIG.
For comparison, a circuit board 20a as shown in FIG. 22 was prepared. The circuit board 20a shown in FIG. 22 is different from the circuit board 20C of the third configuration example and the circuit board 20D of the fourth configuration example in that the material layer 23 is not included. By performing the method of forming the circuit board 20C shown in FIGS. 19 to 21 except for the steps of forming the three material layers 23 and the resin layers 22b, 22d and 22f thereon, the method of FIG. A circuit board 20a as shown is obtained. After forming the barrier layer 24d of the first wiring structure 24 of the circuit board 20a obtained in this manner, the surface of the material layer 23 exposed between the wiring structures 24 was observed using a scanning electron microscope However, abnormal precipitation was observed.

  In the formation of the circuit board 20C and the circuit board 20D in which the material layer 23 is exposed at the time of formation of the barrier layer 24d by electroless plating, generation of a conductive substance on the surface of the material layer 23 and abnormal deposition of electroless plating are effectively suppressed. It was confirmed that

[Verification of reliability]
The circuit board 20C (FIGS. 17 and 21C) of the third configuration example, the circuit board 20D (FIG. 18) of the fourth configuration example, and the circuit board 20a (FIG. 22) of the comparative example are reliable. Conducted sex test.

  As a pretreatment of the reliability test, after drying for 24 hours in an oven at an atmosphere of 125 ° C., moisture absorption treatment is carried out for 40 hours in a constant temperature and humidity chamber with a temperature of 60 ° C. and a humidity of 65%. The reflow process at a temperature of 260 ° C. was performed three times.

  Next, as a reliability test, under the environment of a temperature of 130 ° C. and a humidity of 85%, a voltage of 3.5 V is maximized via a pad between two independent wiring structures 24 in each of the circuit boards 20C, 20D, 20a. After applying for 150 hours, the insulation evaluation between the two wiring structures 24 was performed. The distance between the two wiring structures 24 is 1 μm.

  As a result, in both the circuit board 20C and the circuit board 20D to which the material layer 23 is applied, insulation is maintained even when a voltage of 3.5 V is applied between the two independent wiring structures 24 for 150 hours, and a defect occurs. Was not recognized. On the other hand, in the circuit board 20a of the comparative example, when a voltage of 3.5 V was applied between two independent wiring structures 24 for 90 hours, the insulation property was not maintained. This is considered to be due to the occurrence of ion migration due to the abnormal deposition of the electroless plating generated between the two wiring structures 24 becoming an electric leak path.

  In the circuit board 20C and the circuit board 20D formed by exposing the material layer 23 during formation of the barrier layer 24d by electroless plating, generation of a conductive substance on the surface of the material layer 23, abnormal deposition of electroless plating, and the cause thereof It has been confirmed that the electrical defects can be effectively suppressed.

  According to the above-described method, it is possible to realize the circuit board 20C and the circuit board 20D having high performance and high reliability with suppressed electrical failure. Similarly, it is possible to realize the circuit board 20A and the circuit board 20B with high performance and reliability.

Next, a sixth embodiment will be described.
Here, an example of an electronic device which can adopt the configurations of the circuit boards 10A to 10D, 20A to 20D and the like described in the first to fifth embodiments will be described as a sixth embodiment.

FIG. 23 is a diagram showing a first configuration example of the electronic device according to the sixth embodiment. FIG. 23 schematically illustrates a cross-section of an essential part of an example of an electronic device.
An electronic device 30 illustrated in FIG. 23 includes a printed circuit board 31, an interposer 32, a semiconductor chip 33, and a semiconductor chip 34. The terminals 31 a and the terminals 32 a provided at corresponding positions of the printed circuit board 31 and the interposer 32 are electrically connected via the bumps 35 such as solder. Terminals 32 b provided at corresponding positions of interposer 32 and semiconductor chip 33 and semiconductor chip 34 are electrically connected to terminals 33 a and terminals 34 a via bumps 36 such as solder. The interposer 32 is provided with a wiring structure 32c for electrically connecting the terminals 32a and 32b on the both surfaces thereof.

  For example, the semiconductor chip 33 and the semiconductor chip 34 are mounted (flip chip connection) on the interposer 32 via the bumps 36, and the interposer 32 is mounted on the printed circuit board 31 via the bumps 35. Alternatively, the semiconductor chip 33 and the semiconductor chip 34 are mounted via the bumps 36 (flip chip connection) on the interposer 32 mounted on the printed circuit board 31 via the bumps 35. The electronic device 30 is formed in such a procedure.

  For example, in the interposer 32 of the electronic device 30, the first to fifth wiring structures 32 c on the semiconductor chip 33 side and the semiconductor chip 34 side that are relatively narrow as shown by the chain line frame X in FIG. The configuration as described in the embodiment of FIG. According to such an interposer 32, the generation of unnecessary conductive material around the wiring structure 32c, the occurrence of electrical leakage or ion migration due to it, and the occurrence of electrical failure such as a short circuit can be effectively suppressed. An interposer 32 with high performance and reliability with reduced electrical defects is realized, and an electronic device 30 with high performance and reliability using such an interposer 32 is realized.

FIG. 24 is a view showing a second configuration example of the electronic device according to the sixth embodiment. FIG. 24 schematically illustrates a cross section of an essential part of an example of the electronic device.
The electronic device 40 shown in FIG. 24 includes a printed board 41 and a component built-in board 42. The terminals 41 a and the terminals 42 a provided at corresponding positions of the printed circuit board 41 and the component built-in board 42 are electrically connected via the bumps 43 such as solder. The component built-in substrate 42 has a resin 44, a semiconductor chip 45 and a semiconductor chip 46 embedded in the resin 44, and a rewiring layer 47 provided on the resin 44. The rewiring layer 47 is provided with a wiring structure 47 a that electrically connects the terminal 42 a used for connection with the printed circuit board 41 and the terminal 45 a of the semiconductor chip 45 and the terminal 46 a of the semiconductor chip 46.

  For example, a pseudo wafer in which the semiconductor chip 45 and the semiconductor chip 46 are embedded in resin is formed, and the rewiring layer 47 is formed thereon, and separated by dicing or the like. Thus, the component built-in substrate 42 is formed. The component-embedded substrate 42 thus formed is mounted on the printed circuit board 41 via the bumps 43 to form the electronic device 40. The electronic device 40 is formed in such a procedure.

  For example, with respect to the wiring structure 47a on the semiconductor chip 45 side and the semiconductor chip 46 side where the interval is relatively narrow as shown in the chain line frame Y of FIG. The configuration as described in the fifth embodiment is adopted.

  According to such a component-embedded substrate 42, the occurrence of unnecessary conductive substances around the wiring structure 47a, and the occurrence of electrical defects such as electrical leaks and ion migrations and shorts caused thereby are effectively suppressed. Be A component built-in substrate 42 with high performance and reliability that suppresses electrical defects is realized, and an electronic device 40 with high performance and reliability using such a component built-in substrate 42 is realized.

  The configurations of the circuit boards 10A to 10D, 20A to 20D and the like described in the first to fifth embodiments are not limited to the electronic device 30 and the electronic device 40 as described above, but circuit portions of various electronic devices. It is possible to adopt.

Next, a seventh embodiment will be described.
The circuit boards 10A to 10D, 20A to 20D and the like described in the first to fifth embodiments and the electronic devices 30, 40 and the like described in the sixth embodiment may be mounted on various electronic devices. Can. For example, the electronic device can be installed in various electronic devices such as a computer (personal computer, super computer, server, etc.), a smartphone, a mobile phone, a tablet terminal, a sensor, a camera, an audio device, a measuring device, an inspection device, and a manufacturing device.

FIG. 25 is an explanatory diagram of the electronic device according to the seventh embodiment. FIG. 25 schematically shows the electronic device.
As shown in FIG. 25, for example, the electronic device 30 (FIG. 23) as described in the sixth embodiment is mounted (embedded) in various electronic devices 50.

  In the electronic device 30, for the wiring structure 32c in the interposer 32, the configuration as described in the first to fifth embodiments is adopted. As a result, in the interposer 32, generation of unnecessary conductive material around the wiring structure 32c, generation of electrical leak and ion migration due to it, generation of electrical defects such as short circuit due to it, and the like are effectively suppressed. A highly reliable electronic device 30 is realized. Various electronic devices 50 having such an electronic device 30 and high performance and reliability are realized.

  Here, the electronic device 50 on which the electronic device 30 described in the sixth embodiment is mounted is shown as an example. Similarly, in addition to the electronic device 40 described in the sixth embodiment, the circuit boards 10A to 10D, 20A to 20D, etc. described in the first to fifth embodiments, and their configurations are adopted. Various electronic devices can also be installed in various electronic devices.

1, 2, 3, 22, 22a, 22b, 22c, 22d, 22e, 22g Resin layer 4, 24a, 25a, 26a Adhesion layer 5, 24c, 25c, 26c Wiring layer 5a, 24b, 25b, 26b Seed layer 6, 24d barrier layer 7, 23 material layer 7a, 8a, 23a, 27, 28a opening 8, 28 resist 9 conductive material 10a, 10A, 10B, 10C, 10D, 20a, 20A, 20B, 20C, 20D circuit board 11, 12, 13, 14, 24, 25, 26, 32c, 47a Wiring structure 21 Substrate 25d, 26d Via 30, 40 Electronic device 31, 41 Printed circuit board 31a, 32a, 32b, 33a, 34a, 41a, 42a, 45a , 46a Terminal 32 Interposer 33, 34, 45, 46 Semiconductor chip 35, 36, 43 Bump 2 component-embedded substrate 44 resin 47 rewiring layer 50 electronic equipment

Claims (13)

A first resin layer,
A wiring structure provided above the first resin layer,
A second resin layer provided above the first resin layer and covering the wiring structure;
And a material layer including a siloxane bond provided between the first resin layer and the second resin layer. The wiring structure includes an adhesion layer provided above the first resin layer;
The circuit board according to claim 1, further comprising: a wiring layer provided above the adhesion layer. The wiring structure is located above a portion of the material layer,
The circuit board according to claim 1, wherein a third resin layer is provided between the part and the wiring structure. The wiring structure is located on a part of the material layer;
The circuit board according to claim 1, wherein the part is in contact with the wiring structure. The material layer has an opening;
The wiring structure is located above the opening,
The circuit board according to claim 1 or 2, wherein a third resin layer is provided between the first resin layer and the wiring structure and in contact with the first resin layer at the opening. The material layer has an opening;
The wiring structure is located in the opening;
The circuit board according to claim 1, wherein the first resin layer and the wiring structure are in contact with each other at the opening.   The circuit board according to claim 1, wherein the material layer includes organosiloxane.   The circuit board according to any one of claims 1 to 7, further comprising a barrier layer provided on the surface of the wiring structure. Forming a material layer containing a siloxane bond above the first resin layer;
Forming an adhesion layer above the material layer;
Forming a wiring layer above the adhesion layer;
Exposing the material layer;
Forming a second resin layer covering the wiring layer above the first resin layer in a state in which the material layer is exposed.   The method further comprises a step of forming a barrier layer on the surface of the wiring layer in a state where the material layer is exposed after the step of exposing the material layer and before the step of forming the second resin layer. The method of manufacturing a circuit board according to claim 9. 11. The method for producing a circuit board according to claim 9, wherein the material layer is formed using a silicon-containing material represented by the following general formula (1), (2) or (3).
(R ² R ^{2 ′} -SiO _2/2 ) _e (O _1/2 R ¹ ) _f (1)
(R ³ —SiO _3/2 ) _c (O _1/2 R ¹ ) _d (2)
(SiO _4/2 ) _a (O _1/2 R ⁴ ) _b (3)
[In the general formulas (1) to (3), R ¹ , R ² , R ^{2 ′} , R ³ and R ⁴ are independently of each other hydrogen, an alkyl group or a triorganosilyl group, or an alkyl group or tri It is a derivative of an organosilyl group. a to f represent composition ratios, and a, c and e are integers of 1 or more, and b, d and f are integers of 0 or more. ] A first resin layer,
A wiring structure provided above the first resin layer,
A second resin layer provided above the first resin layer and covering the wiring structure;
A circuit board provided between the first resin layer and the second resin layer and having a material layer containing a siloxane bond;
An electronic device comprising: an electronic component mounted on the circuit board. A first resin layer,
A wiring structure provided above the first resin layer,
A second resin layer provided above the first resin layer and covering the wiring structure;
A method of manufacturing an electronic device, comprising: mounting an electronic component on a circuit substrate provided between the first resin layer and the second resin layer and having a material layer containing a siloxane bond.

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