JP2019012771A - Circuit board, electronic device, and manufacturing method of circuit board - Google Patents

Abstract

To provide a circuit board, an electronic device, and a manufacturing method of a circuit board that suppress degradation of reliability due to narrowing of interconnections.SOLUTION: An electronic device includes an interposer substrate 3 including a resin insulating layer 9, a copper wiring 7 buried in the resin insulating layer 9, and a barrier film 12 in which the copper wiring 7 is covered from the resin insulating layer 9 and that includes a first metal layer 13 containing nickel, a layer 14 containing nickel fluoride, and a second metal layer 15 containing nickel in order from the copper wiring side, and an electronic component mounted on the interposer substrate 3.SELECTED DRAWING: Figure 2

Description

  The present application relates to a circuit board, an electronic device, and a method for manufacturing the circuit board.

  In recent years, the wiring on a substrate on which a semiconductor chip is mounted has been increasingly miniaturized. Along with this, various wiring structures have been proposed (see, for example, Patent Document 1-2).

International Publication No. 2006/137384 JP 2004-214345 A

In order to prevent diffusion and oxidation of the wiring material to the resin insulation layer during long-term use, a barrier structure in which the wiring is covered from the resin insulation layer with a relatively inert metal film may be adopted for the wiring of the substrate . However, when the miniaturization of wiring progresses, there is a possibility that it cannot pass a reliability test such as HAST (Highly Accelerated Temperature and Humidity Stress Test) due to an increase in electric field strength between wirings.

  Therefore, an object of the present invention is to provide a technique for suppressing a decrease in reliability due to narrowing between wirings.

  In one aspect, a circuit board includes a resin insulating layer, a copper wiring embedded in the resin insulating layer, a barrier film that covers the copper wiring from the resin insulating layer and has a layer containing nickel fluoride, Is provided.

  As one aspect, it is possible to suppress a decrease in reliability due to narrowing between wirings.

FIG. 1 is a diagram illustrating a structure of an electronic device according to the embodiment. FIG. 2 is a diagram showing an example of the internal structure of the interposer substrate. FIG. 3 is a first view showing a manufacturing process of the interposer substrate. FIG. 4 is a second view showing the manufacturing process of the interposer substrate. FIG. 5 is a graph showing the electric field strength between the wirings. FIG. 6 is a diagram illustrating a manufacturing process of an interposer substrate according to a comparative example. FIG. 7 is a graph showing the results of the HAST test. FIG. 8 is a diagram illustrating a structure of an electronic device according to a modification.

  Hereinafter, embodiments will be described. The embodiment described below is merely an example, and the technical scope of the present disclosure is not limited to the following aspect.

FIG. 1 is a diagram illustrating a structure of an electronic device according to the embodiment. The electronic device 1 includes a printed circuit board 2 and an LSI chip 4 mounted on the printed circuit board 2 via an interposer substrate 3. The interposer substrate 3 is electrically connected to the printed circuit board 2 via the solder bumps 5. Further, the LSI chip 4 is electrically connected to the interposer substrate 3 through the micro bumps 6.

  The electronic device 1 is an electronic device having fine wiring on a substrate, and examples thereof include a server, a computer, a communication device, a transportation device, a production device, a household appliance, and other various electronic devices. The printed circuit board 2 is a printed circuit board in which pads and wirings to which the solder bumps 5 are welded are provided on the surface of a plate-shaped core. Etc. The interposer substrate 3 is a relay substrate for facilitating the mounting of the LSI chip 4 on the printed circuit board 2. The upper surface on which pads arranged in accordance with the terminals of the LSI chip 4 are formed, and the printed circuit board. Wiring 7 is embedded between the lower surface on which terminals arranged in accordance with the pads arranged in 2 are formed. In FIG. 1, a plurality of LSI chips 4 are mounted on the interposer substrate 3, but only one LSI chip 4 may be mounted on the interposer substrate 3.

  FIG. 2 is a diagram showing an example of the internal structure of the interposer substrate 3. The wiring 7 embedded in the interposer substrate 3 is embedded in the first resin insulating layer 8 and the second resin insulating layer 9 that form the insulating portion of the interposer substrate 3. The first resin insulation layer 8 and the second resin insulation layer 9 are formed on the substrate 10. The wiring 7 is provided on the first resin insulating layer 8 via the adhesion layer 11. The wiring 7 is covered with the barrier film 12 from the second resin insulating layer 9.

  The barrier film 12 includes a first metal layer 13, a nickel fluoride layer 14, and a second metal layer 15 in this order from the wiring 7 side. The first metal layer 13 and the second metal layer 15 are metal films containing nickel. The nickel fluoride layer 14 is a metal film containing nickel fluoride. The interposer substrate 3 can be manufactured as follows, for example.

  FIG. 3 is a first diagram showing a manufacturing process of the interposer substrate 3. FIG. 4 is a second diagram showing the manufacturing process of the interposer substrate 3.

  In manufacturing the interposer substrate 3, first, an adhesion layer 11 such as Ti (titanium) and a seed layer 16 of Cu (copper) are formed on the substrate 10 on which the first resin insulating layer 8 is formed. (See FIG. 3A). The adhesion layer 11 and the seed layer 16 can be formed by various film forming methods. Examples of the film forming method for forming the adhesion layer 11 and the seed layer 16 include a sputtering method.

  Next, a resist 17 having an opening matching the pattern of the wiring 7 to be formed is formed on the seed layer 16 (see FIG. 3B). The resist 17 is formed, for example, by forming a solder resist over the entire surface of the seed layer 16 and then performing exposure using a mask and development processing immersed in a predetermined solution. The resist 17 may be formed by either a negative type or a positive type. The development process may be any system as long as a desired wiring width can be obtained. For example, in the case of a high-pressure mist system in which a developer is blown off with high-pressure air, the distance between the wirings is 1 μm or less. It is possible to form such a fine wiring.

  Next, electrolytic copper plating is performed on the seed layer 16 exposed in the opening portion of the resist 17 with Cu, and the wiring 7 is formed in the opening portion of the resist 17 (see FIG. 3C). Various methods can be used for electrolytic copper plating. For example, in the formation of fine wiring such that the distance between the wirings is 1 μm or less, the penetration of copper plating into the fine groove of the resist 17 is performed. It is preferable that an appropriate additive that promotes is used.

  Next, the resist 17 and the seed layer 16 are removed (see FIG. 3D). The resist 17 and the seed layer 16 remaining between the wirings 7 are removed by being immersed in an appropriate etching solution.

  The above series of steps is also called a semi-additive method. After the wiring 7 is formed through the above series of steps, the first metal layer 13 is formed on the surface of the wiring 7 (see FIG. 4A). This is an example of the “first step” in the present application. ). The first metal layer 13 is formed of a relatively inert Ni (nickel) metal. Examples of the material for forming the first metal layer 13 include various materials such as NiB, NiWB, and NiBP in addition to NiP and NiWP. With these materials, these materials can be formed on the surface of the wiring 7 without being deposited on the surface of the second resin insulation layer 9 by electroless plating utilizing the property of being deposited on Cu (copper).

  Next, the nickel fluoride layer 14 is formed on the surface of the wiring 7 (see FIG. 4B. This is an example of the “second step” in the present application). The nickel fluoride layer 14 is formed by selectively forming a NiP film on the surface of the wiring 7 by the above-described process by electroless plating using NiP (nickel-phosphorus), and then forming a fluorine-based gas on the NiP film. It is formed by performing a plasma treatment using

The film thickness of NiP formed on the surface of the wiring 7 depends on the wiring width and wiring interval of the wiring 7, but it can be considered to be about 50 nm, for example. The plasma treatment is performed, for example, using CF ₄ (carbon tetrafluoride) gas, with a flow rate of 100 ccm, a pressure of 1.5 Pa, and an RF power of about 300 W for about 600 seconds. Under this processing condition, for example, Ni having a depth of about 10 nm from the surface is fluorinated in a 50 nm NiP film to form a nickel fluoride layer.

  Next, the second metal layer 15 is formed on the surface of the wiring 7 (see FIG. 4C. This is an example of the “third step” in the present application). The second metal layer 15 is selectively formed on the surface of the wiring 7 by electroless plating. The second metal layer 15 can be formed by electroless plating using NiP, NiB, NiWP, NiWB, CoW, or the like, for example. The second metal layer 15 can also be formed of an inert metal such as CoP, CoWP, or Pd. The thickness of the second metal layer 15 is preferably about 50 nm, for example, although it depends on the wiring interval of the wiring 7.

  Next, the second resin insulating layer 9 is formed on the upper side of the substrate 10 (see FIG. 4D). By forming the second resin insulation layer 9 on the upper side of the substrate 10, the wiring 7 is embedded in the second resin insulation layer 9. Since the barrier film 12 is in contact with the second resin insulating layer 9 by the second metal layer 15, adhesion with the second resin insulating layer 9 is also ensured.

  Through the above series of steps, the interposer substrate 3 in which the wiring 7 is covered from the second resin insulating layer 9 by the barrier film 12 having the nickel fluoride layer 14 is completed.

FIG. 5 is a graph showing the electric field strength between the wirings. In various circuit boards such as an interposer board having fine wiring, Cu (copper) is used as a wiring material, and a resin insulating material is used for an insulating layer. The wiring on the circuit board is formed, for example, by a semi-additive method using pattern formation with a photoresist and electrolytic plating in order to cope with miniaturization. In order to increase reliability, Ni (nickel) -based metal that can be electrolessly plated is coated on these wirings as a barrier film. However, as indicated by a broken-line frame in FIG. 5, the electric field strength between the wirings rapidly increases when the distance (space) between the wirings is 1 μm or less. Therefore, if a barrier such as a NiP metal cap conventionally used for wiring of 2 μm or more is used as it is as a barrier of wiring of 1 μm or less, the barrier property is insufficient, and reliability such as HAST is caused due to ion migration and the like. In the test, the leakage current cannot meet the standard.

  In this regard, in the interposer substrate 3 of the above embodiment, the wiring 7 is covered from the second resin insulating layer 9 by the barrier film 12 having the nickel fluoride layer 14 that is chemically more stable than the NiP barrier film. Therefore, the progress of ion migration is suppressed as compared with the NiP metal cap. Therefore, the nickel fluoride layer 14 provided in the interposer substrate 3 of the above embodiment can withstand a relatively high electric field strength generated between the narrow wirings 7. Therefore, the interposer substrate 3 can obtain a good test result even in a reliability test such as HAST.

  Since the effect of the nickel fluoride layer 14 was verified, the verification result is shown below.

  FIG. 6 is a diagram illustrating a manufacturing process of the interposer substrate 103 according to the comparative example used for comparison with the interposer substrate 3. In the interposer substrate 103, after the wiring 107 is formed on the substrate 110 through the first resin insulating layer 108 and the adhesion layer 111 by the same method as the semi-additive method shown in FIG. (See FIG. 6A). The barrier film 112 is formed by electroless plating with a Ni (nickel) metal.

  Next, the second resin insulating layer 109 is formed over the substrate 110 (see FIG. 6B). By forming the second resin insulating layer 109 on the upper side of the substrate 110, the wiring 107 is embedded in the second resin insulating layer 109.

  When the HAST test was performed on two samples of the interposer substrate 103 created through the series of steps and the interposer substrate 3 according to the above-described embodiment, the following results were obtained. FIG. 7 is a graph showing the results of the HAST test.

  “No treatment” in the graph of FIG. 7 indicates the yield of the HAST test of the interposer substrate 103 according to the comparative example. Further, “with fluorination treatment” in the graph of FIG. 7 indicates the yield of the HAST test of the interposer substrate 3 according to the embodiment. The test conditions of the HAST test in this verification are that the wiring width, the wiring interval, and the wiring height are all 1.0 μm, and the thickness of the Ti (titanium) adhesion layer under the wiring is 20 nm. Further, the barrier film 112 of the interposer substrate 103 according to the comparative example is NiP having a thickness of 50 nm. In the interposer substrate 3 according to the embodiment, the first metal layer 13 is Ni having a thickness of 50 nm, the nickel fluoride layer 14 is nickel fluoride having a thickness of about 10 nm, and the second metal layer 15 is Ni having a thickness of 50 nm. . The bias voltage is 3.5V. As is apparent from a comparison between the two bar graphs, the yield of the HAST test of the interposer substrate 3 according to the embodiment was 3 times or more the yield m of the HAST test of the interposer substrate 103 according to the comparative example. From this result, it was confirmed that the circuit board having the nickel fluoride layer in the wiring barrier film has higher reliability than the circuit board having no nickel fluoride layer in the wiring barrier film.

The circuit board disclosed in the present application is not limited to the interposer board 3 of the above embodiment. FIG. 8 is a diagram illustrating a structure of an electronic device according to a modification. The circuit board disclosed in the present application may be, for example, a circuit board (Multi Chip Package) used for rewiring between a plurality of chips on a resin substrate as shown in FIG. The circuit boards disclosed in the present application are various circuit boards other than the interposer, such as a board for Fan Out WLP (Wafer level package), a wiring relay board (interposer board) based on glass or a resin board, and the like. There may be.

1..Electronic device: 2..Print substrate: 3,103..Interposer substrate: 4..LSI chip: 5..Solder bump: 6..Micro bump: 7, 107..Wiring: 8, 108 .. First resin insulation layer: 9, 109 Second resin insulation layer: 10, 110 Substrate: 111 111 Adhesion layer: 12, 112 Barrier film: 13, First metal layer: 14 Nickel fluoride layer: 15 Second metal layer: 16 Seed layer: 17 Resist

Claims (6)

A resin insulation layer;
Copper wiring embedded in the resin insulation layer;
A barrier film covering the copper wiring from the resin insulating layer and having a layer containing nickel fluoride,
Circuit board. The barrier film has, in order from the copper wiring side, a first metal layer containing nickel, a layer containing the nickel fluoride, and a second metal layer containing nickel.
The circuit board according to claim 1. The barrier film is formed on each wiring having a distance of at least 1 μm between adjacent wirings,
The circuit board according to claim 1 or 2. A circuit board comprising: a resin insulating layer; a copper wiring embedded in the resin insulating layer; and a barrier film that covers the copper wiring from the resin insulating layer and includes a layer containing nickel fluoride;
An electronic component mounted on the circuit board,
Electronic equipment. Forming a copper wiring on the first resin insulation layer;
Covering the copper wiring with a barrier film having a layer containing nickel fluoride;
Burying the copper wiring covered with the barrier film with a second resin insulation layer,
A method of manufacturing a circuit board. The step of covering the barrier film includes
A first step of covering the copper wiring with a first metal layer containing nickel;
A second step of fluorinating the surface of the first metal layer by plasma treatment with a fluorine-based gas;
A third step of further covering the copper wiring with a second metal layer containing nickel,
The method for manufacturing a circuit board according to claim 5.

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