JP2019125787A5 - - Google Patents

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JP2019125787A5
JP2019125787A5 JP2019003129A JP2019003129A JP2019125787A5 JP 2019125787 A5 JP2019125787 A5 JP 2019125787A5 JP 2019003129 A JP2019003129 A JP 2019003129A JP 2019003129 A JP2019003129 A JP 2019003129A JP 2019125787 A5 JP2019125787 A5 JP 2019125787A5
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チップ状金属抵抗器及びその製造方法Chip-shaped metal resistor and its manufacturing method

本発明は、チップ状の金属製抵抗体を有するチップ状金属抵抗器及びその製造方法に関するものである。 The present invention relates to a chip-shaped metal resistor having a chip-shaped metal resistor and a method for manufacturing the same.

特許第4460564号(特許文献1)に示されたチップ状金属抵抗器は、チップ状の金属製抵抗体と、この抵抗体の片面に設けられたメッキにより形成された複数の電極と、複数の電極に積層して形成されたメッキにより形成されたハンダ層とを備えている。そして抵抗体の片面には、抵抗体の電極間抵抗値を決定するための絶縁層が設けられている。また複数の電極は、絶縁層を挟んで離間しており、かつ、複数の電極のそれぞれの一部および複数の電極に積層されたハンダ層のそれぞれの一部は、絶縁層の縁部に対し、この縁部に直接接触するようにオーバラップしている。このような構成によれば、抵抗値調整のためのトリミングを行う必要がない。またチップ状金属抵抗器の製造過程において煩雑な切削作業を行う必要がないとのことである。 The chip-shaped metal resistor shown in Patent No. 4460564 (Patent Document 1) includes a chip-shaped metal resistor, a plurality of electrodes formed by plating provided on one side of the resistor, and a plurality of electrodes. It is provided with a solder layer formed by plating formed by laminating on an electrode. An insulating layer for determining the resistance value between the electrodes of the resistor is provided on one side of the resistor. Further, the plurality of electrodes are separated from each other with the insulating layer interposed therebetween, and a part of each of the plurality of electrodes and a part of each of the solder layers laminated on the plurality of electrodes are attached to the edge of the insulating layer. , Overlap so that they are in direct contact with this edge. According to such a configuration, it is not necessary to perform trimming for adjusting the resistance value. In addition, it is not necessary to perform complicated cutting work in the manufacturing process of the chip-shaped metal resistor.

特許第4460564号公報Japanese Patent No. 4460564

しかしながら従来の構造では、メッキにより形成された複数の電極に積層されたメッキにより形成されたハンダ層のそれぞれの一部が、絶縁層の縁部に対し、この縁部に直接接触するようにオーバラップしているので、実装の際に半田付けを行うと、絶縁層の縁部にオーバラップしている半田層の部分に実装用の半田が付くことになる。その結果、抵抗値を低抵抗にするために電極間寸法を小さくすると、半田層間短絡が発生しやすくなる問題がある。 However, in the conventional structure, each part of the solder layer formed by the plating laminated on the plurality of electrodes formed by the plating is overlaid with respect to the edge of the insulating layer so as to be in direct contact with the edge. Since it is wrapped, if soldering is performed at the time of mounting, the solder for mounting will be attached to the portion of the solder layer that overlaps the edge of the insulating layer. As a result, if the dimension between the electrodes is reduced in order to reduce the resistance value, there is a problem that a short circuit between solder layers is likely to occur.

本発明の目的は、抵抗値を低抵抗にしても半田層間短絡が発生しないチップ状金属抵抗器及びその製造方法を提供することにある。 An object of the present invention is to provide a chip-shaped metal resistor in which solder interlayer short circuit does not occur even if the resistance value is low, and a method for manufacturing the chip-shaped metal resistor.

第1の発明は、チップ状の金属製抵抗体と、金属製抵抗体の片面上にメッキにより形成された複数の電極層と、複数の電極層上にメッキにより形成された複数の半田層と、片面上に形成されて金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器を改良の対象とする。本発明のチップ状金属抵抗器では、複数の電極層は絶縁層の上にオーバラップするオーバラップ部を有するように形成されており、複数の半田層が複数の電極層のオーバラップ部を露出させるように形成されている。 The first invention comprises a chip-shaped metal resistor, a plurality of electrode layers formed by plating on one side of the metal resistor, and a plurality of solder layers formed by plating on the plurality of electrode layers. , A chip-shaped metal resistor formed on one surface and provided with an insulating layer for determining the resistance value between electrodes of the metal resistor is targeted for improvement. In the chip-shaped metal resistor of the present invention, the plurality of electrode layers are formed so as to have overlapping portions on the insulating layer, and the plurality of solder layers expose the overlapping portions of the plurality of electrode layers. It is formed to make it.

このように複数の半田層を複数の電極層のオーバラップ部を露出させるように形成すると、絶縁層の両側に位置する半田層間の距離が長くなる。その結果、半田層に付着する実装用の半田間の距離も長くなり、抵抗体の抵抗値を低くしても、半田層間短絡が発生することを防ぐことができる。 When the plurality of solder layers are formed so as to expose the overlapping portions of the plurality of electrode layers in this way, the distance between the solder layers located on both sides of the insulating layer becomes long. As a result, the distance between the mounting solders adhering to the solder layer becomes long, and even if the resistance value of the resistor is lowered, it is possible to prevent the solder interlayer short circuit from occurring.

第2の発明は、チップ状の金属製抵抗体と、金属製抵抗体の片面上にメッキにより形成された複数の電極層と、複数の電極層上にメッキにより形成された複数の半田層と、片面上に形成されて金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法を改良の対象とする。本発明のチップ状金属抵抗器の製造方法は、金属製抵抗体の片面に絶縁層を形成し、複数の電極層を絶縁層の上にオーバラップするオーバラップ部を有するように形成し、複数の半田層を複数の電極層のオーバラップ部を覆うように形成し、複数の半田層のオーバラップ部を覆う部分を除去する各工程を含んでなる。 The second invention comprises a chip-shaped metal resistor, a plurality of electrode layers formed by plating on one side of the metal resistor, and a plurality of solder layers formed by plating on the plurality of electrode layers. The method for manufacturing a chip-shaped metal resistor, which is formed on one surface and includes an insulating layer for determining the resistance value between electrodes of the metal resistor, is targeted for improvement. In the method for manufacturing a chip-shaped metal resistor of the present invention, an insulating layer is formed on one side of a metal resistor, and a plurality of electrode layers are formed so as to have an overlapping portion overlapping on the insulating layer. The solder layer is formed so as to cover the overlapping portion of the plurality of electrode layers, and each step of removing the portion covering the overlapping portion of the plurality of solder layers is included.

このようなチップ状金属抵抗器の製造方法によると、複数の半田層を複数の電極層のオーバラップ部を露出させるように形成したチップ状金属抵抗器を容易に製造することができる。 According to such a method for manufacturing a chip-shaped metal resistor, it is possible to easily manufacture a chip-shaped metal resistor in which a plurality of solder layers are formed so as to expose an overlapping portion of a plurality of electrode layers.

第3の発明は、チップ状の金属製抵抗体と、金属製抵抗体の片面上にメッキにより形成された複数の電極層と、複数の電極層上にメッキにより形成された複数の半田層と、片面上に形成されて金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法を改良の対象とする。本発明のチップ状金属抵抗器の製造方法は、金属製抵抗体の片面に絶縁層を形成し、複数の電極層を絶縁層の上にオーバラップするオーバラップ部を有するように形成し、オーバラップ部及びオーバラップ部間に位置する絶縁層を覆うようにマスキング用絶縁層を形成し、マスキング用絶縁層によって覆われていない複数の電極層の上に複数の半田層を形成し、その後マスキング用絶縁層を除去する各工程を含んでなる。 The third invention comprises a chip-shaped metal resistor, a plurality of electrode layers formed by plating on one side of the metal resistor, and a plurality of solder layers formed by plating on the plurality of electrode layers. The method for manufacturing a chip-shaped metal resistor, which is formed on one surface and includes an insulating layer for determining the resistance value between electrodes of the metal resistor, is targeted for improvement. In the method for manufacturing a chip-shaped metal resistor of the present invention, an insulating layer is formed on one side of a metal resistor, and a plurality of electrode layers are formed so as to have an overlapping portion that overlaps the insulating layer. An insulating layer for masking is formed so as to cover the insulating layer located between the wrap portion and the overlapping portion, and a plurality of solder layers are formed on a plurality of electrode layers not covered by the insulating layer for masking, and then masking is performed. Each step of removing the insulating layer is included.

このようなチップ状金属抵抗器の製造方法によると、複数の半田層を複数の電極層のオーバラップ部を露出させるように形成したチップ状金属抵抗器を容易に製造することができる。 According to such a method for manufacturing a chip-shaped metal resistor, it is possible to easily manufacture a chip-shaped metal resistor in which a plurality of solder layers are formed so as to expose an overlapping portion of a plurality of electrode layers.

第4の発明は、チップ状の金属製抵抗体と、金属製抵抗体の片面上にメッキにより形成された複数の電極層と、複数の電極層上にメッキにより形成された複数の半田層と、片面上に形成されて金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器を改良の対象とする。本発明のチップ状金属抵抗器では、複数の半田層の各内側端縁が複数の電極層の各内側端縁よりも内側に延長することを阻止するように、複数の半田層の各内側端縁と複数の電極層の各内側端縁との間に入り込む延長阻止部を絶縁層が有しているように形成されている。 The fourth invention comprises a chip-shaped metal resistor, a plurality of electrode layers formed by plating on one side of the metal resistor, and a plurality of solder layers formed by plating on the plurality of electrode layers. , A chip-shaped metal resistor formed on one surface and provided with an insulating layer for determining the resistance value between electrodes of the metal resistor is targeted for improvement. The chip-like metal resistor of the present invention, so as to prevent the respective inner edges of the plurality of solder layers extend inward from the inner edge of the plurality of electrode layers, each inner end of the plurality of solder layers The insulating layer is formed so as to have an extension blocking portion that penetrates between the edge and each inner edge of the plurality of electrode layers.

このように絶縁層が延長阻止部を有するように形成することにより、複数の半田層の各内側端縁の相互間の距離を長く保つことができ、よって抵抗体の抵抗値を低くしても半田層間短絡の発生を防止することができる。 By forming the insulating layer so as to have an extension blocking portion in this way, it is possible to maintain a long distance between the inner edge of each of the plurality of solder layers, and therefore even if the resistance value of the resistor is lowered. It is possible to prevent the occurrence of short circuit between solder layers.

チップ状金属抵抗器の絶縁層は、複数の電極層の内側端縁の終端位置を決めて電極間抵抗値を決定する電極間抵抗値決定用絶縁層と、電極間抵抗値決定用絶縁層の上に重なって形成される本体部及び電極間抵抗値決定用絶縁層の端部を越えて延びる延長阻止部を備えて複数の半田層の内側端縁の終端位置を決めて電極間距離を決定する電極間距離決定用絶縁層を有するように構成されていてもよい。 The insulating layer of the chip-shaped metal resistor consists of an insulating layer for determining the resistance value between electrodes and an insulating layer for determining the resistance value between electrodes, which determines the end position of the inner edge of a plurality of electrode layers and determines the resistance value between electrodes. A main body formed on top of each other and an extension blocking portion extending beyond the end of the insulating layer for determining the resistance value between electrodes are provided, and the end positions of the inner end edges of a plurality of solder layers are determined to determine the distance between electrodes. It may be configured to have an insulating layer for determining the distance between electrodes.

発明のチップ状金属抵抗器において、複数の電極層は電極間抵抗値決定用絶縁層を間に挟むように形成された第1の電極形成層と電極間距離決定用絶縁層を間に挟むように形成された第2の電極形成層とをそれぞれ備えていてもよい。 In the chip-shaped metal resistor of the present invention, the plurality of electrode layers sandwich the first electrode forming layer formed so as to sandwich the insulating layer for determining the resistance value between electrodes and the insulating layer for determining the distance between electrodes. A second electrode forming layer formed in the above may be provided.

また第4の発明のチップ状金属抵抗器において、電極間抵抗値決定用絶縁層と電極間距離決定用絶縁層とが、異なる絶縁材料で形成されていても、同じ絶縁材料で形成されていてもよい。 Further, in the chip-shaped metal resistor of the fourth invention, even if the insulating layer for determining the resistance value between electrodes and the insulating layer for determining the distance between electrodes are formed of different insulating materials, they are formed of the same insulating material. May be good.

第4の発明のチップ状金属抵抗器は、金属製抵抗体の片面上に電極間抵抗値決定用絶縁層を形成し、電極間抵抗値決定用絶縁層をマスキング層として第1の電極形成層をメッキにより形成し、電極間抵抗値決定用絶縁層の上及び電極間抵抗値決定用絶縁層と第1の電極形成層の境界部を越えるように電極間距離決定用絶縁層を形成し、電極間距離決定用絶縁層をマスキング層として第2の電極形成層をメッキにより形成し、第2の電極形成層の上に半田層をメッキで形成する各工程を含む製造方法により製造することができる。 In the chip-shaped metal resistor of the fourth invention, an insulating layer for determining the resistance value between electrodes is formed on one surface of a metal resistor, and the insulating layer for determining the resistance value between electrodes is used as a masking layer as a first electrode forming layer. Is formed by plating, and an insulating layer for determining the distance between electrodes is formed on the insulating layer for determining the resistance value between electrodes and beyond the boundary between the insulating layer for determining the resistance value between electrodes and the first electrode forming layer. It can be manufactured by a manufacturing method including each step of forming a second electrode forming layer by plating with an insulating layer for determining the distance between electrodes as a masking layer and forming a solder layer on the second electrode forming layer by plating. can.

第5の発明のチップ状金属抵抗器は、複数の半田層が絶縁層の上にオーバラップするオーバラップ部を有しないように形成されており、複数の半田層は複数の電極層の上にのみ形成されている。このチップ状金属抵抗器は、金属製抵抗体の片面に電極間抵抗値を決定する絶縁層を形成し、この絶縁層の上にマスキング用絶縁層を形成し、その後複数の電極層及び複数の半田層を形成し、最後にマスキング用絶縁層を全部除去するかまたは厚みを減少するように一部を除去することにより製造することができる。 The chip-shaped metal resistor of the fifth invention is formed so that a plurality of solder layers do not have an overlapping portion overlapping on the insulating layer, and the plurality of solder layers are formed on the plurality of electrode layers. Only formed. In this chip-shaped metal resistor, an insulating layer for determining the resistance value between electrodes is formed on one side of a metal resistor, a masking insulating layer is formed on the insulating layer, and then a plurality of electrode layers and a plurality of electrode layers are formed. It can be manufactured by forming a solder layer and finally removing the entire masking insulating layer or removing a part of the insulating layer so as to reduce the thickness.

第6の発明のチップ状金属抵抗器も、複数の半田層が絶縁層の上にオーバラップするオーバラップ部を有しないように形成されており、複数の半田層は複数の電極層の上にのみ形成されている。このチップ状金属抵抗器は、金属製抵抗体の片面にマスキング材料からなる電極間抵抗値を決定する絶縁層を形成し、その後複数の電極層及び複数の半田層を形成し、最後に絶縁層を全部除去するかまたは厚みを減少するように一部を除去することにより製造することができる。 The chip-shaped metal resistor of the sixth invention is also formed so that the plurality of solder layers do not have an overlapping portion overlapping on the insulating layer, and the plurality of solder layers are formed on the plurality of electrode layers. Only formed. In this chip-shaped metal resistor, an insulating layer made of a masking material for determining the resistance value between electrodes is formed on one side of a metal resistor, then a plurality of electrode layers and a plurality of solder layers are formed, and finally an insulating layer is formed. It can be manufactured by removing all of it or removing a part of it so as to reduce the thickness.

本発明に係るチップ状金属抵抗器の第1の実施形態の積層構造を示す断面図である。なお各図において、各層の厚さは説明のために実際の比率よりも厚くまたは薄く表されており、具体的なチップ状金属抵抗器の各層の厚みの比率は図とは異なる。It is sectional drawing which shows the laminated structure of 1st Embodiment of the chip-shaped metal resistor which concerns on this invention. In each figure, the thickness of each layer is shown to be thicker or thinner than the actual ratio for the sake of explanation, and the ratio of the thickness of each layer of the specific chip-shaped metal resistor is different from the figure. (a)乃至(e)は、図1のチップ状金属抵抗器を製造する本発明に係るチップ状金属抵抗器の製造方法に係る第1の実施形態の製造工程を示す図である。(A) to (e) are diagrams showing the manufacturing process of the first embodiment according to the manufacturing method of the chip-shaped metal resistor according to the present invention for manufacturing the chip-shaped metal resistor of FIG. (c)及び(d)は、図1のチップ状金属抵抗器を製造する本発明に係るチップ状金属抵抗器の製造方法に係る第2の実施形態の製造工程を示す図であり、図3(c)より前の工程は図2(a)(b)と同一であるため図示を省略する。(C) and (d) are diagrams showing the manufacturing process of the second embodiment according to the manufacturing method of the chip-shaped metal resistor according to the present invention for manufacturing the chip-shaped metal resistor of FIG. 1, and FIG. Since the steps prior to (c) are the same as those in FIGS. 2 (a) and 2 (b), the illustration is omitted. 本発明に係るチップ状金属抵抗器の第2の実施形態の積層構造を示す断面図である。It is sectional drawing which shows the laminated structure of the 2nd Embodiment of the chip-shaped metal resistor which concerns on this invention. (a)及び(b)はそれぞれ、本発明に係るチップ状金属抵抗器の他の実施形態の積層構造の一部分を示す拡大断面図である。(A) and (b) are enlarged sectional views showing a part of the laminated structure of another embodiment of the chip metal resistor according to the present invention, respectively. (a)乃至(d)は、図4のチップ状金属抵抗器を製造する本発明に係るチップ状金属抵抗器の製造方法に係る第2の実施形態の製造工程を示す図である。(A) to (d) are diagrams showing the manufacturing process of the second embodiment according to the manufacturing method of the chip-shaped metal resistor according to the present invention for manufacturing the chip-shaped metal resistor of FIG. (a)乃至(d)は、第3の実施の形態のチップ状金属抵抗器を製造する製造工程を示す図である。(A) to (d) are diagrams showing a manufacturing process for manufacturing a chip-shaped metal resistor according to a third embodiment. (a)乃至(c)は、第4の実施の形態のチップ状金属抵抗器を製造する製造工程を示す図である。(A) to (c) are diagrams showing a manufacturing process for manufacturing a chip-shaped metal resistor according to a fourth embodiment.

以下、図を参照しつつ、本発明の実施形態について詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(第1の実施形態のチップ状金属抵抗器)
図1は第1の実施形態のチップ状金属抵抗器の積層構造を示す。このチップ状金属抵抗器は、金属製抵抗体10と、一対の電極層20,20と、各電極層20,20上の2つの半田層30,30と、絶縁層40,50とを備えている。
(Chip-shaped metal resistor of the first embodiment)
FIG. 1 shows a laminated structure of chip-shaped metal resistors according to the first embodiment. This chip-shaped metal resistor includes a metal resistor 10, a pair of electrode layers 20 and 20, two solder layers 30 and 30 on each of the electrode layers 20 and 20, and insulating layers 40 and 50. There is.

金属製抵抗体10は一様の厚みを有し、平面視長方形のチップ状である。金属製抵抗体10の具体的な材料としては、典型的にはCu−Mn系合金、Ni−Cu系合金、Ni−Cr系合金などが挙げられ、これらの中からチップ状金属抵抗器に所望されるサイズや抵抗値に応じて選択できる。 The metal resistor 10 has a uniform thickness and is in the shape of a rectangular chip in a plan view. Specific examples of the material of the metal resistor 10 include Cu—Mn-based alloys, Ni—Cu-based alloys, Ni—Cr-based alloys, and the like, which are desired for chip-shaped metal resistors. It can be selected according to the size and resistance value to be applied.

一対の電極層20,20はそれぞれ、金属製抵抗体10の片面にメッキにより形成された金属の層であり、典型的には電気伝導率の高い銅製である。本実施形態では電極層20は2つ示されているが、電極層が3つ以上備えられていてもよい。 Each of the pair of electrode layers 20 and 20 is a metal layer formed by plating on one side of the metal resistor 10, and is typically made of copper having high electrical conductivity. Although two electrode layers 20 are shown in this embodiment, three or more electrode layers may be provided.

半田層30,30は一対の電極層20,20それぞれの上にメッキにより形成されている。半田層30,30は、チップ状金属抵抗器が取り付けられて利用される各種の機器の基板上の電極(図示していない)と半田付けされることにより、基板上の電極と電極層20,20とを電気的に接続する。本実施の形態では、半田層30,30はスズ製である。 The solder layers 30 and 30 are formed by plating on each of the pair of electrode layers 20 and 20. The solder layers 30 and 30 are soldered to electrodes (not shown) on the substrate of various devices to which chip-shaped metal resistors are attached and used, so that the electrodes on the substrate and the electrode layers 20 are soldered to the electrodes 20 and 30. Electrically connect to 20. In this embodiment, the solder layers 30 and 30 are made of tin.

絶縁層40は、一対の電極層20,20の間の金属製抵抗体10の片面上に形成されて、一対の電極層20,20間の距離を決定することにより、金属製抵抗体10の電極間抵抗値を決定する。絶縁層40は、典型的にはエポキシ樹脂系の樹脂膜であり、厚膜印刷により形成される。 The insulating layer 40 is formed on one side of the metal resistor 10 between the pair of electrode layers 20 and 20, and the distance between the pair of electrode layers 20 and 20 is determined by determining the distance between the pair of electrode layers 20 and 20. Determine the resistance value between electrodes. The insulating layer 40 is typically an epoxy resin-based resin film, and is formed by thick film printing.

金属製抵抗体10の片面と反対側の面は、全面に渡って絶縁層50により被覆されている。絶縁層50も絶縁層40と同じくエポキシ樹脂系の樹脂膜であって、絶縁層40と同一の厚膜印刷設備により形成可能である。なお絶縁層40,50は厚膜印刷ではなく、フォトレジスト法により形成してもよい。 The surface of the metal resistor 10 opposite to one side is covered with an insulating layer 50 over the entire surface. The insulating layer 50 is also an epoxy resin-based resin film like the insulating layer 40, and can be formed by the same thick film printing equipment as the insulating layer 40. The insulating layers 40 and 50 may be formed by a photoresist method instead of thick film printing.

第1の実施形態のチップ状金属抵抗器は、各電極層20,20は絶縁層40の上にオーバラップするオーバラップ部22,22をそれぞれ有するように形成されている。そして、各半田層30,30が各電極層20,20のオーバラップ部22,22を露出させるようにそれぞれ形成されている。 In the chip-shaped metal resistor of the first embodiment, the electrode layers 20 and 20 are formed so as to have overlapping portions 22 and 22 on the insulating layer 40, respectively. The solder layers 30 and 30 are formed so as to expose the overlapped portions 22 and 22 of the electrode layers 20 and 20, respectively.

典型的なチップ状金属抵抗器において、金属製抵抗体10の厚さは約0.1〜1.0mm、矩形の各辺のサイズは約0.5〜7mmである。電極層20の厚さは約100μm、半田層30の厚さは約3〜15μm、絶縁層40,50の厚さは約20〜50μmである。 In a typical chip-shaped metal resistor, the thickness of the metal resistor 10 is about 0.1 to 1.0 mm, and the size of each side of the rectangle is about 0.5 to 7 mm. The thickness of the electrode layer 20 is about 100 μm, the thickness of the solder layer 30 is about 3 to 15 μm, and the thickness of the insulating layers 40 and 50 is about 20 to 50 μm.

(チップ状金属抵抗器の製造方法の第1の実施形態)
上記のような第1の実施形態のチップ状金属抵抗器は、図2に示す各製造工程を経て製造することができる。
(First Embodiment of the method for manufacturing a chip-shaped metal resistor)
The chip-shaped metal resistor of the first embodiment as described above can be manufactured through each manufacturing step shown in FIG.

まず最初に、図2(a)に示すように、金属製抵抗体10の片面に絶縁層40を形成する。図2(a)では既に絶縁層50も形成されているが、先に金属製抵抗体10の片面とは反対側の全面に絶縁層50を厚膜印刷し、その後片面に部分的に絶縁層40を厚膜印刷する。 First, as shown in FIG. 2A, the insulating layer 40 is formed on one side of the metal resistor 10. In FIG. 2A, the insulating layer 50 is already formed, but the insulating layer 50 is first printed on the entire surface of the metal resistor 10 opposite to one side, and then the insulating layer is partially printed on one side. 40 is printed on a thick film.

次に、図2(b)に示すように、一対の電極層20,20をメッキにより形成する。金属製抵抗体10の片面の上に、絶縁層40の厚さよりも十分に厚くなるように銅メッキ処理を施せば、電極層20,20には絶縁層40の端縁近くにオーバラップするオーバラップ部22が形成される。 Next, as shown in FIG. 2B, the pair of electrode layers 20 and 20 are formed by plating. If copper plating is applied on one side of the metal resistor 10 so as to be sufficiently thicker than the thickness of the insulating layer 40, the electrode layers 20 and 20 overlap with each other near the edge of the insulating layer 40. The wrap portion 22 is formed.

次に、図2(c)に示すように、2つの半田層30,30をスズメッキにより形成する。各半田層30,30は、一対の電極層20,20それぞれのオーバラップ部22,22を覆うように形成されたオーバラップ部覆い部32,32を有する。 Next, as shown in FIG. 2C, the two solder layers 30 and 30 are formed by tin plating. Each of the solder layers 30 and 30 has an overlap portion covering portion 32 and 32 formed so as to cover the overlap portions 22 and 22 of the pair of electrode layers 20 and 20, respectively.

次に、図2(d)に示すように、各半田層30,30のオーバラップ部覆い部32,32以外の部分の上に、スズメッキ保護膜60,60を形成する。スズメッキ保護膜60,60は適当な樹脂製であり、パターン印刷により形成することができる。 Next, as shown in FIG. 2D, tin-plated protective films 60 and 60 are formed on the portions of the solder layers 30 and 30 other than the overlapped portion covering portions 32 and 32. The tin-plated protective films 60, 60 are made of an appropriate resin and can be formed by pattern printing.

次に、図2(e)に示すように、スズメッキ除去処理を施すことにより、各半田層30,30のスズメッキ保護膜60,60により保護されていない部分、すなわち各半田層30,30のオーバラップ部覆い部32,32が除去されて、一対の電極層20,20それぞれのオーバラップ部22,22が露出する。その後、スズメッキ保護膜60を除去することにより、図1に示すチップ状金属抵抗器を製造することができる。 Next, as shown in FIG. 2E, by performing the tinning removal treatment, the portions of the solder layers 30 and 30 that are not protected by the tinning protective films 60 and 60, that is, the solder layers 30 and 30 are overlaid. The wrap portion covering portions 32 and 32 are removed, and the overlap portions 22 and 22 of the pair of electrode layers 20 and 20 are exposed. Then, by removing the tin-plated protective film 60, the chip-shaped metal resistor shown in FIG. 1 can be manufactured.

他の実施形態の製造方法においては、一対の電極層20,20のオーバラップ部22,22を覆うオーバラップ部覆い部32,32を除去するために、研削のような機械加工や、レーザー光除去等の処理を適用することができる。一対の電極層20,20のオーバラップ部22,22を露出させるのは、半田層30,30及び半田層30,30にそれぞれ実装された半田の相互間の距離が短いことが原因となって、半田層間短絡を発生しないようにするためである。従って半田層30,30を一部除去した部分の寸法精度は高い精度は要求されない。またオーバラップ部22,22表面からのスズの完全除去までが要求されることはなく、ややスズが少々残っていても、逆にオーバラップ部22,22が一部除去されても大きな問題は生じない。 In the manufacturing method of another embodiment, in order to remove the overlapping portion covering portions 32, 32 that cover the overlapping portions 22, 22 of the pair of electrode layers 20, 20, machining such as grinding or laser light is performed. Processing such as removal can be applied. The reason why the overlapping portions 22 and 22 of the pair of electrode layers 20 and 20 are exposed is that the distance between the solder layers 30 and 30 and the solder mounted on the solder layers 30 and 30 is short. This is to prevent short circuits between solder layers. Therefore, high accuracy is not required for the dimensional accuracy of the portion where the solder layers 30 and 30 are partially removed. Further, it is not required to completely remove tin from the surfaces of the overlap portions 22 and 22, and even if a small amount of tin remains, conversely, even if a part of the overlap portions 22 and 22 is removed, there is a big problem. Does not occur.

なお工業的には、このようなチップ状金属抵抗器は複数個が同時に製造される。すなわち金属製抵抗体10は製造時には水平方向に拡く延びており、縦横に多数並んだ各部分に同時に上記の各処理が施され、各処理の終了後に各部分が切断されて、図1に示すような一定の大きさに分けられる。 Industrially, a plurality of such chip-shaped metal resistors are manufactured at the same time. That is, the metal resistor 10 extends in the horizontal direction at the time of manufacture, and each of the above-mentioned treatments is simultaneously applied to each of a large number of vertically and horizontally arranged parts, and each part is cut after the completion of each treatment, as shown in FIG. It is divided into certain sizes as shown.

このような製造方法により製造された第1のチップ状金属抵抗器は、各半田層30,30が一対の電極層20,20のオーバラップ部22,22を露出させるように形成されて、絶縁層40の両側に位置する各半田層30,30の間の距離が長くなり、その結果、各半田層30,30に付着する実装用の半田間の距離も長くなるので、抵抗体の抵抗値が低い場合でも、各半田層30,30の間で短絡が発生することを防ぐことができる。 The first chip-shaped metal resistor manufactured by such a manufacturing method is formed so that the solder layers 30 and 30 expose the overlap portions 22 and 22 of the pair of electrode layers 20 and 20 to insulate the first chip-shaped metal resistor. Since the distance between the solder layers 30 and 30 located on both sides of the layer 40 becomes long, and as a result, the distance between the mounting solders adhering to the solder layers 30 and 30 also becomes long, the resistance value of the resistor becomes long. Even when the value is low, it is possible to prevent a short circuit from occurring between the solder layers 30 and 30.

(チップ状金属抵抗器の製造方法の第2の実施形態)
図3はチップ状金属抵抗器の製造方法の第2の実施形態を示す。第2の実施形態の製造方法は、第1の実施形態の製造方法における図2(b)に示す工程までは第1の実施形態の製造方法と同一であり、その後の製造工程についてのみ説明する。
(Second embodiment of the method for manufacturing a chip-shaped metal resistor)
FIG. 3 shows a second embodiment of a method for manufacturing a chip-shaped metal resistor. The manufacturing method of the second embodiment is the same as the manufacturing method of the first embodiment up to the step shown in FIG. 2B in the manufacturing method of the first embodiment, and only the subsequent manufacturing steps will be described. ..

図3(c)に示すように、金属製抵抗体10の片面に絶縁層40を形成し、一対の電極層20,20を絶縁層40の上にオーバラップ部22,22をそれぞれ有するように形成した図2(b)の状態の半加工品に対し、オーバラップ部22,22及びオーバラップ部22,22間に位置する絶縁層40を覆うようにマスキング用絶縁層62が形成される。マスキング用絶縁層62は適当な樹脂製であって、スクリーン印刷により形成することができる。 As shown in FIG. 3 (c), the insulating layer 40 is formed on one side of the metal resistor 10, and the pair of electrode layers 20 and 20 have the overlapping portions 22 and 22 on the insulating layer 40, respectively. The masking insulating layer 62 is formed so as to cover the insulating layer 40 located between the overlapping portions 22 and 22 and the overlapping portions 22 and 22 with respect to the formed semi-processed product in the state of FIG. 2 (b). The masking insulating layer 62 is made of a suitable resin and can be formed by screen printing.

次に、図3(d)に示すように、マスキング用絶縁層62に覆われていない一対の電極層20,20の上にそれぞれ半田層30,30をメッキにより形成する。その後、マスキング用絶縁層62を除去することにより、図1に示すチップ状金属抵抗器を製造することができる。 Next, as shown in FIG. 3D, the solder layers 30 and 30 are formed by plating on the pair of electrode layers 20 and 20 not covered by the masking insulating layer 62, respectively. Then, by removing the masking insulating layer 62, the chip-shaped metal resistor shown in FIG. 1 can be manufactured.

(第2の実施形態のチップ状金属抵抗器)
図4は、本発明に係るチップ状金属抵抗器の第2の実施の形態の積層構造を示す断面図であり、第1の実施の形態と同じ機能を有する部材には同じ符号を付して示した上で詳細な説明を省略する。
(Chip-shaped metal resistor of the second embodiment)
FIG. 4 is a cross-sectional view showing the laminated structure of the second embodiment of the chip-shaped metal resistor according to the present invention, and the members having the same functions as those of the first embodiment are designated by the same reference numerals. Although it is shown, a detailed description will be omitted.

各図において、第2の実施形態のチップ状金属抵抗器は、チップ状の金属製抵抗体10と、金属製抵抗体10の片面にメッキにより形成された一対の電極層70,70と、一対の電極層70,70それぞれの上にメッキにより形成された半田層30,30と、片面上に形成された絶縁層80と、金属製抵抗体10の片面と反対側の面を被覆する絶縁層50とを備えている。 In each figure, the chip-shaped metal resistor of the second embodiment includes a chip-shaped metal resistor 10 and a pair of electrode layers 70, 70 formed by plating on one side of the metal resistor 10. The solder layers 30 and 30 formed by plating on each of the electrode layers 70 and 70, the insulating layer 80 formed on one side, and the insulating layer covering the surface opposite to one side of the metal resistor 10. It has 50 and.

第2の実施形態のチップ状金属抵抗器においては、各半田層30の各内側端縁が一対の電極層70,70の各内側端縁よりも内側に延長することを阻止するように、各半田層30,30の各内側端縁と一対の電極層70,70の各内側端縁との間に入り込む延長阻止部81,81を絶縁層80が有しているように形成されている。 In the chip-shaped metal resistor of the second embodiment, each inner edge of each solder layer 30 is prevented from extending inward from each inner edge of the pair of electrode layers 70, 70. The insulating layer 80 is formed so as to have extension blocking portions 81, 81 that enter between the inner edge of the solder layers 30 and 30 and the inner edges of the pair of electrode layers 70 and 70.

絶縁層80は2つの層に分かれて形成されている。電極間抵抗値決定用絶縁層82は金属製抵抗体10の片面上に形成され、電極間距離決定用絶縁層84は電極間抵抗値決定用絶縁層82の上層に形成される。電極間距離決定用絶縁層84は電極間抵抗値決定用絶縁層82の上に重なって形成される本体部83及び電極間抵抗値決定用絶縁層82の端部を超えて延びる延長阻止部81,81を備えている。 The insulating layer 80 is formed by being divided into two layers. The insulating layer 82 for determining the resistance value between electrodes is formed on one surface of the metal resistor 10, and the insulating layer 84 for determining the distance between electrodes is formed on the upper layer of the insulating layer 82 for determining the resistance value between electrodes. The insulating layer 84 for determining the distance between electrodes is an extension blocking portion 81 extending beyond the end portions of the main body portion 83 formed by overlapping the insulating layer 82 for determining the resistance value between electrodes and the insulating layer 82 for determining the resistance value between electrodes. , 81 is provided.

一対の電極層70,70は、電極間抵抗値決定用絶縁層82を間に挟むように形成された第1の電極形成層72と、電極間距離決定用絶縁層84を間に挟むように形成された第2の電極形成層74とをそれぞれ備えている。 The pair of electrode layers 70, 70 sandwiches the first electrode forming layer 72 formed so as to sandwich the insulating layer 82 for determining the resistance value between electrodes and the insulating layer 84 for determining the distance between electrodes. Each includes a second electrode forming layer 74 formed.

各層の材料は第1の実施形態のチップ状金属抵抗器と同様であり、すなわち絶縁層50、80は樹脂製、一対の電極層70,70は銅製、半田層30,30はスズ製である。絶縁層80の電極間抵抗値決定用絶縁層82と電極間距離決定用絶縁層84とは同じ絶縁材料で形成されているが、他の実施形態では異なる絶縁材料で形成されている。 The material of each layer is the same as that of the chip-shaped metal resistor of the first embodiment, that is, the insulating layers 50 and 80 are made of resin, the pair of electrode layers 70 and 70 are made of copper, and the solder layers 30 and 30 are made of tin. .. The insulating layer 82 for determining the resistance value between electrodes and the insulating layer 84 for determining the distance between electrodes of the insulating layer 80 are formed of the same insulating material, but in other embodiments, they are formed of different insulating materials.

各図は、各層の厚みの比率は実際の製品と正確に一致して示していないが、図4の第2の実施形態のチップ状金属抵抗器では、電極間抵抗値決定用絶縁層82と第1の電極形成層72とはほぼ同じ厚さに形成されている。図5(a)の他の実施形態では電極間抵抗値決定用絶縁層82よりも第1の電極形成層72の方が少し厚くなっており、そのため境界には電極間抵抗値決定用絶縁層82の上に第1の電極形成層72のオーバラップが僅かに生じている。逆に、図5(b)に示すさらに他の実施形態においては、電極間抵抗値決定用絶縁層82よりも第1の電極形成層72が少し薄くなるように形成されている。 Although each figure does not show the ratio of the thickness of each layer exactly in agreement with the actual product, in the chip-shaped metal resistor of the second embodiment of FIG. 4, the insulating layer 82 for determining the resistance value between electrodes is used. It is formed to have substantially the same thickness as the first electrode forming layer 72. In another embodiment of FIG. 5A, the first electrode forming layer 72 is slightly thicker than the insulating layer 82 for determining the resistance value between electrodes, and therefore the insulating layer for determining the resistance value between electrodes is at the boundary. There is a slight overlap of the first electrode forming layer 72 on the 82. On the contrary, in still another embodiment shown in FIG. 5B, the first electrode forming layer 72 is formed to be slightly thinner than the insulating layer 82 for determining the resistance value between electrodes.

このように絶縁層が延長阻止部81,81を有するように形成することにより、半田層30の各内側端縁の相互間の距離を長く保つことができ、よって抵抗体の抵抗値を低くしても半田層30間短絡の発生を防止することができる。 By forming the insulating layer so as to have the extension blocking portions 81 and 81 in this way, the distance between the inner edges of the solder layers 30 can be kept long, and thus the resistance value of the resistor is lowered. However, it is possible to prevent the occurrence of a short circuit between the solder layers 30.

(チップ状金属抵抗器の製造方法の第2の実施形態)
上記のような第2の実施形態のチップ状金属抵抗器は、図6に示す各製造工程を経て製造することができる。
(Second embodiment of the method for manufacturing a chip-shaped metal resistor)
The chip-shaped metal resistor of the second embodiment as described above can be manufactured through each manufacturing step shown in FIG.

まず最初に、図6(a)に示すように、金属製抵抗体10の片面に電極間抵抗値決定用絶縁層82を形成する。金属製抵抗体10の片面とは反対側の面には絶縁層50が形成されている。 First, as shown in FIG. 6A, an insulating layer 82 for determining the resistance value between electrodes is formed on one side of the metal resistor 10. An insulating layer 50 is formed on the surface of the metal resistor 10 opposite to one side.

次に、図6(b)に示すように、電極間抵抗値決定用絶縁層82をマスキング層として一対の第1の電極形成層72、72を銅メッキにより形成する。 Next, as shown in FIG. 6B, the pair of first electrode forming layers 72 and 72 are formed by copper plating with the insulating layer 82 for determining the resistance value between electrodes as a masking layer.

次に、図6(c)に示すように、電極間抵抗値決定用絶縁層82の上及び電極間抵抗値決定用絶縁層82と第1の電極形成層の境界部を越えるように電極間距離決定用絶縁層84を形成する。 Next, as shown in FIG. 6 (c), above the insulating layer 82 for determining the resistance value between the electrodes and between the electrodes so as to cross the boundary between the insulating layer 82 for determining the resistance value between the electrodes and the first electrode forming layer. The insulation layer 84 for determining the distance is formed.

次に、図6(d)に示すように、電極間距離決定用絶縁層84をマスキング層として第2の電極形成層74をメッキにより形成する。その後、第2の電極形成層74の上に半田層30をメッキで形成することにより、図4に示す第2の実施形態のチップ状金属抵抗器を構成することができる。 Next, as shown in FIG. 6D, the second electrode forming layer 74 is formed by plating with the insulating layer 84 for determining the distance between electrodes as a masking layer. Then, by forming the solder layer 30 on the second electrode forming layer 74 by plating, the chip-shaped metal resistor of the second embodiment shown in FIG. 4 can be formed.

以上の通り、第2の実施形態のチップ状金属抵抗器によると、絶縁層80が延長阻止部81を有するように形成したので、各半田層30,30の各内側端縁の相互間の距離を長く保つことができ、よって金属製抵抗体10の抵抗値が低い場合でも半田層30,30間の短絡の発生を防止することができる。 As described above, according to the chip-shaped metal resistor of the second embodiment, since the insulating layer 80 is formed so as to have the extension blocking portion 81, the distance between the inner edges of the solder layers 30 and 30 is mutual. Therefore, even when the resistance value of the metal resistor 10 is low, it is possible to prevent the occurrence of a short circuit between the solder layers 30 and 30.

(チップ状金属抵抗器の第3の実施の形態及びその製造方法)
図7(a)乃至(d)は、本発明のチップ状金属抵抗器の第3の実施の形態の製造方法の工程を示している。最初に、図7(a)に示すように、金属製抵抗体10の片面に電極間抵抗値決定用絶縁層40を形成する。金属製抵抗体10の片面とは反対側の面には絶縁層50が形成されている。
(Third Embodiment of a chip-shaped metal resistor and a method for manufacturing the same)
7 (a) to 7 (d) show the process of the manufacturing method of the 3rd Embodiment of the chip metal resistor of this invention. First, as shown in FIG. 7A, an insulating layer 40 for determining the resistance value between electrodes is formed on one side of the metal resistor 10. An insulating layer 50 is formed on the surface of the metal resistor 10 opposite to one side.

次に、図7(b)に示すように、電極間抵抗値決定用絶縁層40の上にマスキング用絶縁層62を形成した後に、一対の電極層20,20を銅メッキにより形成し、さらにマスキング用絶縁層62をマスキング層として半田層30,30をスズメッキにより形成する。なお本実施の形態では、マスキング用絶縁層62の厚みは、100μm程度ある。 Next, as shown in FIG. 7B, after forming the masking insulating layer 62 on the insulating layer 40 for determining the resistance value between electrodes, the pair of electrode layers 20 and 20 are formed by copper plating, and further. The solder layers 30 and 30 are formed by tin plating with the masking insulating layer 62 as the masking layer. In this embodiment, the thickness of the masking insulating layer 62 is about 100 μm.

次に図7(c)に示すように、マスキング用絶縁層62を全部除去するか、図7(d)に示すようにマスキング用絶縁層62の厚みを減少するように一部除去する。残ったマスキング用絶縁層62´は保護層となる。 Next, as shown in FIG. 7 (c), the masking insulating layer 62 is completely removed, or as shown in FIG. 7 (d), a part of the masking insulating layer 62 is removed so as to reduce the thickness. The remaining masking insulating layer 62'is a protective layer.

このようにすると、複数の電極層20,20は電極間抵抗値決定用絶縁層40及びマスキング用絶縁層62上にオーバラップするオーバラップ部を有しないように形成され、複数の半田層30,30が複数の電極層20,20の上にのみ形成されたチップ状金属抵抗器を簡単に製造することができる。なお印刷ずれを考慮してマスキング用絶縁層62を電極間抵抗値決定用絶縁層40よりも小さく形成してもよい。この場合には、電極層20,20の一部が電極間抵抗値決定用絶縁層40の上に一部オーバラップすることになるが、複数の半田層30,30は複数の電極層20,20の上にのみ形成される。またこのようにすると半田層30が電極層20,20の端部にオーバラップしない状態になるので、実装用回路上の半田付け用電極に対する実装ずれが小さくなる利点が得られる。 In this way, the plurality of electrode layers 20, 20 are formed so as not to have an overlapping portion on the insulating layer 40 for determining the resistance value between electrodes and the insulating layer 62 for masking, and the plurality of solder layers 30, A chip-shaped metal resistor in which 30 is formed only on a plurality of electrode layers 20, 20 can be easily manufactured. In consideration of printing misalignment, the masking insulating layer 62 may be formed smaller than the insulating layer 40 for determining the resistance value between electrodes. In this case, a part of the electrode layers 20 and 20 partially overlaps the insulating layer 40 for determining the resistance value between the electrodes, but the plurality of solder layers 30 and 30 have the plurality of electrode layers 20 and 20. Formed only on top of 20. Further, in this case, the solder layer 30 does not overlap with the ends of the electrode layers 20 and 20, so that there is an advantage that the mounting deviation with respect to the soldering electrode on the mounting circuit is small.

(チップ状金属抵抗器の第4の実施の形態及びその製造方法)
図8(a)及び(b)は、本発明のチップ状金属抵抗器の第4の実施の形態の製造方法の工程を示している。最初に、図8(a)に示すように、金属製抵抗体10の片面に電極間抵抗値決定用絶縁層40をマスキング用材料により形成する。金属製抵抗体10の片面とは反対側の面には絶縁層50が形成されている。
(Fourth Embodiment of Chip Metal Resistor and Method for Manufacturing thereof)
8 (a) and 8 (b) show the process of the manufacturing method of the 4th Embodiment of the chip metal resistor of this invention. First, as shown in FIG. 8A, an insulating layer 40 for determining the resistance value between electrodes is formed on one side of the metal resistor 10 with a masking material. An insulating layer 50 is formed on the surface of the metal resistor 10 opposite to one side.

次に、図8(b)に示すように、一対の電極層20,20を銅メッキにより形成し、さらに半田層30,30をスズメッキにより形成する。なお本実施の形態では、電極間抵抗値決定用絶縁層40の厚みは、100μm程度ある。 Next, as shown in FIG. 8B, the pair of electrode layers 20 and 20 are formed by copper plating, and the solder layers 30 and 30 are further formed by tin plating. In this embodiment, the thickness of the insulating layer 40 for determining the resistance value between electrodes is about 100 μm.

次に図8(c)に示すように、マスキング用材料により形成された電極間抵抗値決定用絶縁層40をその厚みを減少するように一部除去する。残った電極間抵抗値決定用絶縁層40´は保護層となる。なお電極間抵抗値決定用絶縁層40をすべて除去してもよいのは勿論である。 Next, as shown in FIG. 8C, the insulating layer 40 for determining the resistance value between electrodes formed of the masking material is partially removed so as to reduce its thickness. The remaining insulating layer 40'for determining the resistance value between electrodes serves as a protective layer. Of course, the insulating layer 40 for determining the resistance value between the electrodes may be completely removed.

このようにすると、複数の電極層20は電極間抵抗値決定用絶縁層40の上及び電極間抵抗値決定用絶縁層40と電極形成層の境界部を越え絶縁層40の上にオーバラップするオーバラップ部を有しないように形成され、複数の半田層30,30は複数の電極層20,20の上にのみ形成されたチップ状金属抵抗器を簡単に製造することができる。 In this way, the plurality of electrode layers 20 overlap on the insulating layer 40 for determining the resistance value between electrodes and on the insulating layer 40 beyond the boundary between the insulating layer 40 for determining the resistance value between electrodes and the electrode forming layer. A chip-shaped metal resistor formed so as not to have an overlap portion and having the plurality of solder layers 30 and 30 formed only on the plurality of electrode layers 20 and 20 can be easily manufactured.

本発明のチップ状金属抵抗器によれば、絶縁層の両側に位置する半田層間の距離を長くすることができる。よって金属抵抗体の抵抗値が低い場合でも、半田層間短絡が発生することがない。 According to the chip-shaped metal resistor of the present invention, the distance between the solder layers located on both sides of the insulating layer can be increased. Therefore, even when the resistance value of the metal resistor is low, short circuit between solder layers does not occur.

10 金属製抵抗体
20 電極層
22 オーバラップ部
30 半田層
40,50,80 絶縁層
60 スズメッキ保護膜
62 マスキング用絶縁層
70 電極層
72 第1の電極形成層
74 第2の電極形成層
81 延長阻止部
82 電極間抵抗値決定用絶縁層
83 本体部
84 電極間距離決定用絶縁層
10 Metal resistor 20 Electrode layer 22 Overlap part 30 Solder layer 40, 50, 80 Insulation layer 60 Tin-plated protective film 62 Masking insulation layer 70 Electrode layer 72 First electrode forming layer 74 Second electrode forming layer 81 Extension Blocking part 82 Insulating layer for determining resistance between electrodes 83 Main body 84 Insulating layer for determining distance between electrodes

Claims (12)

チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器であって、
前記複数の電極層は前記絶縁層の上にオーバラップするオーバラップ部を有するように形成されており、
前記複数の半田層は前記複数の電極層の前記オーバラップ部を露出させるように形成されていることを特徴とするチップ状金属抵抗器。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A chip-shaped metal resistor formed in the metal resistor and provided with an insulating layer for determining the resistance value between electrodes of the metal resistor.
The plurality of electrode layers are formed so as to have an overlapping portion that overlaps the insulating layer.
A chip-shaped metal resistor characterized in that the plurality of solder layers are formed so as to expose the overlapped portion of the plurality of electrode layers.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法であって、
前記金属製抵抗体の前記片面に前記絶縁層を形成し、
前記複数の電極層を前記絶縁層の上にオーバラップするオーバラップ部を有するように形成し、
前記複数の半田層を前記複数の電極層の前記オーバラップ部を覆うように形成し、
前記複数の半田層の前記オーバラップ部を覆う部分を除去することを特徴とするチップ状金属抵抗器の製造方法。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A method for manufacturing a chip-shaped metal resistor, which is formed in a metal resistor and includes an insulating layer for determining the resistance value between electrodes of the metal resistor.
The insulating layer is formed on one side of the metal resistor to form the insulating layer.
The plurality of electrode layers are formed so as to have an overlapping portion that overlaps the insulating layer.
The plurality of solder layers are formed so as to cover the overlapped portion of the plurality of electrode layers.
A method for manufacturing a chip-shaped metal resistor, which comprises removing a portion of the plurality of solder layers that covers the overlapped portion.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法であって、
前記金属製抵抗体の前記片面に前記絶縁層を形成し、
前記複数の電極層を前記絶縁層の上にオーバラップするオーバラップ部を有するように形成し、
前記オーバラップ部及び前記オーバラップ部間に位置する前記絶縁層を覆うようにマスキング用絶縁層を形成し、
前記マスキング用絶縁層によって覆われていない前記複数の電極層の上に前記複数の半田層を形成し、その後前記マスキング用絶縁層を除去することを特徴とするチップ状金属抵抗器の製造方法。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A method for manufacturing a chip-shaped metal resistor, which is formed in a metal resistor and includes an insulating layer for determining the resistance value between electrodes of the metal resistor.
The insulating layer is formed on one side of the metal resistor to form the insulating layer.
The plurality of electrode layers are formed so as to have an overlapping portion that overlaps the insulating layer.
A masking insulating layer is formed so as to cover the overlapping portion and the insulating layer located between the overlapping portions.
A method for manufacturing a chip-shaped metal resistor, which comprises forming the plurality of solder layers on the plurality of electrode layers not covered by the masking insulating layer, and then removing the masking insulating layer.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器であって、
前記複数の半田層の各内側端縁が前記複数の電極層の各内側端縁よりも内側に延長することを阻止するように、前記複数の半田層の前記各内側端縁と前記複数の電極層の前記各内側端縁との間に入り込む延長阻止部を前記絶縁層が有していることを特徴とするチップ状金属抵抗器。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A chip-shaped metal resistor formed in the metal resistor and provided with an insulating layer for determining the resistance value between electrodes of the metal resistor.
Each inner edge of the plurality of solder layers and the plurality of electrodes so as to prevent each inner edge of the plurality of solder layers from extending inward from each inner edge of the plurality of electrode layers. A chip-shaped metal resistor, characterized in that the insulating layer has an extension blocking portion that enters between the inner edges of the layer.
前記絶縁層は、前記複数の電極層の前記内側端縁の終端位置を決めて前記電極間抵抗値を決定する電極間抵抗値決定用絶縁層と、前記電極間抵抗値決定用絶縁層の上に重なって形成される本体部及び前記電極間抵抗値決定用絶縁層の端部を越えて延びる前記延長阻止部を備えて前記複数の半田層の前記内側端縁の終端位置を決めて電極間距離を決定する電極間距離決定用絶縁層を有している請求項4に記載のチップ状金属抵抗器。 The insulating layer is above the insulating layer for determining the resistance value between electrodes and the insulating layer for determining the resistance value between electrodes, which determines the end position of the inner edge of the plurality of electrode layers and determines the resistance value between electrodes. The main body portion formed so as to overlap the electrodes and the extension blocking portion extending beyond the end portion of the insulating layer for determining the resistance value between the electrodes are provided, and the terminal positions of the inner end edges of the plurality of solder layers are determined and between the electrodes. The chip-shaped metal resistor according to claim 4, which has an insulating layer for determining the distance between electrodes for determining the distance. 前記複数の電極層は前記電極間抵抗値決定用絶縁層を間に挟むように形成された第1の電極形成層と前記電極間距離決定用絶縁層を間に挟むように形成された第2の電極形成層とをそれぞれ備えている請求項5に記載のチップ状金属抵抗器。 The plurality of electrode layers are formed so as to sandwich a first electrode forming layer formed so as to sandwich the insulating layer for determining the resistance value between electrodes and an insulating layer for determining the distance between electrodes. The chip-shaped metal resistor according to claim 5, further comprising an electrode forming layer of the above. 前記電極間抵抗値決定用絶縁層と前記電極間距離決定用絶縁層とが、異なる絶縁材料で形成されている請求項5に記載のチップ状金属抵抗器。 The chip-shaped metal resistor according to claim 5, wherein the insulating layer for determining the resistance value between electrodes and the insulating layer for determining the distance between electrodes are formed of different insulating materials. 前記電極間抵抗値決定用絶縁層と前記電極間距離決定用絶縁層とが、同じ絶縁材料で形成されている請求項5に記載のチップ状金属抵抗器。 The chip-shaped metal resistor according to claim 5, wherein the insulating layer for determining the resistance value between electrodes and the insulating layer for determining the distance between electrodes are formed of the same insulating material. 請求項5乃至8のいずれか1項に記載のチップ状金属抵抗器の製造方法であって、
前記金属製抵抗体の前記片面上に前記電極間抵抗値決定用絶縁層を形成し、
前記電極間抵抗値決定用絶縁層をマスキング層として前記第1の電極形成層をメッキにより形成し、
前記電極間抵抗値決定用絶縁層の上及び前記電極間抵抗値決定用絶縁層と前記第1の電極形成層の境界部を越えるように前記電極間距離決定用絶縁層を形成し、
前記電極間距離決定用絶縁層をマスキング層として前記第2の電極形成層をメッキにより形成し、
前記第2の電極形成層の上に前記半田層をメッキで形成することを特徴とするチップ状金属抵抗器の製造方法。
The method for manufacturing a chip-shaped metal resistor according to any one of claims 5 to 8.
An insulating layer for determining the resistance value between electrodes is formed on one surface of the metal resistor.
The first electrode forming layer was formed by plating using the insulating layer for determining the resistance value between electrodes as a masking layer.
The insulating layer for determining the distance between the electrodes is formed on the insulating layer for determining the resistance value between the electrodes and beyond the boundary between the insulating layer for determining the resistance value between the electrodes and the first electrode forming layer.
The second electrode forming layer was formed by plating using the insulating layer for determining the distance between electrodes as a masking layer.
A method for manufacturing a chip-shaped metal resistor, which comprises forming the solder layer on the second electrode forming layer by plating.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器であって、
前記複数の半田層は前記絶縁層の上にオーバラップするオーバラップ部を有しないように前記複数の電極層の上にのみ形成されていることを特徴とするチップ状金属抵抗器。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A chip-shaped metal resistor formed in the metal resistor and provided with an insulating layer for determining the resistance value between electrodes of the metal resistor.
A chip-shaped metal resistor characterized in that the plurality of solder layers are formed only on the plurality of electrode layers so as not to have an overlapping portion overlapping on the insulating layer.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法であって、
前記金属製抵抗体の前記片面に前記絶縁層を形成し、
前記絶縁層の上にマスキング用絶縁層を形成し、
その後前記複数の電極層及び前記複数の半田層を形成し、
その後前記マスキング用絶縁層を全部除去するかまたは厚みを減少するように一部除去することを特徴とするチップ状金属抵抗器の製造方法。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A method for manufacturing a chip-shaped metal resistor, which is formed in a metal resistor and includes an insulating layer for determining the resistance value between electrodes of the metal resistor.
The insulating layer is formed on one side of the metal resistor to form the insulating layer.
An insulating layer for masking is formed on the insulating layer, and the insulating layer is formed.
After that, the plurality of electrode layers and the plurality of solder layers are formed, and the plurality of electrode layers and the plurality of solder layers are formed.
After that, a method for manufacturing a chip-shaped metal resistor, which comprises removing all the insulating layer for masking or partially removing the insulating layer for masking so as to reduce the thickness.
チップ状の金属製抵抗体と、前記金属製抵抗体の片面上にメッキにより形成された複数の電極層と、前記複数の電極層上にメッキにより形成された複数の半田層と、前記片面上に形成されて前記金属製抵抗体の電極間抵抗値を決定する絶縁層とを備えてなるチップ状金属抵抗器の製造方法であって、
前記金属製抵抗体の前記片面にマスキング材料からなる前記絶縁層を形成し、
その後前記複数の電極層及び前記複数の半田層を形成し、
その後前記絶縁層を全部除去するかまたは厚みを減少するように一部除去することを特徴とするチップ状金属抵抗器の製造方法。
A chip-shaped metal resistor, a plurality of electrode layers formed by plating on one surface of the metal resistor, a plurality of solder layers formed by plating on the plurality of electrode layers, and a plurality of solder layers on the one surface. A method for manufacturing a chip-shaped metal resistor, which is formed in a metal resistor and includes an insulating layer for determining the resistance value between electrodes of the metal resistor.
The insulating layer made of a masking material is formed on one side of the metal resistor, and the insulating layer is formed.
After that, the plurality of electrode layers and the plurality of solder layers are formed, and the plurality of electrode layers and the plurality of solder layers are formed.
A method for manufacturing a chip-shaped metal resistor, which is characterized in that the insulating layer is then completely removed or partially removed so as to reduce the thickness.
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JP3971335B2 (en) * 2003-04-08 2007-09-05 ローム株式会社 Chip resistor and manufacturing method thereof
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