JPH06350230A - Printed wiring board and production thereof - Google Patents

Printed wiring board and production thereof

Info

Publication number
JPH06350230A
JPH06350230A JP13726993A JP13726993A JPH06350230A JP H06350230 A JPH06350230 A JP H06350230A JP 13726993 A JP13726993 A JP 13726993A JP 13726993 A JP13726993 A JP 13726993A JP H06350230 A JPH06350230 A JP H06350230A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
electrodes
insulating film
dielectric film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP13726993A
Other languages
Japanese (ja)
Inventor
Nobuji Yonemoto
宜司 米本
Tsuguhisa Ishii
嗣久 石井
Yoshiki Akizuki
義樹 秋月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Ten Ltd
Original Assignee
Denso Ten Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Ten Ltd filed Critical Denso Ten Ltd
Priority to JP13726993A priority Critical patent/JPH06350230A/en
Publication of JPH06350230A publication Critical patent/JPH06350230A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To deal with the miniaturization of electronic component by forming a dielectric film between the electrodes formed on a printed wiring board through lamination of patterns having width decreasing toward the upper layer thereby preventing solder bridge without sacrifice of solderability. CONSTITUTION:Wiring patterns 5 and electrodes 2 are formed of a copper foil on the surface of a board body 1 and then a dielectric film layer 3 is formed thereon except the electrode parts 2 which are connected with the lead terminals of an electronic component. The dielectric film layer 3 is formed by screen printing of an epoxy resin resist ink, for example. After curing the dielectric film layer 3, second time screen printing is conducted while superposing a narrow insulation pattern detouring the electrode parts 2 on the underlying dielectric film layer 3 thus forming an upper dielectric film layer 4. A plurality of insulation layer patterns are formed with the width decreasing toward the upper layer. This structure widens the allowable range of shift and prevents the upper dielectric film layer 4 from adhering to the electrode 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体部品、チップ部
品等がプリント配線基板に半田付け実装されるにあた
り、半田ブリッジにより該部品が短絡されるのを防止し
たプリント配線基板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board which prevents short-circuiting of semiconductor parts, chip parts, etc. by solder bridges when the parts are soldered and mounted on the printed wiring board, and a method of manufacturing the same. .

【0002】[0002]

【従来の技術】従来、この種のプリント配線基板の構造
としては、図4に示すようなものがあった。図4におい
て、1はフェノール樹脂やエポキシ樹脂等の絶縁材より
なる基板本体、2と5は前記基板本体1の表面に銅箔で
形成された電極及び配線パターン、3は電子部品のリー
ド線と接続される該電極部分2を残し、それ以外の部分
をスクリーン印刷等の方法によりエポキシ樹脂等のレジ
ストインクで被覆したソルダ−レジストと呼ばれるもの
で外部と絶縁されている。
2. Description of the Related Art Conventionally, as a structure of a printed wiring board of this type, there has been one as shown in FIG. In FIG. 4, 1 is a substrate body made of an insulating material such as phenol resin or epoxy resin, 2 and 5 are electrodes and wiring patterns formed of copper foil on the surface of the substrate body 1, and 3 are lead wires of electronic parts. The electrode portion 2 to be connected is left and the other portion is covered with a resist ink such as an epoxy resin by a method such as screen printing to be insulated from the outside by a so-called solder resist.

【0003】前記基板上に形成された電極に電子部品の
リード端子が対応するように載置され、この状態で各リ
ード端子と電極を半田付けする。これによって、電気的
に接続されると共に、機械的に固定される。
The lead terminals of the electronic component are placed so as to correspond to the electrodes formed on the substrate, and in this state, the lead terminals and the electrodes are soldered. As a result, they are electrically connected and mechanically fixed.

【0004】[0004]

【発明が解決しようとする課題】図4に示す従来構成で
は、電子部品の小型化及び高密度実装化により、電子部
品のリード端子の間隔が狭い場合、例えば隣接する電極
2の間隔が0.25mm程度で形成されている場合は、半田付
けする際、半田が溶解状態で隣接する他の電極部分に流
れ込み固化し、短絡を起こす、いわゆる半田ブリッジと
呼ばれる半田不良が発生する欠点があった。
In the conventional structure shown in FIG. 4, due to the miniaturization and high-density mounting of electronic components, when the lead terminals of the electronic components are closely spaced, for example, the spacing between adjacent electrodes 2 is 0.25 mm. In the case of being formed in a certain degree, when soldering, there is a drawback in that the solder flows into another adjacent electrode portion in a melted state and solidifies to cause a short circuit, resulting in a so-called solder bridge.

【0005】即ち、図4(b)に示すように、従来は電
極のパターン2の厚さとレジスト3の厚さがほぼ同じた
め、半田ブリッジが発生しやすかった。そこで、より厚
いレジストを電極2の周囲に設けることにより、半田の
流入、流出を防ぐことができ、半田ブリッジの発生を防
止できる。しかし、一回のスクリーン印刷で十分な厚さ
を得ることは、技術的に難しい。そこで同一のレジスト
パターンのスクリーン印刷を繰り返し行い、レジストを
多層にすることにより十分な厚さを得る方法が知られて
いる。しかし、前述のように隣接する電極2の間隔が0.
25mm程度で形成される場合、図4に示すように下層のレ
ジスト3と隣接する電極2の間隔は50μm 程度となるた
め、スクリーン印刷が繰り返されるとレジストインクに
にじみや、ずれを生じ、上層のレジスト4が隣接する電
極2に付着し、半田付け性を悪くする恐れがあった。
That is, as shown in FIG. 4B, conventionally, since the thickness of the electrode pattern 2 and the thickness of the resist 3 are substantially the same, solder bridges are likely to occur. Therefore, by providing a thicker resist around the electrode 2, the inflow and outflow of solder can be prevented, and the occurrence of solder bridges can be prevented. However, it is technically difficult to obtain a sufficient thickness with one screen printing. Therefore, a method is known in which the same resist pattern is repeatedly screen-printed to obtain a sufficient thickness by forming the resist in multiple layers. However, as described above, the distance between the adjacent electrodes 2 is 0.
When it is formed with a thickness of about 25 mm, the distance between the lower resist 3 and the adjacent electrode 2 is about 50 μm as shown in FIG. 4, so that when the screen printing is repeated, the resist ink bleeds or shifts, and There is a possibility that the resist 4 may adhere to the adjacent electrode 2 and deteriorate the solderability.

【0006】本発明は、より厚いレジスト等を電極の周
囲に精度良く設けることにより、半田付け性の悪化をま
ねくことなく半田ブリッジの発生を防止し、小型化する
電子部品に対応することを目的とする。
An object of the present invention is to provide a thicker resist or the like around the electrodes with high accuracy to prevent the occurrence of solder bridges without deteriorating the solderability, and to correspond to miniaturized electronic parts. And

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
に本発明は、電子部品が半田付け実装されるプリント配
線基板において、該プリント配線基板の電極間に形成さ
れる絶縁膜を、上層になるほど幅の細いパターンとして
積層形成したことを特徴とするものである。また、電子
部品が半田付け実装されるプリント配線基板において、
該プリント配線基板の電極間に印刷により形成されるレ
ジストを、上層になるほど幅の細いレジストパターンと
して重ねて印刷形成したことを特徴とするものである。
In order to solve the above problems, the present invention provides a printed wiring board on which an electronic component is mounted by soldering, an insulating film formed between electrodes of the printed wiring board being used as an upper layer. It is characterized in that the layers are formed as a pattern having a narrower width. Also, in a printed wiring board on which electronic components are mounted by soldering,
It is characterized in that a resist formed by printing between electrodes of the printed wiring board is formed by printing by superimposing it as a resist pattern having a narrower width in an upper layer.

【0008】また、電子部品が半田付け実装される前記
プリント配線基板において、該プリント配線基板の電極
間に貼付される絶縁材質をフィルム状に加工したもの
を、上層になるほど幅の細いフィルムパターンとして重
ねて貼付したことを特徴とするものである。また、前記
プリント配線基板において、電極間に上層になるほど幅
の細いレジストパターンとフィルムパターンを組み合わ
せ、重ねて形成したことを特徴とするものである。
Further, in the printed wiring board on which the electronic parts are mounted by soldering, an insulating material stuck between the electrodes of the printed wiring board is processed into a film shape to form a film pattern having a narrower width toward the upper layer. It is characterized in that they are attached in layers. Further, the printed wiring board is characterized in that a resist pattern and a film pattern, which are narrower in width toward the upper layer between electrodes, are combined and formed in layers.

【0009】さらに、電極を印刷形成したプリント配線
基板の少なくとも所定の電極及び電極間の表面に、レジ
ストまたは絶縁フィルム等の絶縁膜を積層し、その後、
半田付けの必要な電極部分上の前記絶縁膜をレーザ光を
照射して除去し、該電極部分を露出させて形成したこと
を特徴とするものである。
Further, an insulating film such as a resist or an insulating film is laminated on at least a predetermined electrode and a surface between the electrodes of a printed wiring board on which electrodes are printed and formed.
It is characterized in that the insulating film on the electrode portion requiring soldering is irradiated with laser light to be removed, and the electrode portion is exposed.

【0010】[0010]

【作用】電子部品が半田付け実装されるプリント配線基
板において、該プリント配線基板の電極間に形成される
絶縁膜を、上層になるほど幅の細いパターンとして積層
形成することにより、上層になるほど絶縁膜の幅が細い
ことで、ずれの許容範囲が増え、上層の絶縁膜が隣接す
る電極に付着することを防止でき、より厚い絶縁膜層を
精度良く形成できる。
In the printed wiring board on which the electronic component is mounted by soldering, the insulating film formed between the electrodes of the printed wiring board is laminated in a pattern having a narrower width in the upper layer. Since the width is narrow, the allowable range of misalignment is increased, the upper insulating film can be prevented from adhering to the adjacent electrode, and a thicker insulating film layer can be accurately formed.

【0011】この絶縁膜としては、例えば印刷により形
成されるレジストを用いることができ、上層になるほど
幅の細いレジストパターンとして重ねて印刷形成するこ
とにより、前述の通りより厚い絶縁膜層を精度良く形成
できる。さらに、この場合の印刷形成と同様に、プリン
ト配線基板の電極間に貼付される絶縁材質をフィルム状
に加工したものを用いる場合も、厚いフィルムでは電極
に対応し切り抜かれている部分の切断面の精度が悪いた
め、薄いフィルムを重ねて使用する。
As the insulating film, for example, a resist formed by printing can be used. By forming the resist pattern by overlapping and forming a resist pattern having a narrower width in the upper layer, a thicker insulating film layer can be accurately formed as described above. Can be formed. Further, similar to the print formation in this case, when a film-shaped insulating material stuck between the electrodes of the printed wiring board is used, the cut surface of the portion cut out corresponding to the electrodes in the thick film is used. Since the accuracy of is poor, use thin films on top of each other.

【0012】しかし、前記レジストの場合と同様にずれ
が生じ、隣接する電極に付着してしまうので、上層にな
るほど幅が細いフィルムパターンを重ねて配線基板に貼
付することでずれの許容範囲が増え、従って上層のフィ
ルムが隣接する電極に付着することを防止でき、より厚
いフィルム層が形成できる。またフィルムを貼付形成す
る場合、レジストをスクリーン印刷する場合に比べてた
れやにじみの心配が全くないため、より高精度の加工が
でき、信頼性がより向上する。
However, as in the case of the resist, a deviation occurs and adheres to an adjacent electrode. Therefore, by adhering a film pattern having a narrower width to the upper layer and adhering it to the wiring board, the deviation allowable range is increased. Therefore, it is possible to prevent the upper film from adhering to the adjacent electrodes, and to form a thicker film layer. Further, when the film is pasted and formed, there is no fear of dripping or bleeding as compared with the case where the resist is screen-printed, so that the processing can be performed with higher accuracy and the reliability is further improved.

【0013】前記プリント配線基板において、下層にフ
ィルム、上層にレジスト或いはその逆等組み合わせるこ
とによって、それぞれの材質の特性を持つ層状の壁を形
成することができる。プリント配線基板において少なく
とも所定の電極及び電極間の表面にレジスト、絶縁フィ
ルム等の絶縁膜を積層し、その後、半田付けの必要な電
極部分上の絶縁膜だけをレーザ光を照射して除去し、該
電極部分を後加工で露出させて形成する場合、絶縁膜を
レーザ光を使用して除去するので、高精度で微細加工が
しやすく、上層を細くする必要がないので、電極の周囲
に、より厚い絶縁膜の積層の壁が形成でき、また、より
電極が隣接した箇所に適応できる。
In the printed wiring board, by combining a film as a lower layer and a resist as an upper layer or vice versa, it is possible to form a layered wall having characteristics of respective materials. At least a predetermined electrode in the printed wiring board and a surface between the electrodes, a resist, an insulating film such as an insulating film is laminated, and then only the insulating film on the electrode portion that needs to be soldered is removed by irradiating laser light, When the electrode portion is formed by being exposed by post-processing, since the insulating film is removed by using laser light, it is easy to perform fine processing with high accuracy and there is no need to make the upper layer thin. It is possible to form a wall of a stack of thicker insulating films, and it is possible to adapt to a position where electrodes are more adjacent.

【0014】[0014]

【実施例】本発明の一実施例を図1に示す。図1(a)
は平面図、(b)はA−A’断面図を示している。基板
本体1の表面に銅箔で配線パターン5及び電極2を形成
し、電子部品のリード端子と接続される該電極部分2を
残し、それ以外の部分を絶縁膜層3で被覆する。絶縁膜
層3としては、例えばスクリーン印刷法によりエポキシ
樹脂のレジストインクで、スクリーン印刷を行って形成
する。絶縁膜層3が硬化した後に、図1(a)に示すよ
うに電極付近をより避けるような幅が細い絶縁膜パター
ンを下層の絶縁膜層3上に重ねて例えば2回目のスクリ
ーン印刷を行い、上層の絶縁膜層4を形成する。このよ
うにして、上層になるほど幅の細い複数層の絶縁膜パタ
ーンを形成する。本実施例によれば、隣接する電極間に
おいて、下層の絶縁膜層3の幅に比べ、上層の絶縁膜層
4になるほど幅が細いため、図2に示すようにずれの許
容範囲が増えることにより上層の絶縁膜4が隣接する電
極2に付着するのを防止でき、より厚い絶縁膜層が精度
良く形成できる。
FIG. 1 shows an embodiment of the present invention. Figure 1 (a)
Shows a plan view, and (b) shows a sectional view taken along line AA '. The wiring pattern 5 and the electrodes 2 are formed on the surface of the substrate body 1 with a copper foil, the electrode portions 2 connected to the lead terminals of the electronic component are left, and the other portions are covered with the insulating film layer 3. The insulating film layer 3 is formed by screen printing with a resist ink of an epoxy resin by a screen printing method, for example. After the insulating film layer 3 is cured, an insulating film pattern having a narrow width that avoids the vicinity of the electrodes is overlapped on the lower insulating film layer 3 as shown in FIG. 1A, and the second screen printing is performed, for example. , The upper insulating film layer 4 is formed. In this manner, a plurality of layers of insulating film patterns are formed, the width of which is narrower toward the upper layer. According to the present embodiment, the width of the upper insulating film layer 4 is smaller than the width of the lower insulating film layer 3 between the adjacent electrodes, so that the allowable range of deviation increases as shown in FIG. As a result, the upper insulating film 4 can be prevented from adhering to the adjacent electrode 2, and a thicker insulating film layer can be accurately formed.

【0015】また絶縁膜層3、4としては、レジストの
代わりに絶縁材質をフィルム状に加工したものを用いて
もよい。この場合、厚いフィルムでは電極に対応して切
り抜かれる部分の切断面の精度が悪いため、薄いフィル
ムを重ねて使用する。しかし、前記レジストの場合と同
様に重ねることによりずれが生じ、隣接する電極に上層
のフィルム付着する恐れがあり、同様に上層になるほど
幅の細いフィルムパターンを重ねて配線基板に貼り付け
ることでずれの許容範囲が増えることにより、隣接する
電極に上層のフィルムが付着するのを防止でき、より厚
いフィルム層を精度良く形成できる。
Further, as the insulating film layers 3 and 4, a film made of an insulating material may be used instead of the resist. In this case, since the precision of the cut surface of the thick film corresponding to the electrode is poor, thin films are stacked. However, as in the case of the above-mentioned resist, a shift may occur due to stacking, and an upper layer film may be attached to an adjacent electrode. Similarly, as the upper layer is stacked, a film pattern having a narrower width is stacked and stuck to a wiring board. By increasing the allowable range of the above, it is possible to prevent the upper layer film from adhering to the adjacent electrodes, and it is possible to accurately form a thicker film layer.

【0016】さらに、電極2により近い下層の絶縁膜3
として高精度の加工の可能なフィルムを貼り付け、上層
の絶縁膜4としてフィルムより生産性の高いレジスト使
用し、該フィルムパターンよりも幅が細いレジストパタ
ーンを形成することにより、高精度と生産性の両立がで
きる。図3は本発明に係わるプリント配線基板の製造方
法を示す一実施例である。かかる製造方法は、基板本体
11の表面に銅箔で配線パターン及び電極12を印刷形成し
たプリント配線基板の表面全体を絶縁膜13を積層して覆
い、所定の電極部分12上の絶縁膜13だけをレーザ光16を
照射して除去し、該電極部分を露出させて形成するもの
である。本実施例によれば絶縁膜13をレーザ光16を使用
して除去するので、絶縁膜3の積層の厚さに係わらず高
精度で微細加工ができ、より厚い絶縁膜3の積層が得ら
れ、また上層を細くする必要がないので、より電極2が
隣接した箇所に適応できる。
Further, the lower insulating film 3 closer to the electrode 2
By attaching a film that can be processed with high precision as the upper layer, using a resist having higher productivity than the film as the upper insulating film 4, and forming a resist pattern having a width narrower than the film pattern, high precision and productivity can be obtained. Can be compatible. FIG. 3 is an embodiment showing a method for manufacturing a printed wiring board according to the present invention. Such a manufacturing method is for a substrate body
The entire surface of the printed wiring board on which the wiring pattern and the electrodes 12 are formed by printing with a copper foil on the surface of 11 is laminated and covered, and only the insulating film 13 on the predetermined electrode portion 12 is irradiated with the laser beam 16. And then removed to expose the electrode portion. According to the present embodiment, since the insulating film 13 is removed by using the laser beam 16, fine processing can be performed with high accuracy regardless of the thickness of the stacked insulating film 3, and a thicker stacked insulating film 3 can be obtained. Moreover, since it is not necessary to make the upper layer thin, it is possible to adapt to a position where the electrode 2 is adjacent.

【0017】尚、本実施例において、半田付けの必要な
電極部分12上の前記絶縁膜13を取り去る方法として、従
来より、配線パターン及び電極12を印刷形成した基板の
表面全体に感光性の絶縁フィルムを熱圧着し、電極間な
ど絶縁膜の必要な箇所に写真法にて光をあて、感光によ
り該絶縁フィルムを硬化させた後、溶剤にて感光してい
ない電極部分12上の絶縁フィルムを取り除くことにより
電極部分12を露出させる方法がある。この方法では、溶
剤にて除去された絶縁膜の断面を垂直な平面として形成
することが極めて困難であり、加工精度が悪いため、積
層した厚い絶縁膜のパターン形成には不向きである。
In the present embodiment, as a method of removing the insulating film 13 on the electrode portion 12 that needs to be soldered, conventionally, a photosensitive insulating film is formed on the entire surface of the substrate on which the wiring pattern and the electrode 12 are formed by printing. The film is thermocompression-bonded, and light is applied to necessary portions of the insulating film such as between electrodes by a photographic method to cure the insulating film by photosensitization, and then the insulating film on the electrode part 12 not exposed to the solvent is removed. There is a method of exposing the electrode portion 12 by removing it. In this method, it is extremely difficult to form the cross section of the insulating film removed by the solvent as a vertical flat surface, and the processing accuracy is poor, so that it is not suitable for forming a pattern of a stacked thick insulating film.

【0018】[0018]

【発明の効果】以上詳細に説明したように、本発明によ
れば、より厚いレジスト等を電極の周囲に設けることに
より、半田付け性の悪化をまねくことなく半田ブリッジ
の発生を防止でき、小型化する電子部品に対応すること
が可能となる。
As described in detail above, according to the present invention, by providing a thicker resist or the like around the electrodes, it is possible to prevent the occurrence of solder bridges without deteriorating the solderability, and to reduce the size. It becomes possible to deal with the electronic parts that are becoming more and more popular.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す、プリント配線基板の
平面図及び断面図
FIG. 1 is a plan view and a sectional view of a printed wiring board showing an embodiment of the present invention.

【図2】本発明の効果を説明するための基板断面図FIG. 2 is a substrate cross-sectional view for explaining the effect of the present invention.

【図3】本発明による、プリント配線基板の製造方法の
一実施例を示す基板の断面図
FIG. 3 is a sectional view of a board showing an embodiment of a method for manufacturing a printed wiring board according to the present invention.

【図4】従来のプリント配線基板の平面図及び断面図FIG. 4 is a plan view and a sectional view of a conventional printed wiring board.

【図5】従来の問題を示す基板の断面図FIG. 5 is a sectional view of a substrate showing a conventional problem.

【符号の説明】 1・・・基板本体 2・・・電極 3・・・絶縁膜層(レジスト層、フィルム層等) 4・・・絶縁膜層(レジスト層、フィルム層等) 5・・・配線パターン 16・・・レーザ光[Explanation of Codes] 1 ... Substrate body 2 ... Electrode 3 ... Insulating film layer (resist layer, film layer, etc.) 4 ... Insulating film layer (resist layer, film layer, etc.) 5 ... Wiring pattern 16 ... Laser light

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】電子部品が半田付け実装されるプリント配
線基板において、該プリント配線基板の電極間に形成さ
れる絶縁膜を、上層になるほど幅の細いパターンとして
積層形成したことを特徴とするプリント配線基板。
1. A printed wiring board on which an electronic component is mounted by soldering, wherein an insulating film formed between electrodes of the printed wiring board is laminated and formed as a pattern having a width narrower toward an upper layer. Wiring board.
【請求項2】電子部品が半田付け実装されるプリント配
線基板において、該プリント配線基板の電極間に印刷に
より形成されるレジストを、上層になるほど幅の細いレ
ジストパターンとして重ねて印刷形成したことを特徴と
するプリント配線基板。
2. A printed wiring board on which electronic components are mounted by soldering, wherein a resist formed by printing between electrodes of the printed wiring board is printed and formed as a resist pattern having a width narrower toward an upper layer. Characterized printed wiring board.
【請求項3】電子部品が半田付け実装されるプリント配
線基板において、該プリント配線基板の電極間に貼付さ
れる絶縁材質をフィルム状に加工したものを、上層にな
るほど幅の細いフィルムパターンとして重ねて配線基板
に貼付形成したことを特徴とするプリント配線基板。
3. A printed wiring board on which electronic parts are mounted by soldering, wherein an insulating material stuck between electrodes of the printed wiring board is processed into a film shape and laminated as a film pattern having a narrower width toward an upper layer. A printed wiring board, which is formed by pasting on a wiring board.
【請求項4】請求項2または請求項3において、電極間
に上層になるほど幅の細いレジストパターンとフィルム
パターンを組み合わせ、重ねて形成したことを特徴とす
るプリント配線基板。
4. The printed wiring board according to claim 2 or 3, wherein a resist pattern and a film pattern each having a width narrower in an upper layer between the electrodes are combined and formed in combination.
【請求項5】電極を印刷形成したプリント配線基板の少
なくとも所定の電極及び電極間の表面に、レジストまた
は絶縁フィルム等の絶縁膜を積層し、その後、半田付け
の必要な電極部分上の前記絶縁膜をレーザ光を照射して
除去し、該電極部分を露出させて形成したことを特徴と
するプリント配線基板の製造方法。
5. An insulating film such as a resist or an insulating film is laminated on at least a predetermined electrode and a surface between the electrodes of a printed wiring board on which electrodes are printed, and then the insulation on the electrode portion that needs to be soldered. A method for manufacturing a printed wiring board, characterized in that the film is formed by irradiating the film with laser light to expose the electrode portion.
JP13726993A 1993-06-08 1993-06-08 Printed wiring board and production thereof Withdrawn JPH06350230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13726993A JPH06350230A (en) 1993-06-08 1993-06-08 Printed wiring board and production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13726993A JPH06350230A (en) 1993-06-08 1993-06-08 Printed wiring board and production thereof

Publications (1)

Publication Number Publication Date
JPH06350230A true JPH06350230A (en) 1994-12-22

Family

ID=15194728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13726993A Withdrawn JPH06350230A (en) 1993-06-08 1993-06-08 Printed wiring board and production thereof

Country Status (1)

Country Link
JP (1) JPH06350230A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996039796A1 (en) * 1995-06-06 1996-12-12 Ibiden Co., Ltd. Printed wiring board
US6525275B1 (en) 1996-08-05 2003-02-25 Ibiden Co., Ltd. Multilayer printed circuit boards
US6831234B1 (en) 1996-06-19 2004-12-14 Ibiden Co., Ltd. Multilayer printed circuit board
JP2006202881A (en) * 2005-01-19 2006-08-03 Ibiden Co Ltd Printed wiring board and its manufacturing method
US7265044B2 (en) 2002-08-22 2007-09-04 Jsr Corporation Method for forming bump on electrode pad with use of double-layered film
WO2024066221A1 (en) * 2022-09-30 2024-04-04 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing semiconductor structure

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996039796A1 (en) * 1995-06-06 1996-12-12 Ibiden Co., Ltd. Printed wiring board
US6291778B1 (en) 1995-06-06 2001-09-18 Ibiden, Co., Ltd. Printed circuit boards
US6303880B1 (en) 1995-06-06 2001-10-16 Ibiden Co., Ltd. Printed circuit boards
US6831234B1 (en) 1996-06-19 2004-12-14 Ibiden Co., Ltd. Multilayer printed circuit board
US6525275B1 (en) 1996-08-05 2003-02-25 Ibiden Co., Ltd. Multilayer printed circuit boards
US7265044B2 (en) 2002-08-22 2007-09-04 Jsr Corporation Method for forming bump on electrode pad with use of double-layered film
JP2006202881A (en) * 2005-01-19 2006-08-03 Ibiden Co Ltd Printed wiring board and its manufacturing method
JP4669703B2 (en) * 2005-01-19 2011-04-13 イビデン株式会社 Printed wiring board and manufacturing method thereof
WO2024066221A1 (en) * 2022-09-30 2024-04-04 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing semiconductor structure

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