JP2019109111A - Circuit board and measuring apparatus - Google Patents

Circuit board and measuring apparatus Download PDF

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JP2019109111A
JP2019109111A JP2017241567A JP2017241567A JP2019109111A JP 2019109111 A JP2019109111 A JP 2019109111A JP 2017241567 A JP2017241567 A JP 2017241567A JP 2017241567 A JP2017241567 A JP 2017241567A JP 2019109111 A JP2019109111 A JP 2019109111A
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conductor
conductor layer
conductor pattern
circuit board
wiring
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JP6982927B2 (en
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秀行 長井
Hideyuki Nagai
秀行 長井
佐藤 達也
Tatsuya Sato
佐藤  達也
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Hioki EE Corp
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Abstract

To realize improvement of manufacturing efficiency and reduction of manufacturing cost.SOLUTION: A circuit board has four conductor layers 101a to 101d on which a wire W1 connecting a terminal Tv1a to a terminal Tv2a and a wire W2 connecting a terminal Tv1b to a terminal Tv2b are formed, and which are stacked in an order from a top surface 100u to an under surface 100b. The wire W1 comprises a conductor pattern P1 formed on the conductor layer 101a, a conductor pattern P2 formed on the conductor layer 101c, a via V1 connecting conductor patterns P1, P2 on a side of the terminals Tv1a, Tv1b, and a via V2 connecting conductor patterns P1, P2 on a side of the terminals Tv2a, Tv2b. The wire W2 comprises a conductor pattern P3 formed on the conductor layer 101b, a conductor pattern P4 formed on the conductor layer 101d, a via V3 connecting the conductor patterns P3, P4 on a side of the terminals Tv1a, Tv1b, and a via 4 connecting the conductor patterns P3, P4 on a side of the terminals Tv2a, Tv2b.SELECTED DRAWING: Figure 3

Description

本発明は、電圧検出部と測定対象とを接続する配線が形成された回路基板、およびその回路基板を備えた測定装置に関するものである。   The present invention relates to a circuit board on which a wire connecting a voltage detection unit and an object to be measured is formed, and a measuring apparatus including the circuit board.

測定対象に測定用電流を供給したときに生じる電圧を測定して測定対象の被測定量を測定する際に、電流径路に測定電流が流れることによって生じる磁界の影響を軽減する測定装置として、下記特許文献1において出願人が開示した4端子対法で測定を行う回路基板検査装置が知られている。この回路基板検査装置では、測定電流供給用の電流プローブおよび電圧検出用の電圧プローブに接続されている同軸ケーブルのシールドをリード線で接続することにより、測定対象に流れる測定電流の向きとは逆向きに、シールドとリード線とで形成される電流径路に測定電流が流れ、これによって、測定電流によって生じる磁束(磁界)が相殺される結果、磁束による測定結果への影響を軽減して検査精度を向上させることが可能となっている。   When measuring the measured amount of the measurement target by measuring the voltage generated when the measurement current is supplied to the measurement target, as a measuring device that reduces the influence of the magnetic field generated by the measurement current flowing in the current path, There is known a circuit board inspection apparatus which performs measurement by the four-terminal pair method disclosed by the applicant in Patent Document 1. In this circuit board inspection apparatus, by connecting the shield of the coaxial cable connected to the current probe for supplying the measurement current and the voltage probe for detecting the voltage with the lead wire, the direction opposite to the direction of the measurement current flowing to the measurement object is reversed. The measurement current flows in the current path formed by the shield and the lead, and the magnetic flux (magnetic field) generated by the measurement current is offset by this, so that the influence of the magnetic flux on the measurement result is reduced and the inspection accuracy It is possible to improve the

一方、電圧検出部、ケーブル、電圧プローブおよび測定対象によって形成される電圧ループに外部磁界が通過したときには、その電圧ループに誘導起電力が発生し、その誘導起電力によって電圧検出値が影響を受ける。このため、出願人は、電圧検出部に接続される2本のケーブルを撚ることによって外部磁界によって発生する誘導起電力を相殺する技術を既に開発している。また、出願人は、誘導起電力を相殺する技術を測定装置内の回路基板で実現するために、多層基板における2つの導体層にそれぞれ形成した導体パターンをビアで接続して、2本の螺旋状の配線を撚り合わせた撚り形状の配線を形成し、この撚り形状の配線によって誘導起電力を相殺する技術を既に開発している。   On the other hand, when an external magnetic field passes through a voltage loop formed by the voltage detection unit, the cable, the voltage probe, and the measurement object, an induced electromotive force is generated in the voltage loop, and the voltage detection value is affected by the induced electromotive force. . For this reason, the applicant has already developed a technique for canceling the induced electromotive force generated by the external magnetic field by twisting two cables connected to the voltage detection unit. Moreover, in order to realize the technique of canceling the induced electromotive force on the circuit board in the measuring apparatus, the applicant connects the conductor patterns respectively formed in the two conductor layers in the multilayer substrate with vias to form two spirals. We have already developed a technology to form a twist-shaped wire in which the wire-like wires are twisted and to offset the induced electromotive force by this twist-shaped wire.

特開2011−257340号公報(第5頁、第4図)JP, 2011-257340, A (page 5, FIG. 4)

ところが、出願人が既に開発している撚り形状の配線を基板内に形成する従来の回路基板には、改善すべき以下の課題ある。具体的には、撚り形状の配線を基板内に形成するには、2つの導体層に短い配線を間隔を空けてそれぞれ並べ、1つの導体層の各配線の各端部と他の1つの導体層の各配線の各端部とをビアで接続して第1の螺旋状の配線を作成し、その第1の螺旋状の配線と撚り合わせた状態となるように第2の螺旋状の配線を第1の螺旋状の配線と同様に作成する。しかしながら、撚り形状の配線を基板内に形成するには、数多くのビアを形成して各配線の各端部同士を接続する必要がある。したがって、従来の回路基板には、製造工程が煩雑となるため、製造効率が低下すると共に、製造コストが高騰するという課題が存在する。   However, there are the following problems to be improved in the conventional circuit board in which the twist-shaped wiring already developed by the applicant is formed in the substrate. Specifically, in order to form a twist-shaped wire in the substrate, short wires are arranged in two conductor layers at intervals, and each end of each wire of one conductor layer and another conductor are formed. A second spiral wiring is formed by connecting each end of each wiring of the layer with a via to create a first spiral wiring and twisting the first spiral wiring. Are created in the same manner as the first spiral wiring. However, in order to form the twist-shaped wiring in the substrate, it is necessary to form many vias and connect the respective ends of the wirings. Therefore, in the conventional circuit board, since the manufacturing process becomes complicated, there is a problem that the manufacturing efficiency is lowered and the manufacturing cost is increased.

本発明は、かかる問題点に鑑みてなされたものであり、製造効率の向上および製造コストの低減を実現し得る回路基板および測定装置を提供することを主目的とする。   The present invention has been made in view of such problems, and has as its main object to provide a circuit board and a measuring device which can realize improvement in manufacturing efficiency and reduction in manufacturing cost.

上記目的を達成すべく請求項1記載の回路基板は、電圧検出部が接続される一対の第1端子のいずれか一方と測定対象に接触させる一対のプローブがそれぞれ接続される一対の第2端子のいずれか一方とを接続する第1配線、および前記各第1端子の他方と前記各第2端子の他方とを接続する第2配線が形成された回路基板であって、当該回路基板の一面側から他面側に向かって設けられた第1導体層、第2導体層、第3導体層および第4導体層の少なくとも4つの導体層を有し、前記第1配線は、前記第1導体層および前記第2導体層のいずれか一方の導体層に形成された第1導体パターンと、前記第3導体層および前記第4導体層のいずれか一方の導体層に形成された第2導体パターンと、前記第1導体パターンおよび前記第2導体パターンを前記第1端子側で接続する第1ビアと、前記第1導体パターンおよび前記第2導体パターンを前記第2端子側で接続する第2ビアとを備えて構成され、前記第2配線は、前記第1導体層および前記第2導体層の他方の導体層に形成された第3導体パターンと、前記第3導体層および前記第4導体層の他方の導体層に形成された第4導体パターンと、前記第3導体パターンおよび前記第4導体パターンを前記第1端子側で接続する第3ビアと、前記第3導体パターンおよび前記第4導体パターンを前記第2端子側で接続する第4ビアとを備えて構成されている。   In order to achieve the above object, the circuit board according to claim 1 is a pair of second terminals to which one of a pair of first terminals to which a voltage detection unit is connected and a pair of probes to be brought into contact with a measurement object are respectively connected A circuit board on which a first wiring connecting any one of the first terminals and a second wiring connecting the other of the first terminals and the other of the second terminals is formed, the one surface of the circuit substrate And at least four conductor layers of a first conductor layer, a second conductor layer, a third conductor layer, and a fourth conductor layer provided from the side toward the other surface, and the first wiring is the first conductor Layer and a first conductor pattern formed on any one conductor layer of the second conductor layer, and a second conductor pattern formed on any one conductor layer of the third conductor layer and the fourth conductor layer The first conductor pattern and the second conductor pattern And a second via for connecting the first conductor pattern and the second conductor pattern at the second terminal side, and the second wiring is A third conductor pattern formed on the other conductor layer of the first conductor layer and the second conductor layer, and a fourth conductor formed on the other conductor layer of the third conductor layer and the fourth conductor layer A pattern and a third via connecting the third conductor pattern and the fourth conductor pattern on the first terminal side, and a fourth via connecting the third conductor pattern and the fourth conductor pattern on the second terminal side It is configured with a via.

また、請求項2記載の回路基板は、請求項1記載の回路基板において、前記第1導体パターンは、前記第1導体層に形成され、前記第2導体パターンは、前記第3導体層に形成され、前記第3導体パターンは、前記第2導体層に形成され、前記第4導体パターンは、前記第4導体層に形成されている。   The circuit board according to claim 2 is the circuit board according to claim 1, wherein the first conductor pattern is formed on the first conductor layer, and the second conductor pattern is formed on the third conductor layer. The third conductor pattern is formed on the second conductor layer, and the fourth conductor pattern is formed on the fourth conductor layer.

また、請求項3記載の回路基板は、請求項1または2記載の回路基板において、前記第1配線で構成される第1ループの開口面積と、前記第2配線で構成される第2ループの開口面積とが互いに等しくなるように構成されている。   According to a third aspect of the present invention, in the circuit board according to the first or second aspect, an opening area of a first loop constituted by the first wiring and a second loop constituted by the second wiring The opening areas are configured to be equal to one another.

また、請求項4記載の回路基板は、電圧検出部が接続される一対のA端子のいずれか一方と測定対象に接触させる一対のプローブがそれぞれ接続される一対のB端子のいずれか一方とを接続するA配線、および前記各A端子の他方と前記各B端子の他方とを接続するB配線が形成された回路基板であって、当該回路基板の一面側から他面側に向かって設けられたA導体層、B導体層およびC導体層の少なくとも3つの導体層を有し、前記A配線は、前記A導体層および前記C導体層のいずれか一方の導体層に形成されたA導体パターンと、前記A導体層および前記C導体層の他方の導体層に形成されたB導体パターンと、前記A導体パターンおよび前記B導体パターンを前記A端子側で接続するAビアと、前記A導体パターンおよび前記B導体パターンを前記B端子側で接続するBビアとを備えて構成され、前記B配線は、前記B導体層に形成されたC導体パターンと、前記他方の導体層における前記A端子側に形成されたD導体パターンと、前記他方の導体層における前記B端子側に形成されたE導体パターンと、前記C導体パターンおよび前記D導体パターンを前記A端子側で接続するCビアと、前記C導体パターンおよび前記E導体パターンを前記B端子側で接続するDビアとを備えて構成されている。   The circuit board according to claim 4 is any one of a pair of A terminals to which a voltage detection unit is connected and one of a pair of B terminals to which a pair of probes to be brought into contact with the object to be measured are respectively connected. A circuit board on which an A wiring to be connected and a B wiring to connect the other of the respective A terminals and the other of the respective B terminals are formed, provided from one surface side to the other surface side of the circuit substrate And at least three conductor layers of an A conductor layer, a B conductor layer, and a C conductor layer, wherein the A wiring is an A conductor pattern formed on any one conductor layer of the A conductor layer and the C conductor layer , A B conductor pattern formed in the other conductor layer of the A conductor layer and the C conductor layer, an A via connecting the A conductor pattern and the B conductor pattern on the A terminal side, and the A conductor pattern And said B lead And a B via connecting the pattern on the B terminal side, wherein the B wiring is formed on the C terminal pattern formed on the B conductor layer and on the A terminal side of the other conductor layer The D conductor pattern, the E conductor pattern formed on the B terminal side in the other conductor layer, the C via connecting the C conductor pattern and the D conductor pattern on the A terminal side, the C conductor pattern, And a D via for connecting the E conductor pattern on the B terminal side.

また、請求項5記載の回路基板は、請求項4記載の回路基板において、前記A導体パターン、前記B配線、前記電圧検出部、前記各プローブおよび前記測定対象で構成されるAループ、並びに前記A導体パターンの一部、B導体パターン、前記Aビア、前記Bビア、前記B配線、前記電圧検出部、前記各プローブおよび前記測定対象で構成されるBループを同じ向きで同じ磁束密度の外部磁界が通過したときに当該各ループに生じる誘導起電力が互いに打ち消し合うように当該各ループの開口面積が規定されている。   The circuit board according to claim 5 is the circuit board according to claim 4, wherein the A conductor pattern, the B wiring, the voltage detection unit, the A loop constituted by the respective probes and the measurement object, and the above-mentioned A part of the A conductor pattern, the B conductor pattern, the A via, the B via, the B wiring, the voltage detection unit, the respective probes, and the B loop composed of the measuring object in the same direction and the same magnetic flux density The open areas of the respective loops are defined such that the induced electromotive forces generated in the respective loops cancel each other when the magnetic field passes.

また、請求項6記載の測定装置は、請求項1から5のいずれかに記載の回路基板と、前記電圧検出部と、前記回路基板に形成された第3配線を介して前記測定対象に測定用電流を供給する電流供給部と、前記電圧検出部によって検出された電圧値および前記測定用電流の電流値に基づいて前記測定対象の被測定量を測定する測定部とを備えている。   Moreover, the measuring apparatus of Claim 6 measures the said measurement object via the circuit board in any one of Claims 1-5, the said voltage detection part, and the 3rd wiring formed in the said circuit board. And a measurement unit configured to measure the measured amount of the measurement target based on the voltage value detected by the voltage detection unit and the current value of the measurement current.

請求項1記載の回路基板、および請求項6記載の測定装置では、第1導体層および第2導体層のいずれか一方に形成された第1導体パターンと、第3導体層および第4導体層のいずれか一方に形成された第2導体パターンと、第1導体パターンおよび第2導体パターンを接続する第1ビアおよび第2ビアとを備えて第1配線が構成され、第1導体層および第2導体層の他方に形成された第3導体パターンと、第3導体層および第4導体層の他方に形成された第4導体パターンと、第3導体パターンおよび第4導体パターンを接続する第3ビアおよび第4ビアとを備えて第2配線が構成されている。つまり、この回路基板および測定装置では、外部磁界による誘導起電力の影響を少なく抑えることが可能な第1配線および第2配線を4つの導体パターンと4つのビアで構成することができる。このため、この回路基板および測定装置によれば、2つの導体層にそれぞれ並べた数多くの配線を数多くのビアで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することができる。   In the circuit board according to claim 1 and the measuring apparatus according to claim 6, the first conductor pattern formed on any one of the first conductor layer and the second conductor layer, and the third conductor layer and the fourth conductor layer A first wiring comprising a second conductor pattern formed on any one of the first conductor pattern and a first via and a second via connecting the first conductor pattern and the second conductor pattern; A third conductor pattern connecting the third conductor pattern formed on the other of the two conductor layers, the fourth conductor pattern formed on the other of the third conductor layer and the fourth conductor layer, and the third conductor pattern and the fourth conductor pattern The second wiring is configured to include the via and the fourth via. That is, in the circuit board and the measuring apparatus, the first wiring and the second wiring capable of suppressing the influence of the induced electromotive force due to the external magnetic field can be constituted by four conductor patterns and four vias. For this reason, according to this circuit board and the measuring device, it is configured such that two spiral wirings formed by connecting many wirings arranged in two conductor layers with many vias are twisted together. Compared to the conventional configuration which suppresses the influence of the induced electromotive force due to the external magnetic field by reducing the number of vias and the manufacturing process can be simplified, the manufacturing efficiency is sufficiently improved and the manufacturing cost is sufficient. Can be reduced to

また、請求項2記載の回路基板、および請求項6記載の測定装置によれば、第1導体パターンを第1導体層に形成し、第2導体パターンを第3導体層に形成し、第3導体パターンを第2導体層に形成し、第4導体パターンを第4導体層に形成したことにより、例えば、第1導体パターンを第1導体層に形成し、第2導体パターンを第4導体層に形成し、第3導体パターンを第2導体層101bに形成し、第4導体パターンを第3導体層に形成する構成と比較して、第1配線で構成される第1ループの開口面積と第2配線で構成される第2ループの開口面積とを同程度に近づけることができる。このため、この回路基板および測定装置によれば、回路基板の周囲に外部磁界が発生しているときに各ループに発生する誘導起電力を同程度に近づけることができるため、誘導起電力を確実に打ち消すことができる結果、外部磁界による誘導起電力の影響をより少なく抑えることができる。   Further, according to the circuit board of claim 2 and the measuring apparatus of claim 6, the first conductor pattern is formed on the first conductor layer, the second conductor pattern is formed on the third conductor layer, and By forming the conductor pattern in the second conductor layer and forming the fourth conductor pattern in the fourth conductor layer, for example, the first conductor pattern is formed in the first conductor layer, and the second conductor pattern is formed in the fourth conductor layer Compared to the configuration in which the third conductor pattern is formed in the second conductor layer 101b and the fourth conductor pattern is formed in the third conductor layer, the opening area of the first loop formed of the first wiring and The opening area of the second loop constituted by the second wiring can be made almost the same. For this reason, according to this circuit board and the measuring device, since the induced electromotive force generated in each loop can be brought to the same degree when the external magnetic field is generated around the circuit board, the induced electromotive force is ensured. As a result, the influence of the induced electromotive force due to the external magnetic field can be reduced.

また、請求項3記載の回路基板、および請求項6記載の測定装置によれば、第1配線で構成される第1ループの開口面積と、第2配線で構成される第2ループの開口面積とが等しくなるように構成したことにより、回路基板の周囲に外部磁界が発生している場合に各ループに発生する誘導起電力を等しくすることができるため、誘導起電力同士をより確実に打ち消すことができる結果、外部磁界による誘導起電力の影響をさらに少なく抑えることができる。   According to the circuit board of claim 3 and the measuring apparatus of claim 6, the opening area of the first loop constituted by the first wiring and the opening area of the second loop constituted by the second wiring Since the induced electromotive forces generated in the respective loops can be equalized when an external magnetic field is generated around the circuit board, the induced electromotive forces are more reliably cancelled. As a result, the influence of the induced electromotive force due to the external magnetic field can be further reduced.

また、請求項4記載の回路基板、および請求項6記載の測定装置では、A導体層およびC導体層のいずれか一方に形成されたA導体パターンと、A導体層およびC導体層の他方に形成されたB導体パターンと、A導体パターンおよびB導体パターンを接続するAビアおよびBビアとを備えてA配線が構成され、B導体層に形成されたC導体パターンと、上記の他方の導体層に形成されたD導体パターンおよびE導体パターンと、C導体パターンおよびD導体パターンを接続するCビアと、C導体パターンおよびE導体パターンを接続するDビアとを備えてB配線が構成されている。つまり、この回路基板および測定装置では、4つのビアで外部磁界による誘導起電力の影響を少なく抑えることが可能なA配線およびB配線を構成することができる。このため、この回路基板および測定装置によれば、2つの導体層にそれぞれ並べた数多くの配線を数多くのビアで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することができる。   In the circuit board according to claim 4 and the measuring apparatus according to claim 6, the A conductor pattern formed on either one of the A conductor layer and the C conductor layer, and the other of the A conductor layer and the C conductor layer The C conductor pattern formed in the B conductor layer comprising the formed B conductor pattern and the A via and B via connecting the A conductor pattern and the B conductor pattern, and the other conductor described above B wiring is configured by including D conductor pattern and E conductor pattern formed in the layer, C via connecting C conductor pattern and D conductor pattern, and D via connecting C conductor pattern and E conductor pattern There is. That is, in the circuit board and the measuring device, it is possible to configure the A wiring and the B wiring which can suppress the influence of the induced electromotive force due to the external magnetic field by four vias. For this reason, according to this circuit board and the measuring device, it is configured such that two spiral wirings formed by connecting many wirings arranged in two conductor layers with many vias are twisted together. Compared to the conventional configuration which suppresses the influence of the induced electromotive force due to the external magnetic field by reducing the number of vias and the manufacturing process can be simplified, the manufacturing efficiency is sufficiently improved and the manufacturing cost is sufficient. Can be reduced to

また、請求項5記載の回路基板、および請求項6記載の測定装置では、AループおよびBループを同じ向きで同じ磁束密度の外部磁界が通過したときに各ループに生じる誘導起電力が互いに打ち消し合うように各ループの開口面積が規定されている。このため、この回路基板および測定装置によれば、回路基板の周囲に外部磁界が発生している場合において、その外部磁界による誘導起電力の影響をさらに少なく抑えることができる。   Further, in the circuit board according to claim 5 and the measuring apparatus according to claim 6, when the external magnetic field having the same magnetic flux density passes through the A loop and the B loop in the same direction, the induced electromotive forces generated in the respective loops cancel each other. The open area of each loop is defined to fit. Therefore, according to the circuit board and the measuring device, when an external magnetic field is generated around the circuit board, the influence of the induced electromotive force due to the external magnetic field can be further suppressed.

測定装置1,1A,1Bの構成を示す構成図である。It is a block diagram which shows the structure of measuring device 1, 1A, 1B. 回路基板100の構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of a circuit board 100. 回路基板100の構成を説明する説明図である。FIG. 2 is an explanatory view illustrating the configuration of a circuit board 100. 回路基板200の構成を示す断面図である。FIG. 2 is a cross-sectional view showing a configuration of a circuit board 200. 回路基板200の構成を説明する第1の説明図である。FIG. 2 is a first explanatory view illustrating the configuration of a circuit board 200. 回路基板200の構成を説明する第2の説明図である。FIG. 7 is a second explanatory view illustrating the configuration of the circuit board 200. 回路基板200の構成を説明する第3の説明図である。FIG. 7 is a third explanatory view illustrating the configuration of the circuit board 200. 回路基板100Aの構成を示す断面図である。It is sectional drawing which shows the structure of 100 A of circuit boards. 回路基板100Aの構成を説明する説明図である。It is an explanatory view explaining composition of circuit board 100A.

以下、回路基板および測定装置の実施の形態について、添付図面を参照して説明する。   Hereinafter, embodiments of a circuit board and a measuring apparatus will be described with reference to the attached drawings.

最初に、図1に示す測定装置1の構成について説明する。測定装置1は、測定装置の一例であって、測定対象50(図3参照)の物理量(例えば、抵抗値)を4端子法で測定可能に構成されている。具体的には、測定装置1は、同図に示すように、電流供給部11、電圧検出部12、処理部13、および回路基板100(図2,3参照)を備えて構成されている。   First, the configuration of the measuring apparatus 1 shown in FIG. 1 will be described. The measuring device 1 is an example of a measuring device, and is configured to be able to measure the physical quantity (for example, resistance value) of the measuring object 50 (see FIG. 3) by a four-terminal method. Specifically, as shown in the figure, the measuring apparatus 1 includes a current supply unit 11, a voltage detection unit 12, a processing unit 13, and a circuit board 100 (see FIGS. 2 and 3).

電流供給部11は、処理部13の制御に従い、測定用電流(例えば、直流定電流)を出力する。   The current supply unit 11 outputs a measurement current (for example, a direct current constant current) according to the control of the processing unit 13.

電圧検出部12は、処理部13の制御に従い、測定対象50に対する測定用電流の供給によって測定対象50に生じる電圧の電圧値Vmを検出する。   The voltage detection unit 12 detects the voltage value Vm of the voltage generated in the measurement target 50 by the supply of the measurement current to the measurement target 50 according to the control of the processing unit 13.

処理部13は、電流供給部11および電圧検出部12を制御する。また、処理部13は、測定部として機能し、電圧検出部12によって検出された電圧値Vmと、電流供給部11から出力された測定用電流の電流値Imとに基づいて測定対象50の抵抗値(被測定量)を測定する測定処理を実行する。   The processing unit 13 controls the current supply unit 11 and the voltage detection unit 12. The processing unit 13 functions as a measurement unit, and the resistance of the measurement target 50 based on the voltage value Vm detected by the voltage detection unit 12 and the current value Im of the measurement current output from the current supply unit 11 Execute measurement processing to measure the value (measured amount).

回路基板100は、電流供給部11、電圧検出部12および処理部13が実装される多層基板であって、図2に示すように、回路基板100の上面100u側(一面側)から下面100b側(他面側)向かって設けられた4つの導体層101a(第1導体層に相当する)、導体層101b(第2導体層に相当する)、導体層101c(第3導体層に相当する)、および導体層101d(第4導体層に相当する:以下、導体層101a〜101dを区別しないときには「導体層101」ともいう)と、各導体層101の間に設けられた3つの絶縁層102a,102b,102cとを備えて構成されている。   The circuit board 100 is a multilayer board on which the current supply unit 11, the voltage detection unit 12, and the processing unit 13 are mounted, and as shown in FIG. 2, the circuit board 100 from the upper surface 100u side (one surface side) to the lower surface 100b side. Four conductor layers 101a (corresponding to the first conductor layer), conductor layers 101b (corresponding to the second conductor layer) provided toward the other surface side, and conductor layers 101c (corresponding to the third conductor layer) And the conductor layer 101d (corresponding to the fourth conductor layer: hereinafter referred to as the “conductor layer 101” when the conductor layers 101a to 101d are not distinguished from one another) and the three insulating layers 102a provided between the conductor layers 101. , 102b and 102c.

また、図3に示すように、導体層101aには、電流供給部11の一方の電極が接続される端子Ti1a、および測定対象50の端子50aに接触させる電流供給用のプローブ21aが接続される端子Ti2aが設けられ、導体層101dには、電流供給部11の他方の電極が接続される端子Ti1b、および測定対象50の端子50bに接触させる電流供給用のプローブ21bが接続される端子Ti2bが設けられている。   Further, as shown in FIG. 3, the conductor layer 101a is connected to a terminal Ti1a to which one electrode of the current supply unit 11 is connected and a probe 21a for current supply to be in contact with the terminal 50a of the object 50 to be measured. A terminal Ti2a is provided, a terminal Ti1b to which the other electrode of the current supply unit 11 is connected, and a terminal Ti2b to which a probe 21b for supplying current to be brought into contact with the terminal 50b of the object 50 is connected It is provided.

また、図2,3に示すように、導体層101aには、電圧検出部12の一方の電極が接続される端子Tv1a(第1端子に相当する)、および測定対象50の端子50aに接触させる電圧検出用のプローブ22aが接続される端子Tv2a(第2端子に相当する)が設けられ、導体層101dには、電圧検出部12の他方の電極が接続される端子Tv1b(第1端子に相当する)、および測定対象50の端子50bに接触させる電圧検出用のプローブ22bが接続される端子Tv2b(第2端子に相当する)が設けられている。この場合、図2では、端子Ti1a,Ti1b,Ti2a,Ti2b、および後述する配線W3a,W3bの図示を省略している。なお、以下の説明において、端子Tv1a,Tv1bを区別しないときには「端子Tv1」ともいい、端子Tv2a,Tv2bを区別しないときには「端子Tv2」ともいう。また、端子Ti1a,Ti1b,Ti2a,Ti2b,Tv1a,Tv1b,Tv2a,Tv2bを区別しないときには「端子T」ともいう。   Further, as shown in FIGS. 2 and 3, the conductor layer 101a is brought into contact with the terminal Tv1a (corresponding to a first terminal) to which one electrode of the voltage detection unit 12 is connected and the terminal 50a of the object 50 to be measured. A terminal Tv2a (corresponding to a second terminal) to which the voltage detection probe 22a is connected is provided, and a terminal Tv1b (corresponding to a first terminal) to which the other electrode of the voltage detection unit 12 is connected to the conductor layer 101d And a terminal Tv2b (corresponding to a second terminal) to which a voltage detection probe 22b to be brought into contact with the terminal 50b of the measurement object 50 is connected. In this case, in FIG. 2, the terminals Ti1a, Ti1b, Ti2a, Ti2b, and wirings W3a, W3b described later are not shown. In the following description, when the terminals Tv1a and Tv1b are not distinguished from each other, they are also referred to as “terminal Tv1”, and when the terminals Tv2a and Tv2b are not distinguished from each other, also referred to as “terminal Tv2”. The terminals Ti1a, Ti1b, Ti2a, Ti2b, Tv1a, Tv1b, Tv2a, Tv2b are also referred to as "terminal T".

また、回路基板100には、各端子T同士を接続する配線が形成されている。具体的には、図3に示すように、回路基板100の導体層101aには、端子Ti1aと端子Ti2aとを接続する配線W3aが形成され、回路基板100の導体層101dには、端子Ti1bとTi2bとを接続する配線W3bが形成されている。この場合、配線W3a,W3bは、第3配線に相当する。   In addition, in the circuit board 100, a wire for connecting the terminals T is formed. Specifically, as shown in FIG. 3, in the conductor layer 101a of the circuit board 100, the wiring W3a connecting the terminals Ti1a and Ti2a is formed, and in the conductor layer 101d of the circuit board 100, the terminals Ti1b and A wire W3b connecting Ti2b is formed. In this case, the wires W3a and W3b correspond to a third wire.

また、回路基板100には、図2,3に示すように、端子Tv1aと端子Tv2aとを接続する配線W1(第1配線に相当する)、および端子Tv1bと端子Tv2bとを接続する配線W2(第2配線に相当する)が形成されている。この場合、この回路基板100では、電圧検出部12によって行われる電圧値Vmの検出に際して、電圧値Vmに対する外部磁界の影響を低減させるため、配線W1および配線W2がループをなすように構成されている。   In the circuit board 100, as shown in FIGS. 2 and 3, the wiring W1 (corresponding to a first wiring) connecting the terminal Tv1a and the terminal Tv2a, and the wiring W2 connecting the terminal Tv1b and the terminal Tv2b (Corresponding to the second wiring) is formed. In this case, in the circuit board 100, the wire W1 and the wire W2 are configured to form a loop in order to reduce the influence of the external magnetic field on the voltage value Vm when detecting the voltage value Vm performed by the voltage detection unit 12. There is.

具体的には、配線W1は、図2,3に示すように、回路基板100の導体層101aに形成された導体パターンP1(第1導体パターンに相当する)と、回路基板100の導体層101cに形成された導体パターンP2(第2導体パターンに相当する)と、導体パターンP1,P2を端子Tv1側で接続するビアV1と、導体パターンP1,P2を端子Tv2側で接続するビアV2とを備えて構成されている。   Specifically, as shown in FIGS. 2 and 3, the wiring W1 includes a conductor pattern P1 (corresponding to a first conductor pattern) formed on the conductor layer 101a of the circuit board 100 and a conductor layer 101c of the circuit board 100. A conductor pattern P2 (corresponding to a second conductor pattern) formed in the first embodiment, a via V1 connecting the conductor patterns P1 and P2 on the terminal Tv1 side, and a via V2 connecting the conductor patterns P1 and P2 on the terminal Tv2 side It is configured to be equipped.

また、配線W2は、図2,3に示すように、回路基板100の導体層101bに形成された導体パターンP3(第3導体パターンに相当する)と、回路基板100の導体層101dに形成された導体パターンP4(第4導体パターンに相当する)と、導体パターンP3,P4を端子Tv1側で接続するビアV3と、導体パターンP3,P4を端子Tv2側で接続するビアV4とを備えて構成されている。なお、以下の説明において、ビアV1〜V4を区別しないときには「ビアV」ともいう。   Further, as shown in FIGS. 2 and 3, the wiring W2 is formed on the conductor pattern P3 (corresponding to a third conductor pattern) formed on the conductor layer 101b of the circuit board 100 and the conductor layer 101d on the circuit board 100. A conductor pattern P4 (corresponding to a fourth conductor pattern), a via V3 connecting the conductor patterns P3 and P4 on the terminal Tv1 side, and a via V4 connecting the conductor patterns P3 and P4 on the terminal Tv2 side It is done. In the following description, when the vias V1 to V4 are not distinguished from each other, they are also referred to as "vias V".

また、この回路基板100では、図2に示すように、配線W1(導体パターンP1,P2およびビアV1,V2)で構成されるループL1(同図に破線で示すループ:第1ループに相当する)の開口面と、配線W2(導体パターンP3,P4およびビアV3,V4)で構成されるループL2(同図に一点鎖線で示すループ:第2ループに相当する)の開口面とが対向し(同じ向きを向き)、ループL1の開口面積とループL2の開口面積とが互いに等しくなるように構成されている。   Further, in this circuit board 100, as shown in FIG. 2, a loop L1 (a dashed loop in the figure: equivalent to a first loop) constituted by the wires W1 (the conductor patterns P1 and P2 and the vias V1 and V2). And the open surface of a loop L2 (a loop indicated by an alternate long and short dash line in the figure: corresponding to a second loop) composed of the wires W2 (conductor patterns P3 and P4 and vias V3 and V4) The opening area of the loop L1 and the opening area of the loop L2 are configured to be equal to each other (in the same direction).

ここで、回路基板100の周囲に外部磁界が発生していて、その外部磁界が各ループL1,L2を通過したときには、各ループL1,L2に誘導起電力が発生する。この場合、この回路基板100では、図3に示すように、ループL1が電圧検出部12の一方の電極に接続され、ループL2が電圧検出部12の他方の電極に接続されている。また、この回路基板100では、各ループL1,L2の開口面同士が対向し、各ループL1,L2の開口面積が互いに等しくなるように構成されている。このため、この回路基板100では、各ループL1,L2に発生する誘導起電力が互いに打ち消し合うように電圧検出部12に作用する。この結果、この回路基板100では、電圧検出部12が測定対象50の電圧値Vmを検出する際の外部磁界による誘導起電力の影響を少なく抑えることが可能となっている。したがって、この回路基板100を備えた測定装置1では、電圧検出部12によって検出された電圧値Vmに基づく測定対象50の抵抗値を正確に測定することが可能となっている。   Here, when an external magnetic field is generated around the circuit board 100 and the external magnetic field passes through the loops L1 and L2, an induced electromotive force is generated in the loops L1 and L2. In this case, in the circuit board 100, as shown in FIG. 3, the loop L1 is connected to one electrode of the voltage detection unit 12, and the loop L2 is connected to the other electrode of the voltage detection unit 12. Further, in the circuit board 100, the opening faces of the loops L1 and L2 face each other, and the opening areas of the loops L1 and L2 are configured to be equal to each other. Therefore, in the circuit board 100, the induced electromotive forces generated in the loops L1 and L2 act on the voltage detection unit 12 so as to cancel each other. As a result, in the circuit board 100, the influence of the induced electromotive force due to the external magnetic field when the voltage detection unit 12 detects the voltage value Vm of the measurement target 50 can be suppressed to a low level. Therefore, in the measuring device 1 provided with the circuit board 100, it is possible to accurately measure the resistance value of the measuring object 50 based on the voltage value Vm detected by the voltage detection unit 12.

一方、この回路基板100では、上記したように、導体層101a,101cにそれぞれ形成した導体パターンP1,P2を2つのビアV1,V2で接続した配線W1でループL1を構成し、導体層101b,101dにそれぞれ形成した導体パターンP3,P4を2つのビアV3,V4で接続した配線W2でループL2を構成することで、外部磁界による誘導起電力の影響を少なく抑えることが可能となっている。つまり、この回路基板100では、4つのビアVで外部磁界による誘導起電力の影響を少なく抑えることが可能な配線W1,W2を構成することができる。このため、この回路基板100では、2つの導体層101にそれぞれ並べた数多くの配線を数多くのビアVで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアVの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することが可能となっている。   On the other hand, in the circuit board 100, as described above, the loop W1 is formed by the wiring W1 in which the conductor patterns P1 and P2 formed on the conductor layers 101a and 101c are connected by two vias V1 and V2, respectively. By forming the loop L2 by the wiring W2 in which the conductor patterns P3 and P4 respectively formed on 101d are connected by two vias V3 and V4, it is possible to suppress the influence of the induced electromotive force due to the external magnetic field. That is, in the circuit board 100, the wirings W1 and W2 can be configured by the four vias V, which can suppress the influence of the induced electromotive force due to the external magnetic field to a small extent. For this reason, in this circuit board 100, it should be configured to be in a state in which two spiral wires formed by connecting many wires arranged in two conductor layers 101 by many vias V are twisted together. As compared with the conventional configuration which reduces the influence of the induced electromotive force due to the external magnetic field, the number of vias V is small and the manufacturing process can be simplified, so that the manufacturing efficiency is sufficiently improved and the manufacturing cost is sufficient. It is possible to reduce.

次に、測定装置1を用いて測定対象50の被測定量としての抵抗値を4端子対法で測定する測定方法、およびその際の各部の動作について、図面を参照して説明する。   Next, a measurement method of measuring the resistance value of the measurement target 50 as the measurement target by the four-terminal pair method using the measurement apparatus 1 and the operation of each part at that time will be described with reference to the drawings.

まず、図3に示すように、回路基板100に設けられている端子Ti2a,Ti2bに電流供給用のプローブ21a,21bをそれぞれ接続し、端子Tv2a,Tv2bに電圧検出用のプローブ22a,22bをそれぞれ接続する。   First, as shown in FIG. 3, the probes 21a and 21b for supplying current are respectively connected to the terminals Ti2a and Ti2b provided on the circuit board 100, and the terminals Tv2a and Tv2b are respectively connected with the probes 22a and 22b for voltage detection. Connecting.

次いで、図3に示すように、プローブ21a,22aを測定対象50の端子50aに接触させ、プローブ21b22bを測定対象50の端子50bに接触させる。   Next, as shown in FIG. 3, the probes 21 a and 22 a are brought into contact with the terminal 50 a of the object to be measured 50, and the probe 21 b 22 b is brought into contact with the terminal 50 b of the object to be measured 50.

続いて、図外の操作部を操作して測定の開始を指示する。これに応じて、処理部13が測定処理を実行する。この測定処理では、処理部13は、電流供給部11を制御して、測定用電流(直流定電流)を出力させる。この際に、測定用電流が配線W3a,W3bおよびプローブ21a,21bを介して測定対象50に供給される。   Subsequently, an operation unit (not shown) is operated to instruct start of measurement. In response to this, the processing unit 13 executes a measurement process. In this measurement process, the processing unit 13 controls the current supply unit 11 to output a measurement current (DC constant current). At this time, the measurement current is supplied to the measurement target 50 via the wires W3a and W3b and the probes 21a and 21b.

次いで、処理部13は、電圧検出部12を制御して、測定用電流の供給によって測定対象50の端子50a,50bの間に生じる電圧の電圧値Vmを検出させる。この場合、電圧検出部12は、端子50a,50bにそれぞれ接触しているプローブ22a,22bおよび配線W1,W2を介して電圧値Vmを検出する。   Next, the processing unit 13 controls the voltage detection unit 12 to detect the voltage value Vm of the voltage generated between the terminals 50a and 50b of the measurement target 50 by the supply of the measurement current. In this case, the voltage detection unit 12 detects the voltage value Vm via the probes 22a and 22b and the wires W1 and W2 in contact with the terminals 50a and 50b, respectively.

ここで、この測定装置1では、各々の開口面積が互いに等しくかつ開口面同士が対向する(同じ向きを向いている)ループL1,L2を構成する配線W1,W2が回路基板100に形成され、配線W1,W2が電圧検出部12の各電極にそれぞれ接続されている。このため、この測定装置1では、回路基板100の周囲に外部磁界が発生して、その外部磁界が各ループL1,L2を通過している場合においても、各ループL1,L2の双方に発生する誘導起電力が互いに打ち消し合うように電圧検出部12に作用する結果、誘導起電力の影響が少なく抑えられて、電圧検出部12によって電圧値Vmが正確に検出される。   Here, in the measuring device 1, the wires W 1 and W 2 constituting the loops L 1 and L 2 in which the opening areas are equal to each other and the opening surfaces face each other (same direction) are formed on the circuit board 100. The wires W1 and W2 are connected to the electrodes of the voltage detection unit 12, respectively. For this reason, in the measuring device 1, an external magnetic field is generated around the circuit board 100, and the external magnetic field is generated in both of the loops L1 and L2 even when passing through the loops L1 and L2. As a result of the induced electromotive forces acting on the voltage detection unit 12 so as to cancel each other, the influence of the induced electromotive force is suppressed to a low level, and the voltage detection unit 12 accurately detects the voltage value Vm.

続いて、処理部13は、電圧検出部12によって検出された電圧値Vmと、電流供給部11から出力された測定用電流の電流値Imとに基づいて測定対象50の抵抗値(被測定量)を測定する。この場合、上記したように電圧検出部12によって電圧値Vmが正確に検出されている。このため、この測定装置1では、抵抗値の測定精度を十分に向上させることが可能となっている。   Subsequently, the processing unit 13 determines the resistance value of the measurement target 50 based on the voltage value Vm detected by the voltage detection unit 12 and the current value Im of the measurement current output from the current supply unit 11 (measured amount Measure). In this case, as described above, the voltage detection unit 12 correctly detects the voltage value Vm. For this reason, in this measuring device 1, it is possible to sufficiently improve the measurement accuracy of the resistance value.

なお、上記した回路基板100において、導体層101aに導体パターンP1を形成し、導体層101cに導体パターンP2を形成し、導体層101bに導体パターンP3を形成し、導体層101dに導体パターンP4を形成する構成に代えて、導体層101bに導体パターンP1を形成し、導体層101dに導体パターンP2を形成し、導体層101aに導体パターンP3を形成し、導体層101cに導体パターンP4を形成する構成を採用することもできる。   In the circuit board 100 described above, the conductor pattern P1 is formed in the conductor layer 101a, the conductor pattern P2 is formed in the conductor layer 101c, the conductor pattern P3 is formed in the conductor layer 101b, and the conductor pattern P4 is formed in the conductor layer 101d. Instead of the configuration to be formed, conductor pattern P1 is formed in conductor layer 101b, conductor pattern P2 is formed in conductor layer 101d, conductor pattern P3 is formed in conductor layer 101a, and conductor pattern P4 is formed in conductor layer 101c. Configurations can also be adopted.

このように、この回路基板100および測定装置1では、導体層101a,101cにそれぞれ形成された導体パターンP1,P2と、導体パターンP1,P2を接続するビアV1,V2とを備えて配線W1が構成され、導体層101b,101dにそれぞれ形成された導体パターンP3,P4と、導体パターンP3,P4を接続するビアV3,V4とを備えて配線W2が構成されている。つまり、この回路基板100および測定装置1では、外部磁界による誘導起電力の影響を少なく抑えることが可能な配線W1,W2を4つの導体パターンPと4つのビアVで構成することができる。このため、この回路基板100および測定装置1によれば、2つの導体層101にそれぞれ並べた数多くの配線を数多くのビアVで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアVの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することができる。   As described above, in the circuit board 100 and the measuring device 1, the wiring W1 includes the conductor patterns P1 and P2 formed on the conductor layers 101a and 101c and the vias V1 and V2 connecting the conductor patterns P1 and P2, respectively. The wiring W2 is configured to include the conductor patterns P3 and P4 that are configured and formed in the conductor layers 101b and 101d, respectively, and the vias V3 and V4 that connect the conductor patterns P3 and P4. That is, in the circuit board 100 and the measuring device 1, the wires W1 and W2 capable of suppressing the influence of the induced electromotive force due to the external magnetic field can be configured by the four conductor patterns P and the four vias V. For this reason, according to the circuit board 100 and the measuring device 1, two spiral wires formed by connecting many wires arranged in two conductor layers 101 with many vias V are twisted together. As compared with the conventional configuration in which the influence of the induced electromotive force due to the external magnetic field is reduced by configuring as described above, the number of vias V can be small and the manufacturing process can be simplified, so that the manufacturing efficiency is sufficiently improved. Thus, the manufacturing cost can be sufficiently reduced.

また、この回路基板100および測定装置1によれば、導体パターンP1を導体層101aに形成し、導体パターンP2を導体層101cに形成し、導体パターンP3を導体層101bに形成し、導体パターンP4を導体層101dに形成したことにより、例えば、導体パターンP1を導体層101aに形成し、導体パターンP2を導体層101dに形成し、導体パターンP3を導体層101bに形成し、導体パターンP4を導体層101cに形成する構成と比較して、配線W1で構成されるループL1の開口面積と配線W2で構成されるループL2の開口面積とを同程度に近づけることができる。このため、この回路基板100および測定装置1によれば、回路基板100の周囲に外部磁界が発生しているときに各ループL1,L2に発生する誘導起電力を同程度に近づけることができるため、誘導起電力を確実に打ち消すことができる結果、外部磁界による誘導起電力の影響をより少なく抑えることができる。   Further, according to the circuit board 100 and the measuring device 1, the conductor pattern P1 is formed on the conductor layer 101a, the conductor pattern P2 is formed on the conductor layer 101c, the conductor pattern P3 is formed on the conductor layer 101b, and the conductor pattern P4 is formed. Is formed in the conductor layer 101d, for example, the conductor pattern P1 is formed in the conductor layer 101a, the conductor pattern P2 is formed in the conductor layer 101d, the conductor pattern P3 is formed in the conductor layer 101b, and the conductor pattern P4 is formed As compared with the structure formed in the layer 101c, the opening area of the loop L1 formed by the wiring W1 and the opening area of the loop L2 formed by the wiring W2 can be made nearly equal. For this reason, according to the circuit board 100 and the measuring device 1, when the external magnetic field is generated around the circuit board 100, it is possible to bring the induced electromotive forces generated in the loops L1 and L2 close to the same degree. As a result of being able to reliably cancel out the induced electromotive force, the influence of the induced electromotive force due to the external magnetic field can be further suppressed.

また、この回路基板100および測定装置1によれば、配線W1で構成されるループL1の開口面積と、配線W2で構成されるループL2の開口面積とが等しくなるように構成したことにより、回路基板100の周囲に外部磁界が発生している場合に各ループL1,L2に発生する誘導起電力を等しくすることができるため、誘導起電力同士をより確実に打ち消すことができる結果、外部磁界による誘導起電力の影響をさらに少なく抑えることができる。   Further, according to the circuit board 100 and the measuring device 1, the circuit is configured such that the opening area of the loop L1 formed by the wiring W1 and the opening area of the loop L2 formed by the wiring W2 are equal. Since the induced electromotive forces generated in the loops L1 and L2 can be equalized when an external magnetic field is generated around the substrate 100, the induced electromotive forces can be canceled with each other more reliably. The influence of the induced electromotive force can be further reduced.

次に、回路基板の他の一例としての回路基板200、および回路基板200を備えた測定装置1Aについて説明する。なお、以下の説明において、上記した回路基板100および測定装置1と同様の構成要素については、同じ符号を付して、重複する説明を省略する。この回路基板200は、図4に示すように、回路基板200の上面200u側(一面側)から下面200b側(他面側)向かって設けられた3つの導体層201a(A導体層に相当する)、導体層201b(B導体層に相当する)、および導体層201c(C導体層に相当する:以下、導体層201a〜201cを区別しないときには「導体層201」ともいう)と、各導体層201の間に設けられた2つの絶縁層202a,202bとを備えて構成されている。   Next, a circuit board 200 as another example of the circuit board and a measuring apparatus 1A provided with the circuit board 200 will be described. In the following description, the same components as those of the circuit board 100 and the measuring device 1 described above are denoted by the same reference numerals, and redundant description will be omitted. As shown in FIG. 4, the circuit board 200 corresponds to three conductor layers 201a (A conductor layer) provided from the upper surface 200u side (one surface side) to the lower surface 200b side (the other surface side) of the circuit substrate 200. Conductor layer 201b (corresponding to B conductor layer), and conductor layer 201c (corresponding to C conductor layer: hereinafter referred to as “conductor layer 201” when conductor layers 201a to 201c are not distinguished), and each conductor layer It comprises two insulating layers 202a and 202b provided between the electrodes 201.

また、図5に示すように、導体層201aには、電流供給部11の一方の電極が接続される端子Ti1a、および測定対象50の端子50aに接触させる電流供給用のプローブ21aが接続される端子Ti2aが設けられ、導体層201cには、電流供給部11の他方の電極が接続される端子Ti1b、および測定対象50の端子50bに接触させる電流供給用のプローブ21bが接続される端子Ti2bが設けられている。   Further, as shown in FIG. 5, the conductor layer 201a is connected to a terminal Ti1a to which one electrode of the current supply unit 11 is connected and a probe 21a for supplying current to be in contact with the terminal 50a of the object 50 to be measured. A terminal Ti2a is provided, a terminal Ti1b to which the other electrode of the current supply unit 11 is connected, and a terminal Ti2b to which a probe 21b for supplying current to be brought into contact with the terminal 50b of the object 50 is connected It is provided.

また、図4,5に示すように、導体層201aには、電圧検出部12の一方の電極が接続される端子TvAa(A端子に相当する)、および測定対象50の端子50aに接触させる電圧検出用のプローブ22aが接続される端子TvBa(B端子に相当する)が設けられ、導体層201cには、電圧検出部12の他方の電極が接続される端子TvAb(A端子に相当する)、および測定対象50の端子50bに接触させる電圧検出用のプローブ22bが接続される端子TvBb(B端子に相当する)が設けられている。この場合、図4では、端子Ti1a,Ti1b,Ti2a,Ti2b、および後述する配線W3a,W3bの図示を省略している。なお、以下の説明において、端子TvAa,TvAbを区別しないときには「端子TvA」ともいい、端子TvBa,TvBbを区別しないときには「端子TvB」ともいう。また、端子Ti1a,Ti1b,Ti2a,Ti2b,TvAa,TvAb,TvBa,TvBbを区別しないときには「端子T」ともいう。   Further, as shown in FIGS. 4 and 5, the conductor layer 201a has a terminal TvAa (corresponding to an A terminal) to which one electrode of the voltage detection unit 12 is connected and a voltage to be brought into contact with the terminal 50a of the object 50 to be measured. A terminal TvBa (corresponding to a B terminal) to which the detection probe 22a is connected is provided, and a terminal TvAb (corresponding to an A terminal) to which the other electrode of the voltage detection unit 12 is connected is provided on the conductor layer 201c. A terminal TvBb (corresponding to a B terminal) to which a voltage detection probe 22b to be brought into contact with the terminal 50b of the measurement target 50 is connected is provided. In this case, in FIG. 4, the terminals Ti1a, Ti1b, Ti2a, Ti2b and wires W3a, W3b described later are not shown. In the following description, when terminals TvAa and TvAb are not distinguished from each other, they are also referred to as “terminal TvA”, and when terminals TvBa and TvBb are not distinguished from each other, also referred to as “terminal TvB”. The terminals Ti1a, Ti1b, Ti2a, Ti2b, TvAa, TvAb, TvBa, and TvBb are also referred to as "terminal T".

また、回路基板200には、各端子T同士を接続する配線が形成されている。具体的には、図5に示すように、回路基板200の導体層201aには、端子Ti1aと端子Ti2aとを接続する配線W3aが形成され、回路基板200の導体層201cには、端子Ti1bとTi2bとを接続する配線W3bが形成されている。   Further, on the circuit board 200, a wire for connecting the terminals T is formed. Specifically, as shown in FIG. 5, a wiring W3a connecting the terminals Ti1a and Ti2a is formed in the conductor layer 201a of the circuit board 200, and the terminals Ti1b and W1a are formed in the conductor layer 201c of the circuit board 200. A wire W3b connecting Ti2b is formed.

また、回路基板200には、図4,5に示すように、端子TvAaと端子TvBaとを接続する配線Wa(A配線に相当する)、および端子TvAbと端子TvBbとを接続する配線Wb(B配線に相当する)が形成されている。この場合、この回路基板200では、電圧検出部12によって検出される電圧値Vmの検出に際して、電圧値Vmに対する外部磁界の影響を低減させるため、配線W1および配線W2によってループが構成される。   In the circuit board 200, as shown in FIGS. 4 and 5, the wiring Wa (corresponding to the A wiring) connecting the terminal TvAa and the terminal TvBa, and the wiring Wb (B connecting the terminal TvAb and the terminal TvBb) (Corresponding to wiring) is formed. In this case, in the circuit board 200, when detecting the voltage value Vm detected by the voltage detection unit 12, in order to reduce the influence of the external magnetic field on the voltage value Vm, a loop is formed by the wire W1 and the wire W2.

具体的には、配線Waは、図4,5に示すように、回路基板200の導体層201aに形成された導体パターンPa(A導体パターンに相当する)と、回路基板200の導体層201cに形成された導体パターンPb(B導体パターンに相当する)と、導体パターンPa,Pbを端子TvA側で接続するビアVa(Aビアに相当する)と、導体パターンPa,Pbを端子TvB側で接続するビアVb(Bビアに相当する)とを備えて構成されている。   Specifically, as shown in FIGS. 4 and 5, the wiring Wa is formed on the conductor pattern Pa (corresponding to the A conductor pattern) formed on the conductor layer 201 a of the circuit board 200 and the conductor layer 201 c of the circuit board 200. The formed conductor pattern Pb (corresponding to the B conductor pattern) and the via Va (corresponding to the A via) connecting the conductor patterns Pa and Pb on the terminal TvA side and the conductor patterns Pa and Pb connected on the terminal TvB side And a via Vb (corresponding to a B via).

また、配線Wbは、図4,5に示すように、回路基板200の導体層201bに形成された導体パターンPc(C導体パターンに相当する)と、回路基板200の導体層201cの端子TvA側に(端子TvAbに接続するように)形成された導体パターンPd(D導体パターンに相当する)と、導体層201cの端子TvB側に(端子TvBbに接続するように)形成された導体パターンPe(E導体パターンに相当する)と、導体パターンPcの端子TvA側と導体パターンPdとを接続するビアVc(Cビアに相当する)と、導体パターンPcの端子TvB側と導体パターンPeとを接続するビアVd(Dビアに相当する)とを備えて構成されている。なお、以下の説明において、ビアVa〜Vdを区別しないときには「ビアV」ともいう。   In addition, as shown in FIGS. 4 and 5, the wire Wb has a conductor pattern Pc (corresponding to a C conductor pattern) formed on the conductor layer 201 b of the circuit board 200 and a terminal TvA side of the conductor layer 201 c of the circuit board 200. A conductor pattern Pd (corresponding to a terminal TvAb) (corresponding to a D conductor pattern) and a conductor pattern Pe (a terminal TvBb) formed on a terminal TvB side of the conductor layer 201c (to be connected to the terminal TvBb). E) corresponding to a conductor pattern, a via Vc (corresponding to a C via) connecting the terminal TvA side of the conductor pattern Pc to the conductor pattern Pd, and a terminal TvB side of the conductor pattern Pc to the conductor pattern Pe And a via Vd (corresponding to a D via). In the following description, when the vias Va to Vd are not distinguished, they are also referred to as “vias V”.

また、この回路基板200では、図6に示すように、配線Waの一部(導体パターンPa)、配線Wb(導体パターンPc〜Pe、ビアVc,Vd)、電圧検出部12、プローブ22a,22b、および測定対象50で構成されるループLa(同図における斜線を付したループ:Aループに相当する)の開口面と、図7に示すように、配線Waの一部(導体パターンPaの一部、導体パターンPb、ビアVa,Vb)、配線Wb(導体パターンPc〜Pe、ビアVc,Vd)、電圧検出部12、プローブ22a,22b、および測定対象50で構成されるループLb(同図における斜線を付したループ:Bループに相当する)の開口面とが同じ向きを向くように構成されている。また、この回路基板200では、ループLaおよびループLbを同じ向きで同じ磁束密度の外部磁界が通過したときに各ループLa,Lbに生じる誘導起電力が互いに打ち消し合うように各ループLa,Lbの開口面積が規定されている。具体的には、図6に示すループLaの全体の領域A−1の開口面積と、図7に示すループLbのうちの領域B−1の開口面積から領域B−2および領域B−3の開口面積を差し引いた開口面積とが互いに等しくなるように構成されている。このため、この回路基板200では、回路基板200の周囲に外部磁界が発生しるときに各ループLa,Lbに発生する誘導起電力が互いに打ち消し合うように電圧検出部12に作用する。この結果、この回路基板200では、電圧検出部12が測定対象50の電圧値Vmを検出する際の外部磁界による誘導起電力の影響を少なく抑えることが可能となっている。したがって、この回路基板200を備えた測定装置1では、電圧検出部12によって検出された電圧値Vmに基づく測定対象50の抵抗値を正確に測定することが可能となっている。   Further, in this circuit board 200, as shown in FIG. 6, a part of the wiring Wa (conductor pattern Pa), the wiring Wb (conductor patterns Pc to Pe, vias Vc, Vd), the voltage detection unit 12, the probes 22a, 22b And an opening surface of a loop La (a hatched loop in the figure: equivalent to the A loop) constituted by the measurement target 50 and a part of the wiring Wa (conductor pattern Pa, as shown in FIG. A loop Lb configured by a portion, a conductor pattern Pb, vias Va and Vb, wires Wb (conductor patterns Pc to Pe, vias Vc and Vd), a voltage detection unit 12, probes 22a and 22b, and a measurement target 50 (see FIG. The hatched loop in (: corresponding to the B loop) is configured to face in the same direction as the opening surface of the loop. Further, in this circuit board 200, when the external magnetic field of the same magnetic flux density passes through the loops La and Lb in the same direction, the induced electromotive forces generated in the loops La and Lb cancel each other out. The opening area is defined. Specifically, based on the opening area of the entire area A-1 of the loop La shown in FIG. 6 and the opening area of the area B-1 of the loop Lb shown in FIG. 7, the area B-2 and the area B-3 The opening areas are equal to the opening areas minus the opening areas. Therefore, in the circuit board 200, when an external magnetic field is generated around the circuit board 200, the induced electromotive forces generated in the loops La and Lb act on the voltage detection unit 12 so as to cancel each other. As a result, in the circuit board 200, the influence of the induced electromotive force due to the external magnetic field when the voltage detection unit 12 detects the voltage value Vm of the measurement target 50 can be reduced. Therefore, in the measuring device 1 provided with the circuit board 200, it is possible to accurately measure the resistance value of the measuring object 50 based on the voltage value Vm detected by the voltage detection unit 12.

また、この回路基板200では、上記したように、導体層201a,201cにそれぞれ形成した導体パターンPa,Pbを2つのビアVa,Vbで接続した配線Wa、導体層201b,201cにそれぞれ形成した導体パターンPc〜Peを2つのビアVc,Vdで接続した配線Wb、電圧検出部12、プローブ22a,22bおよび測定対象50でループLa,Lbを構成することで、外部磁界による誘導起電力の影響を少なく抑えることが可能となっている。つまり、この回路基板200では、4つのビアVで外部磁界による誘導起電力の影響を少なく抑えることが可能な配線Wa,Wbを構成することができる。このため、この回路基板200および測定装置1Aにおいても、2つの導体層201にそれぞれ並べた数多くの配線を数多くのビアVで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアVの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することができる。   Further, in the circuit board 200, as described above, the conductor Wa formed by connecting the conductor patterns Pa and Pb respectively formed on the conductor layers 201a and 201c by two vias Va and Vb, and the conductor formed respectively to the conductor layers 201b and 201c By forming the loops La and Lb by the wire Wb connecting the patterns Pc to Pe with two vias Vc and Vd, the voltage detection unit 12, the probes 22a and 22b, and the measurement target 50, the influence of the induced electromotive force due to the external magnetic field can be obtained. It is possible to reduce the number. That is, in the circuit board 200, the interconnections Wa and Wb can be configured by the four vias V which can reduce the influence of the induced electromotive force due to the external magnetic field. Therefore, also in the circuit board 200 and the measuring device 1A, two spiral wires formed by connecting many wires arranged in two conductor layers 201 with many vias V are twisted together. As compared with the conventional configuration in which the influence of the induced electromotive force due to the external magnetic field is reduced by configuring as described above, the number of vias V is small and the manufacturing process can be simplified, so that the manufacturing efficiency is sufficiently improved. The manufacturing cost can be sufficiently reduced.

また、この回路基板200では、上記したように、ループLaおよびループLbを同じ向きで同じ磁束密度の外部磁界が通過したときに各ループLa,Lbに生じる誘導起電力が互いに打ち消し合うように各ループLa,Lbの開口面積が規定されている。このため、この回路基板200および測定装置1Aにおいても、回路基板100の周囲に外部磁界が発生している場合において、その外部磁界による誘導起電力の影響をさらに少なく抑えることができる。   Further, in the circuit board 200, as described above, the induced electromotive forces generated in the loops La and Lb cancel each other when the external magnetic field having the same magnetic flux density passes in the same direction in the loops La and Lb. The open areas of the loops La and Lb are defined. Therefore, also in the circuit board 200 and the measuring apparatus 1A, when an external magnetic field is generated around the circuit board 100, the influence of the induced electromotive force due to the external magnetic field can be further suppressed.

なお、上記した回路基板200において、導体層201aに導体パターンPaを形成し、導体層201cに導体パターンPb,Pd,Peを形成する構成に代えて、導体層201aに導体パターンPb,Pd,Peを形成し、導体層201cに導体パターンPaを形成する構成を採用することもできる。   In the circuit board 200 described above, instead of forming the conductor pattern Pa in the conductor layer 201a and forming the conductor patterns Pb, Pd, Pe in the conductor layer 201c, the conductor patterns Pb, Pd, Pe in the conductor layer 201a Can be employed to form a conductor pattern Pa on the conductor layer 201c.

次に、回路基板の他の一例としての回路基板100A、および回路基板100Aを備えた測定装置1Bについて説明する。なお、以下の説明において、上記した回路基板100および測定装置1と同様の構成要素については、同じ符号を付して、重複する説明を省略する。この回路基板100Aは、図8に示すように、上記した回路基板100と同様に、上面100u側から下面100b側向かって設けられた4つの導体層101a〜101dと、各導体層101の間に設けられた3つの絶縁層102a〜102cとを備えて構成されている。   Next, a circuit board 100A as another example of the circuit board and a measuring apparatus 1B provided with the circuit board 100A will be described. In the following description, the same components as those of the circuit board 100 and the measuring device 1 described above are denoted by the same reference numerals, and redundant description will be omitted. This circuit board 100A is, as shown in FIG. 8, similar to the above circuit board 100, between the four conductor layers 101a to 101d provided from the upper surface 100u side to the lower surface 100b side, and the respective conductor layers 101. And three insulating layers 102a to 102c provided.

また、図8,9に示すように、回路基板100Aの導体層101aには、上記した回路基板100と同様に、端子Ti1a,Ti2a,Tv1a,Tv2aが設けられ、導体層101dには、端子Ti1b,Ti2b,Tv1b,Tv2bが設けられている。また、上記した回路基板100と同様に、導体層101aには、端子Ti1aと端子Ti2aとを接続する配線W3aが形成され、導体層101dには、端子Ti1bとTi2bとを接続する配線W3bが形成されている(図9参照)。なお、図8では、端子Ti1a,Ti1b,Ti2a,Ti2b、および配線W3a,W3bの図示を省略している。   Further, as shown in FIGS. 8 and 9, terminals Ti1a, Ti2a, Tv1a, Tv2a are provided in the conductor layer 101a of the circuit board 100A as in the circuit board 100 described above, and the terminal Ti1b is provided in the conductor layer 101d. , Ti2b, Tv1b, Tv2b are provided. Further, similarly to the circuit board 100 described above, the wiring W3a connecting the terminals Ti1a and Ti2a is formed on the conductor layer 101a, and the wiring W3b connecting the terminals Ti1b and Ti2b is formed on the conductor layer 101d. (See FIG. 9). In FIG. 8, the terminals Ti1a, Ti1b, Ti2a, Ti2b, and the wirings W3a, W3b are not shown.

また、回路基板100Aには、端子Tv1aと端子Tv2aとを接続する配線W1(第1配線に相当する)、および端子Tv1bと端子Tv2bとを接続する配線W2(第2配線に相当する)が形成されている。また、この回路基板100Aにおいても、上記した回路基板100と同様に、電圧検出部12によって検出される電圧値Vmの検出に際して、電圧値Vmに対する外部磁界の影響を低減させるため、配線W1および配線W2がループをなすように構成されている。   In the circuit board 100A, a wire W1 (corresponding to a first wire) connecting the terminal Tv1a and the terminal Tv2a, and a wire W2 (corresponding to a second wire) connecting the terminal Tv1b and the terminal Tv2b are formed. It is done. Further, in the circuit board 100A as well as the circuit board 100 described above, when detecting the voltage value Vm detected by the voltage detection unit 12, in order to reduce the influence of the external magnetic field on the voltage value Vm, the wiring W1 and the wiring W2 is configured to form a loop.

具体的には、配線W1は、図8,9に示すように、回路基板100の導体層101aに形成された導体パターンP1(第1導体パターンに相当する)と、回路基板100の導体層101dに形成された導体パターンP2(第2導体パターンに相当する)と、導体パターンP1,P2を端子Tv1側で接続するビアV1と、導体パターンP1,P2を端子Tv2側で接続するビアV2とを備えて構成されている。   Specifically, as shown in FIGS. 8 and 9, the wiring W1 includes a conductor pattern P1 (corresponding to a first conductor pattern) formed on the conductor layer 101a of the circuit board 100 and a conductor layer 101d of the circuit board 100. A conductor pattern P2 (corresponding to a second conductor pattern) formed in the first embodiment, a via V1 connecting the conductor patterns P1 and P2 on the terminal Tv1 side, and a via V2 connecting the conductor patterns P1 and P2 on the terminal Tv2 side It is configured to be equipped.

また、配線W2は、図8,9に示すように、回路基板100の導体層101bに形成された導体パターンP3(第3導体パターンに相当する)と、回路基板100の導体層101cに形成された導体パターンP4(第4導体パターンに相当する)と、導体層101cにおける端子Tv1側に(端子Tv1bに接続するように)形成された導体パターンP5と、導体層101cにおける端子Tv2側に(端子Tv2bに接続するように)形成された導体パターンP6と、導体パターンP3,P4,P5を端子Tv1側で接続するビアV3と、導体パターンP3,P4,P6を端子Tv2側で接続するビアV4とを備えて構成されている。   Further, as shown in FIGS. 8 and 9, the wiring W2 is formed on the conductor pattern 101 (corresponding to the third conductor pattern) formed on the conductor layer 101b of the circuit board 100 and the conductor layer 101c on the circuit board 100. A conductor pattern P4 (corresponding to a fourth conductor pattern), a conductor pattern P5 formed on the terminal Tv1 side of the conductor layer 101c (so as to be connected to the terminal Tv1b), and a terminal Tv2 side of the conductor layer 101c (terminal Conductor pattern P6 formed so as to connect to Tv2b, via V3 connecting conductor patterns P3, P4 and P5 on the terminal Tv1 side, and via V4 connecting conductor patterns P3, P4 and P6 on the terminal Tv2 side It is configured with.

また、この回路基板100Aでは、図8に示すように、配線W1(導体パターンP1,P2およびビアV1,V2)で構成されるループL1(同図に破線で示すループ)の開口面と、配線W2(導体パターンP3,P4およびビアV3,V4)で構成されるループL2(同図に一点鎖線で示すループ)の開口面とが対向し(同じ向きを向き)、ループL1の開口面積とループL2の開口面積とが互いに等しくなるように構成されている。このため、この回路基板100Aにおいても、回路基板100Aの周囲に外部磁界が発生したときに各ループL1,L2に発生する誘導起電力が互いに打ち消し合うように電圧検出部12に作用する結果、電圧検出部12が測定対象50の電圧値Vmを検出する際の外部磁界による誘導起電力の影響を少なく抑えることができる。したがって、この回路基板100Aを備えた測定装置1においても、電圧検出部12によって検出された電圧値Vmに基づく測定対象50の抵抗値を正確に測定することができる。   Further, in the circuit board 100A, as shown in FIG. 8, an opening surface of a loop L1 (a loop indicated by a broken line in the figure) constituted by the wires W1 (the conductor patterns P1 and P2 and the vias V1 and V2) The opening surface of a loop L2 (a loop indicated by an alternate long and short dash line in the same figure) composed of W2 (conductor patterns P3 and P4 and vias V3 and V4) faces (same direction), the opening area of the loop L1 and the loop The opening areas of L2 are configured to be equal to each other. Therefore, in the circuit board 100A as well, when the external magnetic field is generated around the circuit board 100A, the induced electromotive forces generated in the loops L1 and L2 act on the voltage detection unit 12 so that they cancel each other, resulting in voltage The influence of the induced electromotive force due to the external magnetic field when the detection unit 12 detects the voltage value Vm of the measurement target 50 can be suppressed to a low level. Therefore, also in the measuring device 1 provided with the circuit board 100A, the resistance value of the measuring object 50 based on the voltage value Vm detected by the voltage detection unit 12 can be accurately measured.

また、この回路基板100Aでは、上記したように、導体層101a,101dにそれぞれ形成した導体パターンP1,P2を2つのビアV1,V2で接続した配線W1でループL1を構成し、導体層101b,101cにそれぞれ形成した導体パターンP3,P4を2つのビアV3,V4で接続した配線W2でループL2を構成することで、外部磁界による誘導起電力の影響を少なく抑えることが可能となっている。つまり、この回路基板100Aでは、4つのビアVで外部磁界による誘導起電力の影響を少なく抑えることが可能な配線W1,W2を構成することができる。このため、この回路基板100Aにおいても、2つの導体層101にそれぞれ並べた数多くの配線を数多くのビアVで接続して形成した2つの螺旋状の配線を撚り合わせた状態となるように構成することで外部磁界による誘導起電力の影響を少なく抑える従来の構成と比較して、ビアVの数が少なく製造工程を簡略化することができる分、製造効率を十分に向上させて製造コストを十分に低減することができる。   Further, in the circuit board 100A, as described above, the loop W1 is formed by the wire W1 in which the conductor patterns P1 and P2 formed in the conductor layers 101a and 101d are connected by two vias V1 and V2, respectively. By forming the loop L2 by the wiring W2 in which the conductor patterns P3 and P4 respectively formed in 101c are connected by two vias V3 and V4, it is possible to suppress the influence of the induced electromotive force due to the external magnetic field. That is, in the circuit board 100A, the wirings W1 and W2 can be configured by the four vias V that can reduce the influence of the induced electromotive force due to the external magnetic field. Therefore, also in this circuit board 100A, it is configured to be in a state where two spiral wirings formed by connecting many wirings arranged in two conductor layers 101 with many vias V are twisted together. Therefore, the number of vias V is small and the manufacturing process can be simplified, as compared with the conventional configuration that suppresses the influence of the induced electromotive force due to the external magnetic field, and the manufacturing efficiency is sufficiently improved and the manufacturing cost is sufficient. Can be reduced to

なお、回路基板および測定装置の構成は上記の構成に限定されない。例えば、4つの導体層101を有する回路基板100,100A、および3つの導体層201を有する回路基板200に適用した例について上記したが、5つ以上の導体層101を有する回路基板100,100Aにおける各導体層101のうちの4つの導体層101を用いて配線W1,W2を形成する構成や、4つ以上の導体層201を有する回路基板200における各導体層201のうちの3つの導体層201を用いて配線Wa,Wbを形成する構成を採用することもできる。   The configurations of the circuit board and the measuring device are not limited to the above configurations. For example, although the example applied to the circuit board 100, 100A having four conductor layers 101 and the circuit board 200 having three conductor layers 201 has been described above, the circuit board 100, 100A having five or more conductor layers 101 is described above. A configuration in which the wirings W1 and W2 are formed using four conductor layers 101 of each conductor layer 101, and three conductor layers 201 of each conductor layer 201 in the circuit board 200 having four or more conductor layers 201. It is also possible to employ a configuration in which the wirings Wa and Wb are formed using

また、ループL1,L2の各開口面積が互いに等しくなるように回路基板100,100Aを構成した例について上記したが、ループL1,L2の各開口面積が異なる構成を採用することもできる。また、ループLaの領域A−1の開口面積と、ループLbのうちの領域B−1の開口面積から領域B−2および領域B−3の開口面積を差し引いた開口面積とが互いに等しくなるように回路基板200を構成した例(各ループLa,Lbに生じる誘導起電力が互いに打ち消し合う構成)について上記したが、これらの開口面積が異なる構成(各ループLa,Lbに生じる誘導起電力が完全には打ち消し合わない構成)を採用することもできる。   Although the circuit boards 100 and 100A are configured as described above so that the opening areas of the loops L1 and L2 are equal to each other, configurations in which the opening areas of the loops L1 and L2 are different may be employed. Also, the opening area of the area A-1 of the loop La and the opening area obtained by subtracting the opening areas of the area B-2 and the area B-3 from the opening area of the area B-1 of the loop Lb are equal to each other As described above, the circuit board 200 is configured (the induced electromotive forces generated in the respective loops La and Lb cancel each other), but the configuration in which the opening areas are different (the induced electromotive forces generated in the respective loops La and Lb are completely Can also be adopted.

また、被測定量としての抵抗値を測定する測定装置1に適用した例について上記したが、インピーダンス、インダクタンス、容量等の抵抗値以外の被測定量を測定する測定装置に適用することができる。   Although the example applied to measuring device 1 which measures resistance as a to-be-measured amount was mentioned above, it is applicable to a measuring device which measures other than resistances, such as impedance, inductance, and capacity.

1,1A,1B 測定装置
12 電圧検出部
11 電流供給部
13 処理部
22a,22b プローブ
100,100A,200 回路基板
100b,200b 下面
100u,200u 上面
101a,101b,101c,101d,201a〜201c 導体層
Im 電流値
P1〜P4,Pa〜Pe 導体パターン
Tv1a,Tv1b,Tv2a,Tv2b 端子
TvAa,TvAb,TvBa,TvBb 端子
V1〜V4,Va〜Vd ビア
Vm 電圧値
W1,W2,Wa,Wb,W3a,W3b 配線
L1,L2,La,Lb ループ
1, 1A, 1B measuring device 12 voltage detection unit 11 current supply unit 13 processing unit 22a, 22b probe 100, 100A, 200 circuit board 100b, 200b lower surface 100u, 200u upper surface 101a, 101b, 101c, 101d, 201a to 201c conductor layer Im current values P1 to P4, Pa to Pe conductor patterns Tv1a, Tv1b, Tv2a, Tv2b terminals TvAa, TvAb, TvBa, TvBb terminals V1 to V4, Va to Vd Via Vm voltage values W1, W2, Wa, Wb, W3a, W3b Wiring L1, L2, La, Lb loop

Claims (6)

電圧検出部が接続される一対の第1端子のいずれか一方と測定対象に接触させる一対のプローブがそれぞれ接続される一対の第2端子のいずれか一方とを接続する第1配線、および前記各第1端子の他方と前記各第2端子の他方とを接続する第2配線が形成された回路基板であって、
当該回路基板の一面側から他面側に向かって設けられた第1導体層、第2導体層、第3導体層および第4導体層の少なくとも4つの導体層を有し、
前記第1配線は、前記第1導体層および前記第2導体層のいずれか一方の導体層に形成された第1導体パターンと、前記第3導体層および前記第4導体層のいずれか一方の導体層に形成された第2導体パターンと、前記第1導体パターンおよび前記第2導体パターンを前記第1端子側で接続する第1ビアと、前記第1導体パターンおよび前記第2導体パターンを前記第2端子側で接続する第2ビアとを備えて構成され、
前記第2配線は、前記第1導体層および前記第2導体層の他方の導体層に形成された第3導体パターンと、前記第3導体層および前記第4導体層の他方の導体層に形成された第4導体パターンと、前記第3導体パターンおよび前記第4導体パターンを前記第1端子側で接続する第3ビアと、前記第3導体パターンおよび前記第4導体パターンを前記第2端子側で接続する第4ビアとを備えて構成されている回路基板。
A first wiring for connecting one of a pair of first terminals to which a voltage detection unit is connected and one of a pair of second terminals to which a pair of probes to be brought into contact with a measurement object are connected, and each of the above It is a circuit board in which the 2nd wiring which connects the other of the 1st terminal, and the other of said each 2nd terminal was formed,
At least four conductor layers of a first conductor layer, a second conductor layer, a third conductor layer, and a fourth conductor layer provided from one surface side to the other surface side of the circuit board,
The first wiring includes a first conductor pattern formed in any one of the first conductor layer and the second conductor layer, and any one of the third conductor layer and the fourth conductor layer. A second conductor pattern formed in the conductor layer, a first via connecting the first conductor pattern and the second conductor pattern at the first terminal side, the first conductor pattern and the second conductor pattern; And a second via connected at the second terminal side,
The second wiring is formed in a third conductor pattern formed in the other conductor layer of the first conductor layer and the second conductor layer, and in the other conductor layer of the third conductor layer and the fourth conductor layer. And the third via connecting the third conductor pattern and the fourth conductor pattern on the first terminal side, the third conductor pattern and the fourth conductor pattern on the second terminal side And a fourth via connected to each other.
前記第1導体パターンは、前記第1導体層に形成され、前記第2導体パターンは、前記第3導体層に形成され、前記第3導体パターンは、前記第2導体層に形成され、前記第4導体パターンは、前記第4導体層に形成されている請求項1記載の回路基板。   The first conductor pattern is formed on the first conductor layer, the second conductor pattern is formed on the third conductor layer, and the third conductor pattern is formed on the second conductor layer. The circuit board according to claim 1, wherein four conductor patterns are formed in the fourth conductor layer. 前記第1配線で構成される第1ループの開口面積と、前記第2配線で構成される第2ループの開口面積とが互いに等しくなるように構成されている請求項1または2記載の回路基板。   3. The circuit board according to claim 1, wherein an opening area of the first loop formed of the first wiring and an opening area of the second loop formed of the second wiring are equal to each other. . 電圧検出部が接続される一対のA端子のいずれか一方と測定対象に接触させる一対のプローブがそれぞれ接続される一対のB端子のいずれか一方とを接続するA配線、および前記各A端子の他方と前記各B端子の他方とを接続するB配線が形成された回路基板であって、
当該回路基板の一面側から他面側に向かって設けられたA導体層、B導体層およびC導体層の少なくとも3つの導体層を有し、
前記A配線は、前記A導体層および前記C導体層のいずれか一方の導体層に形成されたA導体パターンと、前記A導体層および前記C導体層の他方の導体層に形成されたB導体パターンと、前記A導体パターンおよび前記B導体パターンを前記A端子側で接続するAビアと、前記A導体パターンおよび前記B導体パターンを前記B端子側で接続するBビアとを備えて構成され、
前記B配線は、前記B導体層に形成されたC導体パターンと、前記他方の導体層における前記A端子側に形成されたD導体パターンと、前記他方の導体層における前記B端子側に形成されたE導体パターンと、前記C導体パターンおよび前記D導体パターンを前記A端子側で接続するCビアと、前記C導体パターンおよび前記E導体パターンを前記B端子側で接続するDビアとを備えて構成されている回路基板。
The A wiring connecting one of a pair of A terminals to which the voltage detection unit is connected and one of a pair of B terminals to which a pair of probes to be brought into contact with the object to be measured are connected It is a circuit board in which B wiring which connects the other and the other of said each B terminal was formed, and
And at least three conductor layers of an A conductor layer, a B conductor layer, and a C conductor layer provided from one surface side to the other surface side of the circuit board,
The A wiring includes an A conductor pattern formed in any one of the A conductor layer and the C conductor layer, and a B conductor formed in the other conductor layer of the A conductor layer and the C conductor layer. It comprises a pattern, an A via connecting the A conductor pattern and the B conductor pattern on the A terminal side, and a B via connecting the A conductor pattern and the B conductor pattern on the B terminal side,
The B wiring is formed on a C conductor pattern formed on the B conductor layer, a D conductor pattern formed on the A terminal side of the other conductor layer, and on the B terminal side of the other conductor layer And a C via connecting the C conductor pattern and the D conductor pattern on the A terminal side, and a D via connecting the C conductor pattern and the E conductor pattern on the B terminal side. Circuit board configured.
前記A導体パターン、前記B配線、前記電圧検出部、前記各プローブおよび前記測定対象で構成されるAループ、並びに前記A導体パターンの一部、B導体パターン、前記Aビア、前記Bビア、前記B配線、前記電圧検出部、前記各プローブおよび前記測定対象で構成されるBループを同じ向きで同じ磁束密度の外部磁界が通過したときに当該各ループに生じる誘導起電力が互いに打ち消し合うように当該各ループの開口面積が規定されている請求項4記載の回路基板。   The A conductor pattern, the B wiring, the voltage detection unit, an A loop composed of the respective probes and the measurement target, and a part of the A conductor pattern, a B conductor pattern, the A via, the B via, When the external magnetic field of the same magnetic flux density passes in the same direction in the same direction in the B loop composed of the B wire, the voltage detection unit, the probes, and the measurement object, the induced electromotive forces generated in the loops cancel each other 5. The circuit board according to claim 4, wherein the open area of each loop is defined. 請求項1から5のいずれかに記載の回路基板と、前記電圧検出部と、前記回路基板に形成された第3配線を介して前記測定対象に測定用電流を供給する電流供給部と、前記電圧検出部によって検出された電圧値および前記測定用電流の電流値に基づいて前記測定対象の被測定量を測定する測定部とを備えている測定装置。   The circuit substrate according to any one of claims 1 to 5, the voltage detection unit, and a current supply unit for supplying a measurement current to the measurement target through a third wiring formed on the circuit substrate, A measuring unit comprising: a measuring unit configured to measure an amount to be measured of the measurement target based on a voltage value detected by the voltage detecting unit and a current value of the measuring current.
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JP2021022473A (en) * 2019-07-26 2021-02-18 株式会社デンソー Battery monitoring device
JP7205410B2 (en) 2019-07-26 2023-01-17 株式会社デンソー battery monitor

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