JP2019102725A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a mounting structure which can inhibit increase in area of a mounting substrate even when the number of mounting semiconductor devices increases.SOLUTION: A semiconductor device comprises at least two groups of chips, each group including a first chip 101(102) for lowering voltage (step-down) of a high-voltage signal directly applied and a second chip 201(202) for signal processing. One lead terminal out of lead terminals L1-L3 to which high voltage is applied is shared; and the lead terminals L1-L3 to which high voltage is applied are arranged away from other lead terminals L4-L20 and suspension lead terminals L4, L12, L20 of a die pad 5.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a multi-chip type semiconductor device, and more particularly to a semiconductor device in which a high voltage is applied to lead terminals.

  In hybrid vehicles and electric vehicles, a battery for driving the vehicle is configured to output a predetermined drive voltage, and it is necessary to constantly monitor the output voltage of the battery. For example, a battery for driving a vehicle of a hybrid car has an output voltage of about 200 V, and it is further boosted to be used at about 500 V. Therefore, a voltage monitoring circuit is required to monitor an abnormal voltage. Further, in recent years, a high voltage monitoring circuit for monitoring an abnormal voltage exceeding 1000 V is required.

  FIG. 10 shows an example of a motor drive device. Motor drive device 100 boosts (for example, boosts to 600 V) a DC high voltage (for example, 200 V) output from high voltage battery B insulated from the vehicle body by boost converter 101, and the boosted voltage is applied via smoothing capacitor 102. The inverter circuit 103 converts the voltage into a three-phase AC voltage for driving the motor and supplies it to the motor M for driving the vehicle. A motor drive circuit of this type is described, for example, in Patent Document 1.

  In such a motor drive device, in order to monitor the boosted voltage, the voltage detection circuit 200 is provided, and the voltages of the node b1 connected to the positive side of the battery B and the node b2 connected to the negative side of the battery B are detected. Based on the detection result, a control circuit (not shown) outputs a control signal to the boost converter 101 and the inverter circuit 103 to control motor drive. Here, the voltage detection circuit 200 can be configured by an operational amplifier and a resistor.

  FIG. 11 shows a general voltage detection circuit. The resistors 202a and 202b connected in series are elements for dividing the high voltage on the positive side of the battery B, and the terminal B1 is connected to the node b1 connected to the positive electrode side of the battery B shown in FIG. The end is grounded to the vehicle body. The series connection point of the resistor 202 a and the resistor 202 b is connected to the non-inverting input terminal of the operational amplifier 201. On the other hand, the resistors 202c and 202d connected in series are elements for dividing the high voltage on the negative side of the battery B, and the terminal B2 is connected to the node b2 connected to the negative side of the battery B shown in FIG. The other end is grounded to the vehicle body. The series connection point of the resistor 202 c and the resistor 202 d is connected to the inverting input terminal of the operational amplifier 201.

  The resistor 202e is an element (feedback resistor) for determining the amplification gain of the operational amplifier 201. One end of the resistor 202e is connected to the inverting input terminal of the operational amplifier 201, and the other end is connected to the output terminal OUT of the operational amplifier 201. . A detection signal output from voltage detection circuit 200 is input to a control circuit (not shown), and a control signal for controlling the operation of boost converter 101 and inverter circuit 103 is output from the control circuit to control the drive of motor M. Become.

  By the way, a voltage detection circuit for detecting a high voltage as used in a motor drive device of a hybrid car or an electric vehicle is formed of an integrated circuit chip including an operational amplifier and a resistance element in accordance with a general manufacturing process of a semiconductor device. If it is mounted and sealed by resin, there is a problem that discharge occurs between the leads to which a high voltage is applied and other leads arranged in the vicinity, and it can not be used. The

  In order to solve such a problem, the applicant of the present application has proposed a semiconductor device having a unique structure (Patent Document 1). The semiconductor device proposed by the applicant of the present invention has a first chip C1 mainly composed of a resistive element and a second chip C2 mainly composed of an operational amplifier as shown in FIG. The two lead terminals L1 and L2 to which the high voltage is applied are disposed at intervals on one side of the resin-sealed semiconductor device, and the other lead terminals to which the high voltage is not applied are disposed on the opposite side facing each other To be configured. In addition, a sealing resin R is embedded between the lead terminals to prevent discharge.

JP, 2016-136608, A

  By the way, in a general hybrid car or an electric car, it is necessary to monitor a battery voltage (for example, 200 V) and a boosted high voltage (for example, about 1400 V) for vehicle control. Therefore, it is necessary to mount two semiconductor devices shown in FIG. 12, and there is a problem that the area of the mounting substrate becomes large.

  The present invention makes it possible to provide a semiconductor device having a mounting structure that can suppress an increase in the area of a mounting substrate even when the number of mounted semiconductor devices increases.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip. In a semiconductor device mounted on a die pad, wire connection between each chip electrode and each chip electrode and a lead terminal for external lead-out, and sealed by a sealing resin, the lead terminal sandwiches the die pad Forming a first lead row and a second lead row composed of a plurality of lead terminals disposed opposite to each other, and the lead terminals of the first lead row include at least a first lead terminal; Providing a second lead terminal and a third lead terminal; and at least a first set and a second set of the first chip and the second chip on the die pad. From the group A plurality of chips are mounted, and the first lead terminal and the second lead terminal are part of chips in a chip electrode formed on the first chip of the first set. The other tip electrode of the first set of first tips connected to the electrode is a portion of the tip electrodes of the tip electrodes formed on the second set of the first set or the first tip of the first set of tips. Connecting to the lead terminals of the second lead array, and connecting another chip electrode of the second chip of the first set to the lead terminals of the second lead array; and the second lead terminal And the third lead terminal is connected to a part of tip electrodes of tip electrodes formed on the first set of the second set, and the second lead terminal is connected to the other set of the first set of the second set. A tip electrode of the second set of tips formed on the second tip of the second set. A second tip of the second set of leads connected to the lead terminals of the second set of leads, and a second tip of the second set of second chips is connected to the lead terminals of the second set of leads; Between the first lead terminal and the second lead terminal, and between the third lead terminal and the second lead terminal, a voltage higher than a voltage applied to each lead terminal of the second lead string The dimension between the lead terminals of the first lead row is set wider than the dimension between the lead terminals of the second lead row so as to be applicable, and at least the leads of the first lead row The sealing resin is filled between the terminals.

  In the invention according to claim 2 of the present application, a first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad. In a semiconductor device in which each chip electrode and each chip electrode and a lead terminal for external lead-out are connected by wire and sealed with a sealing resin, the lead terminals are disposed to face each other across the die pad. Forming a first lead row and a second lead row composed of a plurality of lead terminals, and the lead terminals of the first lead row include at least a first lead terminal and a second lead terminal Having a third lead terminal, the first chip mainly comprising a resistor element, the second chip mainly comprising an operational amplifier, and A plurality of chips consisting of at least a first set and a second set of the first chip and the second chip are mounted on the pad, and the first lead terminal And the second lead terminal is a resistive tip electrode formed on the first chip of the first set of squares, the first lead row side of the first chip of the first set The other resistance chip electrodes respectively connected to the two resistance chip electrodes arranged on one side of the other and arranged on the other side opposite to the one side with respect to the resistance chip electrode are the rectangular first electrodes. Connected to the operational amplifier chip electrode disposed on one side of the first chip side of the first set formed on the second chip of the first set or the lead terminal of the second lead row; The op amp chip electrode is connected to the lead of the second lead string. The second lead terminal and the third lead terminal are resistance chip electrodes formed on the first chip of the second set of the square, which are connected to the terminals; Are connected to two resistive chip electrodes arranged on one side of the first lead row side of the first chip of the pair, and are arranged on another side opposite to the one side with respect to the resistive chip electrodes Another resistive chip electrode being formed is the operational amplifier chip electrode or the op amp chip electrode disposed on one side of the first chip side of the second set formed on the second chip of the second set The other operational amplifier chip electrode is connected to the lead terminal of the second lead array, and the other operational amplifier chip electrode is connected to the lead terminal of the second lead array, and the first lead terminal and the second lead Between the terminals, and the third lead terminal and the second lead terminal Between the two lead terminals, the voltage applied between the respective lead terminals is divided by the resistive element formed on the first chip, and the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip Outputting to one of the inverting input terminals and outputting an output signal subjected to signal processing by the second chip from the lead terminal of the second lead string; and the first lead terminal and the second lead terminal The first to allow application of a voltage higher than a voltage applied to each lead terminal of the second lead row between the third lead terminal and the second lead terminal. The dimension between the lead terminals of the lead row is set wider than the dimension between the lead terminals of the second lead row, and the sealing resin is filled at least between the lead terminals of the first lead row It is characterized in.

  In the invention according to claim 3 of the present application, the first chip having the function of reducing the voltage to be input and the second chip having the function of processing the output signal of the first chip are mounted on the die pad. In a semiconductor device in which each chip electrode and each chip electrode and a lead terminal for external lead-out are connected by wire and sealed with a sealing resin, the lead terminals are disposed to face each other across the die pad. Forming a first lead row and a second lead row composed of a plurality of lead terminals, and the lead terminals of the first lead row include at least a first lead terminal and a second lead terminal A third lead terminal is provided, and the first chip mainly includes a resistor element, and the resistor element includes a first voltage-dividing resistor string and a second voltage-dividing resistor string. , Including feedback resistors And the second chip mainly comprises an operational amplifier, and at least a first set and a second set of the first chip and the second chip on the die pad. A plurality of sets of chips are mounted, and the first lead terminal and the second lead terminal are resistance chip electrodes formed on the first set of first chips in a rectangular shape. A voltage dividing circuit for dividing a voltage applied to one of the two resistive chip electrodes disposed on one side of the first lead row of the first set of first chips; Connected to a first set of voltage divider resistors and to a first set of voltage divider resistors for dividing the voltage applied to the other resistor tip electrodes of the two resistor tip electrodes. On the other side opposite to the one side from the resistive tip electrode A first set of resistor chips serving as a first series connection point for outputting a first divided voltage of the first set of first voltage-dividing resistors among the other resistor chip electrodes disposed. An electrode, and a resistive tip electrode serving as a second series connection point of a first set for outputting a second divided voltage of the second set of voltage-dividing resistors of the first set; The operational amplifier chip electrode disposed on one side of the first chip side of the first set formed on the second chip of the first set, either the inverting input terminal or the non-inverting input terminal of the operational amplifier The operational amplifier chip electrodes respectively connected to the corresponding operational amplifier chip electrodes and disposed on one side of the first set on the side of the first chip formed on the second chip of the first set, Op amp chip electrode as the output terminal of the op amp and the inverting input The feedback resistor is connected between an operational amplifier chip electrode serving as a terminal, and the other operational amplifier chip electrode is connected to the lead terminal of the second lead string, and the first lead terminal and the second lead The voltage applied to the terminal is divided by the first voltage-dividing resistor string of the first set or the second voltage-dividing resistor string of the first set, and formed on the second chip of the first pair Outputting to the inverted input terminal or the non-inverted input terminal of the operational amplifier, and outputting an output signal processed by the second chip of the first set from the lead terminal of the second lead string. And said second lead terminal and said third lead terminal are resistive chip electrodes formed on the first chip of said second set of squares, said first chip of said second set Are disposed on one side of the first lead row side of the Applied to a second set of first voltage divider resistors for dividing the voltage applied to one of the resistive tip electrodes of one of the resistive tip electrodes, and to another resistive tip electrode of the two resistive tip electrodes Among the other resistive tip electrodes which are respectively connected to the second set of second voltage-dividing resistor rows for dividing the voltage and are disposed on another side opposite to the one side from the resistive tip electrode A resistive tip electrode serving as a first series connection point of a second set for outputting a first divided voltage of the first set of voltage-dividing resistors of the second set; and a second set of the second set of second electrodes A second set of second series connection points for outputting a second divided voltage of the voltage-dividing resistor array, and a second set of second chips having a square shape. Of the op amp chip electrodes arranged on one side of the first chip side of the second set, One side of the second set of first chips formed on the first set of second chips, each connected to an operational amplifier chip electrode serving as either an inverting input terminal or a non-inverting input terminal of the second group. The feedback resistor is connected between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal among the operational amplifier chip electrodes disposed on the side, and the other operational amplifier chip electrode is And a voltage applied to the second lead terminal and the third lead terminal connected to the lead terminals of the second lead column, the voltage dividing resistor column of the second set or the second Divided by the second voltage-dividing resistor string of the second set, and output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed on the second chip of the second set; Outputting an output signal subjected to signal processing by the second chip of the second set from the lead terminals of the second lead row, between the first lead terminal and the second lead terminal, and the third lead Between the terminal and the second lead terminal, the voltage applied between the lead terminals is divided by the resistor element formed on the first chip, and the inversion of the operational amplifier formed on the second chip is made. Outputting an output signal subjected to signal processing by the second chip from the lead terminal of the second lead string, and outputting the signal to any one of the input terminal and the non-inversion input terminal; Between the two lead terminals and between the third lead terminal and the second lead terminal, a voltage higher than the voltage applied to each lead terminal of the second lead row can be applied, respectively Said first The dimension between the lead terminals of the second lead row is set wider than the dimension between the lead terminals of the second lead row, and the sealing resin is filled at least between the lead terminals of the first lead row It is characterized by

  According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the second lead row side on the first chip of the first set or on the first chip of the second set is provided. An auxiliary wiring is disposed on the surface, and the other chip electrode and the second chip formed on the first chip of the first set or the second chip of the second set The lead terminals of the lead array are characterized in that they are connected via the respective auxiliary electrodes of the respective sets.

  The invention according to claim 5 is the semiconductor device according to claim 2 or 3, wherein the second chip is formed on the first chip of the first set or on the first chip of the second set. The auxiliary wiring is disposed on the surface of the lead row side, and the other operational amplifier chip electrode and the lead terminal of the second lead row are connected via the respective auxiliary wiring of the pair It is characterized by

  According to a sixth aspect of the present invention, in the semiconductor device according to the first aspect, one of the lead terminals of the second lead row and the first set or the first set of the second set are formed. The chip electrode or any lead terminal of the second lead row and the chip electrode formed on the first set or the second set of the second chip are relays mounted on the die pad It is characterized in that it is connected via a chip.

  The invention according to claim 7 of the present application is the semiconductor device according to any one of claims 2 or 3, wherein any lead terminal of the second lead row and the first chip of the first set or second set of chips are provided. The resistance chip electrode formed on top, or any lead terminal of the second lead row, and the operational amplifier chip electrode formed on the first chip or the second chip of the second set are the die pads It is characterized in that it is connected via a relay chip mounted on top.

  The invention according to claim 8 of the present application is the semiconductor device according to any one of claims 1 to 3, characterized in that a suspension lead of the die pad is disposed in the second lead row.

  The invention according to claim 9 of the present application is the semiconductor device according to any one of claims 1 to 3, characterized in that the back surface side of the die pad is resin-sealed with the sealing resin.

  The invention according to claim 10 of the present application is the semiconductor device according to any one of claims 1 to 3, wherein any lead terminal of the second lead row is provided with an ESD protection element mounted on the die pad. It connects with the said chip electrode, the said resistance chip electrode, or the said operational amplifier chip electrode via the chip | tip.

  According to an eleventh aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the first chip of the first set or the second set and the voltage lower than the voltage input to the first chip A flat dielectric member is disposed between the die pad or the lead terminal of the second lead row connected to an electric potential, and the capacitance and the dielectric of the first chip or the second set of the first chip It is characterized in that the capacity of the body member is connected in series.

  According to a twelfth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, one of a chip electrode and an operational amplifier chip electrode formed on the first chip or the second chip of the second chip. The lead terminal of the second lead row to which the unit is connected is connected to a potential lower than the input voltage, the dielectric member is disposed on the die pad, and the second chip is disposed on the dielectric member The capacitance of the first chip or the second set of the first chip, the capacitance of the dielectric member, and the capacitance of the first set or the second set of the second chips are It is characterized by connecting in series in pairs.

  According to a thirteenth aspect of the present invention, in the semiconductor device according to any one of the eleventh and twelfth aspects, one of a chip electrode or an operational amplifier chip electrode formed on the first chip or the second chip of the second chip. The lead terminal of the second lead row connected by the second part is connected to a potential lower than the input voltage, the dielectric member is disposed on the die pad, and the first set or the first pair is disposed on the dielectric member. The second set of second chips is disposed, and the capacitance of the first set or second set of first chips, the capacitance of the dielectric member, and the first set or second set of It is characterized in that the capacity of 2 chips is connected in series in each set.

  The invention according to claim 14 is the semiconductor device according to any one of claims 11 to 13, wherein the dielectric member is the first chip or the second chip of the first chip or the second chip. It is characterized in that it is an insulating resin layer integrally formed on the back surface of the substrate.

  The invention according to claim 15 is the semiconductor device according to any one of claims 1 to 14, wherein the first chip of the first set and the first chip of the second set are formed by an integral chip. It is characterized by being.

  The invention according to claim 16 is the semiconductor device according to any one of claims 1 to 15, wherein the second lead terminal is connected to a chip electrode of the first chip of the first set, and It is characterized in that it is separated into lead terminals connected to the tip electrodes of the first set of the second set.

  The semiconductor device of the present invention uses the second lead terminal in common, and can be disposed at positions sufficiently separated from the first lead terminal or the third lead terminal, respectively, and two pairs of input terminals are provided. With this structure, the two-input voltage detection circuit can be formed of a semiconductor device with a small mounting area.

  In the semiconductor device according to the present invention, when a high voltage is applied between the first lead terminal and the second lead terminal, the signal reduced by the pressure reducing function of the first chip of the first set is When processing is performed in one set of second chips and a high voltage is applied between the third lead terminal and the second lead terminal, the pressure is reduced by the pressure reduction function of the second set of first chips. And the second set of second chips process the signals so that the two sets of voltage detection circuits can operate at the same time, as in the case where two conventional voltage detection circuits are provided. Processing becomes possible. The semiconductor device of the present invention can be used as a voltage detection circuit of a battery for driving a vehicle, and the effect of reducing the size of a component mounted on a vehicle is large.

  Furthermore, by sealing the back surface side of the die pad with a sealing resin, discharge between the lead terminal and the die pad can be suppressed. The chip electrode and the lead terminal can be wire-connected via the auxiliary wiring, and even if the number of chips mounted on the die pad is increased, the dimension between the wires can be secured, It is also possible to prevent defects such as deformation of the wire due to contact by the wire bonding jig at the time of bonding or occurrence of contact between the wires due to the pressure of the sealing resin injected at the time of resin sealing. Even if the chip electrode and the lead terminal are wire-connected via the relay chip, the dimensions between the wires can be secured, and the wire bonding jig may be in contact during wire bonding to deform the wire, or It is also possible to prevent problems such as contact between wires due to the pressure of the sealing resin injected at the time of resin sealing. By adding the ESD protection element to the relay chip, the electrodes connected to the relay chip can be effectively protected from electrostatic breakdown. These are effects obtained similarly to the effects disclosed in the present application.

  In the semiconductor device according to the present invention, the voltage applied to the first chip is divided by connecting the capacitance of the dielectric member on the flat plate in series to the capacitance of the first chip to which a high voltage is input. Therefore, the breakdown voltage can be further increased.

  In particular, by adopting an insulating resin layer integrally formed on the back surface of the first chip or the second chip as a flat dielectric member, a dielectric member to be a separate member separated from the chip is stacked. Therefore, there is an advantage in that it can be easily formed without the need for assembling.

  The first set and the second set of the first chips do not necessarily have to be separate configurations, and the integrated one-chip structure has an advantage that the process of mounting on the die pad can be simplified.

  The second lead terminal is not only used as a common terminal, but also by using a separated structure, even when there is a slight difference in voltage difference applied between two separated electrodes. The scope of application is broadened.

It is a block diagram of the voltage detection circuit of the 1st Example of this invention. It is explanatory drawing of the connection state when the voltage detection circuit of the 1st Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 2nd Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 3rd Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 4th Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 5th Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 6th Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 7th Example of this invention is mounted in a lead frame. It is explanatory drawing of the connection state when the voltage detection circuit of the 8th Example of this invention is mounted in a lead frame. It is explanatory drawing of a motor drive circuit. It is explanatory drawing of a general voltage detection circuit. It is explanatory drawing of the semiconductor device which this applicant proposed previously.

  The semiconductor device of the present invention is a semiconductor device provided with two sets of input terminals to which a high voltage of about 2000 V can be applied. Therefore, in the present invention, the first chip that depresses (steps down) a high voltage signal that is directly applied and the second chip that processes the signal that has been depressurized (stepped down) via the first chip is one. As a set, it has a multi-chip structure provided with two sets of chips. The lead terminals of the first lead row to which the high voltage is directly applied are spaced apart from one another. In the present invention, in particular, a low voltage is applied by applying a high voltage to the lead terminals at both ends and applying a low voltage to the lead terminals disposed in the central portion of the lead terminals of the first lead row. It is possible to use lead terminals as common terminals or to arrange them in close proximity even when they are separated. Hereinafter, examples of the present invention will be described in detail.

  The first embodiment of the present invention will be described with reference to a voltage detection circuit for detecting a high voltage exceeding 2400 V between one of the two input terminals and a high voltage of 200 V between the other input terminals. Do. FIG. 1 is an explanatory diagram of a voltage detection circuit according to a first embodiment of the present invention. As shown in FIG. 1, the circuit configuration itself of the voltage detection circuit according to the present invention is not significantly different from the circuit configuration of the conventional voltage detection circuit described in FIG. ) And a second chip 20 for processing the reduced (step-down) voltage signal passed through the first chip 10. The present invention is different in that two sets of this voltage detection circuit are provided.

  The voltage detection circuit is configured as follows. The resistors 2a and 2b connected in series are elements for dividing the high voltage on the positive side of the battery. The positive node of the battery is connected to the terminal B1, and the other end is grounded to the vehicle body. The series connection point of the resistor 2 a and the resistor 2 b is connected to the non-inverting input terminal of the operational amplifier 1.

  On the other hand, a resistor 2c and a resistor 2d connected in series are elements for dividing the high voltage on the negative side of the battery. The negative node of the battery is connected to the terminal B2, and the other end is connected to the vehicle body. The series connection point of the resistor 2 c and the resistor 2 d is connected to the inverting input terminal of the operational amplifier 1.

  The resistor 2 e is an element (feedback resistor) for determining the amplification gain of the operational amplifier 1, one end of the resistor 2 e is connected to the inverting input terminal of the operational amplifier 1 and the other end is connected to the output terminal OUT of the operational amplifier 1.

  The first chip 10 in which the resistance element is formed is a semiconductor element (for example, thin film resistor) which can be formed by a general semiconductor device manufacturing method, for example, a thick insulating film (for example, CVD method) on a P-type silicon substrate. The formed oxide film having a thickness of about 6 to 8 μm is formed, and a resistance element is formed on the insulating film. As an example, when the resistance 2a is 12 MΩ, the resistance 2 b is 15 kΩ, the resistance 2 c is 12 MΩ, the resistance 2 d is 20 kΩ, and the resistance 2 e is 60 kΩ, a high voltage of about 2400 V can be reduced (step down).

  Similarly, the second chip 20 forms an operational amplifier on a P-type silicon substrate, for example, by a conventional semiconductor device manufacturing method.

  The resistance value or the like of the resistive element forming the voltage detection circuit may be set in accordance with the detection voltage of each element. For example, when performing voltage detection of each of a battery provided to drive a motor and a battery having a relatively low voltage to drive a control circuit, an optimal circuit design may be performed for each.

  FIG. 2 schematically shows a state in which the voltage detection circuit described in FIG. 1 is mounted on a lead frame, and a first chip 101 made of a resistive element and a second chip 201 made of an operational amplifier are shown. The lead frame is shown mounted with a second set of voltage detection circuits, and a second set of voltage detection circuits configured of a second chip 102 made of a resistive element and a second chip 202 made of an operational amplifier.

  The lead frame includes three lead terminals L1 to L3 (corresponding to a first lead row) on the left side of the drawing, and corresponds to 17 lead terminals L4 to L20 (corresponding to a second lead row) on the right side of the drawing. The leads L1, L3, L4, and L20 are lead terminals disposed at the four corners of the semiconductor device, and are lead terminals having a large area for improving mounting strength. The lead terminals L2 and L12 are lead terminals disposed at the center of the semiconductor device, and are large-area lead terminals in order to prevent warpage of the resin-sealed semiconductor device.

  The lead terminal L1 is connected to the positive electrode side of the battery. The series connection of the resistor 21c and the resistor 21d is such that one end is connected to the lead terminal L1, and the other end is connected from the lead terminal L11 to the ground potential, specifically to the vehicle body. The connection point between the resistor 21 c and the resistor 21 d is connected to the inverting input terminal of the operational amplifier 11 formed in the second chip 201 using the wire 3.

  On the other hand, the lead terminal L2 is connected to the negative electrode side of the battery. In series connection of the resistors 21a and 21b, one end is connected to the lead terminal L2, and the other end is grounded from the lead terminal L11 to the ground potential, specifically to the vehicle body. The series connection point of the resistor 2 a and the resistor 2 b is connected to the non-inverting input terminal of the operational amplifier 11 by the wire 3.

  The output terminal of the operational amplifier 11 formed in the second chip 201 is connected to one end of the resistor 21 e formed in the first chip 101 by the wire 3. The other end of the resistor 21 e is connected to the connection point of the resistor 21 c and the resistor 21 d, and is connected to the inverting input terminal of the operational amplifier 11 using the wire 3, whereby the resistor 21 e becomes a feedback resistor of the operational amplifier 11.

  The power supply terminal of the operational amplifier 11 is formed in the second chip 201, the power supply V + is connected to the lead terminal L6, the power supply V− is connected to the lead terminal L10, and the power supply voltage is supplied from each lead terminal.

  Although the output terminal of the operational amplifier 11 can be directly connected to the lead terminal L5 serving as the output terminal by the wire 3, in order to avoid contact with the wire 3 connecting the power supply V + of the operational amplifier 11 and the lead terminal L6, the first It can also be connected to the lead terminal L5 by the wire 3 via the auxiliary electrode 4 separately formed on the chip 101.

  The lead terminals L1 and L2 to which the high voltage is applied are spaced apart by a predetermined dimension according to the voltage applied to each lead terminal in order to secure a predetermined creepage distance. In this embodiment, as shown in FIG. 2, since the voltage applied to the first lead row is larger than the voltage applied to the second lead row, the dimension between the lead terminals of the first lead row is the first It is wider than the dimension between the lead terminals of the two lead rows.

  Similarly, the lead terminal L3 is connected to the positive electrode side of another battery. The series connection of the resistors 22a and 22b connects one end to the lead terminal L3 and the other end to the ground potential from the lead terminal L19, specifically to the vehicle body. The connection point between the resistors 22 a and 22 b is connected to the non-inverted input terminal of the operational amplifier 12 formed in the second chip 202 by the wire 3.

  On the other hand, the lead terminal L2 is connected to the negative electrode side of another battery. In the series connection of the resistors 22c and 22d, one end is connected to the lead terminal L2, and the other end is connected from the lead terminal 19 to the ground potential, specifically to the vehicle body. The series connection point of the resistor 22 c and the resistor 22 d is connected to the non-determination input terminal of the operational amplifier 12 by a wire.

  The output terminal of the operational amplifier 12 formed in the second chip 202 is connected to one end of the resistor 22 e formed in the first chip 102 by the wire 3. The other end of the resistor 22e is connected to a connection point between the resistor 22c and the resistor 22d, and is connected to the inverting input terminal of the operational amplifier 12 using the wire 3. The resistor 22e becomes a feedback resistor of the operational amplifier 12.

  The power supply terminal of the operational amplifier 12 is formed in the second chip 202, the power supply V + is connected to the lead terminal L14, the power supply V− is connected to the lead terminal L18, and the power supply voltage is supplied from each lead terminal.

  Although the output terminal of the operational amplifier 12 can be directly connected to the lead terminal L13 serving as the output terminal by the wire 3, the first to prevent contact between the power supply V + of the operational amplifier 12 and the wire 3 connecting the lead terminal L14. It can also be connected to the lead terminal L13 by the wire 3 via the auxiliary electrode 4 separately formed on the chip 102.

  The lead terminals L3 and L2 to which the high voltage is applied are spaced apart by a predetermined dimension according to the voltage applied to each lead terminal in order to secure a predetermined creepage distance. In this embodiment, as shown in FIG. 2, since the voltage applied to the first lead row is larger than the voltage applied to the second lead row, the dimension between the lead terminals of the first lead row is the first It is wider than the dimension between the lead terminals of the two lead rows.

  As described above, according to the present embodiment, by using the lead terminal L2 as the common terminal, two sets of voltage detection circuits can be configured by one semiconductor device. Although the area of the semiconductor device configured in this manner is larger than that of the conventional semiconductor device previously proposed by the present applicant, the area is smaller compared to the case where two conventional semiconductor devices are combined. It is possible to

  Also in the semiconductor device of this embodiment, a resin layer R equivalent to the thickness of the lead terminal is formed between the lead terminals exposed to the outside from the semiconductor device to be resin-sealed to prevent discharge between the lead terminals. doing. When a higher voltage is applied, it is preferable that the die pad 5 on which the chip is mounted is not exposed from the semiconductor device body.

  In FIG. 2, the lead terminals L4, L7 to L9, L12, L15 to L17, and L20 are not connected, but may be used to realize connection without using the auxiliary electrode 4 or the like. There is no problem as a structure in which some of the unused lead terminals are not formed in advance.

  A second embodiment will now be described. In the first embodiment described above, the chip electrodes formed on the first chips 101 and 102 and the lead terminals L5, L11, L13 and L19 of the second lead row are directly connected by the wire 3 respectively. Although an example has been described, when the length of the wire 3 is increased, pressure may be applied to the wire 3 at the time of resin sealing, and a defect such as contact with another wire 3 may occur. Therefore, in the present embodiment, as shown in FIG. 3, the chip electrodes formed on the first chips 101 and 102 via the relay chip 300 and the lead terminals L5, L11, L13 and L19 of the second lead row Differs in that they are connected.

  The relay chip 300 can have a structure in which the auxiliary wiring 4 similar to the auxiliary wiring 4 formed on the first chips 101 and 102 is formed as shown in FIG. Specifically, the auxiliary wiring 4 and chip electrodes for connection may be formed on the surface of the relay chip 300 at both ends thereof. When the auxiliary wiring 4 is provided, the length of the wire 3 is shortened, and the connection points of the wires connected to the first chips 101 and 102 and the connection points of the wires connected to the lead terminals L5, L11, L13 and L19 are free. Has the advantage of being able to In addition, by appropriately selecting the mounting position of the relay chip 300, the wire bonding jig contacts at the time of wire bonding and the wires are deformed, or the pressure between the wires is contacted by the pressure of the sealing resin injected at the time of resin sealing. Can be prevented from occurring. The shape of the relay chip 300 is not limited to the shape as described in FIG. 3, and only the electrode for relaying the wire 3 may be provided. In addition, when using a plurality of relay chips 300 as shown in FIG. 3, it is also possible to form the relay chips with different shapes. Furthermore, some of the connections may be configured to be directly wired from the first chips 101, 102 to the lead terminals of the second lead row.

  A third embodiment will now be described. The relay chip 300 is not limited to the case of being used for connection between the first chips 101 and 102 and the lead terminals of the second lead row. For example, as shown in FIG. 4, as in the second embodiment, the first chips 101 and 102 are connected to the lead terminals L5, L11, L13 and L19 of the second lead row via the relay chip 300. In addition to the above, it is also possible to connect between the second chips 201, 202 and the lead terminals L10, L18 of the second lead row. FIG. 4 shows the case where the arrangement of the power supply V− of the second chip 201, 202 differs from the example described in the first and second embodiments, and the power supply of the second chip 201, 201 ( V−) and the lead terminals L10 and L18 are connected via the relay chip 300.

  The shape of the relay chip 300 can be variously changed, and it is possible to use another relay chip 300 instead of forming a plurality of auxiliary wires 4 in one relay chip 300 as shown in FIG. 4. The mounting position of the relay chip 300 and mixed mounting of the connection via the relay chip 300 and the connection not via the relay chip 300 can be appropriately set, and the same effect as that of the second embodiment can be obtained.

  A fourth embodiment will now be described. In the semiconductor device of the present invention, as in a general semiconductor device, an internal circuit is broken when a surge voltage such as static electricity is applied. Therefore, it is preferable to provide an ESD protection element. By the way, it is easy to form an ESD protection element on the second chips 201 and 202 simultaneously with the formation of the operational amplifier circuit on the second chips 201 and 202. However, since a high voltage is applied to the first chips 101 and 102, it is necessary to maintain sufficient insulation around the wiring, and an insulating film thicker than a normal semiconductor device is formed. Specifically, while the oxide film formed on the surface is about 0.7 μm in a general semiconductor device, a thick oxide of 5 μm or more is formed in the semiconductor device of the present invention to apply a high voltage exceeding 1000 V. It is necessary to form a film. Therefore, when the ESD protection element is formed on the semiconductor substrate below the oxide film, the connection with the ESD protection element needs to be formed by removing the thick oxide film.

  Therefore, in the present embodiment, the ESD protection element 6 is formed on the relay chip 300. Since the relay chip 300 can be formed by a general semiconductor device manufacturing process, the oxide film formed on the surface does not have to be thick, and is suitable for forming the ESD protection element 6.

  In the voltage detection circuit having the structure shown in FIG. 5, when a surge voltage is applied to the lead terminals L11 and L19 of the second lead row, the resistance elements of the first chips 101 and 102 are destroyed. By providing the ESD protection element 6 as shown in the diagram, it is possible to prevent the breakdown of the resistance element.

  The ESD protection element 6 can be added also in the first and second embodiments.

  A fifth embodiment will now be described. In the first to fourth embodiments described above, the first chips 101 and 102 and the second chips 201 and 202 are disposed to be directly adhered on the die pad 5 respectively. In the present embodiment, in order to increase the withstand voltage, the flat plate-like dielectric member 7 is mainly laminated under one or both of the first chips 101 and 102. The dielectric member 7 may be, for example, a flat substrate made of ceramics having a thickness of about 200 μm. 6, between one of the lead terminals L1 and L2 of the semiconductor device shown in FIG. 2 and one of the lead terminals L6 and L10 or between one of the lead terminals L2 and L3 and one of the lead terminals L14 and L18. The cross section which passes through is shown typically. Here, the lead terminals L1, L2 and L3 are lead terminals to which a high voltage is applied, and the lead terminals L6, 10, L14 and L18 are connected to a potential lower than the voltage input to the lead terminals L1, L2 and L3. It corresponds to a lead terminal.

  As shown in FIG. 6, a capacitance Cc1 of the first chip 101 or the like, a capacitance Cs of the dielectric member 7, a capacitance Cc2 of the second chip 102 or the like are provided between the lead terminal L1 or the like and the lead terminal L6 or the like. It is configured to be connected in series. Here, the capacitances of the first chips 101 and 102 are capacitances formed by electrode pads of resistive elements formed on an insulating film (such as an oxide film) on a semiconductor substrate, a resistance pattern, and the like. The capacitances of the second chips 201 and 202 are also the same, and are capacitances formed by electrode pads of an operational amplifier formed on a semiconductor substrate, impurity regions, and the like. The capacitance Cs of the dielectric member 7 has a capacitance value determined by the thickness and size of the flat substrate and the dielectric constant specific to the material. When the size of the first chips 101 and 102 is 3.0 mm × 1.5 mm, the size of the flat dielectric member 7 needs to be about 3.7 mm × 2.0 mm, and the dielectric constant 9. 8. When the thickness is 200 μm, the capacitance value Cs of the dielectric member 7 is larger than the capacitance value Cc1 of the first chip 101 or the like, and the capacitance value Cc2 of the second chip 201 or the like, and the capacitance voltage division effect is obtained. The capacitance value can be set to a certain degree.

  As a result, when a high voltage is applied to the first chips 101 and 102, the voltage applied to the capacitances of the first chips 101 and 102 is reduced by voltage division, and a high breakdown voltage of the semiconductor device can be realized. It becomes.

  The high withstand voltage of this embodiment is realized not only by the addition of the flat dielectric member 7 but by the combination with a unique mounting structure proposed by the applicant of the present application. doing.

  A sixth embodiment will now be described. 7, between one of the lead terminals L1 and L2 of the semiconductor device shown in FIG. 2 and one of the lead terminals L6 and L10 or between one of the lead terminals L2 and L3 and one of the lead terminals L14 and L18. The cross section which passes through is shown typically. As compared with the fifth embodiment, the position of the dielectric member 7 is different.

  As shown in FIG. 7, a capacitance Cc1 of the first chip 101 or the like, a capacitance Cs of the dielectric member 7, a capacitance Cc2 of the second chip 201 or the like are provided between the lead terminal L1 or the like and the lead terminal L6 or the like. It is configured to be connected in series. In this case, the thickness of the first chips 101 and 102 is 400 μm, and the thickness of the second chips 201 and 202 is 200 μm. With this configuration, the capacitance value Cs of the dielectric member 7 is larger than the capacitance value Cc1 of the first chip 101 or the like and the capacitance value Cc2 of the second chip 201 or the like, and a capacitance division effect can be obtained. The capacitance value of can be set.

  As a result, when a high voltage is applied to the first chips 101 and 102, the voltage applied to the capacitances of the first chips 101 and 102 is reduced by voltage division, and a high breakdown voltage of the semiconductor device can be realized. It becomes.

  Also in the present embodiment, the high withstand voltage is not realized only by the addition of the flat dielectric member 7, but is realized by the combination with a unique mounting structure proposed by the applicant of the present application. .

  A seventh embodiment will now be described. In the fifth and sixth embodiments, the case where the die pad 5 is in the floating state and is set to the ground potential through the second chips 201 and 202 has been described. However, the arrangement of the lead terminals in the first and second embodiments has a structure in which the suspension lead terminals L4, L12 and L20 of the die pad 5 extend to the second lead row side, and the die pad 5 is grounded Even when connected to the potential, it is possible to maintain a sufficient creeping distance.

  In FIG. 8, between one of the lead terminals L1 and L2 of the semiconductor device shown in FIG. 2 and one of the lead terminals L4 and L12 or between one of the lead terminals L2 and L3 and one of the lead terminals L12 and L20. The cross section which passes through is shown typically.

  As shown in FIG. 8, the capacitance Cc1 of the first chip 101 or the like and the capacitance Cs of the dielectric member 7 are connected in series between the lead terminal L1 or the like and the lead terminal L4 or the like. With this configuration, as described above, when a high voltage is applied to the first chip 101 or the like, the voltage applied to the capacitance of the first chip 101 or the like is reduced by voltage division, and the breakdown voltage of the semiconductor device is increased. It is possible to realize

  Also in the present embodiment, the increase in withstand voltage is realized not only by the addition of the flat dielectric member 7 but by a combination with a unique mounting structure proposed by the applicant of the present application.

  An eighth embodiment will now be described. In the description of the above embodiment, the case where the flat dielectric member 7 made of ceramics is disposed under the first chip 101 or the like or the second chip 201 or the like has been described. Since the dielectric member 7 is a member separated from the first chip 101 or the like or the second chip 201 or the like, the dielectric member 7 is formed on the die pad 5 when the semiconductor device of the present invention is formed. After bonding and fixing, it is necessary to bond and fix the first chip 101 or the like or the second chip 201 or the like on the dielectric member 7.

  Therefore, instead of the dielectric member made of ceramics, an insulating resin layer is integrally formed on the back surface of the first chip 101 etc. or the second chip 201 etc., and this resin layer is a flat dielectric It is also possible to use it as a member. FIG. 9 is a cross-sectional view of the semiconductor device of the eighth embodiment, and shows the case where the resin layer 8 is integrally formed on the first chips 101 and 102 in the fifth embodiment described above. Furthermore, in the sixth or seventh embodiment, there is no problem if the resin layer 8 is integrally molded on the first chip 101 or the second chip 201 or the like.

  In a semiconductor device in which a resin layer is integrally formed, a resistor element or an operational amplifier is formed on a semiconductor substrate, and then a resin having a uniform thickness is formed on the back surface side of the semiconductor substrate (after thinning the back surface if necessary). It can be formed by coating or printing, and cutting and singulating the semiconductor substrate and the resin layer.

  The resin layer used here can be, for example, an epoxy resin generally used as a sealing resin for semiconductor devices. When a resin is used, the dielectric constant of the resin is lower than that of the ceramic, and the resin can be formed thin. As a result, the height of the semiconductor device can be reduced, and the effect is large.

  Although the case where the dielectric member 7 and the resin layer 8 are laminated on only one of the first chip 101 and the like and the second chip 201 and the like has been described, if necessary, the first chip 101 and the like may be used. There is no problem even if it is properly changed such as laminating on both the first chip 102 or the like and only the first set or the second set.

  For the dielectric member 7, a material having a desired dielectric constant may be appropriately selected. Specifically, in addition to ceramics, sapphire, paper, polyimide, etc. may be selected as appropriate.

  Generally, the description of the insulating adhesive member used when mounting the first chip 101 and the like, the second chip 201 and the like, the dielectric member 7 or the resin layer 8 on the die pad 5 has been omitted. It is needless to say that the capacitance value of the dielectric member 7 or the like is set in consideration of the capacitance value of the capacitance formed by the members.

  Although the embodiments of the present invention have been described above, it goes without saying that the present invention is not limited to the above embodiments. For example, the first and second sets of first chips may be integrated as one chip, or the second lead terminal may be separated into two lead terminals, and a large potential difference may occur between the separated lead terminals. If the configuration is not added, the same effect as the above embodiment can be obtained.

  1, 11 and 12: op amp 2, 21 and 22: resistance, 3: wire, 4: auxiliary electrode, 5: die pad, 6: ESD protection element, 7: dielectric member, 8: resin layer, 100: motor drive Device, 200: Voltage detection circuit, 300: Relay chip

Claims (16)

A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, and between each chip electrode and each chip electrode In a semiconductor device in which a lead and a lead terminal for external lead-out are connected by wire and sealed by a sealing resin,
The lead terminals constitute a first lead row and a second lead row composed of a plurality of lead terminals disposed to face each other with the die pad interposed therebetween;
The lead terminals of the first lead row include at least a first lead terminal, a second lead terminal, and a third lead terminal.
A plurality of chips consisting of at least a first set and a second set of the first chip and the second chip are mounted on the die pad.
The first lead terminal and the second lead terminal are connected to a part of tip electrodes of tip electrodes formed on the first tip of the first set, and the first set of Another chip electrode of the first chip is connected to a part of the chip electrodes in the chip electrodes formed on the second chip of the first set or the lead terminals of the second lead row, Connecting another chip electrode of the first set of second chips to a lead terminal of the second lead row;
The second lead terminal and the third lead terminal are connected to a part of tip electrodes of tip electrodes formed on the first set of the second set, and the second set of Another chip electrode of the first chip is connected to a part of the chip electrodes in the chip electrodes formed on the second chip of the second set or the lead terminals of the second lead row, Connecting another chip electrode of the second set of second chips to a lead terminal of the second lead row;
The voltage applied to each lead terminal of the second lead row is higher than between the first lead terminal and the second lead terminal and between the third lead terminal and the second lead terminal. The dimension between the lead terminals of the first lead row is set wider than the dimension between the lead terminals of the second lead row so that a voltage can be applied;
The semiconductor device characterized in that the sealing resin is filled at least between the lead terminals of the first lead row. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, and between each chip electrode and each chip electrode In a semiconductor device in which a lead and a lead terminal for external lead-out are connected by wire and sealed by a sealing resin,
The lead terminals constitute a first lead row and a second lead row composed of a plurality of lead terminals disposed to face each other with the die pad interposed therebetween;
The lead terminals of the first lead row include at least a first lead terminal, a second lead terminal, and a third lead terminal.
The first chip mainly comprises a resistive element;
The second chip mainly comprises an operational amplifier;
A plurality of chips consisting of at least a first set and a second set of the first chip and the second chip are mounted on the die pad.
The first lead terminal and the second lead terminal are resistive chip electrodes formed on the first chip of the first set of rectangles, and the first chip of the first set Another resistor chip electrode is connected to each of the two resistor chip electrodes disposed on one side of the first lead row, and another resistor chip electrode disposed on another side opposite to the one side with respect to the resistor chip electrode An operational amplifier chip electrode disposed on one side of the first set of first chips formed on the first set of second chips, or a lead terminal of the second lead row; Another op amp chip electrode connected to the lead terminal of the second lead string;
The second lead terminal and the third lead terminal are resistive chip electrodes formed on the first chip of the second set of squares, and the second chip of the first chip of the second set Another resistor chip electrode is connected to each of the two resistor chip electrodes disposed on one side of the first lead row, and another resistor chip electrode disposed on another side opposite to the one side with respect to the resistor chip electrode An operational amplifier chip electrode disposed on one side of the first chip side of the second set formed on the second chip of the second set, or a lead terminal of the second lead row Another op amp chip electrode connected to the lead terminal of the second lead string;
A voltage applied between each lead terminal is formed in the first chip between the first lead terminal and the second lead terminal, and between the third lead terminal and the second lead terminal. Divided by the resistance element, and output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed in the second chip, and the output signal subjected to the signal processing in the second chip is the second Output from the lead terminals of the
The voltage applied to each lead terminal of the second lead row is higher than between the first lead terminal and the second lead terminal and between the third lead terminal and the second lead terminal. The dimension between the lead terminals of the first lead row is set wider than the dimension between the lead terminals of the second lead row so that a voltage can be applied;
The semiconductor device characterized in that the sealing resin is filled at least between the lead terminals of the first lead row. A first chip having a function of reducing an input voltage and a second chip having a function of processing an output signal of the first chip are mounted on a die pad, and between each chip electrode and each chip electrode In a semiconductor device in which a lead and a lead terminal for external lead-out are connected by wire and sealed by a sealing resin,
The lead terminals constitute a first lead row and a second lead row composed of a plurality of lead terminals disposed to face each other with the die pad interposed therebetween;
The lead terminals of the first lead row include at least a first lead terminal, a second lead terminal, and a third lead terminal.
The first chip mainly includes a resistive element, and the resistive element includes a first voltage-dividing resistor string, a second voltage-dividing resistor string, and a feedback resistor.
The second chip mainly comprises an operational amplifier;
A plurality of chips consisting of at least a first set and a second set of the first chip and the second chip are mounted on the die pad.
The first lead terminal and the second lead terminal are resistive chip electrodes formed on the first chip of the first set of rectangles, and the first chip of the first set A first set of first voltage-dividing resistor rows for dividing a voltage applied to one of the resistor tip electrodes of the two resistor tip electrodes disposed on one side of the first lead row side; The other of the resistor chip electrodes is connected to the first pair of second voltage-dividing resistor rows for dividing the voltage applied to the other resistor chip electrodes of the two resistor chip electrodes, and is opposed to the one side from the resistor chip electrodes Of the first set of first series connection points for outputting a first divided voltage of the first set of first voltage-dividing resistor rows among other resistor tip electrodes arranged on one side of Outputting a second divided voltage of the first set of second voltage-dividing resistor strings, and A resistive tip electrode to be a second series connection point of a set is disposed on one side of the first set on the side of the first set of chips formed on the second set of the first set of rectangular shapes Of the first set of the second chips, each of which is connected to an operational amplifier chip electrode serving as either an inverting input terminal or a non-inverting input terminal of the operational amplifier among the operational amplifier chip electrodes. The feedback resistor is connected between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal among the operational amplifier chip electrodes disposed on one side of the first chip side of the set Another op amp chip electrode is connected to a lead terminal of the second lead string, and a voltage applied to the first lead terminal and the second lead terminal is set to the first set Inversion input terminal or non-inversion input terminal of the operational amplifier formed on the first chip of the first set by dividing by the first voltage dividing resistance array or the second set of voltage dividing resistances of the first set Outputting the signal output from any of the first set of second chips from the lead terminal of the second lead string;
The second lead terminal and the third lead terminal are resistive chip electrodes formed on the first chip of the second set of squares, and the second chip of the first chip of the second set A second set of first voltage-dividing resistor rows for dividing a voltage applied to one of the resistor tip electrodes of the two resistor tip electrodes disposed on one side of the first lead row side; Another one is connected to the second set of second voltage-dividing resistance rows for dividing the voltage applied to the other resistance tip electrodes of the two resistance tip electrodes, and is opposed to the one side with respect to the resistance tip electrodes Of the second set of first series connection points for outputting the first divided voltage of the first set of voltage-dividing resistors of the second set among the other resistor tip electrodes arranged on one side of And a second divided voltage output of the second set of second voltage-dividing resistor strings. A resistive tip electrode to be a second series connection point of a set is disposed on one side of a side of the first set of the second set formed on the second set of the second set of square chips. Of the second operational amplifier chip electrodes respectively connected to the operational amplifier chip electrodes serving as either the inverting input terminal or the non-inverting input terminal of the operational amplifier among the operational amplifier chip electrodes; The feedback resistor is connected between the operational amplifier chip electrode serving as the output terminal of the operational amplifier and the operational amplifier chip electrode serving as the inverting input terminal among the operational amplifier chip electrodes disposed on one side of the first chip side of the set Another op amp chip electrode is connected to the lead terminal of the second lead string, and the voltage applied to the second lead terminal and the third lead terminal is the second set Inversion input terminal or non-inversion input terminal of the operational amplifier formed on the second chip of the second set by dividing by the first voltage dividing resistance array or the second set of voltage dividing resistors of the second set Outputting an output signal that has been signal processed by the second chip of the second set from the lead terminal of the second lead string;
A voltage applied between each lead terminal is formed in the first chip between the first lead terminal and the second lead terminal, and between the third lead terminal and the second lead terminal. Divided by the resistance element, and output to either the inverting input terminal or the non-inverting input terminal of the operational amplifier formed in the second chip, and the output signal subjected to the signal processing in the second chip is the second Output from the lead terminals of the
The voltage applied to each lead terminal of the second lead row is higher than between the first lead terminal and the second lead terminal and between the third lead terminal and the second lead terminal. The dimension between the lead terminals of the first lead row is set wider than the dimension between the lead terminals of the second lead row so that a voltage can be applied;
The semiconductor device characterized in that the sealing resin is filled at least between the lead terminals of the first lead row. In the semiconductor device according to claim 1,
An auxiliary wiring is disposed on the surface of the second lead row side on the first chip of the first set or on the first chip of the second set;
The other chip electrodes formed on the first set of second chips or the second set of second chips and the lead terminals of the second lead row are connected to the respective sets of the auxiliary electrodes. A semiconductor device characterized in that it is connected via an electrode. The semiconductor device according to claim 2 or 3
An auxiliary wiring is disposed on the surface of the second lead row side on the first chip of the first set or on the first chip of the second set;
A semiconductor device characterized in that the other operational amplifier chip electrode and the lead terminal of the second lead row are connected via the auxiliary wiring of each set. In the semiconductor device according to claim 1,
Any lead terminal of the second lead row and a chip electrode formed on the first chip of the first set or second set, or any lead terminal of the second lead row, A semiconductor device characterized in that a chip electrode formed on the first chip or the second chip of the first set or the second set is connected via a relay chip mounted on the die pad. The semiconductor device according to claim 2 or 3
Any lead terminal of the second lead row and a resistive tip electrode formed on the first chip of the first set or the second set, or any lead terminal of the second lead row; A semiconductor device characterized in that an operational amplifier chip electrode formed on the first chip or the second chip of the second set is connected via a relay chip mounted on the die pad. .   The semiconductor device according to any one of claims 1 to 3, wherein a suspension lead of the die pad is disposed in the second lead row.   The semiconductor device according to any one of claims 1 to 3, wherein a back surface side of the die pad is resin-sealed by the sealing resin.   The semiconductor device according to any one of claims 1 to 3, wherein one of the lead terminals of the second lead row is connected to the chip electrode via a relay chip including an ESD protection element mounted on the die pad. A semiconductor device characterized in that it is connected to the resistive chip electrode or the operational amplifier chip electrode.   The semiconductor device according to any one of claims 1 to 3, wherein the first chip or the second set of the first chip and the die pad connected to a potential lower than a voltage input to the first chip or the second chip The flat dielectric member is disposed between the lead terminals of the first and second lead rows, and the capacitance of the first chip or the first chip of the second set and the capacitance of the dielectric member are connected in series. A semiconductor device characterized by   The semiconductor device according to any one of claims 1 to 3, wherein the chip electrode formed on the first chip or the second chip of the second set or the second lead to which a part of the operational amplifier chip electrode is connected. Connecting the lead terminals of the column to a potential lower than the input voltage, disposing the dielectric member on the die pad, disposing the second chip on the dielectric member, and The capacitance of the second chip of the first chip, the capacitance of the dielectric member, and the capacitance of the first chip or the second chip of the second pair are connected in series in each pair. Semiconductor device.   13. The semiconductor device according to claim 11, wherein a chip electrode formed on the first chip or the second chip of the second set or a part of the op amp chip electrode is connected to the second lead. The lead terminals of the column are connected to a potential lower than the input voltage, the dielectric member is disposed on the die pad, and the first set or the second set of second chips is placed on the dielectric member. Arranging the capacitance of the first chip or the second set of the first chip, the capacitance of the dielectric member, and the capacitance of the first set or the second set of the second chip, respectively The semiconductor device characterized by connecting in series by group of.   The semiconductor device according to any one of claims 11 to 13, wherein the dielectric member is integrally formed on a back surface of the first chip or the second chip of the first set or the second set. A semiconductor device characterized in that it is a resin layer.   15. The semiconductor device according to claim 1, wherein the first chip of the first set and the first chip of the second set are formed as an integral chip. apparatus.   The semiconductor device according to any one of claims 1 to 15, wherein the second lead terminal is connected to the chip electrode of the first chip of the first set and the first chip of the second set. And a lead terminal connected to the tip electrode of the semiconductor device.

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