JP2019091941A - Semiconductor device, inverter circuit, drive device, vehicle, and elevator - Google Patents

Abstract

To provide a semiconductor device which realizes a high threshold.SOLUTION: A semiconductor device according to the present invention includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode, and the gate insulating layer includes at least one element in the group of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), and C (carbon).SELECTED DRAWING: Figure 9

Description

  Embodiments of the present invention relate to a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator.

  SiC (silicon carbide) is expected as a material for the next generation of semiconductor devices. SiC has physical properties superior to that of Si (silicon) in that the band gap is 3 times, the breakdown electric field strength is about 10 times, and the thermal conductivity is about 3 times. By utilizing this characteristic, a semiconductor device capable of low loss and high temperature operation can be realized.

  However, for example, in the case of forming a MISFET (Meatl Insulator Semiconductor Field Effect Transistor) using SiC, the density of interface states existing between the semiconductor and the gate insulating layer is larger than that of Si. For this reason, there is a problem that the mobility of charge decreases and the on-resistance of the MISFET becomes high.

  In order to solve the above problems, for example, there is a method of introducing an element such as N (nitrogen) or phosphorus (P) for terminating the interface state at the interface between SiC and the insulating film. When this method is used, N (nitrogen) or phosphorus (P) acts as an n-type dopant, which may lower the threshold of the n-channel type MISFET.

  In order to prevent the malfunction of the SiC MOSFET, a threshold of at least 3 V or more is required at the operating temperature (for example, 200 ° C.), and 5 V or more is desirable. Under such circumstances, at the end of nitrogen and phosphorus, the current situation is that it drops to about 1 V.

JP 2011-228429 A

  The problem to be solved by the present invention is to provide a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator capable of realizing a high threshold.

  The semiconductor device according to the embodiment includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode, and the gate insulating layer is made of germanium (Ge), B ( (Boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y ( At least one element of the group consisting of yttrium), La (lanthanum), lanthanides (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), and C (carbon) )including.

FIG. 1 is a schematic cross-sectional view showing a semiconductor device of a first embodiment. The figure which shows the crystal structure of the SiC semiconductor of 1st Embodiment. The enlarged view of the SiC layer of 1st Embodiment, a gate insulating layer, and a gate electrode part. Explanatory drawing of the effect | action of 1st Embodiment, and an effect. The enlarged view of the SiC layer of a 2nd embodiment, a gate insulating layer, and a gate electrode part. The enlarged view of the SiC layer of 3rd Embodiment, a gate insulating layer, and a gate electrode part. The enlarged view of the SiC layer of 4th Embodiment, a gate insulating layer, and a gate electrode part. Explanatory drawing of the effect | action and effect of 4th Embodiment. FIG. 13 is a schematic cross-sectional view showing a semiconductor device of a fifth embodiment. The schematic diagram of the drive device of 6th Embodiment. The schematic diagram of the vehicle of 7th Embodiment. The schematic diagram of the vehicle of 8th Embodiment. The schematic diagram of the elevator of 9th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals are given to the same members and the like, and the description of the members and the like which have been described once is omitted as appropriate.

Moreover, in the following description, the notation of n ⁺ , n, n ⁻ and p ⁺ , p, p ⁻ indicates the relative level of the impurity concentration in each conductivity type. That is, n ⁺ indicates that the n-type impurity concentration is relatively higher than n, and n ⁻ indicates that the n-type impurity concentration is relatively lower than n. Also, p ⁺ indicates that the p-type impurity concentration is relatively higher than p, and p ⁻ indicates that the p-type impurity concentration is relatively lower than p. The n ⁺ type and n ⁻ type may be simply described as n type, p ⁺ type and p ⁻ type simply as p type.

First Embodiment
The semiconductor device according to the present embodiment is provided between a p-type SiC layer having a first surface, a gate electrode, and a first surface of the SiC layer and the gate electrode, and N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and a second layer having an oxygen density higher than that of the first layer and the first layer and the second layer. And a first region containing at least one first element selected from the group of Bi (bismuth) and having a first peak of the concentration of the first element.

  FIG. 1 is a schematic cross-sectional view showing a configuration of a MISFET which is a semiconductor device of the present embodiment. The MISFET 100 is a double implantation MOSFET (DIMOSFET) in which ap well and a source region are formed by ion implantation. Also, the MISFET 100 is an n-channel MOSFET having electrons as carriers.

The MISFET 100 includes an n ⁺ -type SiC substrate 12. In the present specification, the upper surface in FIG. 1 is referred to as the front surface and the lower surface is referred to as the rear surface with respect to the surface of the SiC substrate 12 and the like.

The SiC substrate 12 is, for example, a 4H-SiC SiC substrate having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, for example, N (nitrogen) as an n-type impurity.

  FIG. 2 is a view showing a crystal structure of a SiC semiconductor. A typical crystal structure of a SiC semiconductor is a hexagonal system such as 4H-SiC. One of the faces (top face of the hexagonal prism) having the c axis along the axial direction of the hexagonal prism as a normal is the (0001) plane. A plane equivalent to the (0001) plane is referred to as a silicon plane and is described as a {0001} plane. Si (silicon) is arranged on the silicon surface.

  The other of the plane (top face of the hexagonal column) having the c-axis along the axial direction of the hexagonal column as the normal is the (000-1) plane. A plane equivalent to the (000-1) plane is referred to as a carbon plane and is referred to as a {000-1} plane. C (carbon) is arranged in the carbon surface.

  On the other hand, the side surface (pillar surface) of the hexagonal column is an m-plane which is a plane equivalent to the (1-100) plane, that is, a {1-100} plane. Further, a plane passing through a pair of ridge lines which are not adjacent to each other is an a-plane equivalent to the (11-20) plane, that is, a {11-20} plane. In m-plane and a-plane, both Si (silicon) and C (carbon) are arranged.

  Hereinafter, the case where the surface of the SiC substrate 12 is a surface inclined at 0 degrees to 8 degrees with respect to the silicon surface and the back surface is a surface inclined at 0 degrees to 8 degrees with respect to the carbon surface will be described as an example.

On the surface of the SiC substrate 12, for example, an n ^-- type drift layer 14 having an impurity concentration of n-type impurity of 5 × 10 ¹⁵ or more and 2 × 10 ¹⁶ cm ^-3 or less is formed. The drift layer 14 is, for example, an epitaxial growth layer of SiC formed by epitaxial growth on the SiC substrate 12.

  The surface of the drift layer 14 is also a surface inclined at 0 degrees or more and 8 degrees or less with respect to the silicon surface. The film thickness of the drift layer 14 is, for example, 5 μm or more and 100 μm or less.

A p-type p well region (SiC layer) 16 having an impurity concentration of 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less, for example, is formed on a partial surface of the drift layer 14. There is. The depth of the p well region 16 is, for example, about 0.6 μm. The p well region 16 functions as a channel region of the MISFET 100.

  The surface (first surface) of the p well region (SiC layer) 16 is also a surface inclined at 0 degrees to 8 degrees with respect to the silicon surface.

Some surface of the p-well region 16, an impurity concentration of the n-type impurity 1 × ¹⁰ 18 ^{cm -3} or more 1 × ¹⁰ 22 ^{cm -3 cm} -3 or less of ^{n +} -type source region 18 is formed . The depth of the source region 18 is shallower than the depth of the p well region 16 and is, for example, about 0.3 μm.

In addition, a p ⁺ -type p ⁺ -type impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less on the side surface of the source region 18 on a part of the surface of the p-well region 16. P well contact region 20 is formed. The depth of the p well contact region 20 is shallower than the depth of the p well region 16 and is, for example, about 0.3 μm.

  A gate insulating layer 28 is formed continuously on the surfaces of the drift layer 14 and the p well region (SiC layer) 16 so as to straddle these layers and regions.

  The gate electrode 30 is formed on the gate insulating layer 28. For the gate electrode 30, for example, doped polysilicon or the like is applicable. An interlayer insulating film 32 formed of, for example, a silicon oxide film is formed on the gate electrode 30.

  The p well region 16 below the gate electrode 30 and sandwiched between the source region 18 and the drift layer 14 functions as a channel region of the MISFET 100.

  Gate insulating layer 28 is provided between gate electrode 30 and p well region (SiC layer) 16. The film thickness of the gate insulating layer 28 is, for example, 30 nm or more and 300 nm or less. The silicon oxide film equivalent film thickness of the gate insulating layer 28 is, for example, 30 nm or more and 60 nm or less.

  FIG. 3 is an enlarged view of the p-type SiC layer, the gate insulating layer, and the gate electrode portion of this embodiment.

  The gate insulating layer 28 includes a first layer 28 a, a second layer 28 b, and a first region 40. The second layer 28 b is provided between the first layer 28 a and the gate electrode 30. The second layer 28 b is provided on the first layer 28 a. The second layer 28 b is in contact with the gate electrode 30.

  The first layer 28a and the second layer 28b are, for example, oxides or oxynitrides. The first layer 28a and the second layer 28b are, for example, materials selected from the group of silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide, zirconium aluminum oxide, hafnium silicate, and zirconium silicate.

  The oxygen density of the second layer 28b is higher than the oxygen density of the first layer 28a. The first layer 28a is, for example, silicon oxide, and the second layer 28b is, for example, a high dielectric constant film having a dielectric constant higher than that of silicon oxide. The second layer 28 b is, for example, hafnium oxide.

  The first region 40 is provided between the first layer 28a and the second layer 28b. The first region 40 is provided in the vicinity of the interface between the first layer 28 a and the second layer 28 b. The first region 40 contains at least one first element selected from the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth).

  And the 1st field 40 has the 1st peak of concentration of the 1st element. The full width at half maximum of the first peak is preferably 1 nm or less. The full width at half maximum of the first peak is preferably 0.5 nm or less.

It is desirable that the concentration at a position 1 nm or more away from the peak of the concentration of the first element be sufficiently small, 1 × 10 ¹⁸ cm ⁻³ or less. The concentration of the element can be confirmed by SIMS, but is more preferably below the detection limit of each element (approximately 1 × 10 ¹⁷ cm ⁻³ or less).

  The first element is segregated at the interface between the first layer 28a and the second layer 28b. The first element is bonded to the metal element constituting the second layer 28 b having a high oxygen density.

It is desirable that the concentration of the first element of the first peak be 4 × 10 ¹⁹ cm ⁻³ or more and 6.4 × 10 ²² cm ⁻³ or less.

  Note that the oxygen density, the concentration of the first element, and the distribution thereof can be determined, for example, by SIMS (Secondary Ion Mass Spectrometry).

  In the present embodiment, the oxygen density of the second layer 28b is higher than the oxygen density of the first layer 28a, but even if the oxygen density of the upper layer film is lower than the oxygen density of the lower layer film. There is no problem, and it is important that the film has different layer of oxygen density. It shows in the next embodiment.

  The MISFET 100 includes a conductive source electrode 34 electrically connected to the source region 18 and the p well contact region 20. The source electrode 34 also functions as a p-well electrode for applying a potential to the p-well region 16.

  The source electrode 34 is formed, for example, by laminating a barrier metal layer of Ni (nickel) and a metal layer of Al (aluminum) on the barrier metal layer. The barrier metal layer of Ni and the metal layer of Al may form an alloy by reaction.

  A conductive drain electrode 36 is formed on the side opposite to the drift layer 14 of the SiC substrate 12, that is, on the back surface side. The drain electrode 36 is, for example, Ni (nickel).

  In the present embodiment, for example, N (nitrogen) or P (phosphorus) is preferable as the n-type impurity, but As (arsenic) or Sb (antimony) or the like can also be applied. Further, for example, Al (aluminum) is preferable as the p-type impurity, but B (boron), Ga (gallium), In (indium) or the like can also be applied.

  Hereinafter, the operation and effect of the semiconductor device of the present embodiment will be described.

  In the SiC MISFET, there is a problem that the mobility of carriers decreases and the on-resistance increases due to the interface state at the interface between the SiC layer and the gate insulating layer. Therefore, for example, there is a method of introducing N (nitrogen) or phosphorus (P) for terminating the interface state at the interface between the SiC layer and the insulating film. When this method is used, N (nitrogen) or phosphorus (P) acts as an n-type dopant, and there is a possibility that the threshold may be lowered in the n-channel type MISFET. Therefore, in the n-channel type MISFET, coexistence with the high mobility of electrons and the high threshold is required.

  FIG. 4 is an explanatory view of the operation and the effect of the present embodiment. In the present embodiment, a negative charge fixed to the first region 40 is present. The fixed negative charge raises the threshold of the n-channel type MISFET. Therefore, a MISFET having a high threshold can be realized.

  In the present embodiment, the gate insulating layer 28 has a stacked structure of the first layer 28 a and the second layer 28 b having different oxygen densities. As a result of the first principle calculation by the inventor, the first element selected from N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Bi (bismuth) at the interface of films with different oxygen densities Was found to be stabilized by trapping electrons. A first element selected from N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) traps electrons to form the first layer 28 a and the first layer 28 having different oxygen densities. It fixes to the oxygen defect of an interface with 2 layer 28b. Thus, a fixed negative charge is formed. The first element is bonded to the metal element constituting the film having a higher oxygen density.

The concentration of the first peak is preferably 4 × 10 ¹⁹ cm ⁻³ or more and 6.4 × 10 ²² cm ⁻³ or less. Below the above range, there is a possibility that the threshold increase effect by fixed negative charge can not be obtained. Moreover, it is difficult to introduce the first element into the film beyond the above range. The concentration of the first peak is the concentration at the top of the first peak.

  In addition, it is desirable that the second layer 28 b, that is, the film having the higher oxygen density be in contact with the gate electrode 30. For example, when the second layer 28 b is a metal oxide of high dielectric constant such as haunium oxide or zirconium oxide, a Fermi level pinning effect occurs between the second layer 28 b and the gate electrode 30. Furthermore, the threshold of the MISFET is increased.

  Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1 and 3. In particular, a method of manufacturing the gate insulating layer 28 will be described. The case where the first element is N (nitrogen) will be described as an example.

  First, a silicon oxide film is formed on the SiC layer 16 by thermal oxidation. This silicon oxide film becomes the first layer 28a. Next, the silicon oxide film surface is nitrided by nitrogen plasma treatment.

  Next, a hafnium oxide film is deposited by the CVD method. This hafnium oxide film becomes the second layer 28 b. Thereafter, annealing is performed in a nitrogen atmosphere. By this annealing, N (nitrogen) on the surface of the silicon oxide film traps electrons at the interface between the silicon oxide film surface (first layer) 28 a and the hafnium oxide film (second layer) 28 b to segregate and fix. It becomes negative charge.

  Thereafter, for example, a polycrystalline silicon gate electrode is formed.

  As for the other steps, the MISFET 100 shown in FIGS. 1 and 3 is formed by applying a known manufacturing method.

For example, in the case where the first element is P (phosphorus), As (arsenic), Sb (antimony) or Bi (bismuth), phosphine is used in place of the process of nitriding the silicon oxide film surface with nitrogen plasma. P (phosphorus), As (arsenic), Sb (antimony) and Bi (bismuth) on the surface of silicon oxide film by flowing (PH ₃ ), arsine (AH ₃ ), stibine (SbH ₃ ) and bismucin (BiH ₃ ) The process of adsorbing to Of course, in the case of N (nitrogen), a process of adsorbing NH 3 to the surface of the silicon oxide film may be performed.

  According to this embodiment, an n-channel type MISFET that realizes a high threshold can be realized.

Second Embodiment
The semiconductor device of the present embodiment is the same as that of the first embodiment except that the upper and lower sides of the first layer and the second layer are reversed. Therefore, the contents overlapping with the first embodiment will not be described.

  FIG. 5 is an enlarged view of the p-type SiC layer, the gate insulating layer, and the gate electrode portion of this embodiment. The first layer 28a is formed on the second layer 28b.

  The oxygen density of the second layer 28b is higher than the oxygen density of the first layer 28a. For example, the first layer 28a is silicon oxide and the second layer 28b is hafnium oxide.

  The first region 40 is provided between the second layer 28 b and the first layer 28 a. The first region 40 is provided in the vicinity of the interface between the second layer 28 b and the first layer 28 a. The first region 40 contains at least one first element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), the first layer 28 a and Sb (antimony), Bi (bismuth). contains.

  In the present embodiment, as in the first embodiment, the negative charge fixed to the first region 40 is present. The negative charge raises the threshold of the n-channel type MISFET. Therefore, a MISFET having a high threshold can be realized.

  According to this embodiment, an n-channel type MISFET that realizes a high threshold can be realized.

Third Embodiment
The semiconductor device of this embodiment is provided between the SiC layer and the gate insulating layer, and is selected from the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), Bi (bismuth). The second embodiment is the same as the first embodiment except that a second region containing at least one second element and having a second peak of the concentration of the second element is further provided. Therefore, the contents overlapping with the first embodiment will not be described.

  FIG. 6 is an enlarged view of the p-type SiC layer, the gate insulating layer, and the gate electrode portion of this embodiment. A second region 50 is further provided between the SiC layer 16 and the gate insulating layer 28.

  The second region 50 contains at least one second element selected from the group of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth). The second region 50 has a second peak of the concentration of the second element.

  The full width at half maximum of the second peak is preferably 1 nm or less. The full width at half maximum of the second peak is preferably 0.5 nm or less. The second element is segregated at the interface between the SiC layer 16 and the gate insulating layer 28.

It is desirable that the concentration at a position 1 nm or more away from the peak of the concentration of the second element be sufficiently small, 1 × 10 ¹⁸ cm ⁻³ or less. The concentration of the element can be confirmed by SIMS, but is more preferably below the detection limit of each element (approximately 1 × 10 ¹⁷ cm ⁻³ or less).

  Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1 and 6. In particular, a method of manufacturing the gate insulating layer 28 will be described. The case where the first element and the second element are N (nitrogen) will be described as an example.

  First, a silicon oxide film is formed on the SiC layer 16 by thermal oxidation. This silicon oxide film becomes the first layer 28a.

  Next, the silicon oxide film is oxynitrided, for example, in a nitrogen monoxide (NO) atmosphere. By this oxynitridation, a second region 50 in which N (nitrogen) is segregated is formed at the interface between the SiC layer 16 and the silicon oxide film.

  Next, nitrogen plasma treatment is performed to nitride the silicon oxide film surface.

  Next, a hafnium oxide film is deposited by the CVD method. This hafnium oxide film becomes the second layer 28 b. Thereafter, annealing is performed in a nitrogen atmosphere. By this annealing, N (nitrogen) on the surface of the silicon oxide film is segregated at the interface between the silicon oxide film (first layer) 28 a and the hafnium oxide film (second layer) 28 b and becomes fixed negative charge.

  Thereafter, for example, a polycrystalline silicon gate electrode is formed.

  As for the other steps, the MISFET shown in FIGS. 1 and 6 is formed by applying a known manufacturing method.

  The second element terminates the interface state present at the interface between the SiC layer 16 and the gate insulating layer 28. Therefore, providing the second region 50 improves the mobility of electrons. Thus, the on-resistance of the MISFET is reduced.

  Further, as in the first embodiment, the provision of the first region 40 raises the threshold of the MISFET.

  According to this embodiment, it is possible to realize an n-channel type MISFET capable of achieving both high mobility and high threshold value.

  From the viewpoint of process consistency, it is desirable that the first element and the second element be the same element.

When the surface (first surface) of the SiC layer 16 is a surface inclined at an angle of 0 degrees to 8 degrees with respect to the (0001) plane, the second element is P (phosphorus), As (arsenic), It is desirable that it is Sb (antimony) or Bi (bismuth). This is because the termination structure is stabilized by using P (phosphorus), As (arsenic), Sb (antimony) or Bi (bismuth) on the silicon surface in which Si is arranged on the outermost surface. In particular, P or As is preferable because it is inexpensive. For example, in the case of using P, a manufacturing method is effective in which PH ₃ is placed on a substrate, an oxide film is formed, PH ₃ is placed again on that, and HfO ₂ is formed.

In addition, the surface (first surface) of the SiC layer 16 is inclined by 0 degrees to 8 degrees with respect to the (000-1) plane, or the first surface is set by 0 degrees to 8 degrees with respect to the <0001> direction. In the case of the inclined surface, it is desirable that the second element be N (nitrogen). By using N (nitrogen) in the carbon surface, m-plane, a-plane, etc. in which C (carbon) is arranged on the outermost surface, the termination structure is stabilized. In this case, it is possible to introduce nitrogen into the first region 40 and the second region 50 by forming a thin thermal oxide film, forming HfO ₂ thereon, and performing NO nitriding once. is there. Since nitrogen is stable at each position, it has a structure having the above peak in each region.

The concentration of the second peak is preferably 4 × 10 ¹⁹ cm ⁻³ or more and 6.4 × 10 ²² cm ⁻³ or less. If it is less than the above range, the effect of mobility improvement by the interface termination of the second element may not be obtained. In addition, it is difficult to introduce the second element into the interface beyond the above range. The concentration of the second peak is the concentration at the top of the second peak.

  The concentration of the second element and the distribution thereof can be determined, for example, by SIMS.

Fourth Embodiment
The semiconductor device of this embodiment is the same as that of the first embodiment except that the gate insulating layer includes a plurality of stacked structures of the first layer and the second layer. Therefore, the contents overlapping with the first embodiment will not be described.

  FIG. 7 is an enlarged view of the p-type SiC layer, the gate insulating layer, and the gate electrode portion of this embodiment. As shown in FIG. 7, the gate insulating layer 28 has a two-layer structure of a first layer 28a and a second layer 28b. And, the first region 40 is provided in three layers.

  FIG. 8 is an explanatory view of the operation and the effect of the present embodiment. In this embodiment, a two-layered structure of the first layer 28 a and the second layer 28 b is provided, and three fixed negative charges are also formed. The rise of the threshold of the MISFET is proportional to the number of layers of fixed negative charge. Therefore, according to the present embodiment, the threshold of the MISFET is further increased as compared with the first embodiment.

  Although the case where the two-layered structure of the first layer 28 a and the second layer 28 b is provided is described here as an example, it may be three or more layers. In particular, in the high-breakdown-voltage SiC-MISFET, the degree of freedom with respect to increasing the gate insulating layer thickness is high, so it is easy to increase the threshold value by increasing the number of layers.

Fifth Embodiment
The semiconductor device of this embodiment is provided between a p-type SiC layer and a gate electrode, and is made of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (Beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm) And at least one element selected from the group consisting of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), and a gate insulating layer containing C (carbon). The second embodiment is the same as the first embodiment except that the configuration of the gate insulating layer is different. Therefore, the contents overlapping with the first embodiment will not be described.

  FIG. 9 is a schematic cross-sectional view showing the configuration of the MISFET which is the semiconductor device of this embodiment. The MISFET 200 is a DIMOSFET in which ap well and a source region are formed by ion implantation. Also, the MISFET 200 is an n-channel MOSFET that uses electrons as carriers.

  The gate insulating layer 128 is made of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium) , Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), lanthanides (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu At least one element selected from the group consisting of In addition, the gate insulating layer 128 contains C (carbon).

The maximum concentration of the above element in the gate insulating layer 128 is preferably 1 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or more, and more preferably 1 × 10 ²⁰ cm ⁻³ or more. It is even more desirable to have. The maximum concentration of the element is, for example, 5 × 10 ²⁰ cm ⁻³ or less.

The maximum concentration of C (carbon) in the gate insulating layer 128 is preferably 1 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or more, and 1 × 10 ²⁰ cm ^−3. It is more desirable that it is more than. The maximum concentration of C (carbon) is, for example, 5 × 10 ²⁰ cm ⁻³ or less.

  Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. In particular, a method of manufacturing the gate insulating layer 128 will be described. The case where the said element is B (boron) is demonstrated to an example.

  First, an amorphous silicon film containing B (boron) is deposited on the SiC layer 16 by, for example, a CVD method. Then, the amorphous silicon film is thermally oxidized to form a silicon oxide film containing B at a high concentration.

  During thermal oxidation, C (carbon) diffuses from the surface of the SiC layer 16 into the silicon oxide film. The C and B and O in the silicon oxide film combine to form a complex and form a fixed negative charge.

  Thereafter, for example, a polycrystalline silicon gate electrode is formed.

  For the other steps, the MISFET 200 shown in FIG. 9 is formed by applying a known manufacturing method.

  As a result of the first principle calculation by the inventor, Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm , Yb, and Lu) become stable by forming a complex by bonding with C (carbon) and O (oxygen) in the insulating film, particularly in the silicon oxide film. It became clear. Then, it was also revealed that this complex is stable by trapping electrons in the silicon oxide film to form a negative fixed charge.

  The fixed negative charge formed by the complex raises the threshold of the n-channel type MISFET. Therefore, a MISFET having a high threshold can be realized.

  The element combines with C (carbon) in a ratio of 1: 1 to form a complex. Therefore, it is desirable that the maximum concentration of the element is 80% or more and 120% or less of the maximum concentration of C (carbon).

  Further, since the above element is bonded to C (carbon) to form a complex, the concentration of the above element at a predetermined position in the gate insulating layer is the same as that at the predetermined position in the gate insulating layer. It is desirable that it is 80% or more and 120% or less of the concentration of C (carbon). For example, the concentration measured when SIMS measurement is performed in the film thickness direction is 80% of the concentration of C (carbon) at the same position (first position) in the range where the measurement is performed. It is desirable that it is 120% or less.

  According to this embodiment, an n-channel type MISFET that realizes a high threshold can be realized.

Sixth Embodiment
The inverter circuit and the drive device of this embodiment are a drive device provided with the semiconductor device of the first embodiment.

  FIG. 10 is a schematic view of a drive device of the present embodiment. The driving device 300 includes a motor 140 and an inverter circuit 150.

  The inverter circuit 150 is configured of three semiconductor modules 100a, 100b, 100c in which the MISFET 100 of the first embodiment is used as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including output terminals U, V, and W of three AC voltages is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

  According to the present embodiment, the operation of the inverter circuit 150 and the drive device 300 is stabilized by providing the MISFET having the high threshold.

Seventh Embodiment
The vehicle of the present embodiment is a vehicle provided with the semiconductor device of the first embodiment.

  FIG. 11 is a schematic view of a vehicle according to the present embodiment. The vehicle 400 of this embodiment is a railway vehicle. Vehicle 400 includes motor 140 and inverter circuit 150. The inverter circuit 150 is configured by three semiconductor modules having the same configuration as the semiconductor module 100 of the first embodiment. By connecting three semiconductor modules in parallel, a three-phase inverter circuit 150 including output terminals U, V, W of three AC voltages is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 causes the wheel 90 of the vehicle 400 to rotate.

  According to the present embodiment, the operation of the vehicle 400 is stabilized by providing the MISFET having the high threshold.

Eighth Embodiment
The vehicle of the present embodiment is a vehicle provided with the semiconductor device of the first embodiment.

  FIG. 12 is a schematic view of a vehicle according to the present embodiment. The vehicle 1000 of the present embodiment is a car. Vehicle 1000 includes a motor 140 and an inverter circuit 150.

  The inverter circuit 150 is configured of three semiconductor modules 100a, 100b, 100c in which the MISFET 100 of the first embodiment is used as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including output terminals U, V, and W of three AC voltages is realized.

  The motor 140 is driven by the AC voltage output from the inverter circuit 150. Motors 140 rotate wheels 90 of vehicle 1000.

  According to the present embodiment, the reliability of the vehicle 1000 is improved by providing the MISFET having the high threshold.

Ninth Embodiment
The elevator according to this embodiment is an elevator equipped with the semiconductor device according to the first embodiment.

  FIG. 13 is a schematic view of an elevator according to the present embodiment. The elevator 1100 according to this embodiment includes a car 1010, a counterweight 1012, a wire rope 1014, a hoist 1016, a motor 140, and an inverter circuit 150.

  The inverter circuit 150 is configured of three semiconductor modules 100a, 100b, 100c in which the MISFET 100 of the first embodiment is used as a switching element. By connecting the three semiconductor modules 100a, 100b, and 100c in parallel, a three-phase inverter circuit 150 including output terminals U, V, and W of three AC voltages is realized.

  The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 causes the hoisting machine 1016 to rotate, and the car 1010 moves up and down.

  According to the present embodiment, the reliability of the elevator 1100 is improved by providing the MISFET having the high threshold.

  As described above, in the first to fifth embodiments, the case of 4H-SiC has been described as an example of the crystal structure of silicon carbide, but the present invention is not limited to silicon carbide of other crystal structures such as 6H-SiC, 3C-SiC, etc. It is also possible to apply.

  In the first to fifth embodiments, the n channel planar type MISFET is described as an example, but the present invention can be applied to an n channel trench type MISFET. The present invention can also be applied to n-channel IGBTs (Insulated Gate Bipolar Transistors).

  In the seventh to ninth embodiments, the semiconductor device of the present invention is applied to a vehicle or an elevator as an example, but the semiconductor device of the present invention is applied to, for example, a power conditioner of a solar power generation system. It is also possible.

  The present invention can also be applied to a semiconductor device provided with a gate insulating layer formed on a surface which is inclined at 0 degrees to 8 degrees with respect to the {111} plane of silicon. The present invention can also be applied to a semiconductor device provided with a gate insulating layer formed on a surface which is inclined at 0 degrees to 8 degrees with respect to the {111} plane of diamond.

  The conventional charge trapping film requires charge injection work, but has the advantage of being able to be filled at high density. In the conventional charge trap film, charge is released as time passes, and there is a problem that the threshold value is lowered. This means that the trap state is not so stable.

  On the other hand, in the present invention, stable negative fixed charge can be formed in the gate insulating layer. As it is very stable, no charge flows in or out of the insulating film. The only problem is that the trap volume can not be so high. However, that point can be solved by increasing the density by forming multiple layers or forming a thick film and forming a trap on the entire film.

  While certain embodiments of the present invention have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and modifications thereof are included in the scope and the gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

16 p well region (SiC layer)
28 gate insulating layer 28 a first layer 28 b second layer 30 gate electrode 40 first region 50 second region 100 MISFET (semiconductor device)
140 motor 150 inverter circuit 200 MISFET (semiconductor device)
300 driving device 400 vehicle 1000 vehicle 1100 elevator

Claims (9)

p-type SiC layer,
A gate electrode,
A gate insulating layer between the SiC layer and the gate electrode;
The gate insulating layer is made of Ge (germanium), B (boron), Al (aluminum), Ga (gallium), In (indium), Be (beryllium), Mg (magnesium), Ca (calcium), Sr (strontium) , Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), lanthanides (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu A semiconductor device comprising C (carbon) and at least one element in the group of The semiconductor device according to claim 1, wherein the maximum concentration of the element in the gate insulating layer is 1 × 10 ¹⁸ cm ⁻³ or more. The semiconductor device according to claim 1, wherein the maximum concentration of C (carbon) in the gate insulating layer is 1 × 10 ¹⁸ cm ⁻³ or more.   The semiconductor device according to any one of claims 1 to 3, wherein the maximum concentration of the element in the gate insulating layer is 80% to 120% of the maximum concentration of C (carbon) in the gate insulating layer. .   The concentration of the element at a first position in the gate insulating layer is 80% or more and 120% or less of the concentration of C (carbon) at the first position. The semiconductor device according to claim 1.   An inverter circuit comprising the semiconductor device according to any one of claims 1 to 5.   A driving device comprising the semiconductor device according to any one of claims 1 to 5.   A vehicle comprising the semiconductor device according to any one of claims 1 to 5. An elevator comprising the semiconductor device according to any one of claims 1 to 5.

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