JP2019083264A - Wiring board and wiring board for multiple parts - Google Patents

Abstract

To provide a wiring board or the like that has a plurality of surface pads on which electronic components are to be mounted subsequently to the first main surface of the board body and has improved mountability of an electronic component by suppressing variation in thickness of a plated layer coated on the surface of each of the surface pads.SOLUTION: A wiring board 1a includes a board body 2 that is constituted by insulating materials s1 and s2 and has a first main surface 3 and a second main surface 4 opposite to each other with a rectangular outline in plan view, and four side surfaces 5 located between the main surfaces 3 and 4, two surface pads 6a and 6b formed on the main surface 3, and a plurality of inner layer wirings 7a to 7c, 8a, 8b, 8p, 9a, and 9b formed inside the board body 2, and the inner layer wirings 7a to 7c, and the like have ends 8ae, 8be, 9ae, and 9be on different side surfaces 5 of the board body 2, and two sets of conductive circuits C1 and C2 are formed by two of the inner layer wirings 7a to 7c and the like and the two surface pads 6a and 6b, are electrically isolated from each other, and the conductive circuits C1 and C2 are connected to the inner layer wirings 7a to 7c, and the like through one of the surface pad 6a and 6b.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board having excellent mountability in a plurality of surface pads provided on the first main surface of a substrate body, and a multi-layered wiring board having a plurality of the wiring boards.

  For example, in the internal metallized layer formed on the bottom surface of the recess (cavity) of each of the plurality of packages arranged adjacent to each other in plan view in the product region, the plated layers coated on the surface of each internal metallized layer In order to suppress variations in thickness between layers, the invention of a multi-cavity substrate has been proposed in which a plating current can be applied through a surface metallized layer formed on the surface of a rectangular frame in each package (for example, Patent Document 1).

  However, in the case of the multi-cavity substrate, although it is possible to suppress the variation in the plated layer coated on the surface of the internal metallized layer among the plurality of packages, the thickness of the plated layer coated for each of the plurality of internal metallized layers in each package. Variation was not considered an issue to be solved. Therefore, when the thickness of the plating layer covered every surface of the plurality of internal metallized layers varies, when the electronic component is mounted over the plurality of internal metallized layers later, the internal metallized layer There was a risk that it could not be mounted with high precision on top of each other.

JP, 2008-18967, A (pages 1-8, FIGS. 1-7)

  The present invention solves the problems described in the background art, and has a plurality of surface pads on which electronic components are to be mounted on the first main surface of the substrate body, and the surface is coated on each of the plurality of surface pads Providing a wiring board having improved mountability of the electronic component by suppressing variation in thickness between metal layers due to metal plating, and a multi-layered wiring board having a plurality of the wiring boards at the same time; It will be an issue.

Means for Solving the Problems and Effects of the Invention

According to the present invention, in order to solve the above problems, a plurality of sets of energizing circuits are formed inside the substrate main body, which individually pass through a plurality of surface pads formed on the first main surface of the substrate main body and include inner layer wiring. The invention is conceived on the idea of making the plurality of conducting circuits independent of one another and further including a high electrical conductive layer for each of the surface pads in accordance with the electrical environment (electrical conditions).
That is, the wiring substrate (claim 1) of the present invention is made of an insulating material, and the first and second main surfaces facing each other in a rectangular outline in plan view and the first main surface and the second main surface A substrate body having side surfaces of four sides located between the two main surfaces, a plurality of surface pads formed on the first main surface of the substrate body, and a plurality of inner layers formed inside the substrate body And the inner layer wire has an end on a side surface of the substrate body, and a plurality of conductive circuits are formed by the plurality of inner layer wires and the plurality of surface pads. The plurality of conductive circuits are electrically independent of each other, and the conductive circuits pass through at least one surface pad and are connected to the inner layer wiring.

According to the above wiring board, the following effect (1) can be obtained.
(1) The constituent materials of each circuit passing through at least one of the surface pads and connected to the inner layer wiring are similar to each other and electrically independent of each other. Because of this, the difference in electrical resistance between the current-carrying paths is reduced. Therefore, by supplying a plating current from each of the end portions to the plurality of sets of current-carrying circuits, the surfaces of the surface pads are coated with metal films having similar thicknesses. Therefore, it is possible to precisely mount the electronic component with desired positions and postures straddling the upper side of the plurality of surface pads later.

The insulating material is a high temperature fired ceramic (alumina, mullite, aluminum nitride or the like), a low temperature fired ceramic (glass-ceramic or the like), or an epoxy resin or the like.
In addition, the first and second main surfaces may be referred to as relative names, one of which may be referred to as the front surface, and the other as the back surface.
In addition, the surface pad may include the metal layer formed by laminating a plurality of metal thin film layers, and a high electric conductive layer formed on the surface of the metal layer and having a thickness larger than the thickness of the metal layer. And the form which consists only of a metallizing layer is also included.
The term "pass through the surface pad" means that the conductor (for example, via conductor) in the conductive circuit is connected to the surface pad at two or more places separated from each other.
Furthermore, the inner layer wiring includes both a form of a linear conductor and a form in which a plan view shows an arbitrary pattern.
Furthermore, the conductive circuit includes at least the inner layer wire, the surface pad, and the via conductor disposed along the thickness direction of the insulating material.
In addition, as the high electrical conductivity layer, for example, when the insulating material is a high temperature fired ceramic such as alumina, copper or copper alloy, or silver or silver alloy is used. In such a case, the pattern wiring, the via conductor, and the inner layer wiring which constitute the conductive circuit are formed by metallizing such as tungsten (hereinafter, simply described as W) or molybdenum (hereinafter, simply as Mo). Be done.

Further, the present invention also includes a wiring board (claim 2), wherein the surface pad includes a high electric conductive layer having a lower electric resistance than the conductor constituting the inner layer wiring.
According to this, even if there is a difference in the electrical resistance among the plurality of sets of the energizing circuits due to the difference in the length and the thickness (including the volume) of the energizing path, the current is different for each energizing circuit. Since the high electrical conductive layer is included in the passing surface pad, it is possible to reduce the difference in electrical resistance between the plurality of sets of current-carrying circuits. Therefore, it is possible to more reliably achieve the effect (1).
Furthermore, when a multi-piece wiring board to be described later is configured, between the surface pad of the wiring board located on the peripheral side of the multi-piece wiring board in plan view and the surface pad of the wiring board located on the center side in plan view It is also possible to reduce variations in the thickness of the metal film coated by metal plating (hereinafter referred to as effect (2)).
The high electrical conductivity layer is at least about 20 nΩm smaller in electrical resistivity than the conductor constituting the inner layer wiring, and is, for example, made of copper or a copper alloy, or silver or a silver alloy.
Further, according to the present invention, the surface pad is formed of a metal layer formed on the first main surface of the substrate body, and formed on the top surface of the metal layer, and having a thickness greater than the thickness of the metal layer. A wiring board (claim 3) comprising a high electrical conductive layer is also included.
According to this, since the surface pad includes the high electrical conductive layer having a thickness larger than the thickness of the metal layer formed on the first main surface of the substrate main body, the effect (1) is further enhanced. It becomes possible to play reliably.

The present invention also includes a wiring board (claim 4) in which the plurality of sets of energizing circuits cross each other when the substrate body is transmitted in a plan view.
According to this, the plurality of sets of energization circuits cross each other when passing through the substrate body in plan view. For example, even if the inner layer wire of one conducting circuit and the inner layer wire of the other conducting circuit cross each other in an orthogonal manner when passing through the substrate body in plan view, the conducting circuits Are electrically independent of each other, it is possible to obtain the effect (1).
Note that the intersecting angle is in the range of 30 degrees to 90 degrees in perspective by planar view.

Further, in the present invention, the plurality of sets of energizing circuits are two sets of energizing circuits, and both ends of each of the two sets of energizing circuits are a pair of opposing side surfaces or an adjacent pair in the substrate body. The wiring board (claim 5) exposed separately on the side is also included.
Among the above, in the embodiment in which both ends of each of the two sets of energizing circuits are individually exposed to the pair of identical side surfaces facing each other in the substrate main body, a plurality of wiring boards in a multi-cavity wiring board described later Since it is possible to arrange the current paths for the plating current to be commonly applied along substantially the same direction, it is possible to simplify the circuit structure in the product area of the wiring board for multiple cavities (hereinafter, the effect is achieved) (3))).
On the other hand, in the embodiment in which both ends of each of the two sets of energizing circuits are exposed separately for each of a pair of adjacent side surfaces in the substrate body, an inadvertent short circuit between the two sets of energizing circuits is easily prevented. (Hereinafter referred to as effect (4)).

In addition, according to the present invention, a wiring substrate is formed on the second main surface of the substrate main body with a plurality of external connection terminals individually connected to the plurality of sets of energization circuits (claim 6) Also included.
According to this, when the plating current is supplied to each of the plurality of sets of energizing circuits, the surface of each of the external connection terminals individually connected to each energizing circuit is simultaneously coated with the same metal coating by metal plating. Becomes possible (hereinafter referred to as effect (5)).

On the other hand, the multi-cavity wiring board of the present invention (Claim 7) comprises a product area in which a plurality of the wiring boards are arranged vertically and horizontally adjacent to each other in plan view and an ear portion surrounding the periphery of the product area. The invention is characterized in that a plurality of plating electrodes electrically connected individually to the plurality of energizing circuits for each of the wiring boards are formed on the outer side surface of the ear portion.
According to this, it becomes possible to efficiently provide a plurality of wiring boards capable of achieving the effects (1) to (5) in a multi-piece configuration (hereinafter referred to as effect (6)). In particular, with regard to the effect (1), the surface of each of the plurality of surface pads formed on the first main surface of the individual substrate main body, regardless of where the individual wiring substrate is located in the product area. In addition, it becomes possible to coat a metal film by electrolytic metal plating with a relatively uniform thickness. Furthermore, the effect (2) can be reliably obtained.

(A) is a perspective view which shows the wiring board of one form by this invention, (B) is a disassembled perspective view which includes a transparent part etc. in a part of this wiring board. The general | schematic perpendicular | vertical cross section along the arrow of XX in FIG. 1 (A). The general | schematic perpendicular | vertical cross section along the arrow of the YY line in FIG. 1 (A). FIG. 5 is a schematic vertical cross-sectional view similar to FIG. 3 showing a use state of the wiring board. (A) is a perspective view which shows the wiring board of a different form, (B) is a disassembled perspective view of this wiring board. The general | schematic perpendicular | vertical cross section along the arrow of XX in FIG. 5 (A). The general | schematic perpendicular | vertical cross section along the arrow of the YY line in FIG. 5 (A). FIG. 8 is a schematic vertical cross-sectional view similar to FIG. 7 showing a use state of the wiring board. (A) is a plan view of the wiring board for multiple cavities including the wiring board of FIGS. 1 to 4 and (B) is a partial plan view of the wiring board for multiple cavities including the wiring board of FIGS.

Hereinafter, modes for carrying out the present invention will be described.
FIG. 1 (A) is a perspective view showing a wiring board 1a according to one embodiment of the present invention, FIG. 1 (B) is an exploded perspective view of the wiring board 1a, and FIGS. Cross-sectional view along the arrow of line X-X or line Y-Y of FIG.
As shown in FIGS. 1 (A) and 1 (B), the wiring board 1a has a first (main surface) 3 and a second main surface facing each other in a square (rectangular) shape in plan view. (Back surface) 4 and substrate main body 2 having side surfaces 5 of four sides located between the main surfaces 3 and 4 and two (plural) surface pads formed on the first main surface 3 of the substrate main body 2 6a and 6b, and two sets (plurality) of pattern wiring (inner layer wiring) 7a to 7c formed inside the substrate main body 2 and inner layer wirings 8a, 8b, 9a and 9b.
The substrate body 2 is made of, for example, a high-temperature fired ceramic (insulation material) such as alumina, and the upper and lower two ceramic layers s1 and s2 are integrally laminated. The surface pads 6a and 6b and the pattern wirings 7a to 7c have a rectangular shape in plan view.

As shown in FIG. 1 (B) and FIG. 3, of the two sets, the pattern wiring (inner layer wiring) 7a formed between the ceramic layers s1 and s2 and the inner layer wiring 8a are one of the surface pads 6a. The first current-carrying circuit C1 which is individually connected to each other via the center portions on both end sides in the long side direction and the two via conductors which individually penetrate the ceramic layer s1. Are configured. The pattern wiring 7a is connected to the inner layer wiring 9a having a bowl shape in a plan view, and further formed on the second main surface 4 of the substrate body 2 via the via conductor 10 penetrating the ceramic layer s2. The connection terminals 11a are also electrically connected. The end (end face) 8ae of the inner layer wiring 8a which is the both ends of the first current-carrying circuit C1 and the end 9ae of the inner layer wiring 9a are exposed separately for each pair of side surfaces 5 opposed in the substrate body 2 ing.
FIG. 1B illustrates ceramic layers s1 and s2 in order to explain an electrical connection between the surface pads 6a and 6b, the pattern wirings 7a to 7c, and the inner layer wirings 8a 8b 9a, and 9b. Are separated from each other along the thickness direction. Therefore, an imaginary broken line is included between the ceramic layers s1 and s2 in FIG. 1B, extending in the axial direction a plurality of via conductors 10 penetrating the ceramic layer s1.

A connection pad (inner layer wire) 8p for connection to one of the via conductors 10 is provided at the tip of the inner layer wire 8a having an L shape in plan view.
The pattern wiring 7a, the inner layer wirings 8a and 9a, the via conductor 10, and the external connection terminal 11a are mainly made of W or Mo.
Furthermore, since the surface pad 6a is connected to the pattern wiring 7a and the inner layer wiring 8a through the two via conductors 10, the first conduction circuit C1 is a conductor through which current always passes. The surface pad 6a is formed on the metal layer 12 formed on the first main surface 3 of the substrate body 2 and on the upper surface of the metal layer 12 as described later, and is larger than the thickness of the metal layer 12 It consists of a thick high electrical conductive layer 13. The high electrical conductive layer 13 is mainly made of copper or silver and has lower electric resistance than the W or Mo.

As shown in FIG. 1 (B) and FIG. 2, the pattern wiring (inner layer wiring) 7b and 7c formed between the ceramic layers s1 and s2 among the two sets is individually connected to the inner layer wirings 8b and 9b. And the second surface which can be conducted mutually by individually connecting with both end sides in the long side direction of the other surface pad 6 b through the two via conductors 10 individually penetrating the ceramic layer s 1. The energizing circuit C2 is configured.
The pattern wiring 7c is also electrically connected to the other external connection terminal 11b formed on the second main surface 4 of the substrate body 2 through the via conductor 10 penetrating the ceramic layer s2. The end 8be of the inner layer wiring 8b, which is both ends of the second current-carrying circuit C2, and the end 9be of the inner layer wiring 9b are exposed separately for each of the pair of side surfaces 5 opposed in the substrate body 2. Incidentally, as shown in FIGS. 1A and 1B, the pair of side surfaces 5 are different from and adjacent to the side surfaces 5 on which both end portions 8ae and 9ae of the first energizing circuit C1 are exposed. ing.

As shown in FIG. 1 (B) and FIG. 2, the long side of the inner layer wire 8a on the side of the first conduction circuit C1 and the surface pad 6b on the side of the second conduction circuit C2 are the substrate main body 2 In the thickness direction, they are separated by an amount corresponding to the thickness of the ceramic layer s1, and when they are transmitted in a plan view, they cross each other at a right angle (90 degrees). That is, the first and second energizing circuits C1 and C2 are electrically independent of each other.
The pattern wirings 7b and 7c, the inner layer wirings 8b and 9b, the via conductors 10, and the external connection terminals 11b are also mainly made of W or Mo.
Further, since the surface pads 6b are also individually connected to the pattern wirings 7b and 7c through the two via conductors 10, they are conductors through which the current always passes in the second conduction circuit C2. The surface pad 6b is formed on the metal layer 12 formed on the first main surface 3 of the substrate body 2 and on the upper surface of the metal layer 12 as shown in the enlarged view of the dashed dotted line portion Z in FIG. And it consists of a high electric conductive layer 13 having a thickness larger than the thickness of the metal layer 12. The metal layer 12 has a total thickness of about 1 μm, and for example, thin film layers of titanium, Mo and copper are sequentially laminated from the side of the first main surface 3. On the other hand, the high electrical conductivity layer 13 is made of copper or silver having a total thickness of about 50 μm, and has a much lower electrical resistance than the W or Mo.

As shown in FIG. 1 (B) and FIG. 3, for example, the plating current supplied to the inner layer wire 8 a from the end 8 ae of the first energizing circuit C 1 is the inner layer wire 8 a and the pad 8 p. A conductive path is provided to transmit power to the end 9ae of the inner layer wire 9a via the via conductor 10, the surface pad 6a, the via conductor 10, the pattern wire 7a, and the inner layer wire 9a. That is, in the first conduction circuit C1, a current always passes through the surface pad 6a, and a part of the conduction path includes the external connection terminal 11a and the via conductor 10 connected thereto.
In FIG. 3, for ease of understanding, the pad 8p of the inner layer wiring 8a and the pattern wiring 7a are shown apart from each other. The same applies to FIG. 4 described later.
On the other hand, as shown in FIG. 1 (B) and FIG. 2, in the second conduction circuit C2, for example, the plating current supplied from the end 8be to the inner layer wire 8b is the inner layer wire 8b, pattern A conductive path is provided to transmit power to the end 9be of the inner layer wire 9b through the wire 7b, the via conductor 10, the surface pad 6b, the via conductor 10, the pattern wire 7c, and the inner layer wire 9b. That is, in the second conduction circuit C2, a current always passes through the surface pad 6b, and a part of the conduction path includes the external connection terminal 11b and the via conductor 10 connected thereto.

As described above, the conduction paths of the first and second conduction circuits C1 and C2 are different from each other in the length of the conduction path between them and the volume of the conductor to be configured. However, the first and second current-carrying circuits C1 and C2 separate the surface pads 6a and 6b containing the high electric conductive layer 13 whose electric resistance is lower than that of the other conductor in the middle of each current-carrying path. Therefore, the difference in the electrical resistance between the two current-carrying circuits C1 and C2 is made as small as possible.
As a result, when the same plating current is supplied along the respective conduction paths of the first and second conduction circuits C1 and C2, the surface current of the surface pads 6a and 6b and the external connection terminals 11a and 11b is different. For example, it is possible to coat a nickel layer by electrolytic metal plating and a gold layer (metal coating, both not shown) with substantially the same thickness and uniformity.
In FIG. 1B, the nickel layer and the gold layer are formed on the surface pads 6a and 6b by changing the lengths and volumes of the conductors which are different from each other between the two current paths to be equal. And can be coated more uniformly.

Therefore, as shown in FIG. 4, it straddles above the two surface pads 6a and 6b provided on the first main surface 3 of the substrate main body 2 and, depending on the predetermined position and posture, the semiconductor element, the light emitting element, etc. The wiring board 1a is easy to mount with high precision in position and posture. Therefore, according to the wiring board 1a, the effects (1), (4) and (5) can be reliably obtained, and the effect (2) can also be obtained.
Incidentally, when the long side of the inner layer wiring 8a on the side of the first conduction circuit C1 and the surface pad 6b on the side of the second conduction circuit C2 are transparent in plan view, they are optional other than perpendicular to each other. (E.g., 30 degrees or more and less than 90 degrees).
Further, in the second conduction circuit C2, the pattern conductor 7b and the external connection terminal 11b may also be electrically connected by the via conductor 10.
Furthermore, the intersection is not limited to the intersection when the above-described inner layer wiring 8a and the surface pad 6b are transmitted in plan view, but a line connecting the center of the end 8ae and the center of the end 9ae, The case where the line connecting the center of the end 8be and the center of the end 9be intersect, that is, the case where the energizing circuit C1 and the energizing circuit C2 intersect in plan view is also included.

FIG. 5 (A) is a perspective view showing a wiring board 1b having a form different from the above, FIG. 5 (B) is an exploded perspective view of the wiring board 1b, FIGS. 6 and 7 are in FIG. 5 (A). Cross-sectional view along the arrow of line X-X or line Y-Y of FIG.
The wiring substrate 1b is, as shown in FIGS. 5A and 5B, a substrate main body 2 having the same first main surface 3 and second main surface 4 and side surfaces 5 of four sides as described above; Two (plural) surface pads 16a and 16b formed on the first main surface 3 of the substrate main body 2 and two sets (plural) pattern wirings (inner layer wiring) 17a formed inside the substrate main body 2 To 17 d, and inner layer interconnections 18 a, 18 b, 19 a and 19 b.

As shown in FIG. 5 (B), FIG. 6, and FIG. 7, the pattern wiring (inner layer wiring) 17a and 17b formed between the ceramic layers s1 and s2 among the two groups is one of the surface pads 16a. The third current-carrying circuit C3 is separately connected through the two via conductors 10 penetrating the ceramic layer s1 to both end sides in the long side direction of the third conductive circuit C3 which can be conducted separately with the inner layer wires 18a and 19a. Configured. The pattern wirings 17a and 17b are also individually connected to one of the external connection terminals 11a formed on the second main surface 4 of the substrate body 2 through the via conductors 10 penetrating the ceramic layer s2 individually. There is. The end 18 ae of the inner layer wire 18 a, which is both ends of the third current-carrying circuit C 3, and the end 19 ae of the inner layer wire 19 a are exposed separately for each pair of side surfaces 5 opposed in the substrate body 2.
Also between the ceramic layers s1 and s2 in FIG. 5 (B), imaginary broken lines in which a plurality of via conductors 10 penetrating the ceramic layer s1 extend in the axial direction are included.

The pattern wirings 17a and 17b, the inner layer wirings 18a and 19a, the via conductor 10, and the external connection terminal 11a are also mainly made of W or Mo.
Furthermore, since the surface pad 16a is individually connected to the pattern wirings 17a and 17b via the two via conductors 10, the third conduction circuit C3 is a conductor through which current always passes. The surface pad 16a is also mainly made of W or Mo.

As shown in FIG. 5 (B), and FIGS. 6 and 7, the pattern wiring (inner layer wiring) 17c and 17d formed between the ceramic layers s1 and s2 among the two groups is separate from the inner layer wiring 18b and 19b. Can be electrically connected to each other by individually connecting to both ends in the long side direction of the other surface pad 16b through two via conductors 10 connected to each other and penetrating the ceramic layer s1 individually. The fourth energizing circuit C4 is configured. The pattern wirings 17c and 17d are also individually connected to the other external connection terminals 11b formed on the back surface 4 of the substrate body 2 through the via conductors 10 which individually penetrate the ceramic layer s2. The surface pad 16b is also mainly made of W or Mo, and is separately connected to the pattern wirings 17c and 17d through the two via conductors 10, so that current always passes through in the fourth conduction circuit C4. It is a conductor.
The end 18be of the inner layer wiring 18b, which is both ends of the fourth current-carrying circuit C4, and the end 19be of the inner layer wiring 19b are exposed separately for each of the pair of side surfaces 5 opposed in the substrate body 2. Incidentally, as shown in FIGS. 5A and 5B, the pair of side surfaces 5 is the same as the side surface 5 on which both end portions 18ae and 19ae of the third energizing circuit C3 are exposed. The end portions 18ae and 19ae and the end portions 18be and 19be are separated by a distance not to short-circuit each other.

As shown in FIGS. 6 and 7, the surface pad 16a and the surface pad 16b, the pattern wiring 17a and 17b and the pattern wiring 17c and 17d, the inner layer wiring 18a and 19a and the inner layer wiring 18b and 19b, the external connection terminal 11a and 11b, and the via conductors 10 individually connecting between them are formed in the same shape, the same size, and the same position. Therefore, since the third and fourth conduction circuits C3 and C4 are in parallel (parallel) with each other in plan view and are in a pair relationship having the same conduction path, the electric resistance between the two circuits C3 and C4 There is almost no difference.
As a result, when the same plating current is supplied along the respective conduction paths of the third and fourth conduction circuits C3 and c4, for each surface of the surface pads 16a and 16b and the external connection terminals 11a and 11b. On the other hand, it is possible to uniformly coat, for example, a nickel layer by electrolytic metal plating and a gold layer (metal coating, neither of which is shown) with substantially the same thickness.

Therefore, as shown in FIG. 8, the semiconductor element and the light emitting element are straddled above the two front surface pads 16a and 16b provided on the first main surface 3 of the substrate body 2 and then at predetermined positions and postures. The wiring board 1 b is easy to accurately mount the electronic components 15 such as, for example. Therefore, according to the wiring board b, the effects (1), (3) and (5) can be reliably obtained.
The surface pads 16a and 16b are, similarly to the surface pads 6a and 6b, the metal layer 12 formed on the first main surface 3 of the substrate body 2 and a high electrical conductive layer formed thick on the top surface thereof. It is good also as a form which consists of 13. According to the wiring board 1b having such a form, when the multi-piece substrate is used, the effect (2) can be reliably obtained.
The third and fourth current-carrying circuits C3 and C4 may not be arranged parallel to each other when one passes through the substrate body 2 in a plan view, and one or both of them may be inclined.

FIG. 9A is a plan view showing a multi-layered wiring board 20a for obtaining a plurality of the wiring boards 1a simultaneously.
As shown in FIG. 9A, the multi-cavity wiring board 20a has a plurality of the wiring boards 1a arranged vertically and horizontally adjacent to each other, and a product region 21 having a rectangular (rectangular) outline in plan view. And an ear 22 surrounding the periphery of the product area 21 and having a rectangular frame shape in plan view. The ear portion 22 is formed by laminating the same ceramic layers s1 and s2 as described above, and has main surfaces 3 and 4 common to the respective wiring boards 1a. The broken line indicating the outer shape of the product area 21 and the broken line dividing the adjacent wiring boards 1a are imaginary cut planned surfaces used later when divided into individual wiring boards 1a.
In the product area 21, in the two wiring boards 1a adjacent along the horizontal direction in FIG. 9A, the inner layer wiring 8a and the inner layer wiring 9a of each first conductive circuit C1 are scheduled to be cut vertically It is connected orthogonal to the plane. On the other hand, in the two wiring boards 1a adjacent along the vertical direction in FIG. 9A, the inner layer wire 8b and the inner layer wire 9b of each of the second current-carrying circuits C2 are orthogonal to the horizontal cutting planned surface. It is connected.

As shown in FIG. 9A, a semicircular recess 23 in plan view and a flat surface formed along the inner wall of each recess 23 on the center side of each of the outer surfaces of the four sides of the ear 22. The plating electrodes 24a, 24b, 24c, and 24d having a semicircular arc shape are individually disposed.
The plating electrode 24a located on the right side of the ear portion 22 includes the inner layer wires 8a of the plurality of wiring boards 1a located on the right end side in the product region 21, the connection wire 25 formed between the ceramic layers s1 and s2, and The plurality of branch wires 26 are individually connected. The plating electrode 24b located on the left side of the ear portion 22 is a connection wire formed between the inner layers 9a of the plurality of wiring boards 1a located on the left end side in the product region 21 and the ceramic layers s1 and s2. It is individually connected via 25 and a plurality of branch wiring lines 26.
For example, the plating current supplied from the plating electrode 24 a on the right side of the ear 22 and the plating electrode 24 b on the left side of the ear 22 passes through the connection wiring 25 and the branch wiring 26, and As a result of power transmission to the surface pad 6a in the first current-carrying circuit C1 in each wiring board 1a, metal in the electrolytic plating solution is deposited on the surface.

On the other hand, as shown in FIG. 9A, the plating electrode 24c located on the upper side of the ear portion 22 includes the inner layer wires 8b of the plurality of wiring boards 1a located on the upper end side in the product region 21; The connection lines 27 formed between s 1 and s 2 and the plurality of branch lines 28 are individually connected. Further, the plating electrode 24d located on the lower side of the ear portion 22 is a connection wire formed between the inner layers 9b of the plurality of wiring boards 1a located on the lower end side in the product region 21 and the ceramic layers s1 and s2. It is individually connected via 27 and a plurality of branch wires 28.
For example, the plating current supplied from the plating electrode 24c on the upper side of the ear portion 22 and the plating electrode 24d on the lower side of the ear portion 22 passes through the connection wiring 27 and the branch wiring 28 to be in the product area 21. As a result of power transmission to the surface pad 6b in the second current-carrying circuit C2 in each wiring board 1a, metal in the electrolytic plating solution is deposited on the surface.

Therefore, in a state where the electrode rods (not shown) are in contact with the inner wall surfaces of the plating electrodes 24a to 24d, the multi-wiring wiring board 20a is sequentially immersed in a nickel plating bath and a gold plating bath (not shown). When nickel plating by electrolytic plating and electrolytic gold plating are sequentially performed, the surface exposed to the outside of the surface pads 6a and 6b in each wiring substrate 1a is a nickel layer and a gold layer (metal coating, any of which has a uniform thickness). (Not shown) can also be coated. Moreover, the difference in thickness of the metal layer between the wiring board 1a located on the peripheral side in the product area 21 and the wiring board 1a located on the center side in the product area 21 can also be made relatively small. It is.
Accordingly, the effect (6) can be exhibited by the multi-piece wiring board 20a.
Note that two or more of the plating electrodes 24 a to 24 d may be formed on each side of the ear portion 22, and these may be connected in parallel to the connection wires 25 and 27.

FIG. 9 (B) is a partial plan view showing a multi-layered wiring board 20b for obtaining a plurality of the wiring boards 1b simultaneously.
As shown in FIG. 9B, the multi-cavity wiring board 20b has a plurality of the wiring boards 1b arranged vertically and horizontally adjacent to each other, and a product region 21 having a rectangular (rectangular) outline in plan view. And an ear 22 surrounding the periphery of the product area 21 and having a rectangular frame shape in plan view. The broken line indicating the outer shape of the product area 21 and the broken line dividing the wiring boards 1a adjacent to each other are imaginary cut planned surfaces as described above.
In the product area 21, in the two wiring boards 1b adjacent along the vertical direction in FIG. 9B, the inner layer wiring 18a and the inner layer wiring 19a of each third conductive circuit C3 are scheduled to be cut horizontally It is connected orthogonal to the plane. Similarly, in the two wiring boards 1b adjacent along the vertical direction, the inner layer wire 18b and the inner layer wire 19b of each of the fourth energizing circuits C4 are connected orthogonally to the horizontal planned surface to be cut .

As illustrated in FIG. 9B, plating electrodes 24a and 24c are formed on the outer side surface of the upper side of the ear portion 22 so as to be separated from each other. Two plating electrodes (24 b, 24 d) are formed on the outer surface of the lower side (not shown) of the ear portion 22 in line symmetry with the plating electrodes 24 a, 24 c.
One plating electrode 24a located on the upper side of the ear portion 22 is separated from the inner layer wire 18a for each wiring board 1b located on the upper end of the product region 21 via the similar connection wire 25 and the plurality of branch wires 26 described above. It is connected to the. Further, the plating electrode (24 b) positioned symmetrically with the plating electrode 24 a at the lower side of the ear 22 not shown is also located at the lower end of the product region 21 via the similar connection wiring 25 and the plurality of branch wirings 26. It is individually connected to the inner layer wiring 19a of each of the located wiring boards 1b.

  On the other hand, the other plating electrode 24c located on the upper side of the ear portion 22 is the inner layer wire 18b for each wiring board 1b located on the upper end of the product region 21 via the similar connection wire 27 and the plurality of branch wires 28. And are individually connected. In addition, the plating electrode (24 d) located symmetrically with the plating electrode 24 c at the lower side of the ear portion 22 (not shown) is also attached to the lower end of the product region 21 via the similar connection wiring 27 and plural branch wirings 28. It is individually connected to the inner layer wiring 19b of each wiring substrate 1b located. The connection wires 25 and 27 and the branch wires 26 and 28 may be short-circuited with each other. Alternatively, the connection wires 25 and 27 and the branch wires 26 and 28 may form, for example, one set between the ceramic layers s 1 and s 2 and the other set as the main portion of the ear 22 in order to prevent a short circuit between each other. It may be formed along the surface 4 and may be formed along the space between the ceramic layers s 1 and s 2 via a via conductor not shown immediately before the product region 21. When the connection wires 25 and 27 and the branch wires 26 and 28 are short-circuited with each other, one current source can cover the plated metal film.

For example, the plating current supplied from the plating electrode 24 a and the plating electrode (24 b) on the lower side (not shown) of the ear portion 22 passes through the connection wiring 25 and the branch wiring 26 to form each product region 21. As a result of power transmission to the surface pad 16a in the third conductive circuit C3 in the wiring board 1b, metal in the electrolytic plating solution is deposited on the surface.
On the other hand, the plating current supplied from the plating electrode 24 c and the plating electrode (24 d) on the lower side (not shown) of the ear portion 22 passes through the connection wiring 27 and the branch wiring 28 to form each product region 21. As a result of power transmission to the surface pad 16b in the fourth conductive circuit C4 in the wiring board 1b, metal in the electrolytic plating solution is deposited on the surface.

Therefore, a nickel plating bath and a gold plating bath (not shown) are provided on the multi-layer wiring board 20b while the electrode rods (not shown) are in contact with the inner wall surfaces of the plating electrodes 24a, (24b), 24c, (24d). In the case where electrolytic nickel plating and electrolytic gold plating are sequentially performed under the same plating conditions, the surface exposed to the outside of the surface pads 16a and 16b in each wiring board 1b has a uniform thickness of nickel layer and gold. A layer (metal coating, none of which is shown) can be coated. Moreover, it is possible to significantly reduce the difference in thickness between the wiring board 1b located on the peripheral side in the product area 21 and the wiring board 1b located on the center side in the product area 21. It is.
Therefore, according to the multi-cavity wiring board 20b, the effect (6) can be more reliably exhibited.

The present invention is not limited to the embodiments described above.
For example, the outer shapes of the front surface 3 and the back surface 4 in plan view of the wiring boards 1a and 1b may be rectangular or rectangular.
The plurality of sets of energizing circuits Cn provided on the wiring boards 1a and 1b may be three or more. In order to apply this form to the wiring board 1a, two or more first conduction circuits C1 may be disposed in parallel, or two or more second conduction circuits C2 may be disposed in parallel; Both the 1st and 2nd electricity supply circuit C1 and C2 may be arrange | positioned in parallel. In the case of such a form, the shapes of the plurality of surface pads may be square, circular, oval, or any different shape in plan view.

Furthermore, the wiring boards 1a and 1b and the wiring boards for multiple placements 20a and 20b may be made of a substrate body 2 in which three or more ceramic layers are laminated.
Further, the insulating material constituting the substrate body 2 of the wiring boards 1a and 1b and the wiring boards 20a and 20b for multiple mounting may be, for example, high temperature baking ceramic such as mullite or aluminum nitride, or low temperature baking ceramic such as glass-ceramic. The resin may be epoxy resin or polyimide resin.
Among the above, when the insulating material is made of glass-ceramic or the like, copper, a copper alloy, silver or a silver alloy is mainly applied to the surface pad, the inner layer wiring, etc. It is recommended to have the same circuit configuration as the third and fourth current-carrying circuits C3 and C4.

Furthermore, the substrate body 2 is a ceramic layer having a through hole of a truncated cone shape or a cylindrical shape at the center side in a rectangular frame shape in plan view or in plan view along the peripheral side of the surface 3 of the ceramic layer s1. Furthermore, it is good also as a form which has a cavity which makes a bottom face the 1st principal surface 3 in which it laminates and the surface pads 6a, 6b, 16a, and 16b are located. The substrate body 2 having such a cavity is also possible in the case where the insulating material is made of the glass-ceramic, resin or the like.
In addition, in the wiring substrate 1a, when a difference in electric resistance is concerned due to a difference in length of the current path between the first and second current circuits C1 and C2, etc., the entire thickness is the same. By making the thickness of each of the metal layers 12 and the thickness of the high electrical conductive layer 13 constituting the surface pads 6a and 6b different from each other, the difference in electrical resistance between the energizing circuits C1 and C2 is reduced. It is good.

  According to the present invention, the first main surface of the substrate main body has a plurality of surface pads on which electronic components are to be mounted, and the thicknesses of metal layers formed by plating are coated on the surfaces of the plurality of surface pads. By suppressing the variation, it is possible to reliably provide the wiring board with the improved mountability of the electronic component and the wiring board for multiple cavities having a plurality of the wiring boards.

1a, 1b ...................................... Wiring board 2 ...................................................... Main body 3 ...................... ............ First main surface 4 ...................................................... Second main surface 5 ...................... ........................ Sides 6a, 6b, 16a, 16b .......... Surface pads 7a to 7c ........................ Pattern wiring (inner layer wiring)
8a, 8b, 8p, 9a, 9b ..... Inner layer wiring 8ae, 8be, 9ae, 9be ........ Ends 11a, 11b ........................ External connection terminal 12 ... ...................................... Metal layer 13 ...................................... High electrical conductivity layers 18a, 18b, 19a, 19b ......... ...... Inner layer wiring 18ae, 18be, 19ae, 19be ... end portions 20a, 20b. ......... Product area 22 ......................................... Ears 24a to 24d ......................... Plating electrodes C1 to C4 ......... ........................... The energizing circuit

Claims (7)

The first main surface and the second main surface which are made of an insulating material and have a rectangular outer shape in plan view, and the opposing first main surface and second main surface, and four sides located between the first main surface and the second main surface A substrate body having
A plurality of surface pads formed on the first main surface of the substrate body;
A plurality of inner layer wires formed inside the substrate body;
The inner layer wiring has an end on the side surface of the substrate body,
The plurality of inner layer wirings and the plurality of surface pads form a plurality of sets of energization circuits, and the plurality of sets of energization circuits are electrically independent of each other, and
The conduction circuit is connected to the inner layer wiring through at least one surface pad.
A wiring board characterized by The surface pad includes a high electrical conductive layer having a lower electrical resistance than the conductor constituting the inner layer wiring.
The wiring board according to claim 1, characterized in that The surface pad comprises a metal layer formed on the first main surface of the substrate body, and the high electrical conductivity layer formed on the top surface of the metal layer and having a thickness greater than the thickness of the metal layer. ,
The wiring board according to claim 2, characterized in that: The plurality of sets of energization circuits cross each other when passing through the substrate body in plan view.
The wiring board according to any one of claims 1 to 3, characterized in that: The plurality of sets of energization circuits are two sets of energization circuits, and both ends of each of the two sets of energization circuits are individually exposed on a pair of opposing side surfaces or an adjacent pair of side surfaces in the substrate body. Yes,
The wiring board according to any one of claims 1 to 4, characterized in that: A plurality of external connection terminals individually connected to the plurality of sets of energization circuits are formed on the second main surface of the substrate body.
The wiring board according to any one of claims 1 to 5, characterized in that: A product area in which a plurality of wiring boards according to any one of claims 1 to 6 are arranged vertically and horizontally adjacent to each other in plan view, and an ear surrounding the periphery of the product area, the outer surface of the ear being A plurality of plating electrodes electrically connected individually to the plurality of energizing circuits for each of the wiring boards are formed.
A wiring board for a large number of units, characterized in that

Images