JP2019079865A - Electronic component - Google Patents

Abstract

To provide a compact electronic component in which the resistance is decreased between a terminal and a via electric wiring.SOLUTION: An electronic component 100 has multiple dielectric layers 11a-e composed of ceramic material, multiple conductor patterns 12b-e constituting at least a part of a circuit element, and multiple terminals 14 provided on the outer surface of the outermost dielectric layer, out of the multiple dielectric layers, including multiple conductor layers 14a, b, where the conductor layer in contact with the outer surface contains a metallic substance and an insulator material. The electronic component includes via wirings 13b-d penetrating the dielectric layers, other than the outermost dielectric layer out of the multiple dielectric layers, and electrically connecting at least two conductor patterns out of the multiple conductor patterns, and a via wiring 15 penetrating the outermost dielectric layer, electrically connecting at least one terminal with at least one conductor pattern, out of the multiple conductor patterns, and in which the first contact area in contact with the at least one terminal is larger than the cross sectional area in parallel with the outer surface of the via wiring.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an electronic component, for example, an electronic component in which a plurality of dielectric layers are stacked.

  Filters for removing unwanted interference are used in wireless communication terminals such as smart phones and mobile phones. It is known to use a laminate in which dielectric layers are laminated as a filter. It is known to use an LGA (Land Grid Array) having land electrodes on the lower surface of the laminate in order to miniaturize electronic components.

  It is known that the conductor pattern inside the laminate or the terminal outside the laminate includes a metal material and an insulator material (for example, Patent Documents 1 to 3). It is known to thicken via wiring in the stack (for example, Patent Documents 4 and 5). It is known to provide a plurality of wires for connecting the conductor pattern in the stacked body and the terminal outside the stacked body (for example, Patent Documents 6 and 7).

JP, 2009-170848, A JP 2004-55554 A JP, 2014-170874, A JP 2007-129048 A JP, 2015-41776, A JP 2017-59749 A JP, 2015-76567, A

  If the via wiring is thickened to reduce the contact resistance between the terminal and the via wiring, miniaturization becomes difficult.

  The present invention has been made in view of the above problems, and has an object to reduce the resistance and reduce the size between the terminal and the via wiring.

  The present invention relates to a plurality of dielectric layers formed of ceramic materials and laminated, and a plurality of conductors formed on the surface of one of the plurality of dielectric layers and constituting at least a part of a circuit element. A pattern, provided on the outer surface of the outermost dielectric layer of the plurality of dielectric layers, including one or more conductive layers, on the outer surface of the one or more conductive layers The conductive layer in contact passes through at least one of the plurality of terminals including the metal material and the insulator material, and at least one of the plurality of dielectric layers other than the outermost dielectric layer, The first via wiring electrically connecting between at least two conductor patterns of the conductor patterns, the outermost dielectric layer, and at least one of the one or more terminals and the terminal Multiple conductor patterns A second contact area electrically connected to at least one conductor pattern of the first via wiring and having a first contact area contacting the at least one terminal larger than a cross-sectional area parallel to the outer surface of the first via interconnection And a wiring.

  In the above configuration, the at least one terminal may include an input terminal to which a high frequency signal is input.

  In the above configuration, the one or more terminals include a ground terminal, and the electronic component penetrates the outermost dielectric layer to electrically connect the ground terminal and at least one of the plurality of conductor patterns. The third via wiring may be configured to have a third contact wiring that is connected in a row and that is in contact with the ground terminal is smaller than the first contact area.

  The present invention relates to a plurality of dielectric layers formed of ceramic materials and laminated, and a plurality of conductors formed on the surface of one of the plurality of dielectric layers and constituting at least a part of a circuit element. A pattern, provided on the outer surface of the outermost dielectric layer of the plurality of dielectric layers, including one or more conductive layers, on the outer surface of the one or more conductive layers The conductive layer in contact passes through at least one of the plurality of terminals including the metal material and the insulator material, and at least one of the plurality of dielectric layers other than the outermost dielectric layer, The first via wiring electrically connecting between at least two of the conductor patterns among the conductor patterns, and the outermost dielectric layer are penetrated, and an input to which a high frequency signal is inputted among the one or more terminals Terminal and the plurality of leads A plurality of second via wire connecting the one conductor patterns for forming a capacitor in parallel with each other within the body pattern, which is an electronic component comprising a.

  In the above configuration, a first contact area in which the plurality of second via wires and the input terminal are in contact with each other may be substantially equal to a cross-sectional area parallel to the outer surface of the first via wire.

  In the above configuration, the one or more terminals include a ground terminal, and the electronic component penetrates the outermost dielectric layer, and at least one conductor of the ground terminal and the plurality of conductor patterns. A second contact area electrically connected to the pattern and in contact with the ground terminal may be provided with a third via wiring substantially equal to the first contact area.

  In the above configuration, the insulator material may include the same material as the material included in the outermost dielectric layer.

  In the above configuration, the insulator material may be at least one of titanium oxide, zirconium oxide and aluminum oxide.

  In the above configuration, the circuit element may include an inductor and / or a capacitor.

  In the above configuration, the one or more terminals include an input terminal to which a high frequency signal is input and an output terminal to output a high frequency signal, and the circuit element is a filter connected between the input terminal and the output terminal. The input terminal may be connected to an output of a power amplifier, and the output terminal may be connected to an antenna.

  According to the present invention, the resistance between the terminal and the via wiring can be reduced and the size thereof can be reduced.

FIG. 1 is a circuit diagram of the electronic component according to the first embodiment. FIG. 2 is a perspective view of the electronic component according to the first embodiment. 3 (a) and 3 (b) are cross-sectional views of the electronic component according to the first embodiment. FIG. 4 is a disassembled perspective view of the electronic component according to the first embodiment. FIG. 5A and FIG. 5B are cross-sectional views of the electronic component according to Comparative Example 1. FIG. FIG. 6 is a view showing the resistance value and the life with respect to D2 / D1 in Example 1 and Comparative Example 1. FIG. 7 is a diagram showing the lifetime with respect to the input power in Example 1 and Comparative Example 1. FIGS. 8A and 8B are cross-sectional views of the electronic component according to the first modification of the first embodiment. FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment. FIGS. 10A and 10B are cross-sectional views of the electronic component according to the second embodiment. FIG. 11 is a cross-sectional view of the electronic component according to the first modification of the second embodiment. FIG. 12 is a circuit diagram of a front end circuit according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  A band pass filter (BPF) will be described as an example of the first embodiment. FIG. 1 is a circuit diagram of the electronic component according to the first embodiment. As shown in FIG. 1, the BPF 108 has an input terminal Tin, an output terminal Tout, a ground terminal Tgnd, capacitors C1 to C9, and strip lines L1 to L5. The capacitors C5 to C7 are connected in series between the input terminal Tin and the output terminal Tout.

  Capacitors C8 and C9 are connected in series between input terminal Tin and output terminal Tout, and are connected in parallel with capacitors C5 to C7. The capacitors C1 to C4 are connected between the input terminal T1, the nodes N1 and N2, the output terminal Tout, and the ground terminal Tgnd, respectively. The strip lines L1 and L4 are connected between the input terminal Tin and the output terminal Tout, respectively, and the ground terminal Tgnd. Strip lines L2 and L3 are connected between nodes N1 and N2 and node N3, respectively. The strip line L5 is connected between the node N3 and the ground terminal Tgnd.

  Among the high frequency signals input to the input terminal Tin, the BPF 108 passes signals in the passband to the output terminal Tout, and suppresses signals in other frequency bands.

  FIG. 2 is a perspective view of the electronic component according to the first embodiment, and FIGS. 3A and 3B are cross-sectional views. As shown in FIG. 2, the electronic component 100 has a laminate 10. Terminals 14 are provided on the lower surface of the laminate 10. The terminals 14 are, for example, an input terminal Tin, an output terminal Tout, and a ground terminal Tgnd.

  As shown in FIGS. 3A and 3B, in the laminate 10, a plurality of dielectric layers 11a to 11e made of a ceramic material are stacked. Conductor patterns 12b to 12e are provided on the top surfaces of the dielectric layers 11b to 11e, respectively. A terminal 14 is provided on the lower surface of the dielectric layer 11 e. The terminal 14 is, for example, LGA, and is provided only in the lower surface of the dielectric layer 11 e. The terminal 14 includes a conductor layer 14a in contact with the lower surface of the dielectric layer 11e, and a conductor layer 14b provided below the conductor layer 14a. Via wirings 13b to 13d and 15 are provided to penetrate dielectric layers 11b to 11e, respectively. Via interconnections 13 b to 13 d and 15 have, for example, a cylindrical shape. Via interconnections 13b to 13d are connected to at least one of conductor patterns 12b to 12e. The via wiring 15 connects at least one of the conductor patterns 12 b to 12 e to the terminal 14. The diameter D2 of the via wire 15 is larger than the diameter D1 of the via wires 13b to 13d.

  FIG. 4 is a disassembled perspective view of the electronic component according to the first embodiment. FIGS. 3A and 3B correspond to the cross section A-A and the cross section B-B in FIG. 4, respectively. In FIG. 4, connections of via wirings 13 b to 13 d and 15 are shown by broken lines. As shown in FIG. 4, the conductor pattern 12a serves as a direction identification mark. The strip lines L1 to L4 are formed by the conductor pattern 12b. Strip line L5 is formed by via interconnections 13b to 13d. Capacitors C5 to C9 are formed of conductor patterns 12c and 12d sandwiching dielectric layer 11c. Capacitors C1 to C4 are formed of conductor patterns 12d and 12e sandwiching dielectric layer 11d.

The dielectric layers 11a to 11e are made of a ceramic material and contain, for example, oxides of Si, Ca and Mg (for example, CaMgSi ₂ O ₆ which is a diopside crystal) as main components. The main components of the dielectric layers 11a to 11e may be oxides other than Si, Ca and / or Mg. Furthermore, the dielectric layers 11a to 11e may contain at least one oxide of Ti, Zr and Al as an insulator material.

  Conductor patterns 12a to 12e, via interconnections 13b to 13d and 15, and conductor layer 14a are metal layers including, for example, Ag, Pd, Pt, Cu, Ni, Au, Au-Pd alloy or Ag-Pt alloy. . Conductor layer 14a includes an insulator material in addition to the above-described metal material. The insulator material is, for example, titanium oxide, zirconium oxide and / or aluminum oxide, and is, for example, the same material as at least a part of the material included in the dielectric layers 11a to 11e. The conductor layer 14b is, for example, a Ni film and a Sn film. The Sn film is a solder layer for mounting the electronic component 100 on a motherboard or the like, and the Ni film is a barrier layer for suppressing interdiffusion between the solder layer and the conductor layer 14a.

  The laminate 10 is manufactured, for example, as follows. The dielectric layers 11a to 11e are produced, for example, using a doctor blade method. Via interconnections 13b to 13d and 15 are formed to penetrate dielectric layers 11b to 11e. For example, via holes penetrating the dielectric layers 11a to 11e are formed by laser beam irradiation. Via interconnections 13b to 13d and 15 are formed in the via holes using the squeegee method or the like. Conductor patterns 12a to 12e and a conductor layer 14a are formed on the surfaces of dielectric layers 11a to 11e. The conductor patterns 12a to 12e and the conductor layer 14a are formed by using, for example, a screen printing method or a transfer method. The dielectric layers 11 a to 11 e are stacked to form a stacked body 10. For example, heat pressure or an adhesive is used for laminating the dielectric layers 11a to 11e. The laminate 10 is fired, for example, at 700 ° C. or higher. Thereby, the dielectric layers 11a to 11e become sintered bodies. Conductor layer 14b is formed under conductor layer 14a. For example, plating such as barrel plating is used to form the conductor layer 14b.

  As described in Patent Document 1, when the conductor layer 14a does not contain an insulator material, the bonding strength between the conductor layer 14a and the dielectric layer 11e is low. Therefore, the terminal 14 is easily peeled off from the dielectric layer 11 e during sintering of the laminate 10. In addition, a crack occurs in the terminal 14 and / or the dielectric layer 11 e. When the conductor layer 14a contains a metal material and an insulator material, peeling and / or cracking of the terminal 14 can be suppressed. In particular, when the insulator material included in the conductor layer 14a is the same as at least a part of the material included in the dielectric layers 11a to 11e, the bonding strength between the conductor layer 14a and the dielectric layer 11e can be increased. As an insulator material, titanium oxide, zirconium oxide and / or aluminum oxide are preferable.

Comparative Example 1
FIG. 5A and FIG. 5B are cross-sectional views of the electronic component according to Comparative Example 1. FIG. As shown in FIGS. 5A and 5B, in the electronic component 110, the diameter D2 of the via wiring 13e penetrating the dielectric layer 11e is substantially the same as the diameter D1 of the via wirings 13b to 13d. . The other configuration is the same as that of the first embodiment, and the description is omitted.

  In Comparative Example 1, since the conductor layer 14a contains an insulator material, the electrical connection between the conductor layer 14a and the via interconnection 13e is inhibited. Thereby, the contact resistance value between the via wire 13e and the terminal 14 is increased. For example, when a high power high frequency signal is input to the input terminal Tin, if the contact resistance between the via wiring 13e and the terminal 14 is high, heat may be generated, and there is a possibility that the vicinity of the bonding portion between the via wiring 13e and the terminal 14 may be fused. is there. On the other hand, when the diameter of the via wires 13b to 13e is increased, the electronic component is increased in size. Thus, it is difficult to miniaturize the electronic component and to lower the contact resistance between the terminal 14 and the via wiring 13e.

[Comparison of Example 1 and Comparative Example 1]
In the first embodiment, the contact area between the via wiring 15 penetrating the dielectric layer 11 e and the conductor layer 14 a is made larger than the diameters of the other via wirings 13 b to 13 d. As a result, the electronic component can be miniaturized, and the contact resistance between the terminal 14 and the via wire 13e can be reduced.

  In Example 1 and Comparative Example 1, the resistance between the input terminal Tin and the output terminal Tout was measured. The resistance value to D2 / D1 was calculated using the measured resistance value. The resistance value is resistance via the via wirings 13b to 13d and 15 and the strip line L1. In addition, the life of the electronic component was measured when a high frequency signal was input to the input terminal Tin. The lifetime was set to 175 ° C. at the environmental temperature, and a high power high frequency signal was applied to the input terminal Tin, and the time until the electronic component was destroyed was taken.

Each condition is as follows.
Materials of the dielectric layers 11a to 11e: Oxides of Si, Ca and Mg as main components, and 3 wt% of TiO ₂ (in terms of oxide).
Thickness of dielectric layers 11a to 11e: 30 μm, 400 μm, 10 μm, 10 μm and 30 μm respectively
Material of the conductor pattern 12b: Ag is a main component, and 13% by weight (in terms of oxide) of TiO ₂ is included.
Dimension of conductor pattern 12b of strip line L1: length: 1400 μm, width: 100 μm, thickness: 20 μm
Materials of via wirings 13b to 13d and 15: Ag is a main component.
Diameter D1 of via wiring 13b to 13d: 65 μm
Diameter D2 of via wiring 15 or 13 e: Example 1: 120 μm, Comparative Example 1: 65 μm
Material of the conductor layer 14 a: Ag is a main component, and 13 wt% (as oxide conversion) of TiO ₂ is included.
Thickness of conductor layer 14a: 10 μm
Frequency of high frequency signal: 3800 MHz
High frequency signal power: 39.98 dBm

  FIG. 6 is a view showing the resistance value and the life with respect to D2 / D1 in Example 1 and Comparative Example 1. In FIG. 6, the solid line shows the calculated resistance value, and the dot shows the measurement result of the life. As shown in FIG. 6, the resistance value decreases as D2 / D1 increases. This is considered to be because the contact resistance between the conductor layer 14 a and the via wiring 15 is lowered. The life of Comparative Example 1 is about 2 hours, but in Example 1 is about 16 hours.

  FIG. 7 is a diagram showing the lifetime with respect to the input power in Example 1 and Comparative Example 1. Dots are measurement points, and straight lines are approximate lines. As shown in FIG. 7, the life of Example 1 is longer than that of Comparative Example 1. When the input power, which is a practical power, is 35 dBm, Example 1 has a two-digit life longer than Comparative Example 1. Thus, by reducing the contact resistance between the conductor layer 14a and the via wiring 15, the life when a high power high frequency signal is input to the input terminal Tin is extended.

Modification 1 of Embodiment 1
FIGS. 8A and 8B are cross-sectional views of the electronic component according to the first modification of the first embodiment. As shown in FIG. 8A, in the electronic component 101, the via wiring 15 contacts the input terminal Tin and the output terminal Tout, and the via wiring 13e contacts the ground terminal Tgnd. The diameter D3 of the via wiring 13e is smaller than the diameter D2 of the via wiring 15 and is about the same as the diameter D1 of the via wirings 13b to 13d. It is mainly a terminal through which a high frequency signal passes to be required to reduce the resistance. Therefore, the diameter D2 of the via wiring 15 in contact with the input terminal Tin and the output terminal Tout may be larger than D1 and D3. The other configuration is the same as that of the first embodiment, and the description is omitted.

  As shown in FIG. 8B, in the electronic component 102, the via wiring 15 contacts the input terminal Tin, and the via wiring 13e contacts the output terminal Tout and the ground terminal Tgnd. What is destroyed by the high power high frequency signal is near the input terminal Tin. Therefore, the diameter D2 of the via wiring 15 in contact with the input terminal Tin may be larger than the diameter D1 of the via wirings 13b to 13d and the diameter D3 of the via wiring 13e in contact with the ground terminal Tgnd and the output terminal Tout. The other configuration is the same as that of the first embodiment, and the description is omitted.

Modification 2 of Embodiment 1
FIG. 9 is a cross-sectional view of the electronic component according to the second modification of the first embodiment. As shown in FIG. 9, in the electronic component 103, the via wiring 15 has a truncated cone shape in which the diameter on the terminal 14 side becomes large. As described above, when the contact area between the conductor layer 14a and the via wiring 15 is increased, the shape of the via wiring 15 can be arbitrarily selected.

  According to the first embodiment and its modification, each of the conductor patterns 12b to 12e is formed on the surface of one of the plurality of dielectric layers 11b to 11e, and provided in the laminate 10 Configure at least a part of (for example, a capacitor and / or an inductor). The one or more terminals 14 are the lower surface (outside surface, that is, the other surface) of the dielectric layer 11 e (the outermost dielectric layer, ie, the outermost dielectric layer in the stacking direction of the dielectric layers 11 a to 11 e). It is provided on the side opposite to the side in contact with the dielectric layer 11d) and includes one or more conductor layers 14a and 14b. Conductor layer 14a in contact with the lower surface of dielectric layer 11e includes a metal material and an insulator material. The via wires 13b to 13d (first via wires) penetrate at least one of the dielectric layers 11b to 11d other than the dielectric layer 11e, and at least two of the plurality of conductor patterns 12b to 12e conduct electricity. Electrically connect between body patterns.

  The via wiring 15 (second via wiring) penetrates the dielectric layer 11 e and electrically connects the terminal 14 and at least one of the conductor patterns 12 b to 12 e. The first contact area of the via interconnection 15 in contact with the terminal 14 is larger than the sectional area of the via interconnections 13 b to 13 d (the sectional area in the plane parallel to the lower surface of the dielectric layer 11 e).

  Thereby, the contact resistance between the terminal 14 and the via wiring 15 can be reduced. In addition, since the via wirings 13b to 13d can be reduced, the electronic component can be miniaturized.

  The via wiring 15 may electrically connect at least one terminal 14 of the one or more terminals 14 with at least one conductor pattern of the plurality of conductor patterns. Thereby, the contact resistance between the via wire 15 and the terminal 14 can be suppressed.

  As in the first embodiment, the via wiring 15 may be connected to all the terminals 14. Thereby, the resistance between all the terminals 14 and the circuit elements can be reduced. The first contact area between the via wire 15 and the terminal 14 is preferably 1.5 times or more of the cross-sectional area of the via wires 13 b to 13 d, more preferably 2 times or more, and still more preferably 4 times or more.

  As in the first embodiment and the first modification, the terminal 14 in contact with the via wire 15 includes the input terminal Tin to which a high frequency signal is input. Thereby, destruction of the electronic component can be suppressed.

  When the cross sectional areas of the via wirings 13b to 13d and the contact areas of the via wirings 15 vary, the smallest contact area among the contact areas of the via wirings 15 in contact with the input terminal Tin is the cross sectional area of the via wirings 13b to 13d. It should be larger than the largest cross-sectional area. The smallest contact area is preferably 1.5 times or more of the largest cross-sectional area, preferably 2 times or more, and more preferably 4 times or more.

  As in the first modification of the first embodiment, the via wire 13e (third via wire) penetrates the dielectric layer 11e, and at least one conductor pattern of the ground terminal Tgnd and the plurality of conductor patterns 12b to 12e. And electrically connected. The second contact area where the via interconnection 13e contacts the ground terminal Tgnd is smaller than the first contact area where the via interconnection 15 contacts the input terminal Tin. The ground terminal Tgnd is a terminal 14 to which large power is not easily applied. Therefore, the contact area of the via interconnection 13e in contact with the ground terminal Tgnd is reduced. This enables downsizing of the electronic component.

  The contact area of the via wiring 13e with the terminal 14 is substantially the same as the cross-sectional area of the via wirings 13b to 13d and the manufacturing error. The smallest first contact area of the first contact area of the via wiring 15 in contact with the input terminal Tin is the second contact area of the via wiring 13e in contact with the terminal 14 (the ground terminal Tgnd and / or the output terminal Tout). It may be larger than the largest second contact area. The smallest first contact area is preferably 1.5 times or more of the largest second contact area, preferably 2 times or more, and more preferably 4 times or more.

  FIGS. 10A and 10B are cross-sectional views of the electronic component according to the second embodiment. As shown in FIGS. 10A and 10B, in the electronic component 104, the diameter D2 of the via wiring 13e which penetrates the dielectric layer 11e and is connected to the input terminal Tin and the output terminal Tout is the via wiring 13b. To 13d and the manufacturing error is substantially the same. The diameter D2 is substantially the same as the diameter D3 of the via wiring 13e which penetrates the dielectric layer 11e and is connected to the ground terminal Tgnd.

  The plurality of via wirings 15a (via wirings in which the via wirings 13d and 13e are connected) electrically connect the input terminal Tin to the electrode 16a of the capacitor C5 formed of the conductor pattern 12d. The plurality of via wires 15a electrically connect the output terminal Tout to the electrode 16b of the capacitor C7 formed of the conductor pattern 12d. The plurality of via wires 15a are connected, for example, in the vicinity of four vertexes of a rectangular shape of the input terminal Tin and the output terminal Tout each having a rectangular planar shape, for example. The other configuration is the same as that of the first embodiment, and the description is omitted.

  In the second embodiment, a plurality of via wirings 15a connecting the input terminal Tin and the electrode 16a are provided. A plurality of via wires 15a for connecting the output terminal Tout and the electrode 16b are provided. As a result, the contact resistance between the via wire 15a and the input terminal Tin and the output terminal Tout can be made lower than that in Comparative Example 1. Therefore, even if a high frequency signal of high power is input to the input terminal Tin, destruction of the vicinity of the input terminal Tin can be suppressed.

Modification 1 of Embodiment 2
FIG. 11 is a cross-sectional view of the electronic component according to the first modification of the second embodiment. As shown in FIG. 11, in the electronic component 105, there is one via wire 13e connected to the output terminal Tout. The other configuration is the same as that of the first embodiment, and the description thereof is omitted. As in the first modification of the second embodiment, the number of via wires 13e connected to the output terminal Tout is at least better than the number of via wires 13e connected to the input terminal Tin.

  According to the first embodiment and its modification, the plurality of via wires 13e penetrate the dielectric layer 11e, and one of the conductor patterns 12d forming the capacitor among the input terminal Tin and the plurality of conductor patterns 12b to 12e. (Electrodes 16a) are connected in parallel with each other. Thus, the plurality of via wires 13e may be connected to the input terminal Tin.

  The first contact area where the plurality of via wires 15a and the input terminal Tin are in contact with each other is substantially equal to the cross-sectional area of the via wires 13b to 13d and the manufacturing error. Thereby, the diameter of the via wiring 15a can be made substantially the same as the diameter of the via wirings 13b to 13d. Thus, the manufacturing process can be simplified. In addition, the electronic components can be miniaturized.

  A second contact area in which the via wiring 13e electrically connecting the ground terminal Tgnd and at least one conductor pattern of the conductor patterns 12b to 12e contacts the ground terminal Tgnd is such that the via wiring 15a contacts the input terminal Tin It is approximately equal to the first contact area and the manufacturing error. Thus, the diameter of the via wiring 15a can be made substantially the same as the diameter of the via wiring 13e. Thus, the manufacturing process can be simplified. In addition, the electronic components can be miniaturized.

  In Examples 1 and 2 and their variations, the insulator material included in the conductor layer 14a includes the same material as the material included in the dielectric layer 11e. Thereby, the bonding strength between the terminal 14 and the dielectric layer 11 e can be increased.

  The insulator material contained in the conductor layer 14a is preferably at least one of titanium oxide, zirconium oxide and aluminum oxide. Thereby, the bonding strength between the terminal 14 and the dielectric layer 11 e can be further increased.

  The insulator material contained in the dielectric layers 11a to 11e is preferably 0.1% by weight or more and 50% by weight or less, and more preferably 1% by weight or more and 10% by weight or less in terms of oxide. The insulator material contained in the conductor layer 14a is preferably 0.1 wt% to 66 wt% in terms of oxide, and more preferably 1 wt% to 20 wt%.

  The conductor layer 14b may include, for example, the same metal material as the conductor layer 14a. In this case, the conductor layer 14b does not contain an insulator material, or the concentration of the insulator material of the conductor layer 14b is lower than the concentration of the insulator material of the conductor layer 14a. Thereby, the resistance of the terminal 14 can be reduced.

  Also, the conductor layer 14b may include a solder layer like a Ni film and a Sn film.

  Although five dielectric layers 11a to 11e have been described, the number of dielectric layers 11a to 11e can be set arbitrarily. Although capacitors and strip lines (or inductors) have been described as examples of circuit elements included in the laminate 10, the circuit elements may be only capacitors or only inductors. Although a band pass filter has been described as an example of the electronic component, the electronic component may be a filter such as a high pass filter or a low pass filter. The electronic component may be a multiplexer such as a diplexer, duplexer, triplexer or quadplexer.

  The third embodiment is an example of a circuit in which the first and second embodiments and their variations are used. FIG. 12 is a circuit diagram of a front end circuit according to a third embodiment. As shown in FIG. 12, the front end circuit 106 includes a high pass filter (HPF) 31, a band pass filter (BPF) 32, a low pass filter (LPF) 33, a switch 34, a duplexer 37, a power amplifier (PA) 38 and a low noise amplifier (LNA) 39 is provided.

  The antenna 30 is connected to the antenna terminal Ta. One end of each of the HPF 31, the BPF 32, and the LPF 33 is connected in common to the antenna terminal Ta. A switch 34 is connected to the other end of each of the HPF 31, the BPF 32 and the LPF 33. The HPF 31 passes high band high frequency signals and suppresses signals of other frequencies. The BPF 32 passes high frequency signals in the middle band lower in frequency than the high band and suppresses signals in other frequencies. The LPF 33 passes a low band high frequency signal whose frequency is lower than that of the middle band and suppresses signals of other frequencies.

  The common terminal Na of the plurality of duplexers 37 is connected to the switch 34. The switch 34 selects one of the plurality of duplexers 37 and connects it to the other ends of the HPF 31, the BPF 32 and the LPF 33. The duplexer 37 has a transmission filter 35 which is a BPF and a reception filter 36 which is a BPF. The transmit filter 35 and the receive filter 36 are connected to the PA 38 and the LNA 39, respectively.

  The transmission signal input to the transmission terminal Tx is amplified by the PA 38. Among the amplified signals, the transmission filter 35 outputs a high frequency signal in the transmission band to the common terminal Na to suppress signals of other frequencies. The filtered transmission signal passes through the switch 34 and the HPF 31, BPF 32 or LPF 33 and is output from the antenna 30.

  The received signal input to the antenna 30 passes through the HPF 31, the BPF 32 or the LPF 33, and the switch 34. Among the high frequency signals input to the common terminal Na, the reception filter 36 passes signals in the reception band and suppresses signals of other frequencies. The filtered reception signal is amplified by the LNA 39 and output to the reception terminal Rx.

  The first and second embodiments and their variations are used, for example, for at least one of the BPF 32, the transmission filter 35, and the reception filter 36. In particular, a high power high frequency signal of 30 dBm or more is applied to the BPF 32 and the transmission filter 35. Therefore, filters in which the input terminal Tin is connected to the output of the power amplifier and the output terminal Tout is connected to the antenna 30 are considered as the first and second embodiments and their modifications. Thereby, it is possible to suppress that the electronic component is broken or the life is shortened by the high power high frequency signal.

  As mentioned above, although the embodiment of the present invention has been described in detail, the present invention is not limited to such a specific embodiment, and various modifications may be made within the scope of the present invention described in the claims. Changes are possible.

DESCRIPTION OF SYMBOLS 10 laminated body 11a-11e dielectric material layer 12a-12e conductor pattern 13b-13e, 15, 15a via wiring 14 terminal 14a, 14b conductor layer 16 electrode

Claims (10)

Multiple dielectric layers stacked of ceramic material,
A plurality of conductor patterns each formed on a surface of one of the plurality of dielectric layers and constituting at least a part of a circuit element;
A conductor provided on the outer surface of the outermost dielectric layer of the plurality of dielectric layers, including one or more conductive layers, in contact with the outer surface of the one or more conductive layers The layer comprises one or more terminals comprising a metallic material and an insulator material
First to penetrate at least one dielectric layer other than the outermost dielectric layer among the plurality of dielectric layers, and electrically connect at least two conductive patterns of the plurality of conductive patterns. With via wiring,
The at least one terminal of the one or more terminals and the at least one conductor pattern of the plurality of conductor patterns are electrically connected through the outermost dielectric layer; A second via wiring whose first contact area in contact with the terminal is larger than a cross-sectional area parallel to the outer surface of the first via wiring;
Electronic components comprising   The electronic component according to claim 1, wherein the at least one terminal includes an input terminal to which a high frequency signal is input. The one or more terminals include a ground terminal,
The electronic component penetrates the outermost dielectric layer, electrically connects the ground terminal and at least one of the plurality of conductor patterns, and a second contact area contacting the ground terminal is the second contact area. The electronic component according to claim 2, further comprising a third via wiring smaller than the first contact area. Multiple dielectric layers stacked of ceramic material,
A plurality of conductor patterns each formed on a surface of one of the plurality of dielectric layers and constituting at least a part of a circuit element;
A conductor provided on the outer surface of the outermost dielectric layer of the plurality of dielectric layers, including one or more conductive layers, in contact with the outer surface of the one or more conductive layers The layer comprises one or more terminals comprising a metallic material and an insulator material
First to penetrate at least one dielectric layer other than the outermost dielectric layer among the plurality of dielectric layers, and electrically connect at least two conductive patterns of the plurality of conductive patterns. With via wiring,
The outermost dielectric layer is penetrated, and an input terminal to which a high frequency signal is input among the one or more terminals and one conductor pattern forming a capacitor among the plurality of conductor patterns are connected in parallel to each other Multiple second via wires, and
Electronic components comprising   5. The electronic component according to claim 4, wherein a first contact area where each of the plurality of second via wires and the input terminal contact each other is substantially equal to a cross-sectional area parallel to the outer surface of the first via wire. The one or more terminals include a ground terminal,
The electronic component penetrates the outermost dielectric layer, electrically connects the ground terminal and at least one conductor pattern of the plurality of conductor patterns, and contacts the ground terminal. The electronic component according to claim 5, further comprising a third via wiring having a contact area substantially equal to the first contact area.   The electronic component according to any one of claims 1 to 6, wherein the insulator material comprises the same material as the material contained in the outermost dielectric layer.   The electronic component according to claim 7, wherein the insulator material is at least one of titanium oxide, zirconium oxide and aluminum oxide.   The electronic component according to any one of claims 1 to 8, wherein the circuit element includes an inductor and / or a capacitor. The one or more terminals include an input terminal to which a high frequency signal is input and an output terminal to which a high frequency signal is output,
The circuit element includes a filter connected between the input terminal and the output terminal.
The input terminal is connected to the output of the power amplifier,
The electronic component according to claim 1, wherein the output terminal is connected to an antenna.

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