JP2019071160A - Nonvolatile memory inspection method and integrated circuit device - Google Patents

Abstract

To inspect a nonvolatile memory without causing deterioration of normal memory cells due to repeated rewriting of data.SOLUTION: A nonvolatile memory inspection method, which is a method for inspecting a nonvolatile memory including a memory cell for which a transistor having a control gate, floating gate, source, and drain is provided, includes: a step S11 for bringing the memory cell into an erased state; a step S12 for bringing the drain in the transistor of the memory cell into a floating state, and applying a first potential and second potential to the control gate and source, respectively; a step S13 for reading data from the memory cell; and a step S14 for determining whether or not the memory cell is normal or defective on the basis of the data read from the memory cell.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a method of inspecting an electrically rewritable non-volatile memory. Furthermore, the present invention relates to an integrated circuit device etc. incorporating such non-volatile memory.

  In recent years, electrically rewritable nonvolatile memories such as flash memories and electrically erasable programmable read-only memories (EEPROMs) and integrated circuit devices incorporating such nonvolatile memories are widely used. When manufacturing or using such a non-volatile memory or integrated circuit device, a memory cell (hereinafter referred to as a "defective memory cell") which becomes defective due to repeated rewriting to guarantee the normal operation of the non-volatile memory It is necessary to test non-volatile memory for the presence or absence of

  If defective memory cells can be identified in inspection of nonvolatile memory, defective memory cells are replaced with redundant memory cells, or if the number of defective memory cells is within a predetermined range, error correction etc. are performed. The normal operation of the non-volatile memory can be secured. Alternatively, when the number of defective memory cells exceeds a predetermined range, it can be recognized that the lifetime of the non-volatile memory has expired.

  When testing a non-volatile memory, it is difficult to identify a defective memory cell based on initial characteristics, and therefore, rewriting of data is actually repeated on the memory cell to determine a defective memory cell. It was However, if data rewriting is repeatedly performed on a memory cell, a long time is required for inspection, and the lifetime is reduced due to deterioration of a normal memory cell (threshold fluctuation of a transistor storing data in the memory cell). It will invite you. Therefore, it is desirable to inspect non-volatile memory without repeatedly rewriting data in the memory cell.

  As a related technology, Patent Document 1 efficiently determines a memory cell that may cause a disturb phenomenon in which the threshold voltage of a memory cell other than the selected memory cell changes, and determines whether it is a defective product or not. A test method of a semiconductor memory device is disclosed for the purpose of efficient determination. This test method is a test method of a semiconductor memory device provided with a plurality of memory cells, in which predetermined terminals of the plurality of memory cells have the same pulse voltage of the same or similar time width as the read time of the memory cells. The phase of applying for a predetermined period of time, the phase of reading data of each memory cell after voltage application, comparing with the initial data of the memory cell before voltage application, and the memory whose data do not match before and after voltage application Determining the cell as a memory cell in which a disturb occurs.

  A BIST (built-in self test) module 15 shown in FIG. 2 of Patent Document 1 receives, from the control circuit, data on pulse width, voltage amplitude and pulse number (application time) in SPD (short pulse disturb) stress test. , Generate a pulse voltage corresponding to the received data. The BIST module 15 supplies the generated pulse voltage to the X decoder 12 to apply the pulse voltage to the gate terminals of all the memory cells 21 almost simultaneously (simultaneously). At this time, the BIST module 15 controls the Y decoder 13 so that the source and drain terminals of all the memory cells 21 become 0V.

  At that time, a pulse voltage that alternately repeats “L” level (0 V) and “H” level (Vpp) in several μs is used, and the application time is, for example, about 2 hours. The test voltage Vpp is a voltage (for example, 10 V) twice as high as the voltage used for writing or reading data of the memory cell 21.

Unexamined-Japanese-Patent No. 2006-351088 (Paragraphs 0006-0007, 0020, 0026-0027, FIG. 2)

  Since the test method of Patent Document 1 applies a pulse voltage of high voltage between the gate terminal and the source terminal of the memory cell 21 and between the gate terminal and the drain terminal, there is a concern about the deterioration of the normal memory cell. Ru. Moreover, since the test method of Patent Document 1 applies a high voltage only to the gate terminal, it detects electron leakage to the gate terminal due to a defect in the gate oxide film and electron injection to the floating gate due to a defect in the tunnel oxide film. Since the source and drain terminals are maintained at 0 V, a defect in which a leak current flows between the impurity diffusion region of the transistor storing data in the memory cell 21 and the semiconductor substrate or well is detected. You can not do it.

  Therefore, in view of the above point, a first object of the present invention is to enable inspection of a non-volatile memory without causing deterioration of a normal memory cell due to repeated data rewriting. A second object of the present invention is to enable detection of a defect in which a leak current flows between an impurity diffusion region of a transistor storing data in a memory cell and a semiconductor substrate or well. Furthermore, a third object of the present invention is to provide an integrated circuit device or the like incorporating such non-volatile memory.

  The present invention was made to solve at least a part of the above-mentioned problems. A method of testing a non-volatile memory according to one aspect of the present invention is a method of testing a non-volatile memory including a memory cell provided with a transistor having a control gate, a floating gate, a source, and a drain. Step (a) to put the memory into the erased state, step (b) to put the drain in the floating state and apply the first potential and the second potential to the control gate and the source, respectively, The method comprises: (c) reading data from the cell; and (d) determining whether the memory cell is normal or defective based on the data read from the memory cell.

  According to the method of testing a non-volatile memory according to one aspect of the present invention, the memory cell is in the erased state, the drain of the memory cell transistor is in the floating state, and the first potential is applied to the control gate and the source. In the defective memory cell, for example, a leak current flows in a defect leak path existing between the drain and the semiconductor substrate or well and hot carriers are generated by performing a test in which the second potential and the second potential are respectively applied. The threshold voltage of the transistor changes. On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change. Therefore, by determining whether the memory cell is normal or defective based on the data read from the memory cell after the test, it is possible to prevent the deterioration of the normal memory cell due to repeated data rewriting. Nonvolatile memory can be examined.

  Here, the step (c) applies the third potential and the reference potential to the control gate and the source respectively to the memory cell transistor, and reads data from the memory cell based on the magnitude of the drain current. It may be included. Regarding the setting of the potentials, when the memory cell transistor is an N-channel transistor, it is desirable that the first potential is set higher than the third potential and the second potential is set higher than the reference potential. . On the other hand, when the transistor of the memory cell is a P-channel transistor, it is desirable that the first potential is set lower than the third potential and the second potential is set lower than the reference potential. As a result, in step (b), a leak current can be supplied to the transistor of the defective memory cell to generate hot carriers, and the threshold voltage of the transistor can be changed.

  Step (a) includes putting the drain in the floating state and applying the reference potential and the fourth potential to the control gate and the source, respectively, to put the memory cell into the erased state with respect to the memory cell transistor. But it is good. Regarding the setting of the potential, when the transistor of the memory cell is an N-channel transistor, it is desirable that the first potential and the second potential be set to the fourth potential or more. On the other hand, when the transistor of the memory cell is a P-channel transistor, it is desirable that the first potential and the second potential be set equal to or lower than the fourth potential. As a result, in step (b), a large leak current can be supplied to the transistor of the defective memory cell to generate sufficient hot carriers, thereby shortening the test time.

  Further, step (d) may include determining that the memory cell is defective if the data read from the memory cell is different from the data in the erased memory cell. Since the memory cell is in the erased state in step (a), when data different from the data in the memory cell in the erased state is read, the threshold voltage of the transistor is changed due to leakage current in step (b). It can be determined that the data has changed.

  In the above, the non-volatile memory inspection method may further include the step (e) of replacing a memory cell determined to be defective with a redundant memory cell. As a result, even in the presence of a defective memory cell, normal operation of the nonvolatile memory can be ensured.

  In addition, the non-volatile memory further includes a word line drive circuit driving the control gate of the memory cell transistor and a source line drive circuit driving the source of the memory cell transistor, and step (b) includes at least the source line. Determining whether or not there is a defective memory cell in the non-volatile memory depending on whether or not the power supply current supplied to the drive circuit is larger than a predetermined value in the steady state; And reading data only from memory cells included in the non-volatile memory determined to have a defective memory cell. By doing so, the inspection time of the non-volatile memory can be shortened by omitting the reading of data when it is determined that there is no defective memory cell in the non-volatile memory.

  Alternatively, the non-volatile memory includes a plurality of memory cells divided into a plurality of blocks, and step (b) sequentially selects one block from the plurality of blocks and is included in the selected block. For the memory cell transistor, the drain is brought into a floating state, the first and second potentials are applied to the control gate and the source, respectively, while for the memory cell transistor included in the non-selected block, , And may not include application of the first and second potentials. As described above, by testing the memory cell in units of blocks, it is possible to reduce the load that is momentarily applied to the power supply circuit or the like when testing the memory cell.

  In that case, the non-volatile memory is a word line drive circuit for driving the control gate of the memory cell transistor included in the selected block, and the source of the memory cell transistor included in the selected block. And the source line drive circuit to be driven, wherein step (b) selects at least the selected block depending on whether the power supply current supplied to the source line drive circuit is larger than a predetermined value in the steady state. The step (c) may include reading data only from the memory cells included in the block determined to have the defective memory cell, including determining whether the defective memory cell exists or not. . By doing so, the inspection time of the non-volatile memory can be shortened by omitting the data reading for the block determined in step (b) that there is no defective memory cell.

  An integrated circuit device according to one aspect of the present invention includes a memory cell provided with a transistor having a control gate, a floating gate, a source, and a drain, and a word line drive circuit for driving a control gate of the memory cell transistor. A source line drive circuit for driving the source of the memory cell transistor, a switch circuit connected to the drain of the memory cell transistor, and a drain of the memory cell via the switch circuit, which can be connected in test mode The word line drive circuit is controlled to turn off the switch circuit to bring the drain into a floating state and to control the word line drive circuit to apply the first potential to the control gate and to apply the second potential to the source. Control and read Control the word line drive circuit to apply the third potential to the control gate and control the source line drive circuit to apply the reference potential to the source to turn on the switch circuit; And a memory control circuit for reading data from the memory cell based on the magnitude of the current. Regarding the setting of the potential, when the transistor of the memory cell is an N-channel transistor, the first potential is set to be higher than the third potential, and the second potential is set to be higher than the reference potential. On the other hand, when the transistor of the memory cell is a P-channel transistor, the first potential is set lower than the third potential, and the second potential is set lower than the reference potential.

  According to the integrated circuit device of one aspect of the present invention, in the test mode, the memory control circuit turns off the switch circuit to set the drain of the memory cell transistor in a floating state and apply the first potential to the control gate. In the defective memory cell, for example, between the drain and the semiconductor substrate or the well by controlling the word line drive circuit to control the source line drive circuit to apply the second potential to the source. Leakage current flows in the defect leak path existing in the circuit, hot carriers are generated, and the threshold voltage of the transistor changes with respect to the erased state. On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change with respect to the erased state. Therefore, by determining whether the memory cell is normal or defective based on the data read from the memory cell in the read mode, it is possible to prevent the deterioration of the normal memory cell due to repeated data rewriting. , Non-volatile memory can be inspected.

  Here, in the erase mode, the memory control circuit turns off the switch circuit to set the drain in a floating state and controls the word line drive circuit to apply the reference potential to the control gate, and the fourth potential is applied to the source. The source line driver circuit may be controlled to apply a voltage. Regarding the setting of the potential, when the transistor of the memory cell is an N-channel transistor, it is desirable that the first potential and the second potential be set to the fourth potential or more. On the other hand, when the transistor of the memory cell is a P-channel transistor, it is desirable that the first potential and the second potential be set equal to or lower than the fourth potential. Thus, in the erase mode, the memory cell is kept in the erase state, and in the test mode, a large leak current can be supplied to the transistor of the defective memory cell to generate sufficient hot carriers, thereby shortening the test time.

FIG. 1 is a block diagram showing a configuration example of an integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a part of the integrated circuit device shown in FIG. The circuit diagram which shows typically the state of the several memory cell in test mode. Sectional drawing which shows the state of the transistor in write mode and test mode. FIG. 2 is a flow chart showing the inspection method of the nonvolatile memory according to the first embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a configuration of part of an integrated circuit device according to a second embodiment of the present invention. FIG. 7 is a flowchart showing a method of inspecting a nonvolatile memory according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same reference numerals are given to the same components, and the overlapping description is omitted.
The present invention is applicable to electrically rewritable nonvolatile memories such as flash memories and EEPROMs, and integrated circuit devices incorporating such nonvolatile memories. Further, the integrated circuit device according to the present invention may incorporate only a non-volatile memory or may incorporate a digital circuit or an analog circuit having a predetermined function in addition to the non-volatile memory. Hereinafter, an embodiment of an integrated circuit device incorporating a flash memory will be described as an example.

First Embodiment
FIG. 1 is a block diagram showing a configuration example of an integrated circuit device according to a first embodiment of the present invention. As shown in FIG. 1, the integrated circuit device includes a memory cell array 10, a power supply circuit 20, a word line booster circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, and a memory. A non-volatile memory including the control circuit 70 is incorporated.

  Memory cell array 10 includes a plurality of memory cells arranged in a matrix in the row direction (horizontal direction in the figure) and the column direction (vertical direction in the figure). In the present embodiment, the memory cells are arranged in m rows and n columns (m, n22). Each memory cell is a non-volatile memory cell storing one bit of data.

  The memory cell array 10 includes a plurality of word lines WL0, WL1,..., WLm, a plurality of source lines SL0, SL1,..., SLm and a plurality of bit lines BL0, BL1,. And contains. Each of the word line and the source line is connected to a plurality of memory cells arranged in each row. Also, each of those bit lines is connected to a plurality of memory cells arranged in each column.

  The power supply circuit 20 includes, for example, a logic power supply potential VDD for a logic circuit, high power supply potentials VP1 and VP2 for memory cell test, a high power supply potential VP3 for data writing and erasing, and a reference power supply potential VSS. It is supplied from the outside. Alternatively, the power supply circuit 20 may generate another power supply potential by stepping up or down the power supply potential of at least one of a plurality of externally supplied power supply potentials.

  In the present embodiment, the reference power supply potential VSS is the lowest potential (reference potential) that is a reference relative to other potentials, and each part of the non-volatile memory and the P-type semiconductor substrate of the integrated circuit device or P well is supplied. The reference power supply potential VSS may have any value, but in the following, the case where the reference power supply potential VSS is the ground potential 0 V will be described.

  The logic power supply potential VDD is, for example, about 1.2 V to 1.8 V, and may be shared with a power supply potential of a microcomputer or the like used together with a nonvolatile memory in the electronic device. The high power supply potentials VP1 to VP3 are, for example, about 5 V to 10 V, and two or three of the high power supply potentials VP1 to VP3 may be equal.

  The power supply circuit 20 supplies the logic power supply potential VDD to the memory control circuit 70, and under the control of the memory control circuit 70, the logic power supply potential VDD and the high power supply potentials VP1 to VP3 are nonvolatile as needed. Supply to each part of memory. In FIG. 1, the power supply potential supplied from power supply circuit 20 to word line boosting circuit 30 is shown as word line power supply potential VWL, and the power supply potential supplied from power supply circuit 20 to source line drive circuit 50 is the source line. It is shown as power supply potential VSL.

  In this embodiment, in order to inspect the non-volatile memory without causing deterioration of the normal memory cell due to repeated data rewriting, the drain of the transistor for storing data in the memory cell is brought into a floating state. A test mode is used in which the high power supply potential VP1 is applied as the first potential to the control gate and the high power supply potential VP2 is applied as the second potential to the source.

  When a defective memory cell exists in the memory cell array 10, in the test mode, a leak current flows through the transistor of the defective memory cell to generate hot carriers, and the threshold voltage of the transistor changes. In the test mode, the power supply circuit 20 supplies the high power supply potential VP1 to the word line boosting circuit 30, and supplies the high power supply potential VP2 to the source line drive circuit 50. The word line boosting circuit 30 supplies the high power supply potential VP1 supplied from the power supply circuit 20 to the word line drive circuit 40.

  Further, in the read mode in which data is read from the memory cell, the power supply circuit 20 supplies the logic power supply potential VDD to the word line booster circuit 30 and the source line drive circuit 50. Word line booster circuit 30 raises logic power supply potential VDD supplied from power supply circuit 20 to generate word line boosted potential VUP, and supplies word line boosted potential VUP as a third potential to word line drive circuit 40. .

  The high power supply potential VP3 is used as the fourth potential in the write mode for writing data to the memory cell and the erase mode for putting the memory cell in the erase state. In the write mode and the erase mode, power supply circuit 20 supplies high power supply potential VP3 to word line booster circuit 30 and source line drive circuit 50. The word line boosting circuit 30 supplies the high power supply potential VP3 supplied from the power supply circuit 20 to the word line drive circuit 40.

  The word line drive circuit 40 is connected to the plurality of word lines WL 0, WL 1,..., WLm, and drives the word line selected by the memory control circuit 70. The source line drive circuit 50 is connected to the plurality of source lines SL1, SL2,..., SLm, and drives the source line selected by the memory control circuit 70.

  Switch circuit 60 includes, for example, a plurality of transistors respectively connected to a path of a plurality of bit lines BL0, BL1,..., BLn, which are turned on or off under control of memory control circuit 70. Do. The memory control circuit 70 can be connected to the memory cells connected to the plurality of bit lines BL0, BL1,..., BLn via the switch circuit 60.

  The memory control circuit 70 includes, for example, a logic circuit including a combinational circuit and a sequential circuit, an analog circuit, and the like. The memory control circuit 70 is supplied with a chip select signal CS, a mode select signal MS, an operation clock signal CK, and an address signal AD. When the non-volatile memory is selected by the chip select signal CS, the memory control circuit 70 sets the non-volatile memory to a write mode, an erase mode, a test mode, or a read mode according to the mode select signal MS. However, when the mode select signal MS indicates the inspection mode, the memory control circuit 70 may sequentially set the nonvolatile memory to the erase mode, the test mode, and the read mode.

  In the write mode and the read mode, the memory control circuit 70 controls each portion of the non-volatile memory to access the memory cell specified by the address signal AD in synchronization with the operation clock signal CK. For example, in the write mode, the memory control circuit 70 inputs write data, and controls each part of the non-volatile memory to write data in the memory cell specified by the address signal AD. In the read mode, the memory control circuit 70 controls each part of the non-volatile memory to read data from the memory cell specified by the address signal AD, and outputs read data.

  In the read mode, the memory control circuit 70 turns on the transistor of the switch circuit 60 connected to the memory cell specified by the address signal AD, and reads data based on the read current flowing to the memory cell. At this time, the memory control circuit 70 uses the read current flowing in the reference cell 70 a as a reference to determine whether the read data is “0” based on the read current flowing in the memory cell specified by the address signal AD. It may be determined whether it is "1".

  FIG. 2 is a circuit diagram showing a configuration example of a part of the integrated circuit device shown in FIG. For example, the memory cell array includes 2048 rows of memory cells, and one row of memory cells includes 1024 memory cells and can store 128 8-bit data. Each memory cell MC includes an N-channel MOS transistor having a control gate, a floating gate, a source, and a drain to store one bit of data.

  Each of word lines WL0 to WLm is connected to the control gate of the transistor of the plurality of memory cells MC arranged in each row. Each of source lines SL0 to SLm is connected to the sources of the transistors of the plurality of memory cells MC arranged in each row. Further, each of the bit lines BL0 to BLn is connected to the drains of the transistors of the plurality of memory cells MC arranged in each column.

  Word line drive circuit 40 (FIG. 1) includes a plurality of word line drivers 41 for driving control gates of the transistors of memory cells MC connected to word lines WL0 to WLm, a plurality of N channel MOS transistors 42, and word lines. And an inverter 43 for supplying a high potential side power supply potential of the driver 41. Each word line driver 41 is configured by, for example, a level shifter, a buffer circuit, or an inverter. The word line power supply potential VWL or the word line boosted potential VUP is supplied from the inverter 43 to each word line driver 41.

  A high active row selection signal activated to a high level when selecting one or more rows of memory cells from among the plurality of memory cells constituting the memory cell array is input to the input terminals of the plurality of word line drivers 41. SW0 to SWm are input from the memory control circuit 70. Word line driver 41 outputs word line power supply potential VWL or word line boosted potential VUP to the word line when the row selection signal is active, and the reference power supply potential VSS when the row selection signal is non-active. Output to word line.

  Source line drive circuit 50 (FIG. 1) drives source of the transistor of memory cell MC connected to source lines SL0 to SLm, source line driver 51, an output terminal of source line driver 51, and source line SL0. .About.SLm, and include a plurality of inverters 52 and a plurality of transmission gates TG whose drain-source paths are connected to each other. The source line driver 51 is configured by, for example, a level shifter, a buffer circuit, or an inverter.

  The source line power supply potential VSL is supplied to the source line driver 51 from the power supply circuit 20 (FIG. 1). A high active source line drive signal SSL, which is activated to a high level when applying a high power supply potential to the source line, is input from the memory control circuit 70 to the input terminal of the source line driver 51. The source line driver 51 outputs the source line power supply potential VSL when the source line drive signal SSL is active, and outputs the reference power supply potential VSS when the source line drive signal SSL is non-active.

  Each transmission gate TG is formed of an N channel MOS transistor and a P channel MOS transistor, and functions as a switch circuit that opens and closes the connection between the output terminal of the source line driver 51 and the source line. In the transmission gate TG, the gate of the N channel MOS transistor is connected to the output terminal of the word line driver 41, and the gate of the P channel MOS transistor is connected to the output terminal of the inverter 52.

  Word line power supply potential VWL or word line boosted potential VUP is supplied to inverter 52 from word line drive circuit 40 (FIG. 1). Row selection signals SW0 to SWm are input to input terminals of the inverter 52. The inverter 52 inverts the row selection signals SW0 to SWm, and applies the inverted signal to the gate of the P-channel MOS transistor of the transmission gate TG.

  Switch circuit 60 includes N channel MOS transistors QN0 to QNn having drain / source paths connected between the drains of the transistors of memory cells MC connected to bit lines BL0 to BLn and memory control circuit 70. The gates of the transistors QN0 to QNn are high active column selection signals SB0 to SBn which are activated to a high level when one or more memory cells are selected from the plurality of memory cells constituting the memory cell array. Is applied from the memory control circuit 70. The memory control circuit 70 can be connected via the switch circuit 60 to the drains of the transistors of the memory cells MC connected to the bit lines BL0 to BLn.

  In the write mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to memory cell MC designated by the address signal, and other than that. The row selection signal and the column selection signal are made inactive, and the source line drive signal SSL is made active. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The high power supply potential VP3 is supplied to the inverter 43, the source line driver 51, and the inverter 52. The high power supply potential VP3 is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the high power supply potential VP3 to the word line WL0. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VP3.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VP3 and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. Thus, the transmission gate TG is turned on, and the high power supply potential VP3 output from the source line driver 51 is applied to the source line SL0.

  Further, the transistor QN0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the reference power supply potential VSS to the bit line BL0. Thus, memory control circuit 70 applies word line drive circuit 40 (FIG. 1) and source line drive circuit to apply high power supply potential VP3 to the control gate and source of the transistor of memory cell MC specified by the address signal. While controlling 50 (FIG. 1), the reference power supply potential VSS is applied to the drain.

  As a result, current flows from the source to the drain of the transistor of the memory cell MC specified by the address signal. The hot carriers (electrons in this embodiment) generated by the current are injected into the floating gate, so that negative charges are accumulated in the floating gate, and thus the threshold voltage of the transistor is increased. Here, in order to generate sufficient hot carriers within a short period, the potential difference between the high power supply potential VP3 and the reference power supply potential VSS is desirably 5 V or more, for example, may be 7.5 V. .

  On the other hand, the word line driver 41 to which non-active row selection signals SW1 to SWm are input outputs the reference power supply potential VSS to the word lines WL1 to WLm. The inverter 52 receiving the non-active row selection signals SW1 to SWm inverts the reference power supply potential VSS to apply the high power supply potential VP3 to the gate of the P-channel MOS transistor of the transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. Also, the transistors QN1 to QNn of the switch circuit 60 to which the non-active column selection signals SB1 to SBn are input are turned off. As a result, since no current flows between the source and drain of the transistor of the memory cell MC not designated by the address signal, the threshold voltage of the transistor does not change.

  In the erase mode, memory control circuit 70 activates the corresponding row select signal to select the word line connected to memory cell MC designated by the address signal, and makes the other row select signals non-active. At the same time, the column selection signals SB0 to SBn are deactivated, and the source line drive signal SSL is activated. Hereinafter, the case where word line WL0 is selected will be described as an example.

  The high power supply potential VP3 is supplied to the inverter 43, the source line driver 51, and the inverter 52. The reference power supply potential VSS is applied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input is not activated, but the reference power supply potential VSS is applied to the word line WL0 by the N channel MOS transistor 42 whose active erase mode signal ER is applied to the gate. Ru. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VP3.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VP3 and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. As a result, the P-channel MOS transistor of transmission gate TG is turned on, and high power supply potential VPP output from source line driver 51 is applied to source line SL0.

  Further, the transistors QN0 to QNn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. In this manner, the memory control circuit 70 turns off the transistors QN0 to QNn of the switch circuit 60 to set the drain of the transistor of the memory cell MC in a floating state (high impedance state) and applies the reference power supply potential VSS to the control gate. Thus, the word line drive circuit 40 (FIG. 1) is controlled, and the source line drive circuit 50 (FIG. 1) is controlled to apply the high power supply potential VP3 to the source.

  As a result, when the negative charge is accumulated in the floating gate of the transistor of the memory cell MC, the negative charge accumulated in the floating gate is released to the source, and the threshold voltage of the transistor is lowered. Here, in order to sufficiently release the negative charge stored in the floating gate within a short period, it is desirable to set the potential difference between the high power supply potential VP3 and the reference power supply potential VSS to 5 V or more. For example, 7.5 V may be used.

  On the other hand, the inverter 52 to which the non-active row selection signals SW1 to SWm are input inverts the reference power supply potential VSS and applies the high power supply potential VP3 to the gate of the P channel MOS transistor of the transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. As a result, since the negative charge stored in the floating gate of the transistor of the memory cell MC not designated by the address signal is not discharged, the threshold voltage of the transistor does not change.

  In the test mode, the memory control circuit 70 activates the row selection signals SW0 to SWm and the source line drive signal SSL, and deactivates the column selection signals SB0 to SBn. The high power supply potential VP <b> 1 is supplied to the inverters 43 and 52, and the high power supply potential VP <b> 2 is supplied to the source line driver 51. The high power supply potential VP1 is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signals SW0 to SWm are input outputs the high power supply potential VP1 to the word lines WL0 to WLm. The source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VP2.

  The high power supply potential VP1 output from the word line driver 41 is also applied to the gate of the N channel MOS transistor of the transmission gate TG connected to the word lines WL0 to WLm. The inverter 52 inverts the row selection signals SW0 to SWm to apply the reference power supply potential VSS to the gate of the P channel MOS transistor of the transmission gate TG. Thus, the transmission gate TG is turned on, and the high power supply potential VP2 output from the source line driver 51 is applied to the source lines SL0 to SLm.

  Further, the transistors QN0 to QNn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. As described above, the memory control circuit 70 turns off the transistors QN0 to QNn of the switch circuit 60 to set the drain of the transistor of the memory cell MC in a floating state (high impedance state) and applies the high power supply potential VP1 to the control gate. Thus, the word line drive circuit 40 (FIG. 1) is controlled, and the source line drive circuit 50 (FIG. 1) is controlled to apply the high power supply potential VP2 to the source.

  At this time, for example, in a defective memory cell having a low reverse withstand voltage between the N-type impurity diffusion region forming the drain of the transistor and the P-type semiconductor substrate or P well, the drain is directed from the drain to the P-type semiconductor substrate or P well. The leakage current flows, and hot carriers (electrons in the present embodiment) generated by the leakage current are accumulated in the floating gate or the oxide film.

  As a result, in the transistor of the defective memory cell, negative charge is accumulated in the floating gate or the oxide film, and the threshold voltage of the transistor is increased. For example, when the threshold voltage of the transistor of the normal memory cell in the erased state is 1V to 1.5V, the threshold voltage of the transistor of the defective memory cell is 2V to 3V.

  From the above, in the inspection of the nonvolatile memory, the nonvolatile memory is shifted from the erase mode to the test mode and then shifted to the read mode to read data from the plurality of memory cells MC included in the nonvolatile memory. Thus, it can be determined whether those memory cells MC are normal or defective. In the inspection of the non-volatile memory, the memory control circuit 70 may generate an address signal which sequentially designates a plurality of memory cells MC included in the non-volatile memory in the read mode.

  In the read mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to the memory cell specified by the address signal, and other rows. The selection signal and the column selection signal are made non-active, and the source line drive signal SSL is made non-active. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The word line boosted potential VUP is supplied to the inverters 43 and 52, and the logic power supply potential VDD is supplied to the source line driver 51. The word line boosted potential VUP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the word line boosted potential VUP to the word line WL0. In addition, the source line driver 51 to which the non-active source line drive signal SSL is input outputs the reference power supply potential VSS.

  Word line boosted potential VUP output from word line driver 41 is also applied to the gate of the N channel MOS transistor of transmission gate TG connected to word line WL0. Thereby, the N channel MOS transistor of the transmission gate TG is turned on, and the reference power supply potential VSS output from the source line driver 51 is applied to the source line SL0.

  Further, the transistor QN0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the bit line potential VBL of about 1 V higher than the reference power supply potential VSS to the bit line BL0. . Thus, the memory control circuit 70 controls the word line drive circuit 40 (FIG. 1) to apply the word line boosted potential VUP to the control gate of the transistor of the memory cell MC specified by the address signal. The source line drive circuit 50 (FIG. 1) is controlled to apply the reference power supply potential VSS, and the transistor QN0 of the switch circuit 60 is turned on to apply the bit line potential VBL to the drain.

  Here, in order to reliably turn on the transistor of the normal memory cell in the erase state, it is desirable to set the potential difference between the word line boosted potential VUP and the reference power supply potential VSS higher than 1.5 V. For example, 3V may be used. As a result, in the memory cell MC specified by the address signal, a drain current flows from the drain to the source of the transistor of the memory cell MC. Since the magnitude of the drain current differs depending on the amount of negative charge stored in the floating gate, the memory control circuit 70 can read data from the memory cell MC based on the magnitude of the drain current.

  The memory control circuit 70 may use, as the reference current value, a value obtained by multiplying the drain current flowing in the reference cell 70a (FIG. 1) in the erased state by a predetermined ratio (for example, 1/2). For example, when the magnitude of the drain current in the memory cell MC specified by the address signal is larger than the reference current value, the memory control circuit 70 determines that the read data is “0”, and is specified by the address signal. When the magnitude of the drain current in the memory cell MC is equal to or less than the reference current value, it is determined that the read data is "1".

  After testing the memory cell MC, in a normal memory cell, the threshold voltage of the transistor storing data is the same as in the erased state, and the magnitude of the drain current is larger than the reference current value. Therefore, when the magnitude of the drain current in the memory cell MC specified by the address signal is larger than the reference current value, the memory control circuit 70 determines that the read data is “0”, and the memory cell MC It can be determined that it is normal.

  On the other hand, in the case of the defective memory cell, the threshold voltage of the transistor storing data is increased, so the drain current is smaller than in the normal memory cell. Therefore, when the magnitude of the drain current in the memory cell MC specified by the address signal is less than or equal to the reference current value, the memory control circuit 70 determines that the read data is "1", and the memory cell MC It can be determined to be defective.

  On the other hand, the word line driver 41 to which non-active row selection signals SW1 to SWm are input outputs the reference power supply potential VSS to the word lines WL1 to WLm. Inverter 52 receiving non-active row selection signals SW1 to SWm inverts reference power supply potential VSS to apply word line boosted potential VUP to the gate of the P channel MOS transistor of transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. Also, the transistors QN1 to QNn of the switch circuit 60 to which the non-active column selection signals SB1 to SBn are input are turned off. As a result, no drain current flows in the transistor of the memory cell MC not designated by the address signal.

  FIG. 3 is a circuit diagram schematically showing the state of a plurality of memory cells in the test mode. In FIG. 3, as an example, a high power supply potential of 8 V is applied to the selected word line connected to the floating gates of the transistors of the plurality of memory cells and the selected source line connected to the source, and connected to the drain The unselected non-selected bit lines are in the high impedance state (HZ). Further, a reference power supply potential VSS is applied to a P-type semiconductor substrate or a P-well in which transistors of a plurality of memory cells are provided.

  In the example shown in FIG. 3, a defect leak path represented by a symbol of resistance exists between the drain of the transistor of the defective memory cell and the P-type semiconductor substrate or P well, and the defect passes from the source to the drain. A leak current flows in the leak path. The defect leak path is a PN junction with a low reverse withstand voltage, and the hot carriers (electrons in the present embodiment) generated by the leak current flowing therethrough are accumulated in the floating gate or the oxide film to thereby threshold voltage of the transistor. Changes.

  On the other hand, although the leak current also flows to the normal memory cell connected to the same bit line as the defective memory cell is connected through the defect leak path, the normal memory cell is physically separated from the defect leak path Therefore, the threshold voltage of the transistor in the normal memory cell is not changed without being affected by the hot carrier. Therefore, in the test mode, only the defective memory cell is stressed, and only the threshold voltage of the transistor in the defective memory cell is changed.

  FIG. 4 is a cross-sectional view showing an example of the state of the transistor in the write mode and the test mode. As shown in FIG. 4, the transistor for storing data in the memory cell includes, for example, a source 2 and a drain 3 formed of N-type impurity diffusion regions provided in a P-type semiconductor substrate 1, and The tunnel oxide film 4, the floating gate 5, the gate oxide film 6, and the control gate 7 are provided in order on the surface of the device. Furthermore, this transistor has sidewalls 8 and 9 provided on the side surfaces of the tunnel oxide film 4 to the control gate 7. Further, the word line WL is connected to the control gate 7, the source line SL is connected to the source 2, and the bit line BL is connected to the drain 3.

  FIG. 4A shows an example of the state of the transistor in the writing mode. In the example shown in FIG. 4A, the high power supply potential 7.5 V is applied to the word line WL and the source line SL, and the ground potential 0 V is applied to the bit line BL. As a result, current flows from the source 2 to the drain 3 of the transistor, and the hot carriers (electrons in this embodiment) having flowed through the channel between the drain 3 and the source 2 obtain energy by the high electric field. Is injected into the floating gate 5. At this time, some electrons are also injected into the tunnel oxide film 4 and the side walls 8 to change the threshold of the transistor, which causes the decrease of the life due to the deterioration of the memory cell.

  FIG. 4B illustrates an example of the state of the transistor in the test mode. In the example shown in FIG. 4B, the high power supply potential 8 V is applied to the word line WL and the source line SL, and the bit line BL is in the high impedance state (HZ). However, in the defective memory cell, a defect leak path represented by a symbol of resistance exists between the drain 3 of the transistor and the P-type semiconductor substrate 1, and from the source 2 to the drain 3 through the defect leak path Leakage current flows. Thereby, the hot carriers (electrons in the present embodiment) generated in the defect leak path are attracted to the control gate 7 and accumulated in the floating gate 5, the tunnel oxide film 4 or the sidewall 9. The threshold voltage rises.

  According to the integrated circuit device of the first embodiment of the present invention shown in FIGS. 1 and 2, in the test mode, the memory control circuit 70 turns off the switch circuit 60 to float the drain of the transistor of the memory cell MC. In this state, the word line drive circuit 40 is controlled to apply the high power supply potential VP1 to the control gate, and the source line drive circuit 50 is controlled to apply the high power supply potential VP2 to the source. In, for example, a leak current flows in a defect leak path existing between the drain and the P-type semiconductor substrate or P well to generate hot carriers, and the threshold voltage of the transistor changes with respect to the erased state.

  On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change with respect to the erased state. Therefore, by determining whether the memory cell MC is normal or defective based on the data read from the memory cell MC in the read mode, deterioration of the normal memory cell is caused by repeated data rewriting. Non-volatile memory can be tested without. In addition, in the test mode, since the non-volatile memory is originally in a state where no steady current flows in the memory cell, the test time can be shortened by testing many memory cells at one time.

  When an N-channel MOS transistor is used as a transistor for storing data in memory cell MC, high power supply potential VP1 is set higher than word line boosted potential VUP, and high power supply potential VP2 is set higher than reference power supply potential VSS. Is desirable. In that case, in the test mode, leak current can be supplied to the transistor of the defective memory cell to generate hot carriers, and the threshold voltage of the transistor can be changed.

  Further, it is desirable that the high power supply potentials VP1 and VP2 be set higher than the high power supply potential VP3. In that case, a large leak current can be supplied to the transistor of the defective memory cell to generate sufficient hot carriers, thereby reducing the test time. Specifically, the potential difference between the high power supply potential VP1 and the reference power supply potential VSS and the potential difference between the high power supply potential VP2 and the reference power supply potential VSS are desirably 5 V or more, for example, 7. It may be 5V or 8V.

<Non-volatile memory inspection method 1>
Next, the inspection method of the non-volatile memory according to the first embodiment of the present invention will be described with reference to FIG. 1, FIG. 2 and FIG.
FIG. 5 is a flowchart showing the inspection method of the nonvolatile memory according to the first embodiment of the present invention. The inspection of the non-volatile memory may be performed in an inspection process in a manufacturing plant, or may be performed in a state where an integrated circuit device incorporating the non-volatile memory is incorporated in an electronic device or the like. The inspection of the non-volatile memory may be performed by the operator operating the IC tester or the like, or may be automatically performed by the memory control circuit 70 or the integrated circuit device.

  In step S11 shown in FIG. 5, the memory control circuit 70 sets the non-volatile memory to the erase mode to put the memory cell MC in the erase state. That is, the memory control circuit 70 sets the drain in a floating state to the transistor storing data in the memory cell MC, applies the reference power supply potential VSS and the high power supply potential VP3 to the control gate and the source, respectively, Control each part of the non-volatile memory so as to put in the erased state. In the present embodiment, data in the memory cell MC in the erased state is defined as "0".

  In step S12, the memory control circuit 70 sets the nonvolatile memory to the test mode, sets the drain in the floating state to the transistor of the memory cell MC, and applies the high power supply potentials VP1 and VP2 to the control gate and the source, respectively. Control each part of the non-volatile memory.

  Thus, for example, in a defective memory cell in which a defect leak path exists between the drain of the transistor and the P-type semiconductor substrate or P well, a leak current flows from the source to the drain through the defect leak path, The generated hot carriers are accumulated in the floating gate or the oxide film, whereby the threshold voltage of the transistor is increased. On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change.

  In step S13, the memory control circuit 70 sets the nonvolatile memory to the read mode and reads data from the memory cell MC. That is, the memory control circuit 70 applies the word line boosted potential VUP and the reference power supply potential VSS to the control gate and the source of the transistor of the memory cell MC, and applies the bit line potential VBL to the drain. Control each part of sexual memory. Furthermore, the memory control circuit 70 reads data from the memory cell MC based on the magnitude of the drain current.

  In step S14, the operator or memory control circuit 70 determines whether the memory cell MC is normal or defective based on the data read from the memory cell MC. In a normal memory cell, the data "0" is read because the magnitude of the drain current is larger than the reference current value, but in the defective memory cell, the magnitude of the drain current is smaller than the reference current value Therefore, data "1" is read out. Thereby, it is determined whether or not there is a defective memory cell, and if there is a defective memory cell, its address can be known.

  In step S14 described above, the operator or memory control circuit 70 determines that the memory cell MC is defective if the data read from the memory cell MC is different from the data "0" in the memory cell MC in the erased state. It is good. Since memory cell MC is in the erased state in step S11, if data different from data "0" in memory cell MC in the erased state is read, the change in threshold voltage of the transistor due to leakage current in step S12. Can determine that the data has changed.

  Furthermore, in step S15, the operator or memory control circuit 70 may replace the memory cell determined to be defective with a redundant memory cell. As a result, even in the presence of a defective memory cell, normal operation of the nonvolatile memory can be ensured. For example, the operator or memory control circuit 70 creates an address conversion table representing the correspondence between an address represented by an externally input address signal and a physical address, and converts the address conversion table to the area of a normal memory cell. Store

  In this address conversion table, the physical address of the memory cell determined to be defective is replaced with the physical address of the redundant memory cell. When an address signal is input from the outside, the memory control circuit 70 converts the address represented by the address signal into a physical address by referring to the address conversion table, and a memory specified by the physical address Control each part of the non-volatile memory to access the cell.

  Alternatively, when the number of memory cells determined to be defective is within a predetermined range, the memory control circuit 70 adds an error correction code to write data input from the outside and stores the same in the memory cells. The error correction may be performed when reading data from the memory cell. As a result, even in the presence of a defective memory cell, normal operation of the nonvolatile memory can be ensured.

  In step S12 described above, the operator measures at least the power supply current supplied to the source line drive circuit 50 using an IC tester or the like, and at least the power supply current supplied to the source line drive circuit 50 is steady state (power supply current Whether or not there is a defective memory cell in the non-volatile memory may be determined according to whether or not the value is substantially constant) and is larger than a predetermined value.

  If there is no defect leak path in any of the memory cells, no leak current flows to the source of the transistor storing data in the memory cell, so the load of the source line drive circuit 50 becomes capacitive and the source in steady state The power supply current supplied to the line drive circuit 50 is equal to or less than a predetermined value (approximately zero).

  On the other hand, in any memory cell, for example, when a defect leak path exists between the drain and the P-type semiconductor substrate or P well, the defect leak through the source to the drain of the transistor storing data in the memory cell. Since the leak current flows in the path, the power supply current supplied to the source line drive circuit 50 in the steady state exceeds the predetermined value.

  Therefore, the operator or memory control circuit 70 determines whether a defective memory cell exists in the non-volatile memory, depending on whether at least the power supply current supplied to the source line drive circuit 50 is larger than a predetermined value in the steady state. It can be determined whether or not.

  Alternatively, when high power supply potentials VP1 and VP2 are equal and the same high power supply potential is supplied to word line drive circuit 40 and source line drive circuit 50, word line drive circuit 40 and source line drive circuit 50 are supplied. Depending on whether or not the supplied power current is larger than a predetermined value in the steady state, it may be determined whether or not there is a defective memory cell in the nonvolatile memory.

  According to the result, in step S13, the memory control circuit 70 may read data only from the memory cells included in the non-volatile memory determined to have a defective memory cell. By doing so, the inspection time of the non-volatile memory can be shortened by omitting the reading of data when it is determined that there is no defective memory cell in the non-volatile memory.

  According to the inspection method of nonvolatile memory in accordance with the first embodiment of the present invention, with the memory cell MC in the erased state, the drain of the transistor in the memory cell MC is in the floating state, and the control gate and the source are used. By performing a test applying high power supply potentials VP1 and VP2, respectively, in the defective memory cell, for example, a leak current flows in a defect leak path existing between the drain and the P-type semiconductor substrate or P well to cause hot carrier. Occurs, and the threshold voltage of the transistor changes.

  On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change. Therefore, by determining whether the memory cell MC is normal or defective based on the data read from the memory cell MC after the test, deterioration of the normal memory cell due to repeated data rewriting is caused. Rather, non-volatile memory can be tested.

Second Embodiment
Next, a second embodiment of the present invention will be described.
FIG. 6 is a circuit diagram showing a configuration example of a part of an integrated circuit device according to a second embodiment of the present invention. In a second embodiment, the non-volatile memory comprises a plurality of memories divided into a plurality of blocks. For example, 2048 rows of memory cells constituting a memory cell array of non-volatile memory are divided into 16 blocks and driven. In that case, one block will contain 128 rows of memory cells. The other points are the same as in the first embodiment.

  FIG. 6 shows block 1 and block 2 of the plurality of divided blocks, and in the following, the configuration and operation of block 1 and block 2 will be described. The block 1 includes word lines WL0 to WLj and source lines SL0 to SLj, and the block 2 includes word lines WL (j + 1) to WLk and source lines SL (j + 1) to SLk. Also, the plurality of bit lines of block 1 and the plurality of bit lines of block 2 are connected to common bit lines BL0 to BLn via respective switch circuits 60. Thereby, it becomes possible to drive a plurality of blocks independently.

  Word line drive circuit 40 (FIG. 1) includes a plurality of word line drivers 41 for driving control gates of the transistors of memory cells MC included in the block selected by row selection signals SW0 to SWk, and a plurality of N channels. A MOS transistor 42 and an inverter 43 for supplying a high potential side power supply potential of the word line driver 41 are included.

  In addition, source line drive circuit 50 (FIG. 1) includes a plurality of source line drivers 51 for driving the sources of the transistors of memory cells MC included in the block selected by source line drive signals SSL1 to SSL2. A plurality of transmission gates TG whose drain-source paths are connected between the output terminal of the source line driver 51 and the source lines SL0 to SLk and a plurality of inverters 52 are included.

  The high active row selection signals SW0 to SWj are input from the memory control circuit 70 to the input terminals of the word line driver 41 of block 1, and the high active row selection signals are input to the input terminals of the word line driver 41 of block 2. SW (j + 1) to SWk are input from the memory control circuit 70. Word line driver 41 outputs word line power supply potential VWL or word line boosted potential VUP to the word line when the row selection signal is active, and the reference power supply potential VSS when the row selection signal is non-active. Output to word line.

  The high active source line drive signal SSL1 is input from the memory control circuit 70 to the input terminal of the source line driver 51 of the block 1, and the high active source line drive signal is input to the input terminal of the source line driver 51 of the block 2. SSL2 is input from the memory control circuit 70. Source line driver 51 outputs source line power supply potential VSL when source line drive signal SSL1 or SSL2 is active, and outputs reference power supply potential VSS when source line drive signal SSL1 or SSL2 is non-active. Do.

  The operation of the non-volatile memory in the write mode and the read mode may be the same as in the first embodiment, or the memory control circuit 70 may turn off the switch circuit 60 of the non-selected block.

  In the erase mode, the memory control circuit 70 may simultaneously put the memory cells MC of all blocks into the erased state or may put the memory cells MC of the sequentially selected blocks into the erased state. For example, when the memory cell MC of block 1 is in the erase state and the memory cell MC of block 2 is not in the erase state, the memory control circuit 70 activates the row selection signals SW0 to SWj to set the row selection signals SW (j + 1) to SW (j + 1) to The SWk and the column selection signals SB0 to SBn are made non-active, the source line drive signal SSL1 is made active, and the source line drive signal SSL2 is made non-active.

  The high power supply potential VP3 is supplied to the inverter 43, the source line driver 51, and the inverter 52. The reference power supply potential VSS is applied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the active erase mode signal ER is input. The word line driver 41 to which active row selection signals SW0 to SWj are input is not activated, but an N channel MOS transistor 42 having an active erase mode signal ER applied to its gate causes reference power supply potential VSS to be applied to word line WL0 to WL0. Applied to WLj. The source line driver 51 to which the active source line drive signal SSL1 is input outputs the high power supply potential VP3 and the source line driver 51 to which the non-active source line drive signal SSL2 is input outputs the reference power supply potential VSS. Output.

  Inverter 52 receiving active row selection signals SW0-SWj inverts high power supply potential VP3 to apply reference power supply potential VSS to the gate of the P channel MOS transistor of transmission gate TG. Thereby, in block 1, the P channel MOS transistor of the transmission gate TG is turned on, and the high power supply potential VP3 output from the source line driver 51 is applied to the source lines SL0 to SLj. On the other hand, in block 2, the transmission gate TG is turned off, and the source lines SL (j + 1) to SLk are in a floating state.

  In block 1 and block 2, transistors QN0-QNn of switch circuit 60 to which non-active column selection signals SB0-SBn are input are turned off. In block 1, the drain of the transistor of the memory cell MC is in a floating state, the reference power supply potential VSS is applied to the control gate, and the high power supply potential VP3 is applied to the source. Thereby, the memory cell MC of block 1 is in the erased state.

  In block 2, on the other hand, inverter 52 receiving non-active row selection signals SW (j + 1) to SWk inverts reference power supply potential VSS to set high power supply potential VP3 to P channel MOS transistors of transmission gate TG. Apply to the gate. Therefore, the transmission gate TG connected to the word lines WL (j + 1) to WLk is turned off. As a result, since the negative charge stored in the floating gate of the transistor of the memory cell MC is not released, the threshold voltage of the transistor does not change.

  In the test mode, the memory control circuit 70 sequentially selects one of the plurality of blocks and tests the memory cells MC included in the selected block. For example, when testing memory cell MC of block 1 and not testing memory cell MC of block 2, memory control circuit 70 activates row selection signals SW0 to SWj and source line drive signal SSL1. The row selection signals SW (j + 1) to SWk, the source line drive signal SSL2, and the column selection signals SB0 to SBn are made inactive.

  The high power supply potential VP <b> 1 is supplied to the inverters 43 and 52, and the high power supply potential VP <b> 2 is supplied to the source line driver 51. The high power supply potential VP1 is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. In block 1, the word line driver 41 to which the active row selection signals SW0 to SWj are supplied outputs the high power supply potential VP1 to the word lines WL0 to WLj. Also, the source line driver 51 to which the active source line drive signal SSL1 is input outputs the high power supply potential VP2.

  The high power supply potential VP1 output from the word line driver 41 is also applied to the gate of the N channel MOS transistor of the transmission gate TG connected to the word lines WL0 to WLj. Thereby, the N channel MOS transistor of transmission gate TG is turned on, and high power supply potential VP2 output from source line driver 51 is applied to source lines SL0 to SLj.

  Further, the transistors QN0 to QNn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. Thus, the memory control circuit 70 sets the drain to the floating state and applies the high power supply potentials VP1 and VP2 to the control gate and the source, respectively, for the transistor of the memory cell MC included in the selected block 1. To control each part of the non-volatile memory. Thereby, the memory cell MC of block 1 shifts to the test mode.

  On the other hand, in block 2, word line driver 41 supplied with non-active row selection signals SW (j + 1) to SWk outputs reference power supply potential VSS to word lines WL (j + 1) to WLk. Further, the source line driver 51 to which the non-active source line drive signal SSL2 is input outputs the reference power supply potential VSS.

  The reference power supply potential VSS output from the word line driver 41 is also applied to the gate of the N channel MOS transistor of the transmission gate TG. Further, the high power supply potential VP1 output from the inverter 52 is applied to the gate of the P channel MOS transistor of the transmission gate TG. Thereby, the transmission gate TG is turned off.

  Further, the transistors QN0 to QNn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. As described above, the memory control circuit 70 causes the source and the drain to be in a floating state and applies the reference power supply potential VSS to the control gate with respect to the transistor of the memory cell MC included in the non-selected block 2. , Control each part of non-volatile memory. Therefore, the memory cell MC of block 2 does not shift to the test mode.

<Method 2 of inspecting non-volatile memory>
Next, a method of inspecting a non-volatile memory according to a second embodiment of the present invention will be described with reference to FIG. 1, FIG. 6, and FIG.
FIG. 7 is a flowchart showing a non-volatile memory inspection method according to a second embodiment of the present invention.

  In step S21 shown in FIG. 7, the memory control circuit 70 sets the non-volatile memory to the erase mode to put the memory cell MC in the erase state. Here, the memory control circuit 70 sequentially selects one block from the plurality of blocks, sets the selected block in the erase mode, and erases the memory cells MC included in the selected block. You may In the present embodiment, data in the memory cell MC in the erased state is defined as "0".

  In step S22, the memory control circuit 70 sequentially selects one block from the plurality of blocks, and sets the memory cells MC included in the selected block to the test mode. That is, the memory control circuit 70 sets the drain in the floating state and applies the high power supply potentials VP1 and VP2 to the control gate and the source respectively for the transistor of the memory cell MC included in the selected block. Each portion of the non-volatile memory is controlled so that the high power supply potentials VP1 and VP2 are not applied to the transistors of the memory cells MC included in the non-block.

  Thereby, when there is a defective memory cell in the selected block, a leak current flows to the transistor of the defective memory cell, and hot carriers generated by the leak current are accumulated in the floating gate or the oxide film, The threshold voltage of the transistor rises. On the other hand, a normal memory cell is not affected by hot carriers, and the threshold voltage of the transistor does not change.

  In step S23, the memory control circuit 70 sets the memory cell MC in the read mode and reads data from the memory cell MC. In the inspection of the non-volatile memory, the memory control circuit 70 may generate an address signal which sequentially designates the plurality of memory cells MC included in the non-volatile memory.

  In step S24, the operator or memory control circuit 70 determines whether the memory cell MC is normal or defective based on the data read from the memory cell MC. In a normal memory cell, since the magnitude of the drain current is larger than the reference current value, data "0" is read, but in the defective memory cell, the magnitude of the drain current is smaller than the reference current value. Therefore, data "1" is read out. Thereby, it is determined whether or not there is a defective memory cell, and if there is a defective memory cell, its address can be known.

  In the above step S22, the operator measures at least the power supply current supplied to the source line drive circuit 50 using an IC tester or the like, and at least the power supply current supplied to the source line drive circuit 50 is predetermined in the steady state. Depending on whether or not it is larger than the value, it may be determined whether or not there is a defective memory cell in the selected block.

  Alternatively, when high power supply potentials VP1 and VP2 are equal and the same high power supply potential is supplied to word line drive circuit 40 and source line drive circuit 50, word line drive circuit 40 and source line drive circuit 50 are supplied. Depending on whether the supplied power current is larger than the predetermined value in the steady state, it may be determined whether or not there is a defective memory cell in the selected block.

  Depending on the result, in step S23, the memory control circuit 70 may read data only from the memory cells MC included in the block determined to have a defective memory cell. In such a case, the inspection time of the non-volatile memory can be shortened by omitting the data reading for the block determined as having no defective memory cell in step S22.

  According to the second embodiment of the present invention, by testing the memory cell MC in block units, the load applied to the power supply circuit 20 (FIG. 1) or the like instantaneously when testing the memory cell MC is reduced. be able to. Furthermore, by erasing the memory cells MC in block units, it is possible to reduce the load momentarily applied to the power supply circuit 20 and the like when the memory cells MC are brought into the erased state.

  In the above embodiments, the N channel MOS transistor is used as a transistor for storing data in the memory cell MC. However, a P channel MOS transistor may be used as a transistor for storing data in the memory cell MC. In that case, a P channel MOS transistor is used in place of the N channel MOS transistor in switch circuit 60, and the N channel MOS transistor and P channel MOS transistor of transmission gate TG are interchanged.

  Further, the reference power supply potential VDD is used as the highest potential (reference potential) which is a reference relative to other potentials. The reference power supply potential VDD is supplied to each part of the non-volatile memory and the N-type semiconductor substrate or N-well of the integrated circuit device. The reference power supply potential VDD may be any value, but when the reference power supply potential VDD is the ground potential 0 V, for example, a logic power supply potential VSS of about −1.2 V to −1.8 V, −3 V A certain word line boosted potential VUP, a bit line potential VBL of about -1 V, and negative high power supply potentials VP1 to VP3 of about -5 V to -10 V are used. Furthermore, row active row select signals SW0 to SWm and row active row select signals SB0 to SBn are used. Hot carriers are not electrons but holes.

  When a P-channel MOS transistor is used as a transistor for storing data in memory cell MC, negative high power supply potential VP1 is lower than word line boosted potential VUP, and negative high power supply potential VP2 is higher than reference power supply potential VDD. It is desirable to set too low. Thus, in the test mode, a leak current can be supplied to the transistor of the defective memory cell to generate hot carriers, and the threshold voltage of the transistor can be changed.

  Furthermore, it is desirable that the negative high power supply potentials VP1 and VP2 be set equal to or lower than the negative high power supply potential VP3. Thus, in the test mode, a large leak current can be supplied to the transistor of the defective memory cell to generate sufficient hot carriers, thereby reducing the test time. Specifically, the potential difference between the reference power supply potential VDD and the negative high power supply potential VP1 and the potential difference between the reference power supply potential VDD and the negative high power supply potential VP2 are preferably 5 V or more. For example, 7.5 V or 8 V may be used.

  Although the embodiments in which the present invention is applied to a flash memory have been described above, the present invention is not limited to the embodiments described above, and the present invention may be embodied by those skilled in the art. Many variants are possible within the technical concept of.

  DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate, 2 ... source | sauce, 3 ... drain, 4 ... tunnel oxide film, 5 ... floating gate, 6 ... gate oxide film, 7 ... control gate, 8, 9 ... sidewall, 10 ... memory cell array, 20 ... Power supply circuit, 30 ... Word line booster circuit, 40 ... Word line drive circuit, 41 ... Word line driver, 42 ... N channel MOS transistor, 43 ... Inverter, 50 ... Source line drive circuit, 51 ... Source line driver, 52 ... Inverters 60 switch circuits 70 memory control circuits 70a reference cells WL0 to WLm word lines SL0 to SLm source lines BL0 to BLn bit lines TG transmission gates MC memory cells QN0 ~ QN n ... N channel MOS transistor

Claims (10)

A method of testing a non-volatile memory including a memory cell provided with a transistor having a control gate, a floating gate, a source, and a drain,
Placing the memory cell in an erased state (a);
Placing the drain in a floating state and applying a first potential and a second potential to the control gate and the source, respectively, for the transistor of the memory cell;
Reading data from the memory cell (c);
And (d) determining whether the memory cell is normal or defective based on the data read from the memory cell. Step (c) includes applying a third potential and a reference potential to the control gate and the source respectively to the transistor of the memory cell and reading data from the memory cell based on the magnitude of the drain current ,
When the transistor of the memory cell is an N-channel transistor, the first potential is set to be higher than the third potential, and the second potential is set to be higher than the reference potential. The non-volatile property according to claim 1, wherein when the transistor is a P-channel transistor, the first potential is set lower than the third potential, and the second potential is set lower than the reference potential. Memory inspection method. Step (a) includes putting the drain in the floating state and applying the reference potential and the fourth potential to the control gate and the source, respectively, to put the memory cell in the erased state with respect to the transistor of the memory cell. ,
When the transistor of the memory cell is an N-channel transistor, the first potential and the second potential are set to a fourth potential or more, and the transistor of the memory cell is a P-channel transistor. The method of testing a non-volatile memory according to claim 1 or 2, wherein the first potential and the second potential are set to be equal to or lower than a fourth potential.   The method according to any one of claims 1 to 3, wherein the step (d) includes determining that the memory cell is defective if the data read from the memory cell is different from the data in the erased memory cell. The inspection method of the non-volatile memory as described in item 1.   The non-volatile memory inspection method according to any one of claims 1 to 4, further comprising the step (e) of replacing a memory cell determined to be defective with a redundant memory cell. The non-volatile memory further includes a word line drive circuit driving a control gate of the memory cell transistor, and a source line drive circuit driving a source of the memory cell transistor.
Whether or not there is a defective memory cell in the non-volatile memory depending on whether or not the step (b) at least the power supply current supplied to the source line drive circuit is larger than a predetermined value in the steady state Including determining
The non-volatile memory according to any one of claims 1 to 5, wherein step (c) includes reading data only from memory cells included in the non-volatile memory determined to have a defective memory cell. Inspection method. The non-volatile memory includes a plurality of memory cells divided into a plurality of blocks,
Step (b) sequentially selects one block among the plurality of blocks, with the drain of the memory cell transistor included in the selected block being in a floating state, and the control gate and the source are selected. 2. The method according to claim 1, further comprising: applying the first and second potentials, while not applying the first and second potentials to the memory cell transistors included in the non-selected block. The inspection method of the non-volatile memory as described in any one of -5. The non-volatile memory is a word line drive circuit for driving control gates of transistors of memory cells included in the selected block, and a source for driving sources of transistors of memory cells included in the selected block. Further including a line drive circuit,
Depending on whether or not step (b) at least the power supply current supplied to the source line drive circuit is larger than a predetermined value in the steady state, whether or not there is a defective memory cell in the selected block Including determining
The method according to claim 7, wherein the step (c) includes reading data only from memory cells included in a block determined to have a defective memory cell. A memory cell provided with a transistor having a control gate, a floating gate, a source, and a drain;
A word line drive circuit for driving a control gate of a transistor of the memory cell;
A source line drive circuit for driving a source of a transistor of the memory cell;
A switch circuit connected to the drain of the memory cell transistor;
The word can be connected to the drain of the transistor of the memory cell through the switch circuit, and in the test mode, the switch circuit is turned off to float the drain and apply the first potential to the control gate. The word line drive circuit is controlled to control the line drive circuit and to control the source line drive circuit to apply the second potential to the source, and to apply the third potential to the control gate in the read mode. A memory control circuit that controls the source line drive circuit to apply a reference potential to the source and turns on the switch circuit to read data from the memory cell based on the magnitude of drain current;
When the transistor of the memory cell is an N-channel transistor, the first potential is set to be higher than the third potential, and the second potential is set to be higher than the reference potential, An integrated circuit device, wherein the first potential is set to be lower than the third potential and the second potential is set to be lower than the reference potential when the transistor of the memory cell is a P-channel transistor. The memory control circuit controls the word line drive circuit to turn off the switch circuit to put the drain into a floating state and to apply a reference potential to a control gate in the erase mode, and controls the fourth potential to the source. Control the source line drive circuit to apply
When the transistor of the memory cell is an N-channel transistor, the first potential and the second potential are set to a fourth potential or more, and the transistor of the memory cell is a P-channel transistor. The integrated circuit device according to claim 9, wherein the first potential and the second potential are set to be equal to or lower than a fourth potential.

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