TWI511143B - Nonvolatile semiconductor memory device - Google Patents

Description

Non-volatile semiconductor memory component

This invention relates to a non-volatile semiconductor memory component.

A semiconductor memory component is a component in which data from which data can be stored and stored can be read. Semiconductor memory components can be classified into volatile memory components and non-volatile memory components. Volatile memory components require a supply of power to persist to preserve data, while non-volatile memory components retain data when the power supply disappears. Therefore, non-volatile memory components are widely used in applications where the power supply may be suddenly disturbed.

The non-volatile memory component comprises an electrically erasable and programmable mable (EEPROM) cell, such as a flash EEPROM cell. Figure 1 shows a vertical cross-sectional view of a flash EEPROM cell 10. Referring to FIG. 1, a deep n-type well 12 is formed on a P-type substrate 11 or a body region, and a P-type well 13 is formed on the N-well 12. An N-type source region 14 and an N-type drain region 15 are formed in the P-well 13. A P-type channel region (not shown) is formed between the source region 14 and the drain region 15. A floating gate 17 isolated by an insulating layer 16 is formed over the P-type channel region. a control gate isolated by another insulating layer 18 A pole 19 is formed above the floating gate 17.

Figure 2 shows the threshold voltage range of the flash EEPROM cell 10 during staging and erase operations. Referring to Figure 2, the flash EEPROM cell 10 has a higher threshold voltage range (about 6 to 7 V) during the staging operation and a lower threshold voltage range (about 1 to 3 V) during the erase operation.

Referring to Figures 1 and 2, during the stylization operation, hot electrons must be injected from the channel region adjacent to the drain region 15 to the floating gate electrode, so that the threshold voltage range of the EEPROM cell increases. Conversely, the hot electrons injected into the floating gate 17 during the staging operation must be removed during the erase operation, so the threshold voltage range of the EEPROM cell will decrease. Accordingly, the threshold voltage value of the EEPROM cell changes after the staging and erasing operations.

Figure 3 shows a partial schematic view of a typical flash memory array using a NOR architecture. Referring to FIG. 3, the flash memory array 30 includes a plurality of memory cell transistors 31 to 33. The unit cell transistors are located in a region interleaved by a plurality of word line lines WL1 to WL4, a plurality of bit lines BL1 to BL4, and a source line SL1. The two adjacent flash memory cells 31 and 32 in FIG. 3 are electrically connected to the same word line WL1 and different bit lines BL1 and BL2, sharing the same source line SL1.

During the stylization operation, a stylized voltage VPP (approximately 4V) is applied to the bit line electrically connected to a selected cell memory, one place A ground voltage VSS is applied to the source line electrically connected to the selected cell memory, and a high voltage VH (about 9V) is applied to the characters electrically connected to the selected cell memory. on-line. At the same time, the ground voltage VSS is applied to the word line electrically connected to the unselected cell memory. For example, if the memory cell 31 is selected to be programmed and the memory cell 32 is selected not to be programmed, the programmed voltage VPP is applied to the bit line BL1, the ground voltage VSS. It is applied to the source line SL1, the bit line BL2, and other word lines WL2 to WL4, and the high voltage VH is applied to the word line WL1. In this case, the threshold voltage value of the cell memory 31 is increased by the stylization operation. However, since the stylized voltage VPP is applied to the same bit line electrically connected to all of the cell memories, the state of the unselected cell memory 33 adjacent to the cell memory 31 may also be Will be affected. This phenomenon is called program disturb. When a stylized disturbance occurs, the threshold voltage value of the unselected cell memory 33 may be changed.

Accordingly, it is necessary to propose an improved mechanism to address the effects of stylized disturbances.

The present invention provides a non-volatile semiconductor memory device comprising a memory array, a step-by-step voltage generator, and a decoding and level conversion circuit. The memory array includes a plurality of memory cells and a plurality of bit lines electrically connected to the memory cells. Step voltage generator Used to generate a step-by-step voltage that changes in at least two steps. The decoding and level conversion circuit is configured to select one of the bit lines to apply the step voltage as a stylized voltage to the selected bit line.

10‧‧‧flash EEPROM cell

11‧‧‧P type substrate

12‧‧‧Deep N well

13‧‧‧P type well

14‧‧‧N-type source region

15‧‧‧N type bungee area

16‧‧‧Insulation

17‧‧‧Floating gate

18‧‧‧Insulation

19‧‧‧Control gate

30‧‧‧Memory array

40‧‧‧ memory components

42‧‧‧Memory array

44‧‧‧ row decoding and level conversion circuits

46‧‧‧ column decoding and level conversion circuit

48‧‧‧Input drive unit

50‧‧‧step voltage generator

502‧‧‧ pump circuit

504‧‧‧Inverter

506‧‧‧ position shifter

BL1-BLN‧‧‧ bit line

M1, 1-M2, 4‧‧‧ memory cell crystal

N1‧‧‧ NMOS transistor

P1, P2‧‧‧ PMOS transistor

SL1‧‧‧ source line

WL1-WLm‧‧‧ character line

Figure 1 shows a vertical cross-sectional view of a flash EEPROM cell.

Figure 2 shows the critical voltage range of the flash EEPROM cell during stylized and erase operations.

Figure 3 shows a partial schematic view of a typical flash memory array using a NOR architecture.

4 is a block diagram showing a non-volatile semiconductor memory device incorporating one embodiment of the present invention.

FIG. 5 shows a partial schematic view of the memory array shown in FIG.

Figure 6 is a circuit diagram showing an embodiment of the step voltage generator shown in Figure 4.

Fig. 7 is a view showing a possible output waveform of one of the step voltage generators shown in Fig. 6.

Figure 8 shows a possible timing diagram of the memory array during a stylized operation.

Figure 9 shows a possible waveform diagram of one of the stylized voltages applied to different bit lines.

Figure 10 shows one of the possible waveforms of the stylized voltage applied to different bit lines. Figure.

Figure 11 shows a possible waveform diagram of one of the stylized voltages applied to different bit lines.

4 shows a block diagram of a non-volatile semiconductor memory device 40 incorporating one embodiment of the present invention. Referring to FIG. 4, the memory device 40 includes a memory array 42, a row of decoding and level conversion circuits 44, a column of decoding and level conversion circuits 46, an input driving unit 48, and a step-by-step voltage generator 50.

FIG. 5 shows a partial schematic view of the memory array 42 shown in FIG. For the sake of brevity, the memory array 42 of FIG. 5 shows only eight memory cell transistors M1, 1 to M2, 4, 2 word lines WL1 and WL2 and 4 bit lines BL1 to BL4. Referring to FIG. 5, the memory cell transistors M1,1 to M2,4 are arranged in two courses, wherein each of the cell transistors M1,1 to M1,4 in the first column Electrically connected to one of the word line WL1 and the four bit lines BL1 to BL4, and each of the unit cell transistors M2,1 to M2,4 in the second column It is connected to one of the word line WL2 and the four bit lines BL1 to BL4.

Referring to FIGS. 4 and 5, in order to program a plurality of memory cell transistors in the memory array 42, the step voltage generator 50 is generated in response to a mode signal PGM output by the input driving unit 48. The one-step voltage VST is applied to the row decoding and level conversion circuit 44. During stylized operation, The column decode and level conversion circuit 46 is responsive to a column of address signals AR output by the input drive unit 48 to select a word line in the memory array 42. For example, the column decode and level conversion circuit 46 first selects the word line WL1, and then. A high voltage VH (about 9 V) is applied to the gates of the unit cell transistors M1,1 to M1,4 by the word line WL1. Then, the row decoding and level conversion circuit 44 sequentially selects the first to fourth bit lines BL1 to BL4, and the step voltage VST is used as a stylized voltage by the bit lines BL1 to BL4. Applied to the drains of the unit cell transistors M1,1 to M1,4.

FIG. 6 shows a circuit diagram of one embodiment of the step voltage generator 50 shown in FIG. Referring to FIG. 6, the step voltage generator 50 includes a pump circuit 502, an inverter 504, PMOS transistors P1 and P2, an NMOS transistor N1, and a level shifter 506. . The pump circuit 502 is configured to generate pump output voltages VPP1 and VPP2, both of which are higher than the level of the supply voltage VCC. In this embodiment, the level of the supply voltage VCC is 3V, the level of the pump output voltage VPP1 is 4V, and the level of the pump output voltage VPP2 is 9V. Further, in the present embodiment, the pump circuit 502 is an internal circuit. In other embodiments of the invention, however, the pump circuit 502 can be external to the memory element 40 to reduce wafer volume and circuit complexity.

Referring to FIG. 6, the inverter 504 is configured to invert an input signal SEL to output an inverted signal /SEL to the gate of the PMOS transistor P1. The source of the PMOS transistor P1 is for receiving the pump output voltage VPP1. The source of the PMOS transistor P2 is configured to receive the pump output voltage VPP2 and the gate for receiving the input The signal SEL is input and the drain is electrically connected to the drain of the PMOS transistor P1. The level shifter 506 is configured to receive the voltage VSP from the drain of the PMOS transistor P1 and generate a one-bit shift voltage VLS, wherein the level shift voltage VLS has a response in response to the input signal SEL The amplitude of the pulse wave that changes in step mode. The drain of the NMOS transistor N1 is for receiving the pump output voltage VPP1, the gate is for receiving the level shift voltage VLS, and the source is for generating the step voltage VST.

FIG. 7 shows a possible output waveform diagram of the step voltage generator 50 shown in FIG. 6. Referring to FIG. 6, when the coincidence enable signal EN is enabled, the level shifter 506 generates the level shift voltage VLS by shifting the gate voltage VSP of the PMOS transistor P1. Referring to FIGS. 6 and 7, at time t0, the enable signal EN is enabled and the input signal SEL has a level of logic 0, which causes the PMOS transistor P1 to turn off and the PMOS transistor P2 to turn on. Therefore, the voltage VSP is pulled up to the pump output voltage VPP2. After time t1, the input signal SEL transitions to a level of logic 1, which causes the PMOS transistor P1 to be turned on and the PMOS transistor P2 to be turned off. Therefore, the voltage VSP drops to the pump output voltage VPP1. This voltage VSP is used as the power supply voltage of the level shifter 506. With this configuration, the level shift circuit 506 generates a level shift voltage VLS that changes in a two-step manner in response to the input signal SEL. In detail, the level of the level shift voltage VLS is lowered by the pump output voltage VPP2 to the pump output voltage VPP1 at time t1. Therefore, the drain voltage of the NMOS transistor N1 drops from the pump output voltage VPP1 to the voltage at time t1. VPP1-VTH, where VTH is the threshold voltage of the NMOS transistor N1.

Referring now to Figure 4, in order to program a plurality of memory cell transistors in the memory array 42, the step voltage generator 50 is responsive to the mode signal output by the input drive unit 48. The step voltage VST is generated by the PGM to the row decoding and level conversion circuit 44. During the stylization operation, the row decoding and level conversion circuit 44 sequentially selects one of the bit lines BL1 to BL4, and the step voltage VST is applied as a stylized voltage to the selected bit. on-line. Figure 8 shows a possible timing diagram of the memory array 42 during stylized operation. Referring to Figures 4 and 8, during time t0 to t4, the column decode and level conversion circuit 46 first selects the word line WL1.

In addition, at time t0, the row decoding and level conversion circuit 44 first selects the bit line BL1. Therefore, the circuit 44 applies the step voltage VST to the cell in FIG. 5 by the bit line BL1. The transistor M1,1 is used as a stylized voltage. Then, at time t1, the circuit 44 selects the bit line BL2. Therefore, the circuit 44 applies the step voltage VST to the cell transistor M1, 2 through the bit line BL2 to serve as a stylized voltage. . During the time t2 to t4, the circuit 44 sequentially selects the bit lines BL3 and BL4. Therefore, the circuit 44 applies the step voltage VST to the unit cell by the bit lines BL3 and BL4. Crystals M1, 3 and M1, 4 are used as stylized voltages. Thereafter, similar steps are performed in other memory cell transistors in the memory array 42, so the details of the operation will not be described again. Referring to Figure 8, due to the step voltage VST The amplitude is reduced in a two-step manner during the stylized operation, thus improving the stylized disturbance between the cells.

Referring to Fig. 8, in the present embodiment, the amplitude of the step voltage VST is decreased in a two-step manner during the stylization operation. However, the invention should not be limited thereto. For example, the waveform of the step voltage VST can be stepped down in multiple steps or stepped up in multiple steps. Figure 9 shows a possible waveform diagram of the step voltage VST applied to different bit lines. Referring to Fig. 9, the waveform of the step voltage VST rises in a two-step manner.

Referring to FIGS. 8 and 9, the pulse waves applied to the adjacent bit lines by the stylized voltages VBL1, VBL2, VBL3, and VBL4 do not overlap each other. However, in order to reduce the total program time of the memory cell, the pulse waves applied to the adjacent bit lines of the stylized voltages VBL1, VBL2, VBL3, and VBL4 may overlap each other. Referring to FIGS. 10 and 11, the stylized voltages VBL1, VBL2, VBL3, and VBL4 applied to adjacent bit lines are sequentially generated and overlap with each other. In the above embodiment, the pulse wave overlap amount P of the stylized voltages VBL1, VBL2, VBL3, and VBL4 is half of the pulse width W. However, the invention should not be limited thereto. The amount of overlap of the stylized voltages can be arbitrarily adjusted. Since the unit cell transistors M1,1 to M1,4 are sequentially programmed, and the stylized operation time intervals of the unit cell transistors M1,1 to M1,4 can overlap each other, the program of the present invention The method can greatly reduce the total stylization time.

The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still categorize based on the teachings and disclosures of the present invention. Alternatives and modifications may be made without departing from the spirit of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

40‧‧‧ memory components

42‧‧‧Memory array

44‧‧‧ row decoding and level conversion circuits

46‧‧‧ column decoding and level conversion circuit

48‧‧‧Input drive unit

50‧‧‧step voltage generator

BL1-BLn‧‧‧ bit line

WL1-WLm‧‧‧ character line

Claims (10)

A non-volatile semiconductor memory device comprising: a memory array comprising a plurality of memory cells and a plurality of bit lines electrically connected to the memory cells; a step-by-step voltage generator for generating a step-by-step voltage that changes in at least two steps; and a decoding and level conversion circuit for selecting one of the bit lines to apply the step voltage as a programmed voltage to the selected one Bit line. The non-volatile semiconductor memory device of claim 1, wherein the step voltage generator is configured to generate the step voltage that rises in at least two steps. A non-volatile semiconductor memory device according to claim 1, wherein the step voltage generator is configured to generate the step voltage that is lowered in at least two steps. The non-volatile semiconductor memory device of claim 1, wherein the decoding and level conversion circuit sequentially selects one of the bit lines and applies the stylized voltage voltages to adjacent bit lines Overlapping each other. The non-volatile semiconductor memory device of claim 1, wherein the decoding and level conversion circuit sequentially selects one of the bit lines, and the stylized voltages applied to the adjacent bit lines are not Will overlap. The non-volatile semiconductor memory device of claim 1, wherein the step voltage generator comprises: an inverter for inverting a bit-aligned switching signal to output an inverted signal; a first transistor having a source for receiving a first voltage source and a gate for receiving the inverted signal; a second transistor having a source for receiving a second voltage source and a gate Receiving the level switching signal and a drain electrically connected to a drain of the first transistor; a quasi-shifter for receiving the voltage of the drain from the first transistor as a power supply a voltage to generate a quasi-shift signal; and a third transistor having a drain to receive the first voltage source, a gate to receive the level shift signal and a source to generate the step a voltage; wherein the step voltage generator generates the step voltage in response to the level switching signal. According to the non-volatile semiconductor memory device of claim 6, wherein the level of the second voltage source is higher than the level of the first voltage source, the decoding and level conversion circuit sequentially selects the bit lines One of the ones, and the stylized voltage voltages applied to adjacent bit lines overlap each other. According to the non-volatile semiconductor memory device of claim 6, wherein the level of the second voltage source is higher than the level of the first voltage source, the decoding and level conversion circuit sequentially selects the bit lines One of the stylized voltages applied to adjacent bit lines does not overlap. According to the non-volatile semiconductor memory device of claim 6, wherein the level of the first voltage source is higher than the level of the second voltage source, the decoding and level conversion circuit sequentially selects the bit lines One of the ones, and the stylized voltage voltages applied to adjacent bit lines overlap each other. The non-volatile semiconductor memory device of claim 6, wherein the level of the first voltage source is higher than the level of the second voltage source, the decoding and the level shift The switching circuit sequentially selects one of the bit lines, and the programmed voltage voltages applied to the adjacent bit lines do not overlap.