JP2019070603A - Abz phase frequency divider - Google Patents

Abstract

To provide an ABZ-phase frequency divider that divides the frequencies of A, B, Z phases while maintaining the mutual phase relations of original A-phase, B-phase and Z-phase signals.SOLUTION: An incremental encoder 1 outputs A-phase and B-phase signals that are a pulse string 90 degrees out of phase in accordance with rotation and outputs a Z-phase signal for one rotation each. A pulse converter 11 detects a multiplied signal whose frequency equals an integral multiple of the frequency of inputted A-phase and B-phase signals and detects a rotation direction signal of the incremental encoder. A counter 12 accepts as its input the multiplied signal, the rotation direction signal and a Z-phase signal, outputs a count value of the multiplied signal in accordance with the rotation direction signal, and clears the count value when the Z-phase signal becomes active. A selector 13 selects consecutive 2-bit signals from the count value and outputs the same. A frequency-divided A, B-phase generator generates, from the 2-bit signals, frequency-divided A-phase and B-phase signals whose frequencies have been divided by a division ratio 1/K (k=positive integer).SELECTED DRAWING: Figure 1

Description

  The present invention relates to frequency division processing of an A-phase signal, a B-phase signal, and a Z-phase signal output from a high resolution incremental encoder.

  An incremental encoder is attached to a driving device such as a motor, a roller of another manufacturing device, a conveying device, etc., and detection of the speed, moving distance, or displacement angle of a rotating body or a moving body is conventionally performed. The incremental encoder outputs an A-phase signal and a B-phase signal, which are pulse trains with a phase difference of 90 degrees, in order to detect forward rotation and reverse rotation of rotation, and additionally to this, 1 for each additional rotation. Some output a Z-phase signal which is one pulse.

In addition, as for the number of pulses per rotation (number of incremental signals) output by the incremental encoder, those with normal accuracy such as 600PPR (PPR is Pulse Per Round) and 1024PPR are used in the conventional control device. .
In recent control devices, incremental encoders such as 9600 PPR, 19200 PPR, and 8192 PPR have come to be used when high accuracy is required for detection speed and displacement angle. This high accuracy incremental encoder also had high frequencies of the output A-phase signal, B-phase signal, and Z-phase signal.
When using such high-precision incremental encoders, motor drives and the like used in combination are newly developed or model-changed to prepare the interfaces of the incremental encoders and used.

  On the other hand, the incremental encoder is not only used in combination with a motor driving device, but also needs to be used simultaneously with another device such as a display device or a monitoring device manufactured by another company or another control device. At such times, such other devices do not support high accuracy, and thus high frequency, incremental encoders, and have the disadvantage that they can not be used.

  As a solution to this, there is a method of dividing and using a signal, and dividing one signal output from the incremental encoder, for example, an A-phase signal is a known technique. For example, if the A-phase signal of the 8192 PPR incremental encoder is divided by 1/8, it becomes a 1024 PPR signal.

Further, as another solution different from the above, techniques for dividing the two A-phase signals and B-phase signals output by the incremental encoder are disclosed in Patent Document 1 and Patent Document 2.
In the patent document 1, there is disclosed a technique in which a 1/2 divider circuit is connected in a dependent manner to divide an A-phase signal and a B-phase signal. Further, in Patent Document 2, a divider circuit based on the division ratio E is disclosed, and it is estimated that the division ratio E does not depend on a division ratio of 1 to the power of two.

Japanese Patent Application Laid-Open No. 5-99947 Japanese Patent Application Laid-Open No. 7-12588

Both of the Patent Document 1 and the Patent Document 2 relate to the division of the A-phase signal and the B-phase signal among the signals output by the incremental encoder, and there is no description about the division of the Z-phase signal. . Here, when the incremental encoder outputs not only the A-phase signal and the B-phase signal but also the Z-phase signal, the division of the A-phase signal, the B-phase signal, and the Z-phase signal divides all three signals. A peripheral device (hereinafter referred to as a ABZ phase divider) is required.
That is, an object of the present invention is to provide a frequency-dividing device for the ABZ-phase, which divides the frequency by holding the mutual phase relationship of the original A-phase signal, B-phase signal and Z-phase signal instead of simply dividing. It is to realize.

In the present invention, the above problems are solved as follows.
(1) The present invention comprises an incremental encoder and an ABZ-phase frequency divider that receives an A-phase signal, a B-phase signal, and a Z-phase signal output from the incremental encoder, the ABZ-phase frequency divider It is characterized by Then, the incremental encoder outputs the A-phase signal and the B-phase signal which are pulse trains with a phase difference of 90 degrees according to the rotation, and outputs the Z-phase signal every one rotation.

  Further, the frequency divider includes a pulse converter and a counter, and the pulse converter inputs the A-phase signal and the B-phase signal, and the frequency of the A-phase signal and the B-phase signal multiplied by integer And a rotation direction signal indicating a rotation direction of the incremental encoder. Next, the counter is an up / down counter that receives the multiplication signal, the rotation direction signal, and the Z phase signal, and the counter counts up or down the multiplication signal according to the rotation direction signal. The count value is output, and the counter clears the previous count value when the Z-phase signal becomes active.

  The present invention is characterized in that the frequency divider is provided with a selector, a divided AB phase generator, a plurality of divided Z phase pulse width setting devices, and a comparator, and the selector counts the output of the counter. Select and output a continuous 2-bit signal from the value. Next, the divided AB phase generator divides the frequency from the 2-bit signal while maintaining the phase relationship between the A phase signal and the B phase signal at a dividing ratio 1 / K (K is a positive integer). It is characterized in that the divided A-phase signal and the divided B-phase signal are generated.

  Subsequently, the plurality of divided Z-phase pulse width setting units and the comparator constantly monitor the count value, and the count value is zero with respect to the Z-phase signal with respect to the Z-phase signal. The pulse width is such that the ratio is 1 / K and the reciprocal multiple of K, and a divided Z-phase signal synchronized with the Z-phase signal is generated.

  Thus, the present invention is characterized by generating the divided A-phase signal, the divided B-phase signal, and the divided Z-phase signal obtained by dividing the A-phase signal, the B-phase signal, and the Z-phase signal. Frequency divider of the ABZ phase.

(2) Furthermore, in the ABZ phase divider, the pulse width of the divided Z phase signal is made variable by changing the values of the plurality of divided Z phase pulse width setting devices to predetermined values. It is a frequency divider of ABZ phase characterized by

The effect of the present invention is that even if the A-phase signal, the B-phase signal, and the Z-phase signal output by the high resolution incremental encoder have high frequencies, the low frequency can be obtained by using the ABZ phase divider of the present invention. The divided A-phase signal, the divided B-phase signal, and the divided Z-phase signal can be obtained.
This makes it possible to use high-resolution incremental encoders in combination with modern controllers with superior performance, and at the same time to use them with other conventional or manufactured displays or monitors, or with other controllers. .

It is a block diagram showing composition of an example of the present invention. Example 1 It is a figure explaining operation of pulse converter 11 and counter 12. Example 1 It is a figure which expands and demonstrates a part of FIG. Example 1 FIG. 6 is a diagram for explaining the details of a selector 13; Example 1 It is a figure explaining generation of division A phase signal A2 and division B phase signal B2. Example 1 It is a figure explaining the mechanism which generates division Z phase signal Z2. (Example 1 and Example 2) It is a figure explaining generation of division Z phase signal Z2. Example 1

  In the following, the description is given with reference to the drawings of the embodiment of the present invention. FIG. 1 explains the configuration of the first embodiment, FIGS. 2 to 7 explain the operation of each part of the first embodiment in detail, and FIGS. 6 and 2 explain the second embodiment. It is.

  FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. In the figure, reference numerals 1 and 2 respectively indicate an incremental encoder and an ABZ frequency divider according to the present invention. The incremental encoder 1 outputs an A-phase signal A1, a B-phase signal B1, and a Z-phase signal Z1, and the A-phase signal A1 and the B-phase signal B1 are pulse trains generated in response to rotation with a 90 degree phase difference. When the direction of rotation changes, the phase difference is reversed. Further, the incremental encoder 1 outputs the Z-phase signal Z1 every one rotation.

Next, the ABZ phase divider 2 incorporates 11 to 24 devices shown in the figure, 11 and 12 are known devices, and 13 and subsequent devices constitute the features of the present invention.
First, 11 and 12 are a pulse converter and a counter, respectively. The pulse converter 11 receives the A-phase signal A1 and the B-phase signal B1 output from the incremental encoder 1 and outputs a multiplication signal and a rotation direction signal DR. Output The multiplied signal has a frequency of one, two or four times the frequency of the A-phase signal A1, but in the case of four in FIG.

Subsequently, the counter 12 receives the multiplication signal 4F, the rotation direction signal DR, and the Z-phase signal Z1 and outputs a count value C. Further, the counter 12 is an up / down counter, counts the multiplied signal 4 F up or down according to the rotation direction signal DR, and outputs a count value C. Here, in FIG. 1, the count value C is also described as C (n-1), C (n-2), .about.C0 in n-digit binary numbers.
The operations of the pulse converter 11 and the counter 12 will be further described in FIG. 2 and FIG. 3 later.

  Also in FIG. 1, 13 and 14 are a selector and an NXOR gate, respectively. First, the selector 13 receives the count value C by the counter 12 and the selection signal S corresponding to the division ratio 1 / K (K is a power of 2), and the selection signal S is output from a microcomputer not shown. It is Then, the selector 13 selects two consecutive bits of the counter C in response to the selection signal S, and outputs the upper digit bit from Y1 and the lower digit bit from Y0.

The signal output from the Y1 is a divided A-phase signal A2, and the output of the Y0 and Y1 calculated by the NXOR gate 14 becomes a divided B-phase signal B2. That is, the output Y1 of the selector 13 and the NXOR gate 14 constitute a divided AB phase generator, and the A phase signal A1 and the B phase signal B1 outputted by the incremental encoder 1 are the selection signal. The division is performed at the division ratio 1 / K specified by S to generate a divided A-phase signal A2 and a divided B-phase signal B2.
The details of the generation of the divided A-phase signal A2 and the divided B-phase signal B2 by the selector 13 and the NXOR gate 14 will be further described later with reference to FIGS.

Similarly, in FIG. 1, reference numerals 15, 17, 19 and 22 are division Z-phase pulse width setters, 16, 18, 20 and 23 are comparators, and 21 and 24 are AND gates and OR gates, respectively. The divided Z-phase pulse width setting unit 15 to the OR gate 24 constantly monitor the count value C, and with the count value C as a base point of zero, the pulse width is divided by the same period with respect to the Z-phase signal Z1. A divided Z-phase signal Z2 having a pulse width that is an inverse multiple (K times) of the ratio 1 / K is generated.
The generation of the divided Z-phase signal Z2 will be further described later with reference to FIGS.

Next, operations of the pulse converter 11 and the counter 12 of FIG. 1 will be described with reference to FIGS. 2 and 3.
First, FIG. 2 shows the waveform of the signal of each part of the incremental encoder 1, the pulse converter 11, and the counter 12 with the passage of time, and (a), (b), and (FIG. 2) c) shows the transition of the waveforms of the A-phase signal A1, the B-phase signal B1 and the Z-phase signal Z1 output from the incremental encoder 1, respectively. Then, as shown in FIG. 2C, the Z-phase signal Z1 is a one-pulse signal that the incremental encoder 1 outputs at time T1, T2, T3, T4 and T5 every one rotation.

Subsequently, (d) and (e) of FIG. 2 represent temporal transitions of the multiplied signal 4F and the rotation direction signal DR output from the pulse converter 11, respectively. Further, (f) of FIG. 2 shows the state of rotation of the incremental encoder 1, and is as follows.
About (f) of FIG. 2 until time T21, rotation by forward rotation from time T21 to T22, stop from time T22 to T41, reverse rotation by time T41 and later, rotation by forward rotation FIG. 2 (f) rotation With reference to the state of (e), the rotation direction signal DR in FIG.

これを数値例で示せば、１回転当たりのパルス数を８，１９２ＰＰＲとし、前記逓倍信号は４Ｆとしているのでここでは逓倍率が４となり、前記最大カウント値Ｃｍａｘは次の数式２の値となる。
(数２)

Further, (g) of FIG. 2 shows the temporal transition of the count value C outputted by the counter 12. When the incremental encoder 1 is forward rotation, it counts up, and when it is reverse rotation, it is countdown operation. Further, at times T1, T2, T3 and T4 when the Z-phase signal Z1 becomes 1, the count value C is cleared to zero.
Further, the maximum count value Cmax at + Cmax and -Cmax is a value according to the following Equation 1.
(1)

If this is shown as a numerical example, the number of pulses per one rotation is 8,192 PPR, and the multiplication signal is 4 F, so the multiplication ratio is 4 here, and the maximum count value Cmax is the value of the following equation 2. .
(2)

  Next, FIG. 3 is an enlarged view of the time between time T21 and time T22 in order to clarify the operations of (a), (b), (d) and (g) in FIG. (A) to (g) of FIG. 3 represent the same signals as those of the same reference numerals in FIG. Further, the temporal transition of (c), (e) and (f) of FIG. 3 is the same as that of FIG. 2 and the description thereof will be omitted.

With respect to (a) and (b) of FIG. 3, when the forward rotation is until time T21, the A-phase signal A1 leads the phase of the B-phase signal B1 by 90 degrees, and at the time of reverse rotation after time T22. The phase signal A1 is 90 degrees delayed. The (d) multiplied signal 4F in FIG. 3 is generated by detecting the rising and falling of the A-phase signal A1 and the B-phase signal B1.
Next, the (g) count value C of FIG. 3 is up-counted or down-counted as shown by the (d) multiplied signal 4F of FIG. 3 and (e) the rotation direction signal DR.

  Here, the pulse converter 11 and the counter 12 are well-known devices, but in order to facilitate the explanation of the present invention shown below, the operations of the said 11 and 12 are explained by the above-mentioned FIG. 2 and FIG. It is.

Next, the operations of the selector 13 and the NXOR gate 14 of FIG. 1 will be described with reference to FIGS. 4 and 5.
First, FIG. 4 illustrates an example of the configuration of the selector 13. In FIG. 4, reference numerals 13a and 13b denote multiplexers. The multiplexers 13a and 13b receive the count value C and the selection signal S, and output a divided upper digit Y1 and a divided lower digit Y0. The selection signal S is set by a microcomputer (not shown) corresponding to the division ratio 1 / K.

In FIG. 4, to facilitate the explanation, it is assumed that the lower 8-bit C (7), .about.C (1), C (0) in binary notation is used for the count value C, and the selection signal S is S (2), S (1) and S (0) are represented by 3 binary bits. The multiplexers 13a and 13b select and output one out of eight inputs according to the selection signals S (2) to S (0) as shown in the truth table of FIG. Here, the multiplexer 13a is inputted from the C (0), and the multiplexer 13b is inputted from the C (1). As a result, continuous two bits out of the count values C (7) to C (0) are output to the outputs Y1 and Y0 of the multiplexers 13a and 13b.
Table 1 below shows combinations of the value of the selection signal S and the signals output to the outputs Y1 and Y0. Table 1 also shows the division ratio obtained by the selection signal S, which will be described later. Note that, since FIG. 4 shows the count value C as a binary number in the lower eight bits, the selection signal S can not be used at 7 in Table 1.

(Table 1)

The frequency-divided A-phase signal A2 and the frequency-divided B-phase signal B2 are generated using the selector 13 and the NXOR gate 14 described with reference to FIG. 4, and this generation will be described next with reference to FIG. FIG. 5 shows the generation of the divided A-phase signal A2 and the divided B-phase signal B2 obtained by dividing the A-phase signal A1 and the B-phase signal B1 outputted by the incremental encoder 1 into, for example, 1/2. This is the case when the selection signal S is 1 in Table 1 above.
First, (a), (b), (d), (e), and (f) in FIG. 5 represent the same signals as those of the same reference numerals in FIG. Omit.

  (H), (i) and (j) of FIG. 5 represent temporal transitions of C (0), C (1) and C (2) of lower 3 bits of the count value C, C (2) in (j) of FIG. 5 becomes the divided A-phase signal A2. Further, (p) of FIG. 5 indicates that the values of C (2) and C (1) are expressed by decimal numbers and continuously change in the range of 0 to 3.

Next, (q) of FIG. 5 represents the output of the above-mentioned NXOR gate 14, and the inputs of the above-mentioned NGOR gate 14 are the above-mentioned C (2) and C (1). Here, N XOR is the negation of the exclusive OR, and the value of (q) in FIG. 5 is as follows at time T51 and T52 in FIG. 5.
Referring to (i) and (j) of FIG. 5, at time T51, C (1) = 0, C (2) = 1 → 0
At time T52, from C (1) = 1, C (2) = 1 → 1
Thus, (q) of FIG. 5 has a waveform as shown in the figure, which becomes the divided B-phase signal B2. Referring to (j) and (q) of FIG. 5, the divided A-phase signal A2 leads the divided B-phase signal B2 by 90 degrees at the time of forward rotation, and the frequency division at the time of reverse rotation. The A-phase signal A2 is delayed by 90 degrees, and is similar to the original A-phase signal A1 and the B-phase signal B1.

  The ABZ-phase frequency divider 2 according to the present invention as described above with reference to FIGS. 4 and 5 performs the A-phase signal A1 and the B-phase signal B1 output from the incremental encoder 1 with the selector 13 and the NXOR gate. The divided A-phase signal A2 and the divided B-phase signal B2 are generated by dividing the frequency into 1 / K while maintaining the mutual phase relationship.

  The division of the A-phase signal A1 and the B-phase signal B1 output from the incremental encoder 1 has been described above according to the present invention, but in addition to this, the division of the Z-phase signal Z1 in FIG. Description will be made with reference to FIGS. 6 and 7. First, in FIG. 1, the divided Z-phase signal Z2 is generated by the OR gate 24 from the divided Z-phase pulse width setting unit 15.

Subsequently, FIG. 6 explains the mechanism for generating the divided Z-phase signal Z2, and FIG. 6 (g) shows the temporal transition of the count value C outputted by the counter 12. The values ZW1, ZW2, ZW3 and ZW4 respectively held by the divided Z-phase pulse width setting devices 15, 17, 19 and 22 are added to (g) of 2). Here, the divided Z-phase pulse width setting units 15, 17, 19 and 22 are also referred to as divided Z-phase pulse width setting units ZW1, ZW2, ZW3 and ZW4.
Next, (t) of FIG. 6 shows the divided Z-phase signal Z2 generated according to the present invention. The divided Z-phase signal Z2 is, for example, 1 at time Ta to Tc, Td to Te, and Tf to Th, which is 1 by the divided Z-phase pulse width setter 15 to the OR gate 24 as shown in Table 2 It is generated as follows.

(Table 2)

Referring to Table 2, since the count value C is larger than the divided Z-phase pulse width setter ZW4 during the time period Ta to Tb, the comparator 23 is activated to output 1; The divided Z-phase signal Z2 becomes 1 through the OR gate 24.
Next, during the period from Tb to Tc, the count value C is larger than the divided Z-phase pulse width setter ZW2 and larger than the divided Z-phase pulse width setter ZW3, the comparator 18 and 20 becomes active to output 1 and the divided Z-phase signal Z2 becomes 1 through the AND gate 21 and the OR gate 24.
The time between Td and Te, and between Tg and Th is the same as between time Tb and Tc, and the description at this time is omitted.
Next, since the count value C is less than the divided Z-phase pulse width setting device ZW1 during a period from Tf to Tg, the comparator 16 becomes active and 1 is outputted, and the minute is outputted through the OR gate 24. The circumferential Z-phase signal Z2 is 1.
Here, ZW1 and ZW2 are negative integers, and ZW3 and ZW4 are positive integers. When the count value C is a value other than the range shown in Table 2, the divided Z-phase signal Z2 is zero.

  As described above, the mechanism for generating the divided Z-phase signal Z2 has been described with reference to FIG. 6, and further description will be given with reference to FIG. FIG. 7 shows the waveform of the signal of each part along with the transition of time, and (a), (b), (d), (e), (h), (i), and (FIG. 7). j) represents the same signal as that of the same symbol in FIG. 5, and the description thereof will be omitted. The direction of rotation of the incremental encoder 1 is represented by forward rotation, stop and reverse rotation in FIG. 5, but is represented by only forward rotation in FIG.

  FIG. 7C shows the Z-phase signal Z1 output from the incremental encoder 1, and the period of 1 is made equal to one cycle of the A-phase signal A1 as shown, for example. Here, in FIG. 7, the dividing ratio 1 / K is set to 1⁄4, and in Table 1, the count value C (3) and C (2) are used with the value of the selection signal S being 2 and Of (k) represents the count value C (3), that is, the divided A-phase signal A2. Further, (r) of FIG. 7 represents the values of C (3) and C (2) in decimal, and indicates that they continuously change in the range of 0 to 3.

  Next, (s) of FIG. 7 represents the output of the N-XOR gate 14 to which the C (3) and C (2) are input, and this becomes the divided B-phase signal B2. The divided A-phase signal A2 and the divided B-phase signal B2 according to (k) and (s) in FIG. 7 are obtained by dividing (a) and (b) in FIG. 7 into 1/4. Become.

(T) of FIG. 7 shows the transition of the divided Z-phase signal Z2, which corresponds to the divided Z-phase pulse width setter ZW1 to ZW4 in Table 3 and Table 6 in FIG. It is a value. The period in which the divided Z-phase signal Z2 is 1 is four times the period in which the Z-phase signal Z1 is 1 corresponding to the dividing ratio 1/4, and one period of the divided A-phase signal A2 Will be the same.
(Table 3)

As described above with reference to FIG. 7, the ABZ-phase frequency divider 2 according to the present invention mutually transmits the A-phase signal A1, the B-phase signal B1 and the Z-phase signal Z1 output from the incremental encoder 1 mutually. The divided A-phase signal A2, the divided B-phase signal B2, and the divided Z-phase signal Z2 are generated while maintaining the phase relationship of (1) and dividing by a predetermined division ratio 1 / K.

  Next, the Z-phase signal Z1 output from the incremental encoder 1 is a signal of one pulse per rotation, and the pulse width is usually narrow. For this reason, the waveform of the Z-phase signal Z1 is often deformed due to noise, and reception may fail at another device having a slow response. However, in the ABZ phase divider 2 according to the present invention, by changing the value of the divided Z phase pulse width setter shown in FIG. The Z-phase signal Z2 is generated to eliminate the influence of noise and to be surely used in combination with other slow-responsive devices.

  By using the ABZ phase divider according to the present invention, a high resolution incremental encoder is used in combination with a recent controller with excellent performance, and at the same time, a display or monitor made by another company or another company or another It becomes possible to use with the control device etc.

1 Incremental Encoder 2 ABZ Phase Divider 11 Pulse Converter 12 Counter 13 Selector 14 N XOR Gate 15, 17, 19, 22 Divided Z Phase Pulse Width Setter 16, 18, 20, 23 Comparator 21 AND Gate 24 OR Gate 13a, 13b Multiplexer

Claims (2)

An incremental encoder, and a frequency divider that receives an A-phase signal, a B-phase signal, and a Z-phase signal output from the incremental encoder,

The incremental encoder outputs the A-phase signal and the B-phase signal, which are pulse trains with a phase difference of 90 degrees according to the rotation, and outputs the Z-phase signal for each rotation.

The frequency divider includes a pulse converter and a counter,
The pulse converter receives the A-phase signal and the B-phase signal, and generates a multiplied signal whose frequency is an integral multiple of the frequencies of the A-phase signal and the B-phase signal, and a rotation direction signal indicating the rotation direction of the incremental encoder. To detect

The counter is an up / down counter that receives the multiplication signal, the rotation direction signal, and the Z-phase signal, and the counter counts up or down the multiplication signal according to the rotation direction signal to count. The counter outputs a value and the counter clears the count value when the Z-phase signal becomes active.

The frequency divider is provided with a selector, a divided AB phase generator, a plurality of divided Z phase pulse width setting devices, and a comparator.
The selector selects and outputs a continuous 2-bit signal from the count value output from the counter,
The divided AB phase generator divides the frequency by a dividing ratio 1 / K (K is a positive integer) while maintaining the phase relationship between the A phase signal and the B phase signal from the 2-bit signal. , Generating a divided A-phase signal and a divided B-phase signal,
The plurality of divided Z-phase pulse width setting units and the comparator constantly monitor the count value, and the pulse width is the division ratio of 1 with respect to the Z-phase signal with the count value at zero as a base point. The pulse width is K which is an inverse multiple of K / K, and a divided Z-phase signal synchronized with the Z-phase signal is generated,
An ABZ-phase frequency divider characterized by generating the divided A-phase signal, divided B-phase signal, and divided Z-phase signal obtained by dividing the A-phase signal, B-phase signal, and Z-phase signal. .
The ABZ-phase divider according to claim 1, wherein the pulse width of the divided Z-phase signal is made variable by changing the values of the plurality of divided Z-phase pulse width setting devices. Phase divider.

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